The SAM4S-WPIR-RD Reference Design Kit is based on SAM4S16C device. It introduces the application of Passive InfraRed Motion Detector Camera.
This User Guide gives design details on the Reference Design Kit and is made up of 4 sections:
Section 1 includes a photo of the board, references and applicable documents.
Section 2 describes the contents and the main features of the Reference Design Kit.
Section 3 provides instructions to power up the board and describes how to use it.
Section 4 describes the hardware resources, function blocks, connectors and schematics.
The Atmel® SAM4S-WPIR-RD Reference Design Kit includes:
Board
– One SAM4S-WPIR-RD board
Power supply
– USB supply
Cables
– One USB cable, type A to type Micro-B
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should there be issues concerning the
contents of the kit.
2.2Board Specifications
Section 2
Kit Contents
Table 2-1. SAM4S-WPIR-RD Board Specifications
CharacteristicsSpecifications
Clock speed 48 MHz MCK
PortsUSB, JTAG
Board supply voltage5V DC from USB or 3 x AAA Alkaline cells
Temperature
- operating
- storage
Relative humidity0 to 90% (non condensing)
Dimensions136 mm x 90mm
RoHS statusCompliant
-10° to +50° C
-40° to +85° C
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2.3Electrostatic Warning
The SAM4S-WPIR-RD board is shipped in a protective anti-static package. The board system must not be subjected to high electrostatic potentials. A grounding strap or similar ESD protective device should be worn when
handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touching the
component pins or any other metallic element on the board.
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3.1Power Up the Board
Unpack the board taking care to avoid electrostatic discharge. Connect the board to PC with the USB cable, or
insert 3 x AAA Alkaline cells on U4 Battery Holder, and then the board should be powered on.
Note:Jumpers JP1, JP4, JP7, JP8, JP9, JP10 must be closed and JP2, JP3 must be open for start-up.
3.2Sample Code and Technical Support
Users can download sample code and get technical support from the Atmel web site:
The SAM4S-WPIR-RD block diagram includes battery holder, LDO, image sensor, 1M byte SRAM, PIR sensor,
JTAG connector, LCD, ZigBee connector, as shown in Figure 4-1.
Figure 4-1. SAM4S-WPIR-RD Block Diagram
Section 4
Hardware
4.2Function Blocks
4.2.1Processor
The board is equipped with a SAM4S16 device in a LQFP100 package.
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4.2.2Clock Circuitry
The board includes 2 clock sources:
One 12 MHz Crystal for Internal Clock (Y2)
One 32.768 kHz Crystal for RTC Clock (Y1)
4.2.3Reset Circuitry
The reset sources for the board are:
Power on reset
JTAG reset from an in-circuit emulator (JTAG interface is equipped on the board)
4.2.4Push Button Switches
User interface (BP1)
4.2.5Power Supplies
The Board is driven by 5V input power rail from USB cable or 3 x AAA battery.
The Board embeds all the necessary power rails required for the microcontroller
Table 4-1 summarizes the power specifications.
Table 4-1. Power Rails Associated with the Systems
NominalNamePowersComponent
3.0VVDDIOPartial Peripheral I/O lineson board
3.0V+3V_PERIPHSRAM and image sensoron board
3.0V+3V_LCDLCD and backlight driveron board
1.2VVDDPLLthe PLL cellFrom SAM4S internal LDO
1.2VVDDCORE
3.0VADVREFanalogon board
the core, including the processor, the
embedded memories and the peripherals
From SAM4S internal LDO
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Figure 4-2. Power Supply
FGND
PC17
R147KR3
R268K
RV1
V5.5MLA0603
C3
10pF
DGND
C51
100nF
J1
USB Micr o B
5V D- D+ ID G
8
9
123
27R
VBU S
L6 220o hm at 100MHz
C6
33 uF
16V
DGND
PB11
PB10
12
475
R4
27R
NSR0320M W2T1G
VBAT
NSR0320M W2T1G
6
RV2
V5.5MLA0603
FGNDDGND
D3
D4
JP8
VIN_SYST EM
VIN_SYST EM
R43 100K
R41 100K
C70
100nF
C58
100nF
DGND
DGND
C59
1uF
C29
1uF
U6
1
IN
2
GND1
EN3GND2
TPS78230DDCR
U5
1
IN
2
GND1
EN3GND2
TPS78230DDCR
OUT
OUT
+3V_LCD
C60
1uF
C57
1uF
JP10
+3VVIN_SYST EM
JP7
JP9
+3V_MCU
+3V_PERIPH
5
4
DGND
5
4
DGND
4.2.6Memory
The SAM4S features an External Bus Interface (EBI) that permits interfacing to a broad range of external memories and virtually to any parallel peripheral. The SAM4S-WPIR-RD board is equipped with a memory device
connected to the SAM4 EBI:
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a standard USB-toJTAG in-circuit emulator such as SAM-ICE™.
Figure 4-4. JTAG Interface
+3V_MCU
4.2.8Image Sensor
The CMOS image sensor, OV7740 from OmniVision, used in this reference design is a low-complexity, low-cost,
low-power, yet powerful sensor. It supports VGA (640x480) at up to 60 fps and QVGA (320x240) at up to 120 fps.
The OV7740 has standard interface output pins such as data, horizontal/vertical synchronization signals, pixel
clock output and main clock input. Interfacing between the CMOS image sensor and the SAM4S device is made
easy by means of the sensor interface (parallel capture mode). The SAM4S is able to sample data from the CMOS
image sensor without CPU intervention and transfer image data into internal or external memory.
Figure 4-5. Image Sensor
PB13
PC15
PA4
PA3
PA21
PA23
PA16
PA15
R29
4.7K
+3V_OVT
R30
4.7K
PA21
PA23
PA16
PA15
R63
100K
DGND
PB13
R64100K
R527R
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
14
16
18
20
DGND
PWDN_OVT
MN7
OV7740
D5
XVCLK1
A4
PWDN
B5
RESETB
C4
SIOC
C5
SIOD
C2
FSIN
E6
PCLK
C3
HREF
D1
VSYNC
E5
DATA0
E2
DATA1
D4
DATA2
D3
DATA3
F5
DATA4
F2
DATA5
E4
DATA6
E3
DATA7
D2
DATA8
E1
DATA9
R6
J2
100K
12
34
56
78
910
1112
13
15
17
19
HTST-110-01-SM-DV
DVDD
DGND
DOVDD
DOVDD
DOGND
AVDD
AVDD
AGND
AGND
VREFH
VREFN
IMAGE SENSOR
NC1
NC2
R7
100K
F4
F3
C1
C6
D6
A1
A6
B1
B6
A3
B2
A2
A5
R8
100K
R9
R10
100K
100K
TDI
TMS
TCK
TDO
NRST
+3V_PERIPH
R28
32
1
Q3
<REF >
PWDN_OVT
100K
R13 0R
R15 DNP
PC10
0R
R32
+3V_OVT
DNP
0R
C56
C34
DNP
100nF
100nF
DGND
0R
L1
C35
1uF
C41
1uF
C47
1uF
AGND_OVT
C36
100nF
DGND
L2
4.7uH
C42
100nF
C48
1uF
R45 0R
DGND
C37
1uF
C40
1uF
C46
1uF
4.2.9PIR sensor
The PIR sensor (RE200B from Nicera) chosen for the reference design is a general purpose dual element. This
model satisfies user's cost reduction needs, keeping most dual element type performances at reasonable levels.
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Figure 4-6. PIR Sensor
U1
1
D
2
S
3
G
RE200B
AGND
R42
47K
ADVREF
R36
10K
AGND
C49
10uF
AGND
ADVREF
R33
1M
R35
1M
AGND
R39 10K
C50
10uF
C45
100nF
R4010K
R34
10K
R37
1M
C39
10uF
MN8
LT1495CS8
2
3
7
6
5
C33100nF
R311M
IN1-
IN1+
OUT2
IN2-
IN2+
OUT1
VCC
GND
1
AD0, ADC single end input
BN03K314S300R
C44
100nF
B1
R38 0R
8
4
AGND
PA17
ADVREF
DGND
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4.2.10ZigBee
The board has a 10-pin male connector for the Atmel RZ600 ZigBee module.
Figure 4-7. ZigBee Interface
4.2.11LED Indicators
The board has one LED indicator for purposes shown below:
Table 4-2. LED Indicators
ReferenceColorFunction
D1BluePIR indicator
4.2.12LCD
ZB_RSTN
ZB_IRQ
SPIO_NPCS1#
MISO
PB2
PB14
PA12
J5
2X10PTS COU DE
12
34
56
78
910
C61
18pF
PB3PA5
PA6
PA13
PA14
C62
2.2nF
MISC
SLP_TR
MOSI
SPCK
DGND
C63
2.2uF
+3V_PER IPH
The LCD module gets reset from the NRST signal. As explained, this NRST is shared with the JTAG port. The LCD
chip select signal is connected to NCS2. The SAM4S communicates with the LCD through PIOC where an 8-bit
parallel “8080-like” protocol data bus has to be implemented by software.
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Figure 4-8. LCD Block
A
+3V_LCD
DGND
R54
10K
R57
4.7K
NCS2
+
PC11
PC8
PC19
PA22
NRST
LED_A
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
C52
10uF
+3V_LCD
C53
100nF
DGND
R560R
C54
100nF
LED_K1
LED_K2
LED_K3
LED_K4
R44
47K
DGND
J4
FH26- 39S- 0.3SHW
1
VDD
2
DB17
3
DB16
4
DB15
5
DB14
6
DB13
7
DB12
8
DB11
9
DB10
10
DB9
11
DB8
12
DB7
13
DB6
14
DB5
15
DB4
16
DB3
17
DB2
18
DB1
19
DB0
20
VDD
21
RD
22
WR
23
RS
24
CS
25
RESET
26
IM0
27
IM1
28
GND
29
LED- A
30
LEDK1
31
LEDK2
32
LEDK3
33
LEDK4
34
Y+
35
Y-
36
X+
37
X-
38
NC
39
GND
LCD
U7
LCD
YXT28MP002A- 39
4.2.13Backlight Control
The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by an
AAT3155 charge pump, MN10.The AAT3155 is controlled by the SAM4S through a single PIO line PC13 interface;
the 0 Ohm resistor R59 is mounted in series on this line, which permits to use it for other custom purposes. In that
case, the pull-up resistor R58 maintains the charge pump permanently enabled by default.
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Figure 4-9. Backlight Control
PC13
4.3Connectors
4.3.1JTAG/ICE Connector
Figure 4-10. JTAG J2
+3V_LCD
R59
0R
B2
BN03K314S300R
+3V_LC D
R58
47K
DGND
C67
4.7uF
C64
1uF
10
11
9
5
4
MN10
C1+
C1EN/SET
IN
GND
AAT3155IT P
C2+
OUTC P
7
C65
6
C2-
8
3
D1
2
D2
1
D3
12
D4
1uF
LED_A
LED_K1
LED_K2
LED_K3
LED_K4
DGND
C66
1uF
Table 4-3. JTAG/ICE Connector J2 Signal Descriptions
PinMnemonicDescription
This is the target reference voltage. It is used to check if the target has power,
1VTref. 3.3V power
2Vsupply. 3.3V power
nTRST TARGET RESET - Active-low output
3
signal that resets the target
4GNDCommon ground
TDI TEST DATA INPUT - Serial data output
line, sampled on the rising edge of the TCK
5
signal.
6GNDCommon ground
7TMS TEST MODE SELECT
8GNDCommon ground
to create the logic-level reference for the input comparators, and to control the
output logic levels to the target. It is normally fed from VDD on the target board
and must not have a series resistor.
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to VDD or leave open in target system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target's JTAG state machine, sampled on the rising edge of the TCK signal.
TCK TEST CLOCK - Output timing signal,
for synchronizing test logic and control
9
register access.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
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PinMnemonicDescription
10GNDCommon ground
Some targets must synchronize the JTAG inputs to internal clocks. To assist in
RTCK - Input Return test clock signal from
11
the target.
12GNDCommon ground
TDO JTAG TEST DATA OUTPUT - Serial
13
data input from the target.
14GNDCommon ground
15nSRST RESETActive-low reset signal. Target CPU reset signal.
16GNDCommon ground
17RFUThis pin is not connected in SAM-ICE.
18GNDCommon ground
19RFUThis pin is not connected in SAM-ICE.
20GNDCommon ground
meeting this requirement, a returned and retimed TCK can be used to
dynamically control the TCK rate. SAM-ICE supports adaptive clocking which
waits for TCK changes to be echoed correctly before making further changes.
Connect to RTCK if available, otherwise to GND.
JTAG data output from target CPU. Typically connected to TDO on target CPU.
4.3.2USB Micro AB
Figure 4-11. USB Device Micro-B Connector J1
Table 4-4. USB Device Micro-B Connector J1 Signal Descriptions
PinMnemonicDescription
1Vbus5v power
2DMData minus
3DPData plus
4IDNot used
5GNDCommon ground
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