The SAM4S Evaluation Kit (SAM4S-EK2) enables evaluation capabilities and code development of
applications running on a SAM4SD32 device.
1.2User Guide
This guide focuses on the SAM4S-EK2 board as an evaluation platform. It is made up of 6 sections:
Section 1 includes references, applicable documents, acronyms and abbreviations.
Section 2 describes the kit contents, its main features and specif ications.
Section 3 provides instructions to power up the SAM4S-EK2 and describes how to use it.
Section 4 provides board specifications, describes the development environment and presents the
hardware resources, default jumper, switch settings and connectors.
The Atmel® SAM4S-EK2 toolkit contains the following items:
Board:
– a SAM4S-EK2 board
– a universal input AC/DC power supply with US, Europe and UK plug adapters
Cables:
– one USB cable
– one serial RS232 cable
A Welcome Letter
Figure 2-1. Unpacked SAM4S-EK2
Section 2
Kit Contents
Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
SAM4S-EK2 User Guide2-1
11176A–ATARM–24-Sep-12
2.2Electrostatic Warning
The SAM4S-EK2 board is shipped in a protective anti-static bag. The board must not be subjected to
high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the components or any other metallic element of the board.
Kit Contents
SAM4S-EK2 User Guide2-2
11176A–ATARM–24-Sep-12
3.1Power up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it into the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch the icons displayed on
the screen and enjoy the demo.
3.2Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can
download sample code and get technical suppor t from th e Atm el web site : http://www.atmel.com
Section 3
Power Up
SAM4S-EK2 User Guide3-1
11176A–ATARM–24-Sep-12
4.1Board Overview
This section introduces the Atmel SAM4S-EK2 Evaluation Kit design. It introduces system-level concepts, such as power distribution, memory, and interface assignments.
The SAM4S-EK2 board is based on the integration of an ARM
NAND Flash and a set of popular peripherals. It is designed to provide a high performance processor
evaluation solution with high flexibility for various kinds of applications.
Figure 4-1. SAM4S-EK2 Block Diagram
Section 4
Evaluation Kit Hardware
®
Cortex®-M4 processor with on-board
SAM4S-EK2 User Guide4-1
11176A–ATARM–24-Sep-12
4.2Features List
Here is the list of the main board components and interfaces:
SAM4SD32 chip LQFP100 package with optional socket footprint
12 MHz crystal
32.768 KHz crystal
Optional SMB connector for external system clock input
NAND Flash
2.8 inch TFT color LCD display with touch panel and b acklight
UART port with level shifter circuit
USART port with level shifter circuit multiplexed with RS485 port with level shifter circuit
Microphone input and mono/stereo headphone jack output
SD/MMC interface
Reset button: NRST
User buttons: Left and Right
QTouch
Full Speed USB device port
JTAG/ICE port
On-board power regulation
Two user LEDs
Pow er LED
BNC connector for ADC input
BNC connector for DAC output
User potentiometer connected to the ADC input
ZigBEE connector
2x32 bit PIO connection interfaces (PIOA, PIOC) and 1x16 bit PIO connection interface (PIOB)
®
buttons: Up, Down, Left, Right, Valid and Slider
Evaluation Kit Hardware
4.3Function Blocks
4.3.1Processor
The SAM4S-EK2 is equipped with a SAM4SD32 device in LQFP100 package.
4.3.2Memory
The SAM4SD32 chip embeds:
2048 Kbytes of embedded Flash
160 Kbytes of embedded SRAM
16 Kbytes of ROM with embedded BootLo ader routines (U AR T, USB) and In-Application Programming
functions (IAP) routines
SAM4S-EK2 User Guide4-2
11176A–ATARM–24-Sep-12
Evaluation Kit Hardware
MN3
WE
18
N.C6
6
VCC
37
CE
9
RE
8
N.C11
20
WP
19
N.C5
5
N.C1
1
N.C2
2
N.C3
3
N.C4
4
N.C12
21
N.C13
22
N.C14
23
N.C15
24
R/B
7
N.C17
26
N.C18
27
N.C19
28
I/O0
29
N.C21
34
N.C22
35
VSS
36
PRE
38
N.C23
39
VCC
12
VSS
13
ALE
17
N.C8
11
N.C7
10
N.C9
14
N.C10
15
CLE
16
N.C16
25
N.C20
33
I/O1
30
I/O3
32
I/O2
31
N.C27
47
N.C26
46
N.C25
45
I/O7
44
I/O6
43
I/O5
42
I/O4
41
N.C24
40
N.C28
48
MT29F2G08ABAEA
JP9
Heade r2
C28
100nF
NAND FLASH
PC18
C29
1uF
+3V3
PC14
DGND
R16
47K
R22
0R
DNP
R2147 K
R190R
DGND
+3V3
C27
100nF
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
R15
47K
+3V3
PC10
PC9
PC16
PC17
+3V3
MN3
WE
18
N.C6
6
VCC
37
CE
9
RE
8
N.C11
20
WP
19
N.C5
5
N.C1
1
N.C2
2
N.C3
3
N.C4
4
N.C12
21
N.C13
22
N.C14
23
N.C15
24
R/B
7
N.C17
26
N.C18
27
N.C19
28
I/O0
29
N.C21
34
N.C22
35
VSS
36
PRE
38
N.C23
39
VCC
12
VSS
13
ALE
17
N.C8
11
N.C7
10
N.C9
14
N.C10
15
CLE
16
N.C16
25
N.C20
33
I/O1
30
I/O3
32
I/O2
31
N.C27
47
N.C26
46
N.C25
45
I/O7
44
I/O6
43
I/O5
42
I/O4
41
N.C24
40
N.C28
48
MT29F2G08ABAEA
JP9
Heade r2
C28
100nF
NAND FLASH
PC18
C29
1uF
+3V3
PC14
DGND
R16
47K
R22
0R
DNP
R2147 K
R190R
DGND
+3V3
C27
100nF
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
R15
47K
+3V3
PC10
PC9
PC16
PC17
+3V3
MN3
WE
18
N.C6
6
VCC
37
CE
9
RE
8
N.C11
20
WP
19
N.C5
5
N.C1
1
N.C2
2
N.C3
3
N.C4
4
N.C12
21
N.C13
22
N.C14
23
N.C15
24
R/B
7
N.C17
26
N.C18
27
N.C19
28
I/O0
29
N.C21
34
N.C22
35
VSS
36
PRE
38
N.C23
39
VCC
12
VSS
13
ALE
17
N.C8
11
N.C7
10
N.C9
14
N.C10
15
CLE
16
N.C16
25
N.C20
33
I/O1
30
I/O3
32
I/O2
31
N.C27
47
N.C26
46
N.C25
45
I/O7
44
I/O6
43
I/O5
42
I/O4
41
N.C24
40
N.C28
48
MT29F2G08ABAEA
JP9
Heade r2
C28
100nF
NAND FLASH
PC18
C29
1uF
+3V3
PC14
DGND
R16
47K
R22
0R
DNP
R2147 K
R190R
DGND
+3V3
C27
100nF
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
R15
47K
+3V3
PC10
PC9
PC16
PC17
+3V3
NOT POPULATED
DNP
XOUT32
XIN32
XIN32
XOUT32
PA7
PA8
XIN
XOUT
PB8
PB9
DGND
DGND
DGND
DGND
DGND
R3DNPR3DNP
R6DNPR6DNP
R9DNPR9DNP
R1DNPR1DNP
C3
20pFC320pF
R40RR40R
C4
20pFC420pF
R2
49.9R 1%R249.9R 1%
Y1Y1
12
3
R8DNPR8DNP
R7DNPR7DNP
MN1MN1
PA7_RTS0_PWMH3
49
PA8_CTS0_AD12BTRG
48
PB8_XOUT
96
PB9 _XIN
97
R110RR11
0R
Y212MHzY212MHz
C120pFC120pF
R10DNPR10DNP
Y3
32.768KHz
Y3
32.768KHz
12
3
R50RR50R
R120RR12
0R
J1J1
1
23
54
C220pFC220pF
SAM4SD32
The SAM4SD32 features an External Bus Interface (EBI) that permits interfacing to a broad range of
external memories and virtually to any parallel peripheral. The SAM4S-EK2 board is equipped with a
memory device connected to the SAM4 EBI:
One NAND Flash MT29F2G08ABAEA.
Figure 4-2. NAND Flash
4.3.3Clock Circuitry
Figure 4-3. External Clock Source
SAM4S-EK2 User Guide4-3
NCS0 chip select signal is used for NAND Flash chip selection. Furthermore, a dedicated jumper can
disconnect it from the on-board mem ories, thereby letting NCS0 free for other custom purposes.
The clock generator of a SAM4SD32 microcontroller is composed of:
A Low Power 32.768 Hz Slow Clock Oscillator with bypass mode
A 3 to 20 MHz Crystal Oscillator, which can be bypassed (12 MHz needed in case of USB)
A factory programmed fast internal RC Oscillator. 3 output frequencies can be selected: 4 (default
value), 8 or 12 MHz.
A 60 to 130 MHz PLL (PLLB) providing a clock for the USB Full Speed Controller
A 60 to 130 MHz programmable PLL (PLLA), capable to provide the clock MCK to the processor and
to the peripherals. The input frequency of PLLA is from 7.5 to 20 MHz
The SAM4S-EK2 board is equipped with one 12 MHz crystal, optional Piezoelectric Ceramic Resonator
12 MHz (Murata ref. CSTCE12M0G15L99-R0), one 32.768 Hz crystal and an external clock input connector (optional, not populated by default).
11176A–ATARM–24-Sep-12
The SAM4SD32 chip internally generates the following clocks:
DGND
+5V
DGND
+5V+3V3
C75
100uF
+
C75
100uF
C65
22uF
+
C65
22uF
C64
100nF
C64
100nF
MN10
BNX002-01
MN10
BNX002-01
SV
1
SG
2
CV
3
CG1
4
CG2
5
CG3
6
C76
100nF
C76
100nF
C66
22uF
+
C66
22uF
MN9
ZEN056V130A24LS
MN9
ZEN056V130A24LS
1
2
3
R92
102K 1%
R92
102K 1%
MN12
MIC29152WU
Micrel's 1.5A LDO, TO263-5
MN12
MIC29152WU
Micrel's 1.5A LDO, TO263-5
VIN
2
VOUT
4
SD
1
GND1
3
ADJ
5
GND2
6
R89
169K 1%
R89
169K 1%
J9
MP179P 2.1mm
J9
MP179P 2.1mm
1
2
3
SLCK, the Slow Clock, which is the only permanent clock of the system
MAINCK, the output of the Main Clock Oscillator selection: either a Crystal Oscillator or a 4/8/12 MHz
Fast RC Oscillator
PLLACK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLA)
PLLBCK, the output of the Divider and 60 to 130 MHz programmable PLL (PLLB)
4.3.4Reset Circuitry
On-board NRST button BP1 provides an external reset control of th e SAM4SD32.
The NRST pin is bidirectional. It is handled by the on-c hip reset controller. It can be driven low to provide
a reset signal out to the external components. Conversely, it can be asserted low from the outside to
reset the microcontroller Core and the per ipherals. The NRST pin integrates a perma nent pull-up re sistor
of 100 kOhm to VDDIO.
On the SAM4S-EK2 board, the NRST signal is connected to the LCD module and JTAG port.
Note:At power-on, the NRST signal is asserted with a default duration of 2 clock cycles. That duration may not be
Evaluation Kit Hardware
sufficient to correctly reset any other system or board devices connected to that signal. First, in your custom
application, you need to check for these device’s datasheets about reset duration requirements. Then, you
need to set an appropriate configuration in the NRST Manager. This is done through the ERSTL field in the
RSTC_MR register. The NRST duration is thereby configurable between 60 µs and 2 s, whether it is subsequently activated by a software reset or a user reset. Refer to the SAM4SD32 datasheet for in-depth
information.
4.3.5Power Supply and Management
The SAM4S-EK2 board is supplied with an external 5V DC block through input J9. It is protected by a
PolyZen diode (MN9) and an LC combinatory filter (MN10). The PolyZen is used in the event of an incorrect power supply connection.
The adjustable LDO regulator MN12 is used for the 3.3V rail main supply. It powers all the 3.3V components on the board.
Figure 4-4. Power Block
The SAM4SD32 product has different types of power supply pins:
VDDIN pin:
Power for the internal voltage regulator, ADC, DAC, and analog comparator power supplies.
SAM4S-EK2 User Guide4-4
The voltage ranges from 1.8V to 3.6V.
11176A–ATARM–24-Sep-12
4.3.6UART
Evaluation Kit Hardware
VDDIO pins:
Po wer for the Peripherals I/O lines.
The voltage ranges from 1.62V to 3.6V.
VDDOUT pin:
Output of the internal voltage regulator.
VDDCORE pins:
Power for the core, including the processor, embedded memories and peripherals.
The voltage ranges fr om 1.62V to 1.95V.
VDDPLL pin:
Power for the PLL A, PLL B and 12 MHz oscillator.
The voltage ranges fr om 1.62V to 1.95V.
Note:VDDPLL should be decoupled and filtered from VDDCORE.
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes. It offers an ideal channel for in-situ programming solutions. This UART
is associated with two PDC channels to reduce the processor time on packet handling.
This two-pin UART (TXD and RXD only) is buffered through an RS232 Transceiver MN6 and brought to
the DB9 male connector J7.
4.3.7USART
Figure 4-5. UART
MN6
MN6
MAX3232CSE
MAX3232CSE
16
VCC
2
V+
6
V-
15
GND
11
T1IN
12
R1OUT
10
T2IN
9
R2OUT
C1+
C2+
T1OUT
R1IN
T2OUT
R2IN
1
C38
C38
100nF
100nF
3
C1-
4
C42
C42
100nF
100nF
5
C2-
14
13
7
8
DGND
1
6
2
7
3
8
4
9
5
FGND
J7J7
10
11
PA10
PA9
+3V3
TP5
TP5
SMD
SMD
R45
R45
100K
100K
+3V3
R46
R46
100K
100K
R470RR470R
R480RR480R
+3V3
C40
C40
100nF
100nF
TP6
TP6
SMD
SMD
DGND
C39
C39
100nF
100nF
C41
C41
100nF
100nF
The Universal Synchronous/Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous/asynchronous serial link. The data frame format is extensively configurable (data
length, parity, number of stop bits) to support a broad range of serial communication standards. The
USART is also associated with PDC channels for TX/RX data access.
Note:For design optimization purposes, both tr ansmitters have been implemented on the same
PIO lines, that is PA21, 22, 23, 24, 25.
To avoid any electrical conflict, the RS485 transceiver is isolated from the receiving line PA21.
Should you need to implement an RS485 channel in place of the RS232, follow the procedure below:
1.make sure your software will permanently set PA23 to a high level - this will permanently disable the
RS232 receiver.
2. change JP31 to make sure that 2-3 pins are connected.
SAM4S-EK2 User Guide4-5
11176A–ATARM–24-Sep-12
4.3.7.1RS232
DGND
DGND
+3V3
J5
5
4
3
2
1
9
8
7
6
10
11
FGND
PA25
DGND
MN5
ADM3312 EARU
C1+
6
C1-
20
C2+
2
C2-
4
C3+
24
C3-
22
VCC
3
V+
1
V-
21
GND
23
SD
19
EN
5
T1IN7T1OUT
18
R1IN
15
R1OUT
10
T2IN8T2OUT
17
R2IN
14
R2OUT
11
T3IN9T3OUT
16
R3IN
13
R3OUT
12
PA24
C34
100nF
PA21_ 232
C31
4.7uF
C35
100nF
R32
47K
PA22
C37
100nF
USART
C33
100nF
R3747 K
PA23
C36
100nF
C32
100nF
+3V3
R310R
R330R
R340R
R350R
R360R
R380R
+3V3
PA25
PA21_ 485
R23
10K
R250R
R30
TBD
DNP
R24
TBD
DNP
+3V3
R260R
R270R
R280R
FGND
R29
120R
MN4
ADM3485 ARZ
RO
1
RE
2
DE
3
DI
4
VCC
8
GND
5
A
6
B
7
JP11
Header2
JP12
Header2
C30
100nF
JP10
Header2
+3V3
DGND
DGND
PA22
RS 485
+3V3
PA24
J4
1
2
3
JP28
Header2 nm
DNP
Evaluation Kit Hardware
SAM4S-EK2 connects the USART1 bus (including TXD, RXD, RTS, CTS handshake signal controls and
EN command) to the DB9 male connector J5 through the RS232 Transceiver MN5.
Figure 4-6. USART Evaluation Kit Hardware
4.3.7.2RS485
As noticed above, the USART1 is shared with the RS485 port, connected to the transceiver MN4, connected to the 3-point connector J4. The design includes selectable jumpers for RS485 bu s termination
resistors selection (JP10, JP11, JP12).
Figure 4-7. RS485
4.3.8Display Interface
The SAM4S-EK2 carries a TFT Transmissive LCD module with touch panel, FTM280C34D. Its integrated driver IC is ILI9325. The LCD displa y area is 2.8 inches diagonally me asured, with a native
resolution of 240 x 320 dots.
11176A–ATARM–24-Sep-12
SAM4S-EK2 User Guide4-6
4.3.8.1LCD Module
LCD_DB3
R590R
Six slots on PCB for LCD shield
PC11
R634.7 K
DNP
DGND
LED_A
PC26
LCD_DB2
NRST
PC8
LCD_DB0
PC27
LCD
C45
100nF
LCD_DB4
DGND
J8
FH26-39S -0.3SHW
VDD
1
DB1 7
2
DB1 6
3
DB1 5
4
DB1 4
5
DB1 3
6
DB1 2
7
DB1 1
8
DB1 0
9
DB9
10
DB8
11
DB7
12
DB6
13
DB5
14
DB4
15
DB3
16
DB2
17
DB1
18
DB0
19
VDD
20
RD
21
WR
22
RS
23
CS
24
RES ET
25
IM0
26
IM1
27
GND
28
LED-A
29
LEDK1
30
LEDK2
31
LEDK3
32
LEDK4
33
Y+
34
Y-
35
X+
36
X-
37
NC
38
GND
39
PC28
DGND
R49
47K
X_RIGHT
Y_DOWN
Y_UP
X_LEFT
D1
PACDN044Y5 R
TVS, SOT23-5
DNP
1
2
345
NOT POPULAT ED
The part is pl aced as
cl o s e as pos s ibl e t o J8
DGND
PC29
DGND
DGND
DGND
JP13Header2
LCD_DB9
LCD_DB 13
LCD_DB 12
LCD_DB 11
LCD_DB 10
LCD_DB 16
LCD_DB 15
LCD_DB 14
PC30
LCD_DB 17
R58
4.7K
LCD_DB5
PC2
PC1
PC0
PC3
X_LEFT
LCD_DB9
R56
10K
PC6
PC5
PC4
PC7
PC23
X_RIGHT
+3V3
DGND
DGND
LCD_DB7
Y_DOWN
LCD_DB8
Y_UP
RA2
4.7Kx4
DNP
1
2
3
45
6
7
8
PC22
PC31
PC13
LCD_DB6
LCD_DB6
LCD_DB7
DGND
PC15
PC[0 ..31]
LED_K4
LCD_DB8
LCD_DB4
LCD_DB5
LED_K3
LED_K2
PC24
PINs
on
BOT
PIN 39
PIN 1
Z7
FTM28 0C34 D
LCD_DB2
LCD_DB3
LCD_DB1
LED_K1
NRST
RA3
4.7Kx4
DNP
1
2
3
45
6
7
8
PC19
LCD_DB0
LCD_DB1
C44
100nF
R614.7 K
DNP
DGND
+3V3
+
C43
10uF
PC25
MN8
AAT3155ITP-T1
C1+
10
C1-
9
EN/SET
11
C2+
7
C2-
6
OUTCP
8
IN
5
GND
4
D1
3
D2
2
D3
1
D4
12
C55
1uF
C54
1uF
C57
4.7uF
C56
1uF
R68
0R
R64
47K
LED_A
LED_K1
+3V3
LED_K4
LED_K3
LED_K2
+3V3
PC13
DGND
DGND
TP7
FB1
BN03K314S3 00R
LCD BACKLI GHT
The LCD module gets reset from the NRST sig nal. As expl ained, this NRST is shared with the JTAG port
and the push-button BP1. The LCD chip select signal is connected to NCS1; the jump er JP13 can disconnect it so that this PIO line is available for other custom usage.
The SAM4SD32 communicates with the LCD through PIOC where an 8-bit parallel “8080-like” protocol
data bus has to be implemented in software.
Figure 4-8. LCD Block
Evaluation Kit Hardware
The LCD backlight is made of four integrated white chip-LEDs arranged in parallel. These are driven by
an AAT3155 charge pump, MN8. The AAT3155 is controlled by the SAM4SD32 through a single PIO
line PC13 interface; the 0 Ohm resistor R68 is mounted in series on this line, which permits to use it for
other custom purposes. In that case, the pull-up resistor R64 maintains the charge pump permanently
enabled by default.
On the anode drive line, a 0 Ohm resistor R59 is implemented in series for an optional current limitation.
Figure 4-9. Backlight Control
11176A–ATARM–24-Sep-12
4.3.8.2Backlight Control
SAM4S-EK2 User Guide4-7
4.3.8.3Touch Screen Interface
AGND_TP
JP32
Header2
LCD TOUCH SCREEN
R74
0R
C59
100nF
C58
100nF
R71
1R
C60
100nF
TP8
PA14
PA13
PA12
C61
4.7uF
PA11
PA17
TP9
DGND
R65
100K
+3V3
+3V3
AGND_TP
+3V3
R62
100K
R73
100K
R72
100K
L2
10uH-100mA
MN7
ADS7843E
XP
2
YP
3
XM
4
YM
5
DCLK
16
DIN
14
DOUT
12
CS
15
BUSY
13
PE NIRQ
11
VREF
9
VCC1
1
VCC2
10
GND
6
IN3
7
IN4
8
X_RIGHT
Y_DOWN
X_LEFT
Y_UP
R670R
R700R
R69 0R
PA16
The LCD module integrates a 4-wire touch panel controlled by MN7 (ADS7843) which is a slave device
on the SAM4SD32 SPI bus. The controller sends back the information about the X and Y positions, as
well as a measurement for the pressure applied to the touch panel. The touch panel can be used with
either a stylus or a finger.
The ADS7843 touch panel controller connects to the SPI0 interface via the NPCS0 control signal. Two
interrupt signals are connected and provide events information back to the microcontroller: PenIrq and
Busy.
Note:PenIrq (PA16) is shared with ZigBEE signal IRQ0.
Busy (PA17) is shared with ZigBEE signal IRQ1.
Therefore, if using a ZigBEE interface in concurrence with the TouchScreen controller, take
care not to have both drivers enabled at the same time on either PA16 or PA17.
For that purpose, 0 Ohm resistors have been implemented on these PIO lines in order to disconnect
either end driver from the other:
On the touch panel controller side, R67 and R69.
On ZigBEE side, R117 and R120.
For further information, refer t o the “Schematics” section.
Evaluation Kit Hardware
Touch ADC auxiliary inputs IN3/IN4 of the ADS7843 are connected to test points (TP8, TP9) for optional
function extension.
Figure 4-10. Touch Panel Control
4.3.9JTAG/ICE
A standard 20-pin JTAG/ICE connector is implemented on the SAM4S-EK2 for the connection of a compatible ARM JTAG emulator interface, such as the SAM-ICE from Segger.
Notes: 1. The NRST signal is connected to BP1 system button and is also used to reset the LCD
module. The 0 ohm resistor R44 may be removed in order to isolate the JTAG port fr om
this system reset signal.
2. The TDO pin is in input mode with the pull-up resistor disabled when the Cortex M4 is
not in debug mode. To avoid current consumption on VDDIO and/or VDDCORE due to
floating input, the internal pull-up resistor corresponding to this PIO line must be
enabled.
11176A–ATARM–24-Sep-12
SAM4S-EK2 User Guide4-8
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