Atec TLA700 User Manual

MagniVu™Acquisition Technology
Provides 500 ps Timing Resolution on
All Channels All the Time Through a
Single Probe

Up to 200 MHz State Acquisition with
400 MHz Data Rate Supports Advanced
Processors and Buses

Simultaneous State and High Speed
Timing Analysis Through the Same
Probes Pinpoints Elusive Integration
Faults

64 Channel Pattern Generator with up
to 268 MHz and up to 2 MB Memory
Depth Provides Digital Stimulus for
Functional Verification, Debugging and
Stress Testing

Four Channel Digitizing Oscilloscope
with up to 1 GHz, 5 GS/s Provides High­fidelity Signal Quality Measurements of
Digital Signals

Expansion Mainframe Supports up to 16
Modules with up to 2,176 LA channels,
1,024 Pattern Generator Channels or 64
Digitizing Oscilloscope channels for
Large, Multiple Processor and Bus
Applications

Microsoft

®

Windows®-based PC
Platform Provides Familiar User
Interface With Network Connectivity

Hardware Debug and Verification
Processor/Bus Debug and Verification
Embedded Software Integration, Debug

and Verification
Embedded Real-time Software

Optimization
System Validation

BREAKTHROUGH SOLUTIONS FOR REAL-TIME
DIGITAL SYSTEMS ANALYSIS

Today’s digital design engineers face daily pressures
to speed new products to the marketplace. The
TLA 700 Series answers the need with breakthrough

solutions for the entire design team, providing the
ability to quickly monitor, capture and analyze real­time system operation in order to debug, verify,
optimize and validate digital systems.

Features and Benefits Applications

Logic Analyzers

TLA 700 Series

®

LOGIC ANALYZERS • TLA 700 SERIES

2

Logic Analyzer Modules

GENERAL

Number of Channels per Module (all chan­nels are acquired including clocks) –

TLA 7N1: 34 channels (2 are clock/qualifier
channels).
TLA 7N2, TLA 7P2: 68 channels (4 are clock/
qualifier channels).
TLA 7N3: 102 channels (4 are clock/qualifier and
2 are qualifier channels).
TLA 7N4, TLA 7P4: 136 channels (4 are
clock/qualifier and 4 are qualifier channels).
Channel Grouping – No limit to number of
groups or number of channels per group (all
channels can be reused in multiple groups).

Module “Merging” – Three 102 channel or 136
channel modules can be “merged” to make up to
a 408 channel module. Merged modules exhibit
the same depth as the lesser of the three individ­ual modules. Word/range/setup-and­hold/glitch/transition recognizers span all three
modules. Only one set of clock connections is
required.

Time Stamp – 50 Bits at 500 ps resolution (6.5
day range).

Clocking/Acquisition Modes- State, timing,
simultaneous.

Number of Mainframe Slots Required – 2.

INPUT CHARACTERISTICS (WITH P6417,
P6418 OR P6434 PROBES)

Capacitive Loading –

1.4 pF typical data; 2pF typical clock (P6418).
2 pF typical (P6417 & P6434).

Threshold Selection Range – From +5.0 V
to –2.0 V in 50 mV increments.

Threshold Selection Channel Granularity –

Separate selection for clock (1) and data (16) for
each 17 channel probe connector.

Threshold Accuracy (including probe) –

±100 mV.

Input Voltage Range –

Operating: 6.5 V

P-P

centered around the pro­grammed threshold.
Non-destructive: ±15 V.

Input Signal Swing (probe overdrive) –

±250 mV or ±25% of signal swing, whichever is
greater (P6417 & P6418).
±300 mV or ± 25% of signal swing (P6434).

Input Signal Minimum Slew Rate –

200 mV/ns typical.

STATE ACQUISITION CHARACTERISTICS
(WITH P6417, P6418 OR P6434 PROBES)

Maximum Synchronous Clock Rate –

100M Hz standard, 200 M Hz optional.

Maximum Data Rate (Half Channels) –

400 MHz, typical. Requires 200 MHz state option.
State Memory Depth – 64 K, 256 K, 1 M, 4 M

or 16M bits per channel.
Setup Time Selection Range – From 8.5 ns

before, to 7.0 ns after clock edge.

Setup-and-hold Window – 2.0 ns typical.
Minimum Clock Pulse Width – 2 ns.
Active Clock Edge Separation – 5 ns.
Demux Channel Selection – 32 channels can

be demultiplexed to other channels through user
interface; for all channels contact local Tektronix
account manager.

TIMING ACQUISITION CHARACTERISTICS
(WITH P6417, P6418 OR P6434 PROBES)

Main Timing Resolution – 4 ns to 50 ms.
Main Timing Resolution with Glitch Storage
Enabled – 10 ns to 50 ms.
Main Timing Memory Depth (with or with­out transitional storage enabled) – 64 K,

256 K, 1 M, 4 M or 16M bits per channel.

Main Timing Memory Depth with Glitch
Storage Enabled – Half of default main

memory depth.

MagniVu – 500 ps.
MagniVu Timing Memory Depth – 2 Kbits

(2048) per channel.

Channel-to-channel Skew – ≤1 ns typical.
Minimum Recognizable Pulse Width (single
channel) – 2 ns.
Minimum Recognizable Glitch Width (single
channel) – 2 ns.
Minimum Recognizable Multi-channel
Trigger Event – Sample period + 2 ns.

TRIGGER CHARACTERISTICS

Independent Trigger States – 16.
Maximum Independent If/then Clauses per
State – 16.
Maximum Number of Events per If/then
Clause – 8.
Maximum Number of Actions per If/then
Clause – 8.
Maximum Number of Trigger Events – 18

(2 counter/timers plus any 16 other resources).

Number of Word Recognizers– 16.
Number of Range Recognizers – 4.
Number of Counter/Timers – 2.
Trigger Event Types – Word, group, channel,

transition, range, anything, counter value, timer
value, signal, glitch, setup-and-hold violation.
Trigger Action Types – Trigger module, trigger
all, store, don’t store, start store, stop store, incre­ment counter, reset counter, start timer, stop
timer, reset timer, goto state, set/clear signal, do
nothing.

Trigger Sequence Rate – DC to 250 MHz
(4 ns).
Counter/Timer Range – 51 bits each (>100
days @ 4 ns).

Counter Rate – DC to 250 MHz (4 ns).
Timer Clock Rate – 250 MHz (4 ns).
Counter/Timer Latency – None (can be tested

or reset immediately after starting).
Range Recognizers – Double bounded (can be
as wide as any group, must be grouped accord­ing to specified order of significance).

Setup-and-hold Violation Recognizer Setup
Time Range – From 8 ns before to 7 ns after

clock edge in 0.5 ns increments.

Setup-and-hold Violation Recognizer Hold
Time Range – From 7 ns before to 8 ns after

clock edge in 0.5 ns increments.

Trigger Position – Any data sample.
MagniVu Trigger Position – MagniVu data is

centered around the module trigger.
Storage Control (data qualification) – Global
(conditional), by state (start/stop), by trigger
action, or transitional.
Storage Window Granularity – Single sample
or block-of-31 samples before and after.

Logic Analyzer Module
Physical Characteristics

Dimensions mm in.

Height 262 10.3
Width 61 2.4
Depth 381 15

Weight kg lb.

Net 3.1 6.7
Shipping 6.3 13.7

P6417 Probe Cable Length – 1.8 m (6 ft.).
P6418 Probe Cable Length – 1.9 m (6.25 ft.).
P6434 Probe Cable Length – 1.5 m (5 ft.).

All three probes have the same electrical length.

Pattern Generator Module

GENERAL

Data Width –

64 Channel full channel mode.
32 Channel half channel mode.

Module “Merging” – Five modules can be
“merged” to make up to a 320 channel module.
Merged modules exhibit the same depth as the
lesser of the 5 individual modules.

Number of Mainframe Slots Required – 2.
Data Rate –

Internal Clock:

0.5 Hz to 134M Hz full channel mode.

1.0Hz to 268 M Hz half channel mode.

External Clock:

DC to 134M Hz full channel mode.
DC to 268 MHz half channel mode.

Characteristics

LOGIC ANALYZERS • TLA 700 SERIES

3

External Clock Input –

Polarity: positive or negative.
Threshold: –2.56 V to +2.54 V, nominal; program­mable in 20 mV increments.
Sensitivity: ≤500 mV

p-p

.

Impedance: 1 kΩ terminated to ground.

Data Depth –

256 K full channel/512K half channel.
1 M full channel/2 M half channel (optional).

PATTERN SEQUENCING CHARACTERISTICS

Blocks – Separate sections of pattern program
that are output in a user definable order by the
Sequencer. Block pattern depth can be from 40
sequences (full channel mode) or 80 sequences
(half channel mode) up to the entire depth of the
TLA 7PG2. A maximum of 4,000 Blocks may be
defined.
Sequencer – A 4000 line memory that allows
the user to pick the output order of individual
Blocks. Each line in the sequencer allows the defi­nition of a Block to be output, a Repeat Count for
that Block, A Wait For event condition for the
Block, the Signal state for that Block (asserted or
unasserted), and a Jump If event condition, with
a sequence line to jump to if the condition is
satisfied.
Sub-Sequences – Up to 50 contiguous lines of
the Sequencer memory may be defined as a Sub­Sequence. A Sub-Sequence can then be treated
like a block. (Example: 15 Sequences of Blocks
are defined as Sub-Sequence A1. Now any line in
the Sequencer can output A1. Five calls to Sub­Sequence A1 will be flattened out to 75
sequences at run time.)
Jump If – Jumps to the specified sequence if a
user defined event is true. The user defined event
is a boolean combination of the eight external
event input lines and the one-of-four intermodule
signals. The user defined Event is selectable
between level and edge (event going from false
to true). One Jump If may be defined for every
Block. The Jump If command works at all clock
rates, including the maximum half channel mode
rate of 268 MHz.
Wait For – Pattern output is paused until the
user defined Event is true. One Wait For may be
defined for every Block.
Assert Signal – One of the four inter-module
signals is selected to be controlled from the pat­tern generator program. Signals may be asserted
and unasserted allowing true interaction with the
logic analyzer modules and with other pattern
generator modules. Signal action (assert or
unassert) may be defined for every Block.
Repeat Count – The sequence is repeated from
1 to 65,536 times. Infinite may also be selected.
One Repeat Count may be defined for every
Block. Note that a Repeat value of 10,000 takes
one sequence line in memory, not 10,000.
Step – While in Step mode, the TLA 7PG2, the
user can manually satisfy (i.e., click an icon) Wait
For and Jump conditional events. This allows the
user to debug the logic flow of the program’s
sequencing.
Initialization Block – The unconditional Jump
command allows the user to implement an equiv­alent function.

COMMON TO P6470 TTL/CMOS & P6471
ECL PROBES

Number of Data Outputs –

16 in Full Channel Mode.
8 in Half Channel Mode.

Number of Clock Outputs – 1.
(Only one of Clock Output and Strobe Output can
be enabled.)

Number of Strobe Outputs – 1.
(Only one of Clock Output and Strobe Output can
be enabled.)

Number of External Event Input – 2.
Clock Output Polarity – Positive.
Strobe Type – RZ only.
Strobe Delay – Zero or Trailing Edge.

P6470 TTL/CMOS PROBE

Output Type –

HD74LVC541A for Data Output.
HD74LVC244A for Clock/Strobe Output.

Rise/Fall Time (20% to 80%) –

Timing values Timing values

measured using measured using

75 Ω termination 75 Ωtermination

(internal to probe), (internal to probe),

1M Ω + <1 pF 510 Ω+ 51 pF

load and V

OH

load and V

OH

set to 5.0 V set to 5.0 V

Clock/Strobe Output:

Rise: 640 ps typical 6.5 ns typical
Fall: 1.1 ns typical 6.3ns typical

Data Output:

Rise: 680 ps typical 5.2 ns typical
Fall: 2.9ns typical 4.5 ns typical

Output Voltage (nominal, load: 1 MΩ)–

V

OH

: 2.0 V to 5.5 V, tri-stateable, programmable in
25 mV increments.
V

OL

: 0 V.

Data Output Skew –

< 510 ps typical between all data output pins of
all modules in the mainframe after inter-module
skew is adjusted manually.
< 480 ps typical between all data output pins of
single probe.

Data Output to Strobe Output Delay –

1.7 ns typical when strobe delay set to zero.

Data Output to Clock Output Delay –

2.4 ns typical.

External Clock Input to Clock Output
Delay –

Full Channel mode: 61.5 ns typical.
Half Channel mode: 61.5 ns typical.

Number of External Inhibit Input – 1.
External Inhibit Input to Output Enable

Delay – 34 ns typical for Data Output.
External Inhibit Input to Output Disable

Delay – 86 ns typical for Data Output.
Probe D Data Output to Output Enable

Delay – (for Internal Inhibit) 7 ns typical for Data

Output.

Probe D Data Output to Output Disable
Delay – (for Internal Inhibit) 8 ns typical for Data

Output.

External Event Input to Clock Output Setup
(for inhibit) (event-filter: off) –

Full Channel mode: 1.5 clocks + 150ns typical.
Half Channel mode: 2 clocks + 150ns t ypical.

External Event Input and Inhibit Input –

Input Type: 74LVC14A.
Minimum Pulse Width: 100ns.

P6471 ECL PROBE

Output Type –

100E151 for data output.
100EL16 for strobe output.
100EL04 for clock output.
All outputs are unterminated.

Rise/Fall Time (20% to 80%) –

Timing values measured

using 51Ωs to –2.0 V

Clock Output:

Rise: 320 ps typical
Fall: 330 ps typical

Data Output:

Rise: 1200 ps typical
Fall: 710 ps typical

Strobe Output:

Rise: 290 ps typical
Fall: 270 ps typical

Data Output Skew –

<170 ps typical between all data output pins of all
modules in the mainframe after inter-module
skew is adjusted manually.
<140 ps typical between all data output pins of
single probe.

Data Output to Strobe Output Delay –

2.94 ns typical when strobe delay set to zero.

Data Output to Clock Output Delay –

780 ps typical.

External Clock Input to Clock Output
Delay – 51 ns typical.

External Event Input –

Input Level: ECL.
Input Type: 10H116.
Minimum Pulse Width: 50 ns.

Pattern Generator Module
Physical Characteristics

Dimensions mm in.

Height 262 10.3
Width 61 2.4
Depth 381 15

Weight kg lb.

Net 3.0 6.5
Shipping 6.2 13.5

P6470 Probe Cable Length– 1.6 m (5 ft.)
P6471 Probe Cable Length – 1.6 m (5 ft.)

Characteristics