Asus B34Y Schematic

5

4

3

2

1

SYSTEM PAGE REF.

01. Block Diagr am

02. System Sett ing

03. CPU(1)_DMI, DP,PEG,FDI

04. CPU(2)_CLK, MSIC,JTAG

05. CPU(3)_DDR3

06. CPU(4)_PROC RSSOE POWER

07. CPU(5)_GRAP HIC POWER

08. CPU(6)_GND

D D

09. CPU(7)_RESE RVED

10. CPU_PCH_XDP

11. CPU DECOUPL ING

16. DDR3(1)_SO- DIMM0

18. DDR3(3)_CA/ DQ Voltage

20. PCH(1)_SATA ,IHDA,RTC,LPC

21. PCH(2)_PCIE ,CLK,SMB,PEG

22. PCH(3)_FDI, DMI,SYS PWR

23. PCH(4)_DP,L VDS,CRT

24. PCH(5)_PCI, NVRAM,USB

25. PCH(6)_CPU, GPIO,MISC

26. PCH(7)_POWE R,GND

27. PCH(8)_POWE R,GND

28. PCH(9)_SPI, SMB

29. CLK_ICS9LRS 3197

30. EC_NPCE795( 1)

31. EC_NPCE795( 2) KB,TP

32. RST_Reset C ircuit

33. LAN_RTL8111 E

C C

34. LAN_RJ45

38. AUD(1)_ALC2 69

40. CB(1)_RTS51 38

44. BUG_Debug

45. CRT(1)_LVDS

46. CRT(1)_CRT

48. TV(1)_HDMI

50. FAN_Fan

51. mSATA, HDD, ODD

52. USB30 Port

53. MINICARD_WL AN

55. Camera

56. LED_Indicat or

57. DSG_Dischar ge

60. DC_DC/BAT C ONN

65. ME_CONN,Ske w Hole
69 G-SENSOR*** **
80_POWER_VCORE& VGFX
81_POWER_SYSTEM
82_POWER_+VCCP

B B

83_POWER_DDR & VTT
84_POWER_+1.8VS
85_POWER_0.85VS
87_POWER_+VGA_C ORE(DSC)
88_POWER_CHARGE R(ISL88731)
90_POWER_DETECT
91_POWER_LOAD S WITCH
92_POWER_PROTEC T
93_POWER_SIGNAL
94_POWER_FLOWCH ART

95. POWER_ HIST ORY

97. SYSTEM_HIST ORY

98. Power On Se quence

99. Power On Ti ming

A A

B34Y Chief River Platform(TACOMA FALL2) Rev 1.2

BLOCK DIAGRAM

LCD Panel

Page 45

CRT

Page 46

HDMI

Page 48

Touchpad
Keyboard

Page 31

PWM Fan

Page 50

Speaker

Page 38

Combo Audio Jack
(IO DB)

Page 66

Discharge Circuit

Reset Circuit

LVDS

RGB

HDMI

TPM(Optional)

Debug Conn.

Azalia Codec

Page 62

EC

NPCE795L

Page 30

ALC269

DC & BATT. Conn.

Page 57

Page 32

Page 44

SPI ROM

Page 38

Skew Holes

LPC

Page 28

Azalia

Page 57

Page 65

CPU

Ivy Bridge

FDI x4

DMI x4

PCH

Panther Point

SATA

SATA

mSATA

0

4

2

ODD
(Optional 2nd Batt)

Page 20~28

Page 3~11

SSD

HDD

DDR3 1333MHz

PCIEx1

USB 2.0

USB 3.0

Page 51

Page 51

Page 51

3

DDR3 SO-DIMM

5

2

3

1

9

3

8

2

MiniCard

WLAN + BT3.0
Rainbow Peak

10/100/1000 LAN

RTL8111F-CG

USB 2.0
(IO DB)

USB 2.0
(IO DB)

CardReader

RTS5138-GR

CMOS Camera

internal MIC

USB30 with charging
Charging is optional

Page 16, 18

Page 53

Page 66

Page 66

Page 40

Page 55

Page 52

Power

+VCC_CORE
+VGFX_CORE

RJ45

Page 34Page 33~34

+VGA_CORE

Load Switch

Power Protect

Page 80

System

Page 81

VTT

Page 82

DDR3

Page 83

+1.8VS

Page 84

+VCCSA

Page 85

Page 87

Charger

Page 88

Detect

Page 90

Page 91

Page 92

Title :

Title :

Title :

Block Diagram

Block Diagram

Block Diagram

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Trunks Chen

Trunks Chen

Trunks Chen

of

1 59Wednesday, February 01, 2 012

of

1 59Wednesday, February 01, 2 012

of

1 59Wednesday, February 01, 2 012

Rev

Rev

Rev

1.0

1.0

1.0

PCH_CPT
GPIO

D D

C C

B B

A A

5

PCH_CPT
GPIO

GPIO 00
GPIO 01

GPIO [2:5]

GPIO 06
GPIO 07
GPIO 08
GPIO 09
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22
GPIO 23
GPIO 24
GPIO 25
GPIO 26
GPIO 27
GPIO 28
GPIO 29
GPIO 30

GPIO 31
GPIO 32
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39
GPIO 40
GPIO 41
GPIO 42
GPIO 43
GPIO 44
GPIO 45
GPIO 46
GPIO 47
GPIO 48
GPIO 49

GPIO 50
GPIO 51
GPIO 52
GPIO 53
GPIO 54
GPIO 55
GPIO 56
GPIO 57
GPIO 58
GPIO 59
GPIO 60
GPIO 61
GPIO 62
GPIO 63
GPIO 64
GPIO 65
GPIO 66
GPIO 67
GPIO 72
GPIO 73
GPIO 74
GPIO 75

5

Signal NameUse As Power

4

Internal &
External
Pull-up/down

4

EC
NPCE795L

3

EC GPIO

GPA0
GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
GPD0
GPD1
GPD2
GPD3
GPD4
GPD5
GPD6
GPD7
GPE0
GPE1
GPE2
GPE3
GPE4
GPE5
GPE6
GPE7
GPF0
GPF1
GPF2
GPF3
GPF4
GPF5
GPF6
GPF7
GPG0
GPG1
GPG2
GPG6
GPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
GPJ0
GPJ1
GPJ2
GPJ3
GPJ4
GPJ5

3

Use As Signal Name

2

1

SM_BUS ADDRESS :

SM-Bus Device

SO-DIMM 0

SO-DIMM 1

N/A

PCIE 1

PCIE 2

Minicard WLAN

PCIE 3

USB3.0

PCIE 4

N/A

PCIE 5

PCIE 6

GLAN

N/A

PCIE 7

N/A

PCIE 8

SATA0

SATA HDD

SATA1

N/A

SATA2

SATA ODD

SATA3

N/A

N/ASATA4

SATA5

N/A

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

SM-Bus Address

1010000x ( A0h )

1010001x ( A4h )

USB 0

USB Port (1)

USB 1

USB Port (2)

USB 3.0 Port (3)N/A

USB 2

USB Port (4)

USB 3

N/A

USB 4

N/A

USB 5

USB 6

N/A
N/A

USB 7

CMOS Camera

USB 8

WLAN

USB 9

Card Reader

USB 10

N/A

USB 11

N/A

USB 12

N/A

USB 13

B34

B34

B34

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

System Setting

System Setting

System Setting

Trunks Chen

Trunks Chen

Trunks Chen

of

of

of

2 59Wednesday, February 01, 2012

2 59Wednesday, February 01, 2012

2 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

4

3

2

+VCCP

+VCCP 4,6,7,26,27,30,32,82

1

U0301A

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

AA11
AC12

AA10

AG11

AE11

AE10

P10

P11

W11

W1
AA6
W6

AC9

W10

W3
AA7
W7

AA3
AC8

U11

AG8

AF3
AD2

AG4

AF4

AC3
AC4

AE7

AC1
AA4

AE6

M2

P6
P1

N3

P7
P3

K1
M8
N4
R2

K3
M7

P4

T3

U7

V4

Y2

U6

T4

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]

FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI0_LSYNC
FDI1_LSYNC

eDP_COMPIO
eDP_ICOMPO
eDP_HPD

eDP_AUX#
eDP_AUX

eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]

eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]

ES1

01V010000003

DMI Intel(R) FDI DP

PCI EXPRESS -- GRAPHICS

DMI_TXN022
DMI_TXN122
DMI_TXN222
DMI_TXN322

DMI_TXP022
DMI_TXP122
DMI_TXP222
DMI_TXP322

DMI_RXN022
DMI_RXN122
DMI_RXN222
DMI_RXN322

DMI_RXP022
DMI_RXP122
DMI_RXP222
DMI_RXP322

C C

VCCIO pull high 24.9 ohm

+VCCP

B B

FDI_TXN[7:0]22

FDI_TXP[7:0]22

FDI_FSYNC022
FDI_FSYNC122

FDI_INT22

FDI_LSYNC022
FDI_LSYNC122

12

DP_COMP

R030224.9Ohm 1%

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

G3
G1
G4

H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7

K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6

G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4

F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4

PEG_COMP

PCIENB_RXN15
PCIENB_RXN14
PCIENB_RXN13
PCIENB_RXN12
PCIENB_RXN11
PCIENB_RXN10
PCIENB_RXN9
PCIENB_RXN8
PCIENB_RXN7
PCIENB_RXN6
PCIENB_RXN5
PCIENB_RXN4
PCIENB_RXN3
PCIENB_RXN2
PCIENB_RXN1
PCIENB_RXN0

PCIENB_RXP15
PCIENB_RXP14
PCIENB_RXP13
PCIENB_RXP12
PCIENB_RXP11
PCIENB_RXP10
PCIENB_RXP9
PCIENB_RXP8
PCIENB_RXP7
PCIENB_RXP6
PCIENB_RXP5
PCIENB_RXP4
PCIENB_RXP3
PCIENB_RXP2
PCIENB_RXP1
PCIENB_RXP0

PCIENB_TXN0

CX0301 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN1

CX0302 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN2

CX0303 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN3

CX0304 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN4

CX0305 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN5

CX0306 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN6

CX0307 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN7

CX0308 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXN8

CX0309 0.22UF/10V /DIS

PCIENB_TXN9

CX0310 0.22UF/10V /DIS

PCIENB_TXN10

CX0311 0.22UF/10V /DIS

PCIENB_TXN11

CX0312 0.22UF/10V /DIS

PCIENB_TXN12

CX0313 0.22UF/10V /DIS

PCIENB_TXN13

CX0314 0.22UF/10V /DIS

PCIENB_TXN14

CX0315 0.22UF/10V /DIS

PCIENB_TXN15

CX0316 0.22UF/10V /DIS

PCIENB_TXP0

CX0317 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP1

CX0318 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP2

CX0319 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP3

CX0320 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP4

CX0321 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP5

CX0322 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP6

CX0323 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP7

CX0324 0.22UF/10V /DIS_non-N13M-GS

PCIENB_TXP8

CX0325 0.22UF/10V /DIS

PCIENB_TXP9

CX0326 0.22UF/10V /DIS

PCIENB_TXP10

CX0327 0.22UF/10V /DIS

PCIENB_TXP11

CX0328 0.22UF/10V /DIS

PCIENB_TXP12

CX0329 0.22UF/10V /DIS

PCIENB_TXP13

CX0330 0.22UF/10V /DIS

PCIENB_TXP14

CX0331 0.22UF/10V /DIS

PCIENB_TXP15

CX0332 0.22UF/10V /DIS

R0301 24.9Ohm1%

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

PCIENB_RXN[15:0] 70

PCIENB_RXP[15:0] 70

If Support PCIE Gen3, change AC Cap to 0.22uF

+VCCP

PEG Compensation(Keep if PEG no used)

Enable PCIE Lane Reversal
Need to PD CFG[2]

PCIEG_RXN15
PCIEG_RXN14
PCIEG_RXN13
PCIEG_RXN12
PCIEG_RXN11
PCIEG_RXN10
PCIEG_RXN9
PCIEG_RXN8
PCIEG_RXN7
PCIEG_RXN6
PCIEG_RXN5
PCIEG_RXN4
PCIEG_RXN3
PCIEG_RXN2
PCIEG_RXN1
PCIEG_RXN0

PCIEG_RXP15
PCIEG_RXP14
PCIEG_RXP13
PCIEG_RXP12
PCIEG_RXP11
PCIEG_RXP10
PCIEG_RXP9
PCIEG_RXP8
PCIEG_RXP7
PCIEG_RXP6
PCIEG_RXP5
PCIEG_RXP4
PCIEG_RXP3
PCIEG_RXP2
PCIEG_RXP1
PCIEG_RXP0

PCIEG_RXN[15:0] 70

PCIEG_RXP[15:0] 70

R1.1

A A

CPU(1)_DMI,DP,PEG,FDI

CPU(1)_DMI,DP,PEG,FDI

CPU(1)_DMI,DP,PEG,FDI

Title :

Title :

Title :

Trunks Chen

Trunks Chen

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Trunks Chen

of

of

of

3 59Wednesday, February 01, 2012

3 59Wednesday, February 01, 2012

3 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

U0301B

H_SNB_IVB#25

D D

+VCCP

H_THRMTRIP#25,32

H_PM_SYNC22

H_CPUPWRGD25

PM_DRAM_PWRGD22

BUF_PLT_RST#24,30,32,33,53,62,70

C C

1

T0401

1

T0402

H_PECI25

12

5%

R040462Ohm

H_PROCHOT# H_PROCHOT#_D

R0406

NB_R0402_5MIL_SMALL

12

R040810KOhm

R0407

NB_R0402_5MIL_SMALL

1 2

R0416 1.5KOhm

TP_SKTOCC#_R

TP_CATERR#_R

12

5%

R040356Ohm

10V240000028

12

H_PM_SYNC_R

12

H_CPUPWRGD_R

12

VDDPWRGOOD_R

R0409130Ohm

R2.1

BUF_CPU_RST#

12

R0417
750Ohm

R1.0 0119
Sandy Bridge:R0417 = 750 ohm (10V220000093)
Ivy Bridge:R0417 = 680 ohm (10V240000041)

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

ES1

4

J3

CLK_EXP_P_R

BCLK

H2

MISC THERMAL PWR MANAGEMENT

DPLL_REF_CLK

DPLL_REF_CLK#

BCLK_ITP

CLOCKS

BCLK_ITP#

BCLK#

AG3
AG1

N59
N58

CLK_EXP_N_R

CLK_DP_P_R
CLK_DP_N_R

+VCCP

3

12

R04220Ohm

12

R04230Ohm

R04251KOhm

@

@

R04261KOhm

CLK_XDP_ITP_P 21
CLK_XDP_ITP_N 21

12

R04280Ohm /eDP

12

R04290Ohm /eDP

CLK_EXP_P 21
CLK_EXP_N 21

CLK_DP_P 21
CLK_DP_N 21

for eDP functio n

2

+1.5VS_VCCDDQ

+3VS

+3VSUS

+VCCP

+3V

+1.5VS_VCCDDQ 7

+3VS 16, 17,20,21,22,23,24,25,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+3VSUS 22,24,27,28,30,33,53,56,81,92

+VCCP 3,6,7,26,27,30,32,82

+3V 24,40,53,55,57, 62,91

1

XDP_Debug

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#

PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AT30

BF44

SM_RCOMP_0

BE43

SM_RCOMP_1

BG43

SM_RCOMP_2

N53
N55

L56

TCK

L55

TMS

J58

M60

TDI

L59

TDO

K58

G58
E55
E59
G55
G59
H60
J59
J61

R0418 140Ohm
R0419 25.5Ohm
R0420 200Ohm

XDP_PREQ#

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI

1 2

1%

1 2

1%

1 2

1%

SM_DRAMRST#

DDR3

MISC

JTAG & BPM

CPUDRAMRST# 5

System Memory Impedance Compensation
Huron River platform Design Guide 436735 P.88 Table 37.

Huron River platform Design Guide Update 440484
SM_RCOMP_1 use 26ohm 1%

DDR3 DRAM RESET

R.10 PU/PD for JTAG signals

XDP_TMS
XDP_TDI
XDP_PREQ#

XDP_TCK
XDP_TRST#

1 2

R0438 51Ohm

1 2

R0439 51Ohm

1 2

R0440 51Ohm

@

1 2

R0441 51Ohm

1 2

R0442 51Ohm

+VCCP

PM_SYS_PWRGD is the power good for +1.5V_VCCD DQ

+1.5VS_VCCDDQ

12

R0449

200Ohm

1%

B B

PM_DRAM_PWRGD

A A

R0451

NB_R0402_5MIL_SMALL

5

1.57 Volt

12

12

R0450

1KOhm

1%

R2.1

12

@

R0452

1.1KOhm

1%

@

PM_PWROK 22,30,92

4

Different from EVEREST

If don't support S3 power reduction

1. Unmount U0404, D0404, C0413, C0420, R0450, R0452, R0453, R0460

2. Change R0449 to 200ohm from 1kohm, change R0409 to 130ohm from 0ohm - Design Guide 1.0 page 106

3. Unmount Q0501, C0501, R0506, R0504, R0507

4. Mount R0501, change r0508 to 0ohm from 1kohm

5 Unmount Q0701, R0703, R0705, Q0702

6. Mount R0702 and short JP0701

7. Unmount R2232, R2231, Q2203

C0401

12

R04610Ohm

@

3

D

1 2

@

Q0401
2N7002

1

THRO_CPU

G

S

2

2

THRO_CPU 30

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

VR_HOT#80

R1.0 0224
Intel Comments

3

H_PROCHOT#

47PF/50V

B34

B34

B34

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

CPU(2)_CLK,MISC,JTAG

CPU(2)_CLK,MISC,JTAG

CPU(2)_CLK,MISC,JTAG

Trunks Chen

Trunks Chen

Trunks Chen

of

of

of

4 59Wednesday, February 01, 2012

4 59Wednesday, February 01, 2012

4 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+DDR3

AP11

AR11

AT13
AU13

BA13
BB11

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37
BF36
BA28

BE39
BD39
AT41

U0301C

AG6

SA_DQ[0]

AJ6

SA_DQ[1]
SA_DQ[2]

AL6

SA_DQ[3]

AJ10

SA_DQ[4]

AJ8

SA_DQ[5]

AL8

SA_DQ[6]

AL7

SA_DQ[7]
SA_DQ[8]

AP6

SA_DQ[9]

AU6

SA_DQ[10]

AV9

SA_DQ[11]

AR6

SA_DQ[12]

AP8

SA_DQ[13]
SA_DQ[14]
SA_DQ[15]

BC7

SA_DQ[16]

BB7

SA_DQ[17]
SA_DQ[18]
SA_DQ[19]

BA7

SA_DQ[20]

BA9

SA_DQ[21]

BB9

SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AU36
AV36
AY26

AT40
AU40
BB26

BB40
BC41

AY40
BA41

AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55

AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54

BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DIM0_CLK_DDR0 16
M_A_DIM0_CLK_DDR#0 16
M_A_DIM0_CKE0 16

M_A_DIM0_CLK_DDR1 16
M_A_DIM0_CLK_DDR#1 16
M_A_DIM0_CKE1 16

M_A_DIM0_CS#0 16
M_A_DIM0_CS#1 16

M_A_DIM0_ODT0 16
M_A_DIM0_ODT1 16

M_A_DQS#[7:0] 16

M_A_DQS[7:0] 16

M_A_A[15:0] 16

M_B_DQ[63:0]17

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_BS017
M_B_BS117
M_B_BS217

M_B_CAS#17
M_B_RAS#17
M_B_WE#17

D D

C C

B B

M_A_DQ[63:0]16

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_BS016
M_A_BS116
M_A_BS216

M_A_CAS#16
M_A_RAS#16
M_A_WE#16

BD13
BF12

BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54

BA58
AW59
AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58

AG58

AG59

AM60

AL59

AF61

AH60

BG39

BD42

AT22

AV43

BF40

BD45

U0301D

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]
SB_DQ[18]
SB_DQ[19]

BF8

SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

BA34
AY34
AR22

BA36
BB36
BF27

BE41
BE47

AT43
BG47

AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59

AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61

BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DIM0_CLK_DDR0 17
M_B_DIM0_CLK_DDR#0 17
M_B_DIM0_CKE0 17

M_B_DIM0_CLK_DDR1 17
M_B_DIM0_CLK_DDR#1 17
M_B_DIM0_CKE1 17

M_B_DIM0_CS#0 17
M_B_DIM0_CS#1 17

M_B_DIM0_ODT0 17
M_B_DIM0_ODT1 17

+DDR3 7,16,17,18,57,83

M_B_DQS#[7:0] 17

M_B_DQS[7:0] 17

M_B_A[15:0] 17

ES1

01V010000003

ES1

01V010000003

R1.0 S3 circuit : DRAM_RST# to memory should b e high during S3

+DDR3

R0507

@

1KOhm

1 2

A A

DDR3_DRAMRST#16,17 CPUDRAMRST# 4

DRAMRST_CNTRL_PCH9,21

5

1 2

R0508 1KOhm

R0508 use 1k ohm
Design Guide 0.9 p107(436735)
Close to DIMM

R0504

1 2

NB_R0402_5MIL_SMALL

12

R05010Ohm

Q0501

2N7002

S

D

3

2

@

G

1

12

1%

4.99KOhm

12

C0501

@

0.1UF/10V

4

@

R0506

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

B34

B34

Date: Sheet

Date: Sheet

3

2

Date: Sheet

B34

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

CPU(3)_DDR3

CPU(3)_DDR3

CPU(3)_DDR3

Trunks Chen

Trunks Chen

Trunks Chen

of

of

of

5 59Wednesday, February 01, 2012

5 59Wednesday, February 01, 2012

5 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+VCCP

+VCORE

Vcc for process or core
Voltage range: 0.3 - 1.52V

U0301F

D D

+VCORE

A26

VCC74

A29

VCC73

A31

VCC72

A34

VCC71

A35

VCC70

A38

VCC69

A39

VCC68

A42

VCC67

C26

VCC66

C27

VCC65

C32

VCC64

C34

VCC63

C37

VCC62

C39

VCC61

C42

VCC60

D27

VCC59

D32

VCC58

D34

VCC57

D37

VCC56

D39

VCC55

D42

VCC54

E26

VCC53

E28

VCC52

E32

VCC51

E34

VCC50

E37

VCC49

E38

VCC48

F25

VCC47

F26

VCC46

F28

VCC45

F32

VCC44

F34

VCC43

F37

VCC42

C C

B B

F38

VCC41

F42

VCC40

G42

VCC39

H25

VCC38

H26

VCC37

H28

VCC36

H29

VCC35

H32

VCC34

H34

VCC33

H35

VCC32

H37

VCC31

H38

VCC30

H40

VCC29

J25

VCC28

J26

VCC27

J28

VCC26

J29

VCC25

J32

VCC24

J34

VCC23

J35

VCC22

J37

VCC21

J38

VCC20

J40

VCC19

J42

VCC18

K26

VCC17

K27

VCC16

K29

VCC15

K32

VCC14

K34

VCC13

K35

VCC12

K37

VCC11

K39

VCC10

K42

VCC9

L25

VCC8

L28

VCC7

L33

VCC6

L36

VCC5

L40

VCC4

N26

VCC3

N30

VCC2

N34

VCC1

N38

VCC0

CORE SUPPLY

PEG AND DDRSENSE LINES SVID QUIET RAILS

POWER

Voltage for the memory control ler and
shared cache de fined at the
motherboard VCC IO_SENSE and
VSS_SENSE_VCCIO

AF46

VCCIO34
VCCIO28
VCCIO27
VCCIO26
VCCIO23
VCCIO22
VCCIO21
VCCIO20
VCCIO19
VCCIO18
VCCIO17
VCCIO16
VCCIO15
VCCIO14
VCCIO13
VCCIO12
VCCIO11
VCCIO10

VCCIO9
VCCIO8
VCCIO7
VCCIO6
VCCIO5
VCCIO4
VCCIO3
VCCIO2
VCCIO1
VCCIO0

VCCIO47
VCCIO46
VCCIO45
VCCIO44
VCCIO43
VCCIO42
VCCIO41
VCCIO40
VCCIO39
VCCIO38
VCCIO37
VCCIO36
VCCIO35
VCCIO33
VCCIO32
VCCIO31
VCCIO30
VCCIO29
VCCIO25
VCCIO24

VCCIO49
VCCIO48

VCCIO_SEL

VCCPQE1
VCCPQE0

VIDALERT#

VIDSCLK

VIDSOUT

AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

AA14
AA15
AB17
AB20
AC13

remove 1UF C0612,C0615,C0608,C0624

AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

W16

+VCCIO_CPU_F

W17

BC22

VCCP_SEL

Filitered(BGA only)

AM25
AN22

12

C0622
1UF/6.3V

A44

H_CPU_SVIDALRT#

B43

H_CPU_SVIDCLK

C44

H_CPU_SVIDDAT

12

C0628
1UF/6.3V

12

C0610
1UF/6.3V

R0601

1 2

NB_R0603_32MIL_SMALL

1 2

R0613 0Ohm

Intel Comments

R0602

12

C0631
1UF/6.3V

12

C0609
1UF/6.3V

+VCCP

5%

1 2

43Ohm

+VCCP

12

R2.1

12

C0632
1UF/6.3V

12

C0606
1UF/6.3V

vx_c0603_small

+VCCP +3VA

12

12

12

@

C0635
1UF/6.3V

C0611
1UF/6.3V

C0618
10UF/6.3V

R0615
10KOhm

1 2

vx_c0603_small

vx_c0603_small

12

C0634

C0636

1UF/6.3V

1UF/6.3V

remove 1UF C0614,C0616,C0623,C0607

vx_c0603_small

12

12

C0619

C0621

10UF/6.3V

10UF/6.3V

vx_c0603_small

12

12

C0626

C0625

1UF/6.3V

1UF/6.3V

12

C0603
10UF/6.3V

vx_c0603_small

vx_c0603_small

12

C0602
10UF/6.3V

VCCIO_SEL

12

12

12

12

H

L

C0637
1UF/6.3V

vx_c0603_small

C0620
10UF/6.3V

C0627
1UF/6.3V

C0605
10UF/6.3V

vx_c0603_small

12

12

12

12

C0613
1UF/6.3V

C0617
10UF/6.3V

C0629
1UF/6.3V

vx_c0603_small

C0604
10UF/6.3V

VCCSA

12

12

1.05V

1.00V

C0630
1UF/6.3V

C0601
10UF/6.3V

Chief River

Decoupling guide from Intel (EE)
+VCCP 1uF * 18pcs

10uF * 10pcs
220uF *1pcs

+VCCP

12

C0633
1UF/6.3V

12

+

CE0603
330UF/2.5V

change size 352 8 2mm (08/12)

Cheif River

+VCCP +VCCP +VCCP +VCCP

Close to CPU

12

R0603
75Ohm

1%

VR_SVID_ALERT# 80

Close to VR

SP0601

1 2

1 2

R0605

54.9Ohm

1%

Close to CPU Close to VR

VR_SVID_CLK 80

R0607
130Ohm

1%

1 2

SP0602

1 2

+VCCP 3,4,7,26,27,30,32,82

+VCORE 9,11,80

R0608
130Ohm

1%

1 2

VR_SVID_DATA 80

SP0603

F43

VCC_SENSE

VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

ES1

A A

01V010000003

5

VCC_SENSE_R VCCSENSE

G43

VSS_SENSE_R

SP0605

AN16
AN17

VCCP_SENSE_R
VSSP_SENSE_R

NB_R0402_20MIL_SMALL

1 2
1 2

SP0606

NB_R0402_20MIL_SMALL

4

NB_R0402_20MIL_SMALL

1 2
1 2

SP0604

NB_R0402_20MIL_SMALL

+VCCP_SENSE
+VSSP_SENSE

VSSSENSE

+VCCP_SENSE 82
+VSSP_SENSE 82

VCCSENSE 80
VSSSENSE 80

Title :

Title :

Title :

CPU(4)_PWR

CPU(4)_PWR

CPU(4)_PWR

Trunks Chen

Trunks Chen

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

3

2

Date: Sheet

Trunks Chen

6 59Wednesday, February 01, 2012

6 59Wednesday, February 01, 2012

6 59Wednesday, February 01, 2012

of

of

of

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

Decoupling guide from Intel PDDG R0.8

+VGFX_CORE
1uF * 11pcs
10uF * 6pcs
22uF * 6pcs

+VGFX_CORE

D D

12

12

12

12

C C

B B

A A

C0727

C0725

1UF/6.3V

1UF/6.3V

12

C0719

C0717

1UF/6.3V

1UF/6.3V

vx_c0603_small

12

C0739

C0738

22UF/6.3V

22UF/6.3V

VCCGT_SENSE80

VSSGT_SENSE80

PLL supply volt age
(DC + AC specif ication)

12

12

12

12

12

C0731
1UF/6.3V

C0722
1UF/6.3V

C0790
10UF/6.3V

C0740
22UF/6.3V

12

vx_c0603_small

12

C0726
1UF/6.3V

C0791
10UF/6.3V

C0741
22UF/6.3V

change size fro m 0805 power request

+VCCSA

vx_c0603_small

5

12

12

Decoupling guide for A14 (EE)

+VCCSA
1uF * 5pcs
10uF * 5pcs

Graphics core v oltage
Voltage range: 0 - 1.52V

12

vx_c0603_small

VCCGT_SENSE
VSSGT_SENSE

+1.8VS

C0783
10UF/6.3V

vx_c0603_small

C0735
1UF/6.3V

12

12

12

C0729

C0732

1UF/6.3V

1UF/6.3V

12

C0788

C0789

10UF/6.3V

10UF/6.3V

vx_c0603_small

12

C0742
22UF/6.3V

SP0706

NB_R0402_20MIL_SMALL

SP0707

NB_R0402_20MIL_SMALL

CE0701
330UF/2V

vx_c0603_small

12

12

C0781
10UF/6.3V

12

12

C0736
1UF/6.3V

C0743
22UF/6.3V

12
12

C0792
10UF/6.3V

C0733
1UF/6.3V

12

C0730
1UF/6.3V

vx_c0603_small

12

C0787
10UF/6.3V

VCCGT_SENSE_R
VSSGT_SENSE_R

12

C0761
1UF/6.3V

12

vx_c0603_small

12

vx_c0603_small

12

vx_c0603_small

C0777
10UF/6.3V

C0734
1UF/6.3V

+

12

C0728
1UF/6.3V

12

C0786
10UF/6.3V

CE0703
330UF/2.5V

12

12

12

MAX:1.2A
TDC: 1.2A

C0764
1UF/6.3V

MAX:6A

C0793
10UF/6.3V

C0737
1UF/6.3V

4

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46

N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58

V59
W50
W51
W52
W53
W55
W56
W61

Y48

Y61

F45

G45

BB3

BC1

BC4

L17

L21

N16

N20

N22

P17

P20

R16

R18

R21

U15

V16

V17

V18

V21
W20

U0301G

VAXG21
VAXG20
VAXG19
VAXG18
VAXG17
VAXG16
VAXG15
VAXG14
VAXG13
VAXG12
VAXG11
VAXG10
VAXG9
VAXG8
VAXG7
VAXG6
VAXG5
VAXG4
VAXG3
VAXG2
VAXG1
VAXG0
VAXG55
VAXG54
VAXG53
VAXG52
VAXG51
VAXG50
VAXG49
VAXG48
VAXG47
VAXG46
VAXG45
VAXG44
VAXG43
VAXG42
VAXG41
VAXG40
VAXG39
VAXG38
VAXG37
VAXG36
VAXG35
VAXG34
VAXG33
VAXG32
VAXG31
VAXG30
VAXG29
VAXG28
VAXG27
VAXG26
VAXG25
VAXG24
VAXG23
VAXG22

VAXG_SENSE
VSSAXG_SENSE

VCCPLL2
VCCPLL1
VCCPLL0

VCCSA15
VCCSA14
VCCSA13
VCCSA12
VCCSA11
VCCSA10
VCCSA9
VCCSA8
VCCSA7
VCCSA6
VCCSA5
VCCSA4
VCCSA3
VCCSA2
VCCSA1
VCCSA0

ES1

01V010000003

DDR3 Reference Voltage

+V_SM_REF 10mil

+V_SM_VREF

AY43

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

+V_SM_VREF

vx_c0603_small

vx_c0603_small

SM_VREF

VDDQ25
VDDQ24
VDDQ23
VDDQ22
VDDQ21
VDDQ20
VDDQ19
VDDQ18
VDDQ17
VDDQ16
VDDQ15
VDDQ14
VDDQ13
VDDQ12
VDDQ11
VDDQ10

VDDQ9
VDDQ8
VDDQ7
VDDQ6
VDDQ5
VDDQ4

DDR3 - 1.5V RAILS

POWER

GRAPHICS

VDDQ3
VDDQ2
VDDQ1
VDDQ0

pull high in p.18

12

C0794

0.1UF/16V @

MAX:10A

12

12

C0704
1UF/6.3V

12

C0775
10UF/6.3V

Chief River

Decoupling guide from Intel (EE)

+1.5VS_VCCDDQ
1uF * 10pcs
10uF * 8pcs
330uF * 1pcs

C0709
1UF/6.3V

12

vx_c0603_small

C0774
10UF/6.3V

12

C0705
1UF/6.3V

vx_c0603_small

12

C0772
10UF/6.3V

12

C0706
1UF/6.3V

12

vx_c0603_small

12

C0769
10UF/6.3V

C0707
1UF/6.3V

vx_c0603_small

12

12

C0767
10UF/6.3V

C0708
1UF/6.3V

Filtered(BGA On ly)

+1.5VS_VCCDDQ

1 2

R0707 0Ohm

12

C0714
1UF/6.3V

SENSE

LINES

1.8V RAIL

QUIET RAILS

VSS_SENSE_VDDQ

VCCDQ1
VCCDQ0

VDDQ_SENSE

AM28
AN26

BC43
BA43

1

T0701

1

T0702

SA RAIL

VCCSA_VID[0]
VCCSA_VID[1]

U10

D48
D49

R0704 0Ohm

VCCSA_SEL0
VCCSA_SEL1

1 2

@

VCCSA_SENSE 85

Close to CPU

VCCSA_SEL0 85
VCCSA_SEL1 85

+VCCSA_SEL0 +VCCSA_SEL1

L

L

H

SENSE LINES

VCCSA_SENSE

Chief River

3

2

12

12

vx_c0603_small

+VCCP

+VCCSA

+1.8VS

+VGFX_CORE

+1.5VS

+V_SM_VREF

C0713
1UF/6.3V

vx_c0603_small

C0765
10UF/6.3V

L

H

L

+DDR3

12

12

C0710
1UF/6.3V

C0770
10UF/6.3V

VCCSA

0.9V

0.85V

0.725V

0.675VH H

+VCCP 3,4,6,26,27,30,32,82

+DDR3 5,16,17,18,57,83

+VCCSA 85

+1.8VS 25,26,80,84

+VGFX_CORE 9,80

+1.5VS 26,53,57,91

+V_SM_VREF 18,83

+1.5VS_VCCDDQ +DDR3

12

12

C0712

C0711

1UF/6.3V

12

C0768
10UF/6.3V

vx_c0603_small

>100 ns

change short pin footprint

1UF/6.3V

CE0702
330UF/2V

> 0 SUSB_EC#

R1.0 0209
Intel Comments

VCCSA_SEL0

VCCSA_SEL1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

Processor I/O supply
voltage for DDR3
(DC + AC specification)

JP0701

2

112

ICCMAX_VDDQ 5A

3MM_OPEN_5MIL

+1.5V_VCCDDQ

+1.5V_VCCDDQ Power Good
(U0404 pin 4)

+0.75VS

+VCCP

R0708
1KOhm

@

1 2

1 2

R0701
1KOhm

1 2

1 2

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

B34

B34

B34

1

R0709
1KOhm

@

R0702
1KOhm

CPU(5)_GFX_PWR

CPU(5)_GFX_PWR

CPU(5)_GFX_PWR

Trunks Chen

Trunks Chen

Trunks Chen

of

of

of

7 59Wednesday, February 01, 2012

7 59Wednesday, February 01, 2012

7 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

D D

4

3

2

1

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53

BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35

D40
D43
D46
D50
D54
D58

G48
G51

G61
H10
H14
H17
H21

H53
H58

M11
M15

D4

D6
E25
E29

E3
E35
E40
F13
F15
F19
F29
F35
F40
F55

G6

H4

J1
J49
J55
K11
K21
K51

K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

U0301I

VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
VSS10
VSS288
VSS287
VSS286
VSS283
VSS282
VSS281
VSS280
VSS279
VSS278
VSS277
VSS285
VSS276
VSS275
VSS274
VSS273
VSS272
VSS271
VSS284
VSS269
VSS268
VSS270
VSS267
VSS266
VSS265
VSS264
VSS263
VSS262
VSS261
VSS260
VSS259
VSS257
VSS256
VSS258
VSS255
VSS253
VSS252
VSS251
VSS250
VSS254
VSS249
VSS248
VSS247
VSS246
VSS245
VSS243
VSS242
VSS241
VSS244
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS228
VSS227

ES1

01V010000003

VSS

NCTF

VSS230
VSS226
VSS229
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS210
VSS202
VSS201
VSS203
VSS200
VSS199
VSS198
VSS197
VSS196
VSS195
VSS194
VSS193
VSS192
VSS190
VSS191
VSS189
VSS188
VSS186
VSS185
VSS184
VSS183
VSS182
VSS187
VSS181
VSS180
VSS179
VSS178

VSS_NCTF13
VSS_NCTF12

VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1

VSS_NCTF0
VSS_NCTF11
VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

BGA only
All NCTF pins should be test points
and should be routed as trace.

U0301H

A13

VSS299

A17

VSS298

A21

VSS297

A25

VSS296

A28

VSS295

A33

VSS294

A37

VSS293

A40

VSS292

A45

VSS291

A49

VSS290

A53

VSS289

A9

VSS300

AA1

VSS177

AA13

VSS175

AA50

VSS174

AA51

VSS173

AA52

VSS172

AA53

VSS171

AA55

VSS170

AA56

VSS169

AA8

VSS176

AB16

VSS168

AB18

VSS167

AB21

VSS166

AB48

VSS165

AB61

VSS164

C C

B B

AC10
AC14
AC46

AD17
AD20

AD61
AE13

AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AH58

AK52

AM13
AM20
AM22
AM26
AM30
AM34

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61

VSS162
VSS161
VSS160

AC6

VSS163
VSS158
VSS157

AD4

VSS159
VSS156
VSS154

AE8

VSS155

AF1

VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134

AG7

VSS140

AH4

VSS133
VSS132
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120

AJ7

VSS131

AK1

VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99

VSS

VSS98

VSS105

VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS81
VSS80
VSS79
VSS82
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS78
VSS70
VSS69
VSS68
VSS71
VSS67
VSS66
VSS65
VSS64
VSS62
VSS61
VSS60
VSS59
VSS63
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS50
VSS49
VSS48
VSS51
VSS45
VSS44
VSS43
VSS42
VSS47
VSS41
VSS40
VSS39
VSS38
VSS37
VSS46
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS26
VSS27
VSS25
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS24
VSS11

VSS9

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

ES1

01V010000003

A A

Title :

Title :

Title :

CPU(6)_GND

CPU(6)_GND

CPU(6)_GND

Trunks Chen

Trunks Chen

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Trunks Chen

of

of

of

8 59Wednesday, February 01, 2012

8 59Wednesday, February 01, 2012

8 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

CFG strapping information:

CFG[2]: PCIE Static Numbering Lane Reversal- CFG[2] is for the 16x

- 1: (Default) Normal Operation, Lane # definition matches sockect pin map definition

- 0: Lane Numbers Reversed

D D

CFG[4]: Embedded DisplayPort Detection

- 1: (Default) Disabled ; No Physical Display Port attached to Embedded DisplayPort

- 0: Enabled ; An external Display Port device is connected to the Embedded Display Port

CFG[6:5]: PCI Express Port Bifurcation Straps

- 11 : (Default) x 1 6

- 10 : x 8 , x 8

- 01 : Reserved

- 00 : x 8 , x 4 , x 4

CFG[7]: PEG DEFER TRAINING

- 1: (Default) PEG Train immediately following xxRESETB de assertion

- 0: PEG Wait for BIOS training

CFG2

C C

CFG4

CFG5

CFG6

CFG7

1 2

1%

R0902 1KOhm

1 2

1%

R0903 1KOhm

@

1 2

1%

R0904 1KOhm

@

1 2

1%

R0905 1KOhm@

1 2

1%

R0906 1KOhm@

4

3

T0913
T0914

T0915
T0916

T0917

1

VCC_VAL_SENSE

1

VSS_VAL_SENSE

1

VAXG_VAL_SENSE

1

VSSAXG_VAL_SENSE

1

VCCAXG_VAL_SENSE

CFG2

CFG4
CFG5
CFG6
CFG7

U0301E

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD39

K48

RSVD37

BA19

RSVD15

AV19

RSVD18

AT21

RSVD22

BB21

RSVD12

BB19

RSVD13

AY21

RSVD17

BA22

RSVD14

AY22

RSVD16

AU19

RSVD20

AU21

RSVD19

BD21

RSVD11

BD22

RSVD10

BD25

RSVD9

BD26

RSVD8

BG22

RSVD1

BE22

RSVD6

BG26

RSVD0

BE26

RSVD4

BF23

RSVD3

BE24

RSVD5

2

1

Chief River

BE7
BG7

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1

DDR_WR_VREF01
DDR_WR_VREF02

RESERVED

RSVD7
RSVD2

RSVD31
RSVD36
RSVD35
RSVD34

RSVD33
RSVD32
RSVD28
RSVD27
RSVD29

RSVD21
RSVD38

RSVD25
RSVD26
RSVD24
RSVD23

RSVD30

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61

DC_TEST_BD61

DC_TEST_BE61

DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1

ES1

01V010000003

PROCESSOR DRIVEN Vref PATH WAS STUFFED BY DEFAULT:

1 2

B B

DDR_WR_VREF01

DRAMRST_CNTRL_PCH5,9,21

DDR_WR_VREF02

A A

DRAMRST_CNTRL_PCH5,9,21

5

R0907 0Ohm

Q0901A

@

UM6K1N

1%

12

2

R0909

1KOhm

1 2

R0910 0Ohm

Q0901B

@

UM6K1N

1%

12

5

R0911

1KOhm

4

61

34

DIMM0_VREF_DQ 18

DIMM1_VREF_DQ 18

3

For iFDIM testing
R0912~ R0917 close to pin < 1 inch

+VCORE+VGFX_CORE

12

R0912

@

49.9Ohm

1%

VAXG_VAL_SENSE VCC_VAL_SENSE

R0913

@

100Ohm

1%

1 2

VSSAXG_VAL_SENSE VSS_VAL_SENSE

12

R0914

@

49.9Ohm

1%

2

@

@

@

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

12

1 2

12

R0915

49.9Ohm

1%

R0916
100Ohm

1%

R0917

49.9Ohm

1%

R1.1 0512

B34

B34

B34

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

CPU(7)_RSVD

CPU(7)_RSVD

CPU(7)_RSVD

Trunks Chen

Trunks Chen

Trunks Chen

of

9 59Wednesday, February 01, 2012

of

9 59Wednesday, February 01, 2012

of

9 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+VTT_PCH_ORG

+3VSUS

+VCCP

+3VS

D D

+VTT_PCH_ORG 22,26,27

+3VSUS 22,24,27,28,30,33,53,56,81,92

+VCCP 3,4,6,7,26,27,30,32,82

+3VS 16,17,20,21,22,23,24,25,26,27,28,30,31,32,33,38,44,45,46 ,48,50,51,53,56,57,62,66,80,85,91,92

remove XDP connector

C C

Check Connector

CPU XDP connector

PCH XDP connector

B B

A A

Title :

Title :

Title :

Engineer:

Engineer:

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

B

B

B

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

B34

B34

B34

Engineer:

CPU_PCH_XDP

CPU_PCH_XDP

CPU_PCH_XDP

Trunks Chen

Trunks Chen

Trunks Chen

1

Rev

Rev

Rev

1.0

1.0

10 59Wednesday, February 01, 2012

10 59Wednesday, February 01, 2012

10 59Wednesday, February 01, 2012

1.0

of

of

of

5

4

3

2

1

D D

Chief River

Decoupling guide from Intel PDDG R0.8

+VCORE 2.2uF * 16 pcs
22uF * 12 pcs

C C

B B

+VCORE

vx_c0402_small

12

C1101

2.2UF/6.3V

vx_c0402_small

12

C1111

2.2UF/6.3V

12

C1136
22UF/6.3V

12

C1144
22UF/6.3V

12

C1102

2.2UF/6.3V

vx_c0402_small

12

C1112

2.2UF/6.3V

vx_c0402_small

12

12

vx_c0402_small

12

C1103

2.2UF/6.3V

vx_c0402_small

vx_c0402_small

12

C1113

2.2UF/6.3V

vx_c0402_small

C1137
22UF/6.3V

C1145
22UF/6.3V

12

C1104

2.2UF/6.3V

12

C1114

2.2UF/6.3V

12

C1138
22UF/6.3V

12

C1146
22UF/6.3V

vx_c0402_small

12

C1105

2.2UF/6.3V

vx_c0402_small

vx_c0402_small

12

C1115

2.2UF/6.3V

vx_c0402_small

12

C1139
22UF/6.3V

12

C1147
22UF/6.3V

vx_c0402_small

12

C1106

2.2UF/6.3V

12

C1117

2.2UF/6.3V

12

C1140
22UF/6.3V

12

C1107

2.2UF/6.3V

vx_c0402_small

vx_c0402_small

12

C1108

2.2UF/6.3V

12

C1141
22UF/6.3V

12

C1109

2.2UF/6.3V

vx_c0402_small

12

12

C1110

2.2UF/6.3V

C1142
22UF/6.3V

12

C1143
22UF/6.3V

A A

Title :

Title :

Title :

Engineer:

Engineer:

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

B

B

B

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

B34

B34

B34

Engineer:

CPU DECOUPLING

CPU DECOUPLING

CPU DECOUPLING

Trunks Chen

Trunks Chen

Trunks Chen

11 59Wednesday, February 01, 2012

11 59Wednesday, February 01, 2012

11 59Wednesday, February 01, 2012

1

Rev

Rev

Rev

1.0

1.0

1.0

of

of

of

5

+DDR3

+0.75VS

+3VS

+V_VREF_CA_DIMM0

+V_VREF_DQ_DIMM0

D D

+DDR3 5,7,17,18,57,83

+0.75VS 17,57,83

+3VS 17,20,21,22,23,24,25,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+V_VREF_CA_DIMM0 17,18

+V_VREF_DQ_DIMM0 18

4

+DDR3

12

+

CE1603
220UF/4V

@

3

+DDR3

Layout Note: Place these caps near SO DIMM 0

12

C1610
10UF/6.3V

vx_c0603_small

12

C1611
10UF/6.3V

vx_c0603_small

vx_c0603_small

12

C1609
10UF/6.3V

vx_c0603_small

12

C1612
10UF/6.3V

@

2

vx_c0603_small

12

C1613
10UF/6.3V

@

12

C1620
10UF/6.3V

@

vx_c0603_small

+0.75VS

12

C1616
1UF/6.3V

12

C1617
1UF/6.3V

12

1

C1618
1UF/6.3V

@

12

C1619
1UF/6.3V

@

M_A_DIM0_CLK_DDR0

M_A_DIM0_CLK_DDR#0

M_A_DIM0_CLK_DDR1

M_A_DIM0_CLK_DDR#1

12

12

C1602
10PF/50V

@

C1601
10PF/50V

@

12

12

1%

150Ohm
R1603

@

1%

150Ohm
R1604

@

PLACE CLOSE TO SODIMM

C C

B B

M_A_DQS[7:0]5

M_A_DQS#[7:0]5

A A

M_A_DIM0_CLK_DDR15

M_A_DIM0_CLK_DDR#15

M_A_DIM0_CLK_DDR05

M_A_DIM0_CLK_DDR#05

M_A_DIM0_CS#15
M_A_DIM0_CS#05

M_A_DIM0_ODT15
M_A_DIM0_ODT05

M_A_DIM0_CKE15
M_A_DIM0_CKE05

SMBus Slave Address: A0H

DM should connect to GND directly
Design Guide 0.9 p86 (436735)

SMB_CLK_S17,28,31,53
SMB_DAT_S17,28,31,53

M_A_A[15:0]5

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_WE#5
M_A_RAS#5
M_A_CAS#5

M_A_BS25
M_A_BS15
M_A_BS05

1 2

R1601 10KOhm

1 2

R1602 10KOhm

M_A_DQS7
M_A_DQS#7
M_A_DQS6
M_A_DQS#6
M_A_DQS5
M_A_DQS#5
M_A_DQS4
M_A_DQS#4
M_A_DQS3
M_A_DQS#3
M_A_DQS2
M_A_DQS#2
M_A_DQS1
M_A_DQS#1
M_A_DQS0
M_A_DQS#0

M_A_DM7
M_A_DM6
M_A_DM5
M_A_DM4
M_A_DM3
M_A_DM2
M_A_DM1
M_A_DM0

J1601A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM_204P

0

1

2

3

4

5

6

7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

RESET#

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

30

M_A_DQ0
M_A_DQ1
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ2
M_A_DQ3

M_A_DQ7
M_A_DQ13
M_A_DQ8
M_A_DQ10
M_A_DQ14
M_A_DQ9
M_A_DQ12
M_A_DQ15
M_A_DQ11

M_A_DQ16

M_A_DQ21

M_A_DQ23

M_A_DQ18

M_A_DQ20

M_A_DQ17

M_A_DQ22

M_A_DQ19
M_A_DQ29
M_A_DQ24
M_A_DQ26
M_A_DQ31
M_A_DQ30
M_A_DQ28
M_A_DQ25
M_A_DQ27

M_A_DQ39

M_A_DQ37

M_A_DQ33

M_A_DQ35

M_A_DQ32

M_A_DQ36

M_A_DQ38

M_A_DQ34
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ42
M_A_DQ40
M_A_DQ44
M_A_DQ41
M_A_DQ43

M_A_DQ53

M_A_DQ49

M_A_DQ55

M_A_DQ50

M_A_DQ52

M_A_DQ48

M_A_DQ51

M_A_DQ54
M_A_DQ58
M_A_DQ62
M_A_DQ57
M_A_DQ61
M_A_DQ63
M_A_DQ56
M_A_DQ60
M_A_DQ59

0~7

8~15

16~23

24~31

32~39

40~47

48~55

56~63

DDR3_DRAMRST# 5,17

12V02GBRM000

M:1202-00EE000
S:1202-00KB000

5

4

M_A_DQ[63:0] 5

3

MAX: 2.68A

+DDR3

TDC: 2.68A

12

12

C1605

0.1UF/10V

C1606

0.1UF/10V

Layout Note: Place these caps near SO DIMM 0

1

PM_EXTTS#0_DIM_A

T1601

Reserve

+V_VREF_CA_DIMM0

vx_c0402_small

+V_VREF_DQ_DIMM0

vx_c0402_small

12

C1624

2.2UF/6.3V

@

12

C1622

2.2UF/6.3V

@

W/S=20/20

12

C1623

0.1UF/10V

W/S=20/20

12

C1625

0.1UF/10V

2

J1601B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM_204P

12V02GBRM000

+DDR3

76

VDD2

82

VDD4

88

VDD6

94

VDD8

100

VDD10

106

VDD12

112

VDD14

118

VDD16

124

VDD18

3

VSS2

9

VSS4

14

VSS6

20

VSS8

26

VSS10

32

VSS12

38

VSS14

44

VSS16

49

VSS18

55

VSS20

61

VSS22

66

VSS24

72

VSS26

128

VSS28

134

VSS30

139

VSS32

145

VSS34

151

VSS36

156

VSS38

162

VSS40

168

VSS42

173

VSS44

179

VSS46

185

VSS48

190

VSS50

196

VSS52

207

GND1

208

GND2

205

NP_NC1

206

NP_NC2

203

VTT1

204

VTT2

199

VDDSPD

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

B34

B34

B34

12

MAX: 0.75A
TDC: 0.75A

+0.75VS

C1615

0.1UF/10V

12

C1607

0.1UF/10V

+3VS

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

12

C1608

0.1UF/10V

12

C1614

vx_c0402_small

2.2UF/6.3V

@

DDR3(1)_SO-DIMM0

DDR3(1)_SO-DIMM0

DDR3(1)_SO-DIMM0

Trunks Chen

Trunks Chen

Trunks Chen

16 59Wednesday, February 01, 2012

16 59Wednesday, February 01, 2012

16 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+DDR3

+0.75VS

+3VS

+V_VREF _CA_DIMM1

+V_VREF _DQ_DIMM1

D D

M_B_DIM0_ CLK_DDR0

M_B_DIM0_ CLK_DDR#0

M_B_DIM0_ CLK_DDR1

M_B_DIM0_ CLK_DDR#1

PLACE CLOSE TO SODIMM

C C

B B

A A

+DDR3 5,7 ,16,18,57,83

+0.75VS 16,57,83

+3VS 16,2 0,21,22,23,24,25,26 ,27,28,30,31,32,33 ,38,44,45,46,48,50 ,51,53,56,57,62,66,8 0,85,91,92

+V_VREF _CA_DIMM1 16 ,18

+V_VREF _DQ_DIMM1 18

M_B_A[15 :0]5

M_B_A0

10KOhm
10KOhm

M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

34
12

M_B_DQS 7
M_B_DQS #7
M_B_DQS 6
M_B_DQS #6
M_B_DQS 5
M_B_DQS #5
M_B_DQS 4
M_B_DQS #4
M_B_DQS 3
M_B_DQS #3
M_B_DQS 2
M_B_DQS #2
M_B_DQS 1
M_B_DQS #1
M_B_DQS 0
M_B_DQS #0

M_B_DM7
M_B_DM6
M_B_DM5
M_B_DM4
M_B_DM3
M_B_DM2
M_B_DM1
M_B_DM0

4

12

C1720
10PF/50V

@

C1721
10PF/50V

@

12

1%

150Ohm
R1707

@

1%

150Ohm
R1708

@

12

12

SMBus Slave Address: A4H

M_B_DQS [7:0]5

M_B_DQS #[7:0]5

5

M_B_DIM0_ CLK_DDR15

M_B_DIM0_ CLK_DDR#15

M_B_DIM0_ CLK_DDR05

M_B_DIM0_ CLK_DDR#05

M_B_DIM0_ CS#15
M_B_DIM0_ CS#05

M_B_DIM0_ ODT15
M_B_DIM0_ ODT05

M_B_W E#5
M_B_RAS #5
M_B_CAS #5

M_B_BS25
M_B_BS15
M_B_BS05

M_B_DIM0_ CKE15
M_B_DIM0_ CKE05

RN1701B

+3VS

RN1701A

DM should connect to GND directly
Design Guide 1.0 P.88 (436735)

SMB_CLK _S16,28,3 1,53
SMB_DAT _S16,28,31,5 3

J1701A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

102

CK1

104

CK1#

101

CK0

103

CK0#

121

S1#

114

S0#

120

ODT1

116

ODT0

113

WE#

110

RAS#

115

CAS#

79

BA2

108

BA1

109

BA0

74

CKE1

73

CKE0

201

SA1

197

SA0

188

DQS7

186

DQS#7

171

DQS6

169

DQS#6

154

DQS5

152

DQS#5

137

DQS4

135

DQS#4

64

DQS3

62

DQS#3

47

DQS2

45

DQS#2

29

DQS1

27

DQS#1

12

DQS0

10

DQS#0

187

DM7

170

DM6

153

DM5

136

DM4

63

DM3

46

DM2

28

DM1

11

DM0

202

SCL

200

SDA

DDR3_DIMM _204P

0

1

2

3

4

5

6

7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

RESET#

12V02GWSM000

H:5.2mm

12

+

CE1703
220UF/4V

@

5

M_B_DQ0

7

M_B_DQ4

15

M_B_DQ2

17

M_B_DQ6

4

M_B_DQ5

6

M_B_DQ1

16

M_B_DQ3

18

M_B_DQ7

21

M_B_DQ1 2

23

M_B_DQ8

33

M_B_DQ1 0

35

M_B_DQ1 4

22

M_B_DQ1 3

24

M_B_DQ9

34

M_B_DQ1 1

36

M_B_DQ1 5

39

M_B_DQ2 0

41

M_B_DQ1 6

51

M_B_DQ1 8

53

M_B_DQ1 9

40

M_B_DQ2 2

42

M_B_DQ2 3

50

M_B_DQ1 7

52

M_B_DQ2 1

57

M_B_DQ2 8

59

M_B_DQ2 9

67

M_B_DQ3 1

69

M_B_DQ2 7

56

M_B_DQ2 4

58

M_B_DQ2 5

68

M_B_DQ2 6

70

M_B_DQ3 0

129

M_B_DQ3 7

131

M_B_DQ3 3

141

M_B_DQ3 4

143

M_B_DQ3 8

130

M_B_DQ3 6

132

M_B_DQ3 2

140

M_B_DQ3 9

142

M_B_DQ3 5

147

M_B_DQ4 1

149

M_B_DQ4 2

157

M_B_DQ4 6

159

M_B_DQ4 5

146

M_B_DQ4 0

148

M_B_DQ4 4

158

M_B_DQ4 3

160

M_B_DQ4 7

163

M_B_DQ5 3

165

M_B_DQ4 9

175

M_B_DQ5 0

177

M_B_DQ5 1

164

M_B_DQ4 8

166

M_B_DQ5 2

174

M_B_DQ5 4

176

M_B_DQ5 5

181

M_B_DQ5 6

183

M_B_DQ6 3

191

M_B_DQ5 8

193

M_B_DQ6 2

180

M_B_DQ6 1

182

M_B_DQ6 0

192

M_B_DQ5 9

194

M_B_DQ5 7

30

DDR3_DR AMRST# 5 ,16

M:1202-00FG000
S:1202-00K8000

0~7

8~15

16~23

24~31

32~39

40~47

48~55

56~63

Layout Note: Place these caps near SO DIMM 1

12

C1709
22UF/6.3V

M_B_DQ[6 3:0] 5

12

C1710
22UF/6.3V

12

+DDR3

C1711
22UF/6.3V

12

C1705

0.1UF/10V

12

C1712
22UF/6.3V

@

12

C1706

0.1UF/10V

Layout Note: Place these caps near SO DIMM 1

1

T1701

Reserve

+V_VREF _CA_DIMM1

vx_c0402_small

+V_VREF _DQ_DIMM1

vx_c0402_small

3

PM_EXTT S#0_DIM_B

12

C1724

2.2UF/6.3V

@

12

C1722

2.2UF/6.3V

@

W/S=20/20

W/S=20/20

12

C1723

0.1UF/10V

12

C1725

0.1UF/10V

12

C1713
22UF/6.3V

@

2

12

C1726
22UF/6.3V

@

J1701B

75

VDD1

81

VDD3

87

VDD5

93

VDD7

99

VDD9

105

VDD11

111

VDD13

117

VDD15

123

VDD17

2

VSS1

8

VSS3

13

VSS5

19

VSS7

25

VSS9

31

VSS11

37

VSS13

43

VSS15

48

VSS17

54

VSS19

60

VSS21

65

VSS23

71

VSS25

127

VSS27

133

VSS29

138

VSS31

144

VSS33

150

VSS35

155

VSS37

161

VSS39

167

VSS41

172

VSS43

178

VSS45

184

VSS47

189

VSS49

195

VSS51

198

EVENT#

125

TEST

77

NC1

122

NC2

126

VREFCA

1

VREFDQ

DDR3_DIMM _204P

12V02GW SM000

+0.75VS+DDR3+DDR3

12

76

VDD2

82

VDD4

88

VDD6

94

VDD8

100

VDD10

106

VDD12

112

VDD14

118

VDD16

124

VDD18

3

VSS2

9

VSS4

14

VSS6

20

VSS8

26

VSS10

32

VSS12

38

VSS14

44

VSS16

49

VSS18

55

VSS20

61

VSS22

66

VSS24

72

VSS26

128

VSS28

134

VSS30

139

VSS32

145

VSS34

151

VSS36

156

VSS38

162

VSS40

168

VSS42

173

VSS44

179

VSS46

185

VSS48

190

VSS50

196

VSS52

207

GND1

208

GND2

205

NP_NC1

206

NP_NC2

203

VTT1

204

VTT2

199

VDDSPD

BG1\HW 1

BG1\HW 1

BG1\HW 1

Size Proj ect Name

Size Proj ect Name

Size Proj ect Name

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

C1716
1UF/6.3V

12

12

+0.75VS

B34

B34

B34

C1717
1UF/6.3V

C1707

0.1UF/10V

12

C1715

0.1UF/10V

12

12

C1718
1UF/6.3V

@

+DDR3

C1708

0.1UF/10V

+3VS

12

C1714

2.2UF/6.3V

@

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

12

C1719
1UF/6.3V

@

vx_c0402_small

DDR3(2)_SO-DIMM1

DDR3(2)_SO-DIMM1

DDR3(2)_SO-DIMM1

Trunks Chen

Trunks Chen

Trunks Chen

of

of

of

17 98Wednesd ay, February 01, 2012

17 98Wednesd ay, February 01, 2012

17 98Wednesd ay, February 01, 2012

Rev

Rev

Rev

2.1

2.1

2.1

5

4

3

2

1

DDR3 Vref

D D

+V_VREF_CA_DIMM0

+V_VREF_DQ_DIMM0

M1: Fixed SO-DIMM VREF_DQ

C C

12

C1804

0.1UF/16V

vx_c0603_small

@

+DDR3

+V_SM_VREF

+DDR3 +V_VREF_DDR3

12

C1803

0.1UF/16V

M1Default

B B

+DDR3 5,7,16 ,17,57,83

+V_VREF_CA_DIMM0 16,17

+V_VREF_DQ_DIMM0 16

+V_SM_VREF 7,83

R1811
1KOhm

1 2

12

R1813
1KOhm

+3V

+5VSUS

+5VA

R1807 0Ohm

R1808 0Ohm

+3V 24 ,40,53,55,57,62,91

+5VSUS 27,52,81,91

+5VA 50,52,56,81

1 2

SP1803 R0402

1 2

1 2

For DDR3_VREF command & address.

+V_VREF_CA_DIMM0

+V_SM_VREF

+V_VREF_DQ_DIMM0

+V_VREF_DQ_DIMM1

+V_VREF_CA_DIMM1

1 2

DIMM0_VREF_DQ9

DIMM1_VREF_DQ9

R1805 0Ohm@

R1806 0Ohm@

1 2

M3

M3: Processor Generated SO-DIMM VREFDQ
– New Requirement

A A

5

4

If support M3 :

1. Mount R1802,R1803,R1805,R1806,R1810,R1811,C1802

2. Un mount R1801,R1804

3

Title :

Title :

Title :

DDR3(3)_CA/DQ Voltage

DDR3(3)_CA/DQ Voltage

DDR3(3)_CA/DQ Voltage

Trunks Chen

Trunks Chen

1

Trunks Chen

18 59Wednesday, February 01, 2012

18 59Wednesday, February 01, 2012

18 59Wednesday, February 01, 2012

of

of

of

Rev

Rev

Rev

1.0

1.0

1.0

Engineer:

Engineer:

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

B

B

B

Date: Sheet

Date: Sheet

2

Date: Sheet

B34

B34

B34

Engineer:

5

4

3

2

1

RTC battery

12

+RTC_BAT

12

3

J2001

4

BATT_HOLDER_2P

D D

C C

B B

+VCC_RTC

1 2

R2003 20KOhm

R2004 20KOhm

R2005

1MOhm

ACZ_BCLK_AUD_M38

ACZ_SYNC_AUD_M38

ACZ_SDOUT_AUD_M38

GND

RTCRST# RC delay
should be 18ms~25ms

12

12

TPM Settings

Clear ME RTC

Registers
Keep ME RTC
Registers

ACZ_RST#_AUD_M38

R2001 1KOhm

12V20GBSM000

M:1220-001O000

1

JRST2001

C2004

1UF/6.3V

C2005

1UF/6.3V

JRST2002

GND

1

2

SGL_JUMP

2

@

1

JRST2002

1

2

SGL_JUMP

2

@

GNDGND

Shunt

Open
(Default)

R2046 33Ohm

R2008

R2058 33Ohm

R2059 33Ohm

12

GND GND

12

Request by CSC
for CMOS clear
function

1MOhm

@

12

CMOS Settings

+VCC_RTC+3VA+RTCBAT

D2001

1

3

2

Clear CMOS

Keep CMOS

INTVRMEN: Integrated SUS 1.05V VRM Enables
Low: Enable External VRs
High:Enable Internal VRs

PCH_INTVRMEN

1V/0.2A

PN change to 10V220000058

GND

C2006
27PF/50V

1 2

@

ACZ_BCLK

ACZ_RST#

ACZ_SDOUT

12

C2003

1UF/6.3V

GND

JRST2001

Shunt
Open
(Default)

1 2

R2030 330KOhm1%

1

G

2

D

S

2N7002

Q2010

@

+12VS

3

GND

R2057

ACZ_SYNCACZ_SYNC_C

33Ohm

reference UB3 modify

T2015

+VCC_RTC

+3VSUS_ORG

+VTT_PCH_VCCIO

C2001

12

18PF/50V

C2002 18PF/50V

1

ACZ_SDIN038

T2025

T2022

T2003

T2002

SPI_CLK28

SPI_CS#028

SPI_SI28

SPI_SO28

RTC_X1_C

12

PN change to 10V220000058

GND

GND

1

GND

T2011

1

T2012

+VCC_RTC

SB_SPKR38

2

3

1

1

1

1

14

X2001

32.768KHZ

1 2

HDA_DOCK_EN#

HDA_DOCK_RST#

SP2005 NB_R0402_5MIL_SMALL

1 2

12

R2002

10MOhm

R2006330KOhm 1%

1

T2028

1

T2029

1

T2030

1

T2031

T2004

U2001A

RTC_X1

RTC_X2

RTC_RST#

SRTC_RST#

SM_INTRUDER#

PCH_INTVRMEN

ACZ_BCLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

PCH_JTAG_TCK_BUF

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

1

SPI_CS#1

0200-00HU000 C.S 907552 A1 QMVY BGA942 INTEL/COUGAR POINT PCH

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN#/GPIO33

N32

HDA_DOCK_RST#/GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

COUGAR_POINT_ES1

+VCC_RTC 22,27

+3VA

+3VA 6, 27,30,56,57,81,88,93

+3VS

+3VS 16, 17,21,22,23,24,25,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+3VSUS_ORG 21,22,24,25,27

+VTT_PCH_VCCIO 26,27

C38

FWH0/LAD0

A38

FWH1/LAD1

B37

FWH2/LAD2

C37

FWH3/LAD3

JTAG

RTCIHDA

SPI

LPC

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA

SATA3RCOMPO

SATA0GP/GPIO21

SATA1GP/GPIO19

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN

SATA 6G

SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

SNN_PCH_DRQ#0
SNN_LPC_DRQ#1

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA0GP

BBS_BIT0_R

R2048 750Ohm1%

R2025 10KOhm

SP2003 NB_R0402_5MIL_SMALL

1 2

1 2

1 2

R1.1
Intel Comments
R2007 = 37.4 ohm
R2047 = 49.9 ohm

1 2

R2007 37.4Ohm1%

1 2

R2047 49.9Ohm1%

SATA_LED#

LPC_AD0 30,44,62
LPC_AD1 30,44,62
LPC_AD2 30,44,62
LPC_AD3 30,44,62

LPC_FRAME# 30,44,62

T2024

1

T2023

1

INT_SERIRQ 30,44,62

SATA_RXN0 51
SATA_RXP0 51
SATA_TXN0 51
SATA_TXP0 51

SATA_RXN2 51
SATA_RXP2 51
SATA_TXN2 51
SATA_TXP2 51

SATA_RXN4 51
SATA_RXP4 51
SATA_TXN4 51
SATA_TXP4 51

GND

+3VS

SATA_LED# 56

BBS_BIT0 24

+VTT_PCH_VCCIO

+VTT_PCH_VCCIO

HDD1_mSATA SSD

ODD

for 14" reserve

R1.1

HDD2_7mm SATA SSD

Strap information:

SB_SPKR: No reboot strap
Low: Disable (Default)
High:Enable

ACZ_SDOUT:

1.Flash descriptor security:
Sampled Low: in effect.
Sampled High: override

2.ACZ_SDOUTwhich sample high on the rising edge of PWROK

A A

5

4

Will also disable Intel ME.

ACZ_SYNC: On Die PLL VR voltage selector
Low: 1.8V (Default)
High: 1.5V
note : CRB has no strap
Hrron River Platform Schematic Design Checklist
(438390 page 48)

SB_SPKR

ACZ_SDOUT

ACZ_SYNC

3

1 2

R2020 1KOhm@

1 2

R2034 1KOhm@

1 2

R2036 1KOhm

VCCVRAM use +1.5VS in mobile

+3VS

+3VSUS_ORG

+3VSUS_ORG

2

Pull High

INT_SERIRQ

SATA0GP

1 2

R2026 10KOhm

1 2

R2027 10KOhm

+3VS

PCH(1)_SATA,IHDA,RTC,LPC

PCH(1)_SATA,IHDA,RTC,LPC

PCH(1)_SATA,IHDA,RTC,LPC

Title :

Title :

Title :

Trunks Chen

Trunks Chen

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet of

Date: Sheet

Date: Sheet

Trunks Chen

20 59Wednesday, February 01, 2012

20 59Wednesday, February 01, 2012

20 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

of

of

5

4

3

+VTT_PCH_ORG

+3VSUS_ORG

2

+3VS

+3VS 16, 17,20,22,23,24,25,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+VTT_PCH_ORG 22,26,27

+3VSUS_ORG 20,22,24,25,27

1

U2001B

BG34

PERn1

D D

PCIE_RXN2_WLAN53

WLAN

PCIE_RXP2_WLAN53
PCIE_TXN2_WLAN53
PCIE_TXP2_WLAN53

PCIE_RXN3_LAN33

R1.2 change

Mini CARD (WLAN)

LAN

CLK_PCIE_LAN#33

CLK_PCIE_LAN33

CLK_REQ3_LAN#33

CLK_XDP_ITP_N4

CLK_XDP_ITP_P4

PCIE_RXP3_LAN33
PCIE_TXN3_LAN33
PCIE_TXP3_LAN33

LAN

PCIE 1

PCIE 2

PCIE 3

PCIE 4

C C

PCIE 5

PCIE 6

CLK_PCIE_WLAN#_PCH53

CLK_PCIE_WLAN_PCH53

CLK_REQ2_WLAN#53

B B

CLK XDP connect to N59, N58

A A

1 2

C2104 0.1UF/10V

1 2

C2112 0.1UF/10V

1 2

C2105 0.1UF/10V

1 2

C2103 0.1UF/10V

CLK_REQ2#

@

12

R21210Ohm

12

R21220Ohm

@

CLK_REQ0#

CLK_REQ1#

CLK_REQ3_LAN#

CLK_REQ4#

CLK_REQ5#

CLK_REQ_PEG_B#

CLK_REQ6#

CLK_REQ7#

PCIE_CLK_XDP_N
PCIE_CLK_XDP_P

GPP_TXN2
GPP_TXP2

GPP_TXN3
GPP_TXP3

BJ34

PERp1

AV32

PETn1

AU32

PETp1

BE34

PERn2

BF34

PERp2

BB32

PETn2

AY32

PETp2

BG36

PERn3

BJ36

PERp3

AV34

PETn3

AU34

PETp3

BF36

PERn4

BE36

PERp4

AY34

PETn4

BB34

PETp4

BG37

PERn5

BH37

PERp5

AY36

PETn5

BB36

PETp5

BJ38

PERn6

BG38

PERp6

AU36

PETn6

AV36

PETp6

BG40

PERn7

BJ40

PERp7

AY40

PETn7

BB40

PETp7

BE38

PERn8

BC38

PERp8

AW38

PETn8

AY38

PETp8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

COUGAR_POINT_ES1

PCI-E*

CLOCKS

SMBALERT#/GPIO11

SML0ALERT#/GPIO60

SMBUSController

SML1ALERT#/PCHHOT#/GPIO74

SML1CLK/GPIO58

SML1DATA/GPIO75

Link

PEG_A_CLKRQ#/GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

E12

H14

C9

A12

C8

G12

C13

E14

M16

M7

T11

P10

M10

CLK_REQ_PEG_A#

AB37

CLK_PCIE_PEG#_PCH_L

AB38

CLK_PCIE_PEG_PCH_L

AV22
AU22

AM12
AM13

BF18
BE18

BJ30
BG30

G24
E24

AK7
AK5

K45

H45

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_COMP

K43

DGPU_EDID_SELECT#

F47

CLK_OUT1

H47

CLK_OUT2

K49

DGPU_PRSNT#

EXT_SCI#

SCL_3A

SDA_3A

SML0_CLK

SML0_DAT

SML1ALERT#

SML1_CLK

SML1_DAT

SP2114 NB_R0402_5MIL_SMALL

1 2

SP2115 NB_R0402_5MIL_SMALL

1 2
1 2

SP2116

NB_R0402_5MIL_SMALL

CLK_BUF_EXP_N
CLK_BUF_EXP_P

CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P

CLK_BUF_DOT96_N
CLK_BUF_DOT96_P

CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P

CLK_BUF_REF14

1 2

R2106 90.9Ohm

1

T2122

1

T2128

R2105 33Ohm5%

1

T2127

EXT_SCI# 30

SCL_3A 28

SDA_3A 28

DRAMRST_CNTRL_PCH 5,9

SML1_CLK

SML1_DAT

CL_CLK 53

CL_DATA 53

CL_RST# 53

CLKREQ_PEG# 70

CLK_PCIE_PEG#_PCH 70
CLK_PCIE_PEG_PCH 70

CLK_EXP_N 4
CLK_EXP_P 4

CLK_DP_N 4
CLK_DP_P 4

CLK_PCI_FB 24

+VCCDIFFCLKN

12

Reserved for Wireless team

1 2

GND

To EC

R1.1

for eDP function

25-MHz is required in:

1. FCIM

2. BTM for PCH Display Clock gereration
in Integrated Graphics platforms

R21421MOhm

1 2

NB_R0402_5MIL_SMALL

CLK_USB48_CR

C2109
10PF/50V

SP2110

1 2

C2101

1 2

10PF/50V

X2103

4

25MHZ

2

1 3

C2102

1 2

XTAL25_OUT_C

10PF/50V

CLK_USB48_CR 40

CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P

CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P

CLK_BUF_REF14

EXT_SCI#

SCL_3A

SDA_3A

SML0_CLK

SML0_DAT

DRAMRST_CNTRL_PCH

SML1_CLK

SML1_DAT

SML1ALERT#

DGPU_EDID_SELECT#

DGPU_PRSNT#

DGPU_PRSNT#

PCH CLKREQ Setting:
Not connected to device.

CLK_REQ1#

CLK_REQ[2:1] Core Power
CLK_REQ[0],[7:3] Suspend Power

CLK_REQ0#

GND

CLK_REQ5#

CLK_REQ4#

CLK_REQ6#

GND

CLK_REQ7#

GND

CLK_REQ_PEG_B#

Connected to device.
Default : Clock free run. (PD 10K).
Reserver 10K PU for power saving purpose.

CLK_REQ2_WLAN#

CLK_REQ3_LAN#

CLKREQ_PEG#

CLKREQ_PEG#

CLK_REQ2_WLAN#

CLK_REQ3_LAN#

1 2

10KOhm

3 4

10KOhm

3 4

10KOhm

1 2

10KOhm

1 2

10KOhm

3 4

10KOhm

1 2

10KOhm

3 4

10KOhm

1 2

R2116 10KOhm

CLOCK TERMINATION for FCIM
Default power-on mode is ICC.

1 2

R2117 10KOhm

5 6

RN2103C

2.2KOhm

7 8

RN2103D

2.2KOhm

3 4

RN2103B

2.2KOhm

1 2

RN2103A

2.2KOhm

1 2

R2120 1KOhm

1 2

R2123 2.2KOhm

1 2

R2124 2.2KOhm

1 2

R2125 10KOhm

1 2

R2145 10KOhm@

1 2

R2126 10KOhm

@

1 2

R2135 10KOhm

1 2

R2129 10KOhm

1 2

R2127 10KOhm

1 2

R2134 10KOhm

1 2

R2128 10KOhm

1 2

R2130 10KOhm

1 2

R2131 10KOhm

1 2

R2132 10KOhm

1 2

R2133 10KOhm

1 2

R2136 10KOhm

1 2

R2140 10KOhm

1 2

R2143 10KOhm@

1 2

R2138 10KOhm@

1 2

R2137 10KOhm@

RN2108A
RN2108B

RN2109B
RN2109A
RN2110A
RN2110B
RN2111A
RN2111B

GND

+3VSUS_ORG

+3VS

GND

+3VS

+3VSUS_ORG

+3VS

+3VSUS_ORG

R1.1

GND

PCH(2)_PCIE,CLK,SMB,PEG

PCH(2)_PCIE,CLK,SMB,PEG

PCH(2)_PCIE,CLK,SMB,PEG

Title :

Title :

Title :

Trunks Chen

Trunks Chen

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

Trunks Chen

of

of

of

21 59Wednesday, February 01, 2012

21 59Wednesday, February 01, 2012

21 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

+3VSUS_ORG

+3VS

+VTT_PCH_ORG

+3VA

+VCC_RTC

+3VSUS

D D

C C

PM_RSMRST# has pull down 10k ohm in EC

B B

+3VSUS_ORG 20,21,24,25,27

+3VS 16,17,20,21,23,24,25,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+VTT_PCH_ORG 26,27

+3VA 6,20,27,30,56,57,81,88,93

+VCC_RTC 20,27

+3VSUS 24,27,28,30,33,53,56,81,92

DMI_RXN03
DMI_RXN13
DMI_RXN23
DMI_RXN33

DMI_RXP03
DMI_RXP13
DMI_RXP23
DMI_RXP33

DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33

DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33

+VTT_PCH_ORG

GND

SUS_PWR_ACK_R

+3VS

PM_PWROK4,30,92

ME_PWROK30

ME_SUSPWRDNACK30

ME_AC_PRESENT30

R2208 0Ohm/SBA

PM_DRAM_PWRGD4

PM_RSMRST#30

PM_PWRBTN#30

T2201

T2202

12

R2211 0Ohm/SBA

1

1

4

12

R2201 49.9Ohm1%

R2202 750Ohm1%

R2213

R2205 10KOhm

SP2212 NB_R0402_5MIL_SMALL

1 2

R2217 0Ohm

/non-SBA

SP2213 NB_R0402_5MIL_SMALL

1 2

12

SP2214 NB_R0402_5MIL_SMALL

1 2

R2212 0Ohm/SBA

12

12

12

12

SUS_PWR_ACK_R

12

DMI_COMP_R

RBIAS_CPY

PM_SYSRST#_R

SYS_PWROK

ME_AC_PRESENT_R

PM_PCH_PWROK_R

PM_APWROK_R

PM_RSMRST_R

BATLOW#

RI#

U2001C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

COUGAR_POINT_ES1

3

DMI

FDI

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SLP_S5#/GPIO63

System Power Management

SLP_LAN#/GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SUSCLK/GPIO62

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

PM_SUS_STAT#

N14

D10

H4

F4

G10

G16

AP14

K14

DSWODVREN

SUSCLK_C

SLP_S5#

ME_PM_SLP_A#

SLP_DSW#_R

GPIO29

2

1 2

R2215 330KOhm@

1 2

R2214 330KOhm1%

PN change to 10V220000058

R2216

12

SP2215 NB_R0402_5MIL_SMALL

1 2

R2210 0Ohm/SBA

R2209 0Ohm/SBA

PM_RSMRST_R

12

12

GND

+VCC_RTC

T2204

1

T2205

1

FDI_TXN0 3
FDI_TXN1 3
FDI_TXN2 3
FDI_TXN3 3
FDI_TXN4 3
FDI_TXN5 3
FDI_TXN6 3
FDI_TXN7 3

FDI_TXP0 3
FDI_TXP1 3
FDI_TXP2 3
FDI_TXP3 3
FDI_TXP4 3
FDI_TXP5 3
FDI_TXP6 3
FDI_TXP7 3

FDI_INT 3

FDI_FSYNC0 3

FDI_FSYNC1 3

FDI_LSYNC0 3

FDI_LSYNC1 3

DSWODVREN - On Die DSW VR Enable

HIGH - Enabled(DEFAULT) ; LOW-Disabled

PCIE_WAKE# 33,53

PM_CLKRUN# 30,62

PM_SUS_STAT# 62

SUSCLK 30

PM_SUSC# 30

PM_SUSB# 30

ME_PM_SLP_M# 30

H_PM_SYNC 4

ME_PM_SLP_LAN# 30

1

+3VSUS_ORG

RI#

BATLOW#

A A

PM_PWROK

DELAY_VR_AND_ALL_SYS92

5

SP2209 NB_R0402_5MIL_SMALL

1 2

1 2

SP2210

NB_R0402_5MIL_SMALL

U2201

A

1

B

2

3 4

GND

Vcc=2~5.5

+3VSUS

5

VCC

Y

4

SYS_PWROK

PCIE_WAKE#

ME_PM_SLP_A#

SUS_PWR_ACK_R

ME_AC_PRESENT

GPIO29

1 2

R2223 10KOhm

1 2

R2224 10KOhm

1 2

R2225 1KOhm

@

1 2

R2230 10KOhm

1 2

R2227 10KOhm

1 2

R2228 10KOhm

1 2

R2229 10KOhm

3

PM_CLKRUN#

PM_PWROK

2

1 2

R2220 10KOhm

1 2

R2221 10KOhm

+3VS

GND

Title :

Title :

Title :

Engineer:

Engineer:

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

B34

B34

B34

Engineer:

1

PCH(3)_FDI,DMI,SYS PWR

PCH(3)_FDI,DMI,SYS PWR

PCH(3)_FDI,DMI,SYS PWR

Trunks Chen

Trunks Chen

Trunks Chen

of

22 59Wednesday, February 01, 2012

of

22 59Wednesday, February 01, 2012

of

22 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

4

3

2

1

+3VS

D D

C C

CRT_B_PCH46
CRT_G_PCH46
CRT_R_PCH46

B B

+3VS 16,17,20,21,22,24,25,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

LCD_BKEN_PCH45
L_VDDEN_PCH45

+3VS

L_CTRL_CLK L_CTRL_DATA

L_CTRL_DATA

EDID_DATA_PCH

EDID_CLK_PCH

GND

CRT_B_PCH

50 ohm

CRT_G_PCH

50 ohm

CRT_R_PCH

50 ohm

3 4

5 6

7 8

1 2

JP2301 SHORT_PIN

Close to CPU

RN2301B

2.2KOhm

RN2301C

2.2KOhm

RN2301D

2.2KOhm

RN2301A

2.2KOhm

12

12

LCD_BKEN_PCH

R2307100KOhm

L_VDDEN_PCH

R2308100KOhm

12

JP2302 SHORT_PIN

R1.1

12

JP2303 SHORT_PIN

12

R2304

150Ohm

12

R2305

150Ohm

12

GND

37.5 ohm

37.5 ohm

37.5 ohm

R2306

150Ohm

12

L_BKLT_CTRL45

EDID_CLK_PCH45
EDID_DATA_PCH45

LVDSA_LCLKN_PCH45
LVDSA_LCLKP_PCH45

LVDSA_L0N_PCH45
LVDSA_L1N_PCH45
LVDSA_L2N_PCH45

LVDSA_L0P_PCH45
LVDSA_L1P_PCH45
LVDSA_L2P_PCH45

DDC_CLK_PCH46

DDC_DATA_PCH46

CRT_HSYNC_PCH46

CRT_VSYNC_PCH46

1

T2301

1

T2302

R2301 2.37KOhm
R2302 0Ohm@

GND

R2303 1KOhm1%

GND

GND

L_CTRL_CLK

12
12

B_PCH
G_PCH
R_PCH

SP2304 NB_R0402_5MIL_SMALL

1 2
1 2

SP2305

NB_R0402_5MIL_SMALL

12

U2001D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

COUGAR_POINT_ES1

SDVO_INTP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42

AV40

AV45
AV46
AU48
AU47
AV47
AV49

P46
P42

AP47
AP49
AT38

AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

DDPD_AUXN
DDPD_AUXP

HDMI_CLKN_PCH
HDMI_CLKP_PCH

SDVO

Display Port BDisplay Port C

HDMI_DDC_CLK_PCH 48
HDMI_DDC_DATA_PCH 48

1

T2303

1

T2304

HDMI_HPD_PCH 48

HDMI_TXN2_PCH 48
HDMI_TXP2_PCH 48
HDMI_TXN1_PCH 48
HDMI_TXP1_PCH 48
HDMI_TXN0_PCH 48
HDMI_TXP0_PCH 48

Display Port D

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN

SDVO_STALLP

SDVO_INTN

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

CRT Disable: (For discrete graphic)

1. NC:

CRT_RED,CRT_GREEN,CRT_BLUE

CRT_HSYCN,CRT_VSYNC

Ω ±0.5% pull-down to GND:

2. 1-k

A A

DAC_IREF

3. Connected to GND:

DisPlay Port Disable: (For UMA)

1. NC:

ALL

HDMI_CLKN_PCH

HDMI_CLKP_PCH

1 2

0Ohm

@

1 4

3 4

0Ohm

RN2302A

L2301
90Ohm/100MHz

2 3

RN2302B

HDMI_CLKN_PCH_R 48

HDMI_CLKP_PCH_R 48

CRT_ITRN

4. Connect to +V3.3:

VCCADAC

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

BG1-HW RD Div.2-NB RD Dept.5

Size Project Name

Size Project Name

Size Project Name

Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

B34

B34

B34

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

PCH(4)_DP,LVDS,CRT

PCH(4)_DP,LVDS,CRT

PCH(4)_DP,LVDS,CRT

Trunks Chen

Trunks Chen

Trunks Chen

of

23 59Wednesday, February 01, 2012

of

23 59Wednesday, February 01, 2012

of

23 59Wednesday, February 01, 2012

Rev

Rev

Rev

1.0

1.0

1.0

5

R1.1

+3VS

D D

U2402

1

R2414 0Ohm

+3VS

R1.1
DGPU_PWR_EN is active high

5

A

VCC

B

4

GND3Y

SN74LVC1G08DCKR

@

1 2

2

+3VSUS

1 2

1 2

R2428 10KOhm@

1 2

R2427 10KOhm

1 2

R2430 10KOhm

1 2

R2429 1KOhm

56

10KOhm

34

10KOhm

78

10KOhm

12

10KOhm

R2420 0Ohm@

MPC_PWR_CTRL#
SATA_ODD_DA# EXTTS_SNI_DRV0_PCH
EXTTS_SNI_DRV0_PCH
EXTTS_SNI_DRV1_PCH

VGA_PWRON91

C C

R1.1

DGPU_PWM_SELECT#
DGPU_SELECT#
DGPU_HOLD_RST#

DGPU_PWR_EN

+3VS

RN2407C
RN2407B
RN2407D
RN2407A

B B

12

R2432
10KOhm

@

R2415 0Ohm@

GND

4

1 2

SUSB_EC# 30,57,91,92

DGPU_HOLD_RST#70

DGPU_PWR_EN57

SATA_ODD_DA#51

CLK_TPMPCI62
CLK_PCI_FB21

CLK_KBCPCI_PCH30

CLK_DEBUG44

DGPU_PWR_EN

+3VS

USB 3.0

R1.0 Adjust port assignment

USB3_RX1_N52

USB3_RX1_P52

USB3_TX1_N52

USB3_TX1_P52

1 2

R2421 10KOhm

1 2

R2422 10KOhm

1 2

R2423 10KOhm

1 2

R2424 10KOhm
SP2401 NB_R0402_5MIL_SMALL

1 2

1

T2406

1 2

SP2402 NB_R0402_5MIL_SMALL

1

T2404

1 2

R2405 1KOhm@

GND

1

T2401

1

T2405

C2403
10PF/50V@

1 2

Reserved for Wireless team

GND

12

R241322Ohm

12

R240922Ohm

12

R241022Ohm

12

R241222Ohm

3

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

DGPU_HOLD_RST#_R
DGPU_SELECT#
DGPU_PWR_EN_R

BBS_BIT1
DGPU_PWM_SELECT#
STP_A16OVR

MPC_PWR_CTRL#
SATA_ODD_DA#

EXTTS_SNI_DRV1_PCH

PCI_PME#

PLT_RST#

CLK_TPMPCI_R
CLK_PCI_FB_R
CLK_KBCPCI_PCH_R
CLK_DEBUG_R
CLK_DBG_R

U2001E

BG26

BJ26

BH25

BJ16

BG16

AH38
AH37
AK43
AK45

C18
N30

H3

AH12

AM4
AM5

Y13
K24

L24
AB46
AB45

B21

M20
AY16

BG46

BE28
BC30
BE32

BJ32
BC28
BE30
BF32

BG32

AV26
BB26
AU28
AY30
AU26
AY26
AV28

AW30

K40
K38
H38
G38

C46
C44
E40

D47
E42
F46

G42
G40
C42
D44

K10

C6

H49
H43
J48
K42
H40

COUGAR_POINT_ES1

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20

TP21
TP22
TP23
TP24

TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PME#

PLTRST#

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

2

+3VSUS

+3VSUS_ORG

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD

PCI

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USBP8P

G30

USB_PN9

USBP9N

E30

USB_PP9

USBP9P

C30

USBP10N

A30

USBP10P

USB

USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

L32
K32
G32
E32
C32
A32

C33

B33

USB_BIAS

A14
K20
B17
C16
L16
A16
D14
C14

+12VS

R2416 22.6Ohm

+3VSUS 22,27,28,30,33,53,56,81,92

+3VS

+3VS 16, 17,20,21,22,23,25,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+3V

+3V 40,53,55,57,62, 91

+3VSUS_ORG 20,21,22,25,27

+12VS 20,28,48,91

R1.0 Adjust port assignment

1 2

1 2

10KOhm

5 6

10KOhm

7 8

10KOhm

5 6

10KOhm

7 8

10KOhm

3 4

10KOhm

1 2

10KOhm

3 4

10KOhm

USB_PN0 52
USB_PP0 52
USB_PN1 66
USB_PP1 66

USB_PN3 40
USB_PP3 40

USB_PN8 55
USB_PP8 55
USB_PN9 66
USB_PP9 66

USB_PN11 53
USB_PP11 53

GND

RN2401A
RN2401C
RN2402D
RN2402C
RN2401D
RN2402B
RN2402A
RN2401B

Place within 500 mils of PCH

USB port - Combo with USB3.0

USB port

Card Reader

Camera

USB port & for debug

WiFi/WiMax

USB_OC# 52

1

move to USBP1 for USB debug port

+3VSUS_ORG

BBS_BIT0,BBS_BIT1 : Boot BIOS Strap

Boot BIOS Strap

BBS_BIT0BBS_BIT1 Boot BIOS Location

0 0

0 1

1 0

1 1 SPI

A A

Sampled on rising edge of PWROK.

BBS_BIT020

5

BBS_BIT0

BBS_BIT1

LPC

Reserved (NAND)

Reserved

@

1 2

@

R2417 1KOhm

1 2

R2418 1KOhm

(PCH)

GND

STP_A16OVR:
A16 swap override Strap/
Top-Block swap override jumper

Low=Enabled A16 swap override/
Top-Block swap override

High=Default

STP_A16OVR

1 2

R2419 1KOhm

4

@

GND

U2401

A

1

B

GND

2

3 4

GND

SN74LVC1G08DCKR

PLT_RST#

3

2

+3V

5

VCC

@

Y

12

R24250Ohm

12

R2426
10KOhm

@

GND

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

BUF_PLT_RST# 4,30,32,33,53,62,70

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

B34

B34

B34

1

PCH(5)_PCI,NVRAM,USB

PCH(5)_PCI,NVRAM,USB

PCH(5)_PCI,NVRAM,USB

Trunks Chen

Trunks Chen

Trunks Chen

1.0

1.0

1.0

of

of

of

24 59Wednesday, February 01, 2012

24 59Wednesday, February 01, 2012

24 59Wednesday, February 01, 2012

Rev

Rev

Rev

+3VS

+3VSUS

+VCCP

+3VSUS_ORG

+1.8VS

+3VS

D D

12

R2525

10KOhm

@

12

R2526

10KOhm

GND

ID0 ID1 PCB Rev.

0 0 R1.1 (SR)
0 1 R1.2 (ER)

C C

B B

1 0 R2.0
1 1 R2.1

EXT_SMI#

ICC_EN#

LAN_PHY_PWR_CTRL

AOAC_ON

RCIN# has pull high at EC side

R1.1

Unused GPIO

PCH_GPIO49

DGPU_PWROK

GPIO0

GPIO1

STP_PCI#

SATA_DET#4

5

+3VS 16, 17,20,21,22,23,24,26,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+3VSUS 22,24,27,28,30,33,53,56,81,92

+VCCP 3,4,6,7,26,27,30,32,82

+3VSUS_ORG 20,21,22,24,27

+1.8VS 7,26,80,84

+3VS

12

R2527

10KOhm

12

R2528

@

10KOhm

GND

R2529 1KOhm1%

R2532 10KOhm

R2538 10KOhm

R2541 10KOhm/AOAC

PCB_ID0

PCB_ID1

PROJECT
_ID0

0
0
1
1

1 2

R2539 10KOhm@

R2540 10KOhm

R2536 10KOhm

R2545 10KOhm

R2537 10KOhm

R2546 10KOhm

+3VSUS_ORG

12

12

12

12

12

12

12

12

12

+3VS

12

@

12

GND

R2534

10KOhm

R2533

10KOhm

PROJECT
_ID1

0
1
0
1

+3VS

+3VS

12

R2549

10KOhm

12

R2530

@

10KOhm

GND

B14 (UMA)
B34 (UMA / N13P-GL)
B74 (UMA / N13P-GS)
X

Model

+3VS GND

FDI TERMINATION VOLTAGE OVERRIDE

- GPIO37 (FDI_OVRVLTG)
LOW - TX, RX terminated to same voltage
(DC Couplong Mode)
DEFAULT

+3VS

DMI TERMINATION VOLTAGE OVERRIDE

- GPIO36 (SATA_ODD_PRSNT#)
LOW - TX, RX terminated to same voltage
(DC Couplong Mode)
DEFAULT

PROJECT_ID0

PROJECT_ID1

1 2

R2518 1KOhm1%

1 2

R2520 200KOhm1%

4

GPIO0

GPIO1

1

T2508

T2506

EXT_SMI#30,44

DGPU_PWROK74,75,85,91

WLAN_LED56

AOAC_ON53

T2514

WLAN_ON53

T2516

SATA_ODD_PRSNT#51

BT_ON/OFF#53

OP_SD#38

BT_LED56

@

FDI_OVRVLTG

SATA_ODD_PRSNT#

PROJECT_ID0

PROJECT_ID1

1

ICC_EN#

LAN_PHY_PWR_CTRL

SATA_DET#4

1 2

WLAN_LED

1

GPIO27

SP2502

PLL_ODVR_EN
STP_PCI#

1

GPIO35

FDI_OVRVLTG

PCB_ID0

PCB_ID1

PCH_GPIO49

1 2

R2519 100KOhm

SP2501

1 2

NB_R0402_5MIL_SMALL

1 2

3

R25060Ohm

NB_R0402_5MIL_SMALL

U2001F

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL/GPIO12

G2

GPIO15

U2

SATA4GP/GPIO16

D40

TACH0/GPIO17

T5

SCLOCK/GPIO22

E8

GPIO24/MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI#/GPIO34

K4

GPIO35

V8

SATA2GP/GPIO36

M5

SATA3GP/GPIO37

N2

SLOAD/GPIO38

M3

SDATAOUT0/GPIO39

V13

SDATAOUT1/GPIO48

V3

SATA5GP/GPIO49

D6

GPIO57

A4

Vss_NCTF1

A44

Vss_NCTF2

A45

Vss_NCTF3

A46

Vss_NCTF4

A5

Vss_NCTF5

A6

Vss_NCTF6

B3

Vss_NCTF7

B47

Vss_NCTF8

BD1

Vss_NCTF9

BD49

Vss_NCTF10

BE1

Vss_NCTF11

BE49

Vss_NCTF12

BF1

Vss_NCTF13

BF49

Vss_NCTF14

COUGAR_POINT_ES1

2

C40

TACH4/GPIO68

B41

RCIN#

NC_1

PECI

TACH5/GPIO69

C41

TACH6/GPIO70

A40

TACH7/GPIO71

P4

AU16

P5

AY11

AY10

PM_THRMTRIP#

T14

INIT3_3V#

AY1

AH8

AK11

AH10

TS Signal Disable Guideline

AK10

TS_VSS[1:4] should pull down to GND
Design Guide 0.9 (436735)

P37

GND

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

A20GATE

PROCPWRGD

THRMTRIP#

GPIO

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

Vss_NCTF15

Vss_NCTF16

Vss_NCTF17

Vss_NCTF18

Vss_NCTF19

Vss_NCTF20

Vss_NCTF21

Vss_NCTF22

Vss_NCTF23

NCTF

Vss_NCTF24

Vss_NCTF25

Vss_NCTF26

Vss_NCTF27

Vss_NCTF28

Vss_NCTF29

Vss_NCTF30

Vss_NCTF31

Vss_NCTF32

1 2

R2511 1.5KOhm1%

1 2

R2512 1.5KOhm1%

1 2

R2513 1.5KOhm1%

1 2

1 2

1

T2504

SNB: unmount
IVB: mount 1k o hm

R25140Ohm @

R2516390Ohm 1%

SATA_ODD_PWRGT 51

GND

+3VS

+3VS

1 2

R251543Ohm

12

R25481KOhm

/IVB

2.2KOhm

/IVB

R2547

12

1

R1.1

+1.8VS

A20GATE 30

H_PECI 4
H_PECI_EC 30

RC_IN# 30

H_CPUPWRGD 4

H_THRMTRIP# 4,32

H_SNB_IVB# 4

1 2

12

PLL_ODVR_EN

12

GND

4

1 2

R2521 1KOhm@

PLL ON DIE VR ENABLE
HIGH - DISABLED (DEFAULT)

GND

LOW - ENABLED

PCH(6)_CPU,GPIO,MISC

PCH(6)_CPU,GPIO,MISC

PCH(6)_CPU,GPIO,MISC

Title :

Title :

Title :

Trunks Chen

Trunks Chen

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

3

2

Date: Sheet

Trunks Chen

of

of

of

25 59Friday, February 03, 2012

25 59Friday, February 03, 2012

25 59Friday, February 03, 2012

Rev

Rev

Rev

1.0

1.0

1.0

PCH_GPIO49

GPIO27

DGPU_PWROK

A A

R2544 10KOhm

R2523 10KOhm

R2542 10KOhm@

5

5

4

3

2

1

D D

C C

B B

GND GND

U2001H

H5

VSS0

AA17

VSS1

AA2

VSS2

AA3

VSS3

AA33

VSS4

AA34

VSS5

AB11

VSS6

AB14

VSS7

AB39

VSS8

AB4

VSS9

AB43

VSS10

AB5

VSS11

AB7

VSS12

AC19

VSS13

AC2

VSS14

AC21

VSS15

AC24

VSS16

AC33

VSS17

AC34

VSS18

AC48

VSS19

AD10

VSS20

AD11

VSS21

AD12

VSS22

AD13

VSS23

AD19

VSS24

AD24

VSS25

AD26

VSS26

AD27

VSS27

AD33

VSS28

AD34

VSS29

AD36

VSS30

AD37

VSS31

AD38

VSS32

AD39

VSS33

AD4

VSS34

AD40

VSS35

AD42

VSS36

AD43

VSS37

AD45

VSS38

AD46

VSS39

AD8

VSS40

AE2

VSS41

AE3

VSS42

AF10

VSS43

AF12

VSS44

AD14

VSS45

AD16

VSS46

AF16

VSS47

AF19

VSS48

AF24

VSS49

AF26

VSS50

AF27

VSS51

AF29

VSS52

AF31

VSS53

AF38

VSS54

AF4

VSS55

AF42

VSS56

AF46

VSS57

AF5

VSS58

AF7

VSS59

AF8

VSS60

AG19

VSS61

AG2

VSS62

AG31

VSS63

AG48

VSS64

AH11

VSS65

AH3

VSS66

AH36

VSS67

AH39

VSS68

AH40

VSS69

AH42

VSS70

AH46

VSS71

AH7

VSS72

AJ19

VSS73

AJ21

VSS74

AJ24

VSS75

AJ33

VSS76

AJ34

VSS77

AK12

VSS78

AK3

VSS79

COUGAR_POINT_ES1

VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

+VTT_PCH_ORG

+VTT_PCH_VCCIO

+VTT_PCH_VCC

+VTT_PCH_VCCIO

+VTT_PCH_ORG

+VTT_PCH_VCCIO

R2605 0Ohm@

1 2

vx_c0603_small

+3VS_VCC3_3

+VTT_PCH_VCCAPLL_FDI

12

+VTT_PCH_VCCDPLL_FDI

SP2606

12

C2601
10UF/6.3V

GND

GND

vx_c0603_small

+VTT_PCH_VCCDPLL_EXP

SP2604

1 2

2 1

L2601 1kOhm/ 100Mhz

@

+VTT_PCH_VCCAPLL_EXP

+VTT_PCH_VCC_EXP

12

12

C2607

C2606
10UF/6.3V

1UF/6.3V

SP2605

1 2

R1.0 0126
Intel Comments

12

C2602

1UF/6.3V

12

C2608

1UF/6.3V

12

12

C2603

1UF/6.3V

GND GND

+VTT_PCH_VCCDPLL_EXP

vx_c0603_small

12

GND

3.507A

12

12

C2609

1UF/6.3V

GND

+3VS_VCCA3GBG

12

C2611

0.1UF/10V

GND

+VCCIO_CPU_VCC_DMI

C2604

1UF/6.3V

C2605
10UF/6.3V

@

C2610

1UF/6.3V

34.2mA

+VCCAFDI_VRM

153mA

1.7A

292mA

50mA

U2001G

AA23

VccCore1

AC23

VccCore2

AD21

VccCore3

AD23

VccCore4

AF21

VccCore5

AF23

VccCore6

AG21

VccCore7

AG23

VccCore8

AG24

VccCore9

AG26

VccCore10

AG27

VccCore11

AG29

VccCore12

AJ23

VccCore13

AJ26

VccCore14

AJ27

VccCore15

AJ29

VccCore16

AJ31

VccCore17

AN19

VccIO1

BJ22

VccAPLLEXP

AN16

VccIO2

AN17

VccIO3

AN21

VccIO4

AN26

VccIO5

AN27

VccIO6

AP21

VccIO7

AP23

VccIO8

AP24

VccIO9

AP26

VccIO10

AT24

VccIO11

AN33

VccIO12

AN34

VccIO13

BH29

Vcc3_3_1

AP16

VccVRM1

BG6

VccAFDIPLL

AP17

VccIO14

AU20

VccDMI1

COUGAR_POINT_ES1

POWER

VCC CORE

VCCIO

FDI

63mA

U48

VccADAC

U47

AK36

AK37

AM37

AM38

AP36

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

50mA

28.2mA

70mA

10mA

0.1UF/10V

C2622

GND

1mA

GND

40mA

68.4mA

+VCCAFDI_VRM

+VCCIO_CPU_VCC_DMI

12

GND

12

GND

2mA

12

GND

12

GND

VssADAC

CRTLVDS

VccALVDS

VssALVDS

VccTX_LVDS1

VccTX_LVDS2

VccTX_LVDS3

VccTX_LVDS4

Vcc3_3_2

Vcc3_3_3

VccVRM2

VccDMI2

DMI

VccClkDMI

VccDFTERM1

VccDFTERM2

VccDFTERM3

VccDFTERM4

DFT / SPI HVCMOS

VccSPI

+VCCA_DAC_1_2

vx_c0603_small

12

12

12

C2612

0.01UF/16V

GND

12

12

C2615

0.01UF/16V

GND

GND

+3VS_VCC_GIO

12

C2618

0.1UF/10V

GND

SP2609

C2619

1UF/6.3V

C2620
10UF/6.3V@vx_c0603_small

C2621

0.1UF/10V

1 2

+VTT_PCH_ORG_VCCCLKDMI

R2614 0Ohm

+V_NVRAM_VCCPNAND +1.8VS

+3VM_VCCPSPI

C2614

C2613

10UF/6.3V

0.1UF/10V

GNDGND

+3VS_VCCA_LVD

+1.8VS_VCCTX_LVD

12

C2616

0.01UF/16V

1 2

R2616 0Ohm

C2617

22UF/6.3V

@

GND

SP2608

1 2

+VTT_PCH_ORG

12

SP2610

12

@

R2617 0Ohm

12

+VCCP

L2604

1kOhm/100Mhz

SP2607

1 2

L2602

1kOhm/100Mhz

+3VS

+3VM_SPI

21

21

+3VS_VCC3_3

+3VS

+3VS

+1.8VS

+VTT_PCH_VCCIO

+VTT_PCH_ORG

+VCCP

+1.05VS +VTT_PCH_ORG

A A

JP2601

2

112

3MM_OPEN_5MIL

6A

5

JP2602

2

112

2MM_OPEN_5MIL

JP2603

2

112

2MM_OPEN_5MIL

1.73A

3.799A

+VTT_PCH_VCC

+VTT_PCH_VCCIO

+1.5VS

4

SP2602

1 2

+VCCAFDI_VRM

160mA

3

+1.8VS

+1.5VS

+1.05VS

+3VS_VCC3_3

+3VM_SPI

+VCCAFDI_VRM

+VTT_PCH_VCCIO 20,27

+VTT_PCH_ORG 22,27

+VCCP 3,4,6,7,27,30,32,82

+1.8VS 7,25,80,84

+1.5VS 53,57,91

+3VS

+3VS 16,17,20,21,22,23,24,25,27,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92

+1.05VS 27,82,85

+3VS_VCC3_3 27

+3VM_SPI 28

+VCCAFDI_VRM 27

2

Title :

Title :

Title :

Engineer:

Engineer:

B34

B34

B34

Engineer:

1

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

PCH(7)_POWER,GND

PCH(7)_POWER,GND

PCH(7)_POWER,GND

Trunks Chen

Trunks Chen

Trunks Chen

Rev

Rev

Rev

1.0

1.0

1.0

of

of

of

26 59Wednesday, February 01, 2012

26 59Wednesday, February 01, 2012

26 59Wednesday, February 01, 2012

U2001I

AY4

VSS159

AY42

VSS160

AY46

VSS161

AY8

VSS162

B11

VSS163

B15

VSS164

B19

VSS165

B23

VSS166

B27

VSS167

B31

VSS168

B35

VSS169

B39

VSS170

B7

VSS171

F45

VSS172

BB12

VSS173

BB16

D D

C C

B B

A A

VSS174

BB20

VSS175

BB22

VSS176

BB24

VSS177

BB28

VSS178

BB30

VSS179

BB38

VSS180

BB4

VSS181

BB46

VSS182

BC14

VSS183

BC18

VSS184

BC2

VSS185

BC22

VSS186

BC26

VSS187

BC32

VSS188

BC34

VSS189

BC36

VSS190

BC40

VSS191

BC42

VSS192

BC48

VSS193

BD46

VSS194

BD5

VSS195

BE22

VSS196

BE26

VSS197

BE40

VSS198

BF10

VSS199

BF12

VSS200

BF16

VSS201

BF20

VSS202

BF22

VSS203

BF24

VSS204

BF26

VSS205

BF28

VSS206

BD3

VSS207

BF30

VSS208

BF38

VSS209

BF40

VSS210

BF8

VSS211

BG17

VSS212

BG21

VSS213

BG33

VSS214

BG44

VSS215

BG8

VSS216

BH11

VSS217

BH15

VSS218

BH17

VSS219

BH19

VSS220

H10

VSS221

BH27

VSS222

BH31

VSS223

BH33

VSS224

BH35

VSS225

BH39

VSS226

BH43

VSS227

BH7

VSS228

D3

VSS229

D12

VSS230

D16

VSS231

D18

VSS232

D22

VSS233

D24

VSS234

D26

VSS235

D30

VSS236

D32

VSS237

D34

VSS238

D38

VSS239

D42

VSS240

D8

VSS241

E18

VSS242

E26

VSS243

G18

VSS244

G20

VSS245

G26

VSS246

G28

VSS247

G36

VSS248

G48

VSS249

H12

VSS250

H18

VSS251

H22

VSS252

H24

VSS253

H26

VSS254

H30

VSS255

H32

VSS256

H34

VSS257

F3

VSS258

COUGAR_POINT_ES1

+3VS_VCC3_3

R2701 0Ohm

L2701 1kOhm/100Mhz

1 2

@

5

R1.0 0126
Intel Comments

21

vx_c0603_small

5

H46

VSS259

K18

VSS260

K26

VSS261

K39

VSS262

K46

VSS263

K7

VSS264

L18

VSS265

L2

VSS266

L20

VSS267

L26

VSS268

L28

VSS269

L36

VSS270

L48

VSS271

M12

VSS272

P16

VSS273

M18

VSS274

M22

VSS275

M24

VSS276

M30

VSS277

M32

VSS278

M34

VSS279

M38

VSS280

M4

VSS281

M42

VSS282

M46

VSS283

M8

VSS284

N18

VSS285

P30

VSS286

N47

VSS287

P11

VSS288

P18

VSS289

T33

VSS290

P40

VSS291

P43

VSS292

P47

VSS293

P7

VSS294

R2

VSS295

R48

VSS296

T12

VSS297

T31

VSS298

T37

VSS299

T4

VSS300

W34

VSS301

T46

VSS302

T47

VSS303

T8

VSS304

V11

VSS305

V17

VSS306

V26

VSS307

V27

VSS308

V29

VSS309

V31

VSS310

V36

VSS311

V39

VSS312

V43

VSS313

V7

VSS314

W17

VSS315

W19

VSS316

W2

VSS317

W27

VSS318

W48

VSS319

Y12

VSS320

Y38

VSS321

Y4

VSS322

Y42

VSS323

Y46

VSS324

Y8

VSS325

BG29

VSS326

N24

VSS327

AJ3

VSS328

AD47

VSS329

B43

VSS330

BE10

VSS331

BG41

VSS332

G14

VSS333

H16

VSS334

T36

VSS335

BG22

VSS336

BG24

VSS337

C22

VSS338

AP13

VSS339

M14

VSS340

AP3

VSS341

AP1

VSS342

BE16

VSS343

BC16

VSS344

BG28

VSS345

BJ28

VSS346

12

C2701

10UF/6.3V

GND GND

GNDGND

+3VS_VCC_CLKF33

12

C2702

1UF/6.3V

+VTT_PCH_VCCIO

+VTT_PCH_VCCA_A_DPL

+VTT_PCH_VCCA_B_DPL

NB_R0402_20MIL_SMALL

1 2

SP2715

+VCCP

12

R2702
0Ohm

@

4

+VTT_PCH_ORG

+3VSUS_ORG

+VTT_PCH_ORG

vx_c0603_small

+1.05VM_ORG

+VTT_PCH_ORG

12

C2715
1UF/6.3V

GND GND

+1.05VM_ORG

SP2701

1 2

R1.0 0303
Intel Comments

+VTT_PCH_VCCA_A_DPL

12

C2703

1UF/6.3V

GNDGND

+VTT_PCH_VCCA_B_DPL

12

C2704

1UF/6.3V

GNDGND

4

R2703 0Ohm@

R2704 0Ohm

R2705 0Ohm@

+3VA

@

21

L2704 1kOhm/100Mhz

C2741

10UF/6.3V

12

C2709
22UF/6.3V

Net broken

1 2

1 2

R2710 0Ohm@

+VTT_CPU_VCCPCPU

12

C2720

4.7UF/6.3V

GND

12

C2707
22UF/6.3V

12

C2740
22UF/6.3V

1 2

1 2

1 2

+VTT_PCH_VCCIO

12

@

GND

12

GNDGND

12

GND

R27080Ohm

12

R1.0 0126
Intel Comments

+VCC_RTC

L2702

21

1kOhm/100Mhz

L2703

21

1kOhm/100Mhz

C2710

22UF/6.3V

C2714

0.1UF/10V

C2716

1UF/6.3V

+VTT_PCH_ORG

12

C2705

0.1UF/10V

GND

GND

+VCCSUS1

12

C2708
1UF/6.3V

@

GND

R1.0 0126
Intel Comments

12

12

C2711

1UF/6.3V

GND

GND

+VCCAFDI_VRM

+VTT_PCH_VCCA_A_DPL

+VTT_PCH_VCCA_B_DPL

+VTT_PCH_ORG_SSCVCC

1 2

R2709 0Ohm

C2717

1UF/6.3V

C2719

1UF/6.3V

12

C2721

6uA

12

C2723

1UF/6.3V

GND

+VTT_PCH_ORG

12

+

CE2701

220UF/2V

@

GND

close PCH

3

+VTT_PCH_VCCACLK

12

C2706

@

0.1UF/10V

R2706NB_R0402_20MIL_SMALL

1 2

+VCCDPLL_CPY

C2712

1UF/6.3V

+VCCDIFFCLKN

12

GND

12

GND

0.1UF/10V

GND

20mA

+VCCPDSW

PCH_VCCDSW

+3VS_VCC_CLKF33

+VCCAPLL_CPY_PCH

12

C2713

1UF/6.3V

GND

+VCCRTCEXT

15mA

15mA

+VCCDIFFCLK

55mA

95mA

0.1UF/10V

12

VCCSST

C2718

GND

+V1.05VM_ORG_VCCSUS

@

12

1mA

12

C2722

0.1UF/10V

GNDGND

12

C2724

C2725

0.1UF/10V

0.1UF/10V

GND

+3VSUS +3VSUS_ORG

JP2703

2

112

1MM_OPEN_M1M2

+5VSUS +5VSUS_ORG

JP2702

2

112

1MM_OPEN_M1M2

+3VS +3VS_VCC3_3

JP2704

2

112

1MM_OPEN_M1M2

3

U2001J

AD49

T16

V12

T38

BH23

AL29

AL24

AA19

AA21

AA24

AA26

AA27

AA29

AA31

AC26

AC27

AC29

AC31

AD29

AD31

W21

W23

W24

W26

W29

W31

W33

N16

Y49

BD47

BF47

AF17
AF33
AF34

AG34

AG33

V16

T17
V19

BJ8

A22

COUGAR_POINT_ES1

97mA

266mA

VccAClk

VccDSW3_3

DcpSusByp

Vcc3_3_4

VccAPLLDMI2

VccIO15

DcpSus1

VccASW1

VccASW2

VccASW3

VccASW4

VccASW5

VccASW6

VccASW7

VccASW8

VccASW9

VccASW10

VccASW11

VccASW12

VccASW13

VccASW14

VccASW15

VccASW16

VccASW17

VccASW18

VccASW19

VccASW20

DcpRTC

VccVRM3

VccADPLLA

VccADPLLB

VccIO16
VccDIFFCLKN1
VccDIFFCLKN2
VccDIFFCLKN3

VccSSC

DcpSST

DcpSus2
DcpSus3

V_PROC_IO

VccRTC

POWER

Clock and Misce llaneous

CPURTC

PCI/GPIO/LPCMISC

SATA USB

HDA

VccIO17

VccIO18

VccIO19

VccIO20

VccIO21

VccSus3_3_1

VccSus3_3_2

VccSus3_3_3

VccSus3_3_4

VccSus3_3_5

VccIO22

V5REF_Sus

DcpSus4

VccSus3_3_6

V5REF

VccSus3_3_7

VccSus3_3_8

VccSus3_3_9

VccSus3_3_10

Vcc3_3_5

Vcc3_3_6

Vcc3_3_7

Vcc3_3_8

VccIO23

VccIO24

VccIO25

VccIO26

VccAPLLSATA

VccVRM4

VccIO27

VccIO28

VccIO29

VccASW21

VccASW22

VccASW23

VccSusHDA

+VTT_PCH_ORG

+VTT_PCH_VCCIO

+VCC_RTC

+3VSUS_ORG

+VCCAFDI_VRM

+3VS_VCC3_3
+1.05VM_ORG

+VCCDIFFCLKN

+1.05VSUS

+1.05VS

2

N26

P26

P28

T27

T29

T23

T24

V23

0.1UF/10V

V24

P24

T26

+VCCAUPLL

1mA

M26

AN23

+VCCA_USBSUS

AN24

1mA

P34

N20

N22

C2732

P20

1UF/6.3V

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

T21

V21

T19

10mA

P32

+1.05VS

+VCCP

+3VSUS

+5VSUS

+1.05VS 26,82,85

+3VS

+3VS 16, 17,20,21,22,23,24,25,26,28,30,31,32,33,38,44,45,46,48,50,51,53,56,57,62,66,80,85,91,92
+VTT_PCH_ORG 22,26
+VCCP 3,4,6,7,26,30,32,82
+VTT_PCH_VCCIO 20,26
+3VSUS 22,24,28,30,33,53,56,81,92
+VCC_RTC 20, 22
+5VSUS 52,81,91

+5VS

+5VS 30, 31,38,46,48,50,51,53,56,57,80,91
+3VSUS_ORG 20,21,22,24,25

+3VA

+3VA 6, 20,30,56,57,81,88,93
+VCCAFDI_VRM 26
+3VS_VCC3_3 26
+1.05VM_ORG
+VCCDIFFCLKN 21

R2714 0Ohm

R2713 0Ohm

2

12

C2726

1UF/6.3V

GND

+3VSUS_ORG_VCCPUSB

12

C2727

+3VSUS_ORG_VCCAUBG

GND

+3VSUS_ORG_VCCPSUS

+3VSUS_ORG_VCCPSUS

12

+3VS_VCCPCORE

GND

+3VS_VCCPPCI

12

C2734

0.1UF/10V

GND

12

GND

12

GND

+VCCAFDI_VRM

12

GND

10mil trace

GND

12

/SBA

12

/non-SBA

+VTT_PCH_VCCUSBCORE

SP2705

C2735

0.1UF/10V

C2736
1UF/6.3V

+VTT_PCH_VCCIO_VCC_SATA

C2738

1UF/6.3V

+3VSUS_ORG_VCCPAZSUS

12

C2739

0.1UF/16V

+1.05VM_ORG

SP2702 R0402

12

C2728

0.1UF/10V

1 2

NB_R0402_20MIL_SMALL

12

GND

1 2

SP2706

NB_R0402_20MIL_SMALL

SP2708 NB_R0402_20MIL_SMALL

1 2

+VTT_PCH_VCCIO_SATA3

SP2709 R0402

+VTT_PCH_ORG_VCCAPLL_SATA3

SP2710 R0402

R1.0 0126
Intel Comments

1.01A

1 2

SP2703 NB_R0402_20MIL_SMALL

1 2

SP2704 NB_R0402_20MIL_SMALL

1 2

+VTT_PCH_VCCIO

+5VSUS_PCH_VCC5REFSUS

C2730
1UF/6.3V

@

+5VS_PCH_VCC5REF

1 2

vx_c0603_small

12

C2737

10UF/6.3V

@

GND

1 2

SP2714

1 2

Date: Sheet

Date: Sheet

Date: Sheet

+VTT_PCH_VCCIO

+3VSUS_ORG

1UF/6.3V

+3VSUS_ORG

1UF/6.3V

+3VS_VCC3_3

GND

+3VS_VCC3_3

+VTT_PCH_VCCIO

+VTT_PCH_VCCIO

+1.05VM_ORG

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

BG1-HW RD Div.2-NB RD Dept .5

Size Project Name

Size Project Name

Size Project Name

C

C

C

B34

B34

B34

1

+3VSUS_ORG

1

2

D2701
1V/0.2A

R2711

3

1 2

10Ohm

12

C2729

C2731

12

21

C2733

0.1UF/10V

L27051kOhm/ 100Mhz @

1

2

D2702
1V/0.2A

GND

R2712

3

1 2

10Ohm

12

GND

SP2707 NB_R0402_20MIL_SMALL

1 2

+VTT_PCH_ORG

+3VSUS_ORG

Title :

Title :

Title :

Engineer:

Engineer:

Engineer:

1

+3VSUS_ORG

+5VSUS_ORG

+3VS

+5VS

+3VS_VCC3_3

PCH(8)_POWER,GND

PCH(8)_POWER,GND

PCH(8)_POWER,GND

Trunks Chen

Trunks Chen

Trunks Chen

Rev

Rev

Rev

1.0

1.0

1.0

of

of

of

27 59Wednesday, February 01, 2012

27 59Wednesday, February 01, 2012

27 59Wednesday, February 01, 2012