Asus A6F Schematic

5

4

3

2

1

FAN + SENSOR

A6F Block

PAGE 4

CLOCK GEN

Diagram

D D

PAGE 2,3

CPU

YONAH-2M

ICS954310

PAGE 5

DISCHARGER
CIRCUIT

PAGE 36

Power On Sequence

FSB
667MHz

PAGE 39

DEBUG PORT

LVDS & INV

PAGE 12

CRT & TV OUT

C C

PAGE 13

MCH-M

Calistoga
945GM

B0:02G010009121

PAGE 6,7,8,9,10,11

DDR2-667

Dual Channel DDR2

SO-DIMM X 2

PAGE 14,15,16

DMI interface

PCIE *1

MINI CARD

WLAN

PRINT PORT

PAGE 44

KEYPAD
MATRIX

PAGE 37

INSTANT KEY

PAGE 37

B B

SUPER I/O
SMSC

LN47N217

PAGE 25

EC IT8510E

PAGE 28,29

LPC
33MHz

Azalia

ICH7-M

B0:02G010008811

PAGE
17,18,19,20

IDE

USB

PCI
33MHz

PAGE 26

10/100/1000LAN

RTL8110SBL

PAGE 33,34

CardBus

R5C841

PAGE 30

PAGE 31

PAGE 32

PAGE 41

CPU VCORE

PAGE 50

SYSTEM PWR

PAGE 51

BAT & CHARGER

PAGE 57

PCMCIA

1394

CARD READER

LED Control

PAGE 37

PAGE 24

ISA
ROM

Azalia Codec

ALC660

PAGE 21,22,23

PAGE 27

PAGE 27

HDD

ODD

USB 2.0
CON X4

PAGE 35

Bluetooth

PAGE 26

Mini PCI

PAGE 38

PAGE 32

MDC

A A

5

Connector

PAGE 34

Camera

PAGE 12

Title :

ASUSTeK COMPUTER INC

Size Project Name

A3

4

3

2

Date: Sheet of

A6F

Monday, March 06, 2006

Engineer:

BLOCK DIAGRAM

Jack WANG

1

Rev

163

1.1

5

H_A#[16..3]6
H_REQ#[4..0]6
H_A#[31..17]6

4

3

2

1

T200

J4

L4
M3
K5
M1
N2

J1
N3
P5
P2

L1
P4
P1
R1

L2
K3

H2
K2

J3

L5
Y2

U5
R3

W6

U4
Y5
U2
R4

T5

T3

W3
W5

Y4

W2

Y1
V4

A6
A5
C4

D5
C6
B4
A3

AA1
AA4
AB2
AA3

M4
N5

T2
V3
B2
C3

B25

U200A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
RSVD[10]

RSVD[11]

SOCKET479P

ADS#
BNR#

BPRI#

ADDR GROUP 0

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

ADDR GROUP 1

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA

THERMDC

THERMTRIP#

THERMHCLKRESERVED

BCLK[0]
BCLK[1]

RSVD[12]
RSVD[A2]

RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]
RSVD[18]
RSVD[19]
RSVD[20]

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
B1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
A25

C7

A22
A21

T22
A2

D2
F6
D3
C1
AF1
D22
C23
C24

H_A#3

D D

H_ADSTB#06

C C

H_ADSTB#16
H_A20M#17

H_FERR#17
H_IGNNE#17

H_STPCLK#17
H_INTR17
H_NMI17
H_SMI#17

B B

H_A#4
H_A#6

H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1 H_PROCHOT_S#

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

12G04600479A

1

H_ADS#
H_BNR#
H_BPRI#H_A#5

H_DEFER#
H_DRDY#
H_DBSY#

H_BR0#
H_IERR#

H_INIT#
H_LOCK#
H_CPURST#

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_HIT#
H_HITM#

PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
CPU_DBR#

CPU_THRM_DA
CPU_THRM_DC

PM_THRMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS# 6
H_BNR# 6
H_BPRI# 6

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6

H_BR0# 6

H_INIT# 17
H_LOCK# 6
H_CPURST# 6

H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY# 6

H_HIT# 6
H_HITM# 6

+VCCP_AGTL+

T202

1

R203 56Ohm /
R204 56Ohm

1 2

R205 56Ohm

1 2

R217 56Ohm /
R206 56Ohm

1 2

R207 56Ohm

1 2

CPU_THRM_DA 4
CPU_THRM_DC 4

PM_THRMTRIP# 4,7,17

CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5

68 ± 5% pull-up to Vcc1_05
If PROCHOT# is not used, then it must be terminated with a
56 pull-up resistor to VCCP.
If PROCHOT# is routed between CPU, IMVP and MCH,
pull-up resistor has to be 75 Ohm ± 5%

1

T201

GND

1

TPC28T

R201
56Ohm

R202

54.9Ohm /

T204

12

+VCCP_AGTL+

+VCCP_AGTL+

C200

0.1UF/10V

N/A

GND

+VCCP_AGTL+

12

R211

2KOhm

1%

R200

1KOhm

1%

1 2

<500 mil (55 Ohm)
T/B trace 5.5
Space 25

1 2

GND

GND

CPU_BSEL05
CPU_BSEL15
CPU_BSEL25

166 L667

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_DSTBN#06
H_DSTBP#06
H_DINV#06

H_DSTBN#16
H_DSTBP#16
H_DINV#16

R212

1KOhm

R214

/

51Ohm

FSB
533

H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

GTL_REF

TEST1

1 2

TEST2

1 2

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

BSEL2BCLK BSEL1HBSEL0

L

U200B

E22

D[0]#

F24

D[1]#

E26

D[2]#

H22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H26

D[12]#

F26

D[13]#

K22

D[14]#

H25

D[15]#

H23

DSTBN[0]#

G22

DSTBP[0]#

J26

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L25

D[20]#

L22

D[21]#

L23

D[22]#

M23

D[23]#

P25

D[24]#

P22

D[25]#

P23

D[26]#

T24

D[27]#

R24

D[28]#

L26

D[29]#

T25

D[30]#

N24

D[31]#

M24

DSTBN[1]#

N25

DSTBP[1]#

M26

DINV[1]#

AD26

GTLREF

C26

TEST1

D25

TEST2

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

SOCKET479P

12G04600479A

12G04600479A

HL133

DATA GRP 0

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DATA GRP 1

DSTBN[3]#
DSTBP[3]#

MISC

DPRSTP#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

DINV[2]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPSLP#
DPWR#

SLP#

PSI#

AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23

AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20

R26
U26
U1
V1

E5
B5
D24
D6
D7
AE6

H

H_D#[0..63] 6

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

H_COMP0

R208 27.4Ohm 1%

H_COMP1

R209 54.9Ohm 1%

H_COMP2

R210 27.4Ohm 1%

H_COMP3

R213 54.9Ohm 1%

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD

H_CPUSLP#
PM_PSI#

1

H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6

Layout Note:
Comp0,2 connect with Z0=27.4 ohm,
make trace length shorter than 0.5".
Comp1,3 connect with Z0=54.9 ohm,
make trace length shorter than 0.5".
Comp[3:0] at least 25 mils away from
any other toggling signal.

27.4 ohm connects with an ~18mil
wide trace to comp0.

54.9 ohm connect with 5mil-wide
to comp1

H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6

1 2
1 2
1 2
1 2

H_DPRSTP# 17,50
H_DPSLP# 17
H_DPWR# 6
H_PWRGD 17

T205

H_CPUSLP# 6,17
PM_PSI# 50

GND

+VCCP_AGTL+ +VCCP

JP200

1 2

SHORT_PIN

/

2.5A

+VCCP

+VCCP_AGTL+

A A

5

+VCCP 6,9,20,52
+VCCP_AGTL+ 3,5,6,9

H_PROCHOT_S#28

H_PROCHOT_S# H_PWRGD

4

+VCCP_AGTL+

R215

56Ohm

3

+VCCP_AGTL+

R216

56Ohm /

Title :

YONAH CPU (1)

1

Jack Wang

263

Rev

1.0

ASUSTeK COMPUTER INC

Size Project Name

Custom

2

Date: Sheet of

A6F

Monday, March 06, 2006

Engineer:

5

4

3

2

1

YUNAH FSB667
LFM TYP HFM
VCC 1.14V 1.2V 1.356V
C4 C3 C0
ICC 0.9A 7.59A 27A

D D

+VCORE

U200C

A7

VCC[1]

A9

VCC[2]

A10

VCC[3]

A12

VCC[4]

A13

VCC[5]

A15

VCC[6]

A17

VCC[7]

A18

VCC[8]

A20

VCC[9]

B7

VCC[10]

B9

VCC[11]

B10

VCC[12]

B12

VCC[13]

B14

VCC[14]

B15

VCC[15]

B17

VCC[16]

B18

VCC[17]

B20

VCC[18]

C9

VCC[19]

C10

VCC[20]

C12

VCC[21]

C13

VCC[22]

C15

VCC[23]

C17

VCC[24]

C18

C C

B B

VCC[25]

D9

VCC[26]

D10

VCC[27]

D12

VCC[28]

D14

VCC[29]

D15

VCC[30]

D17

VCC[31]

D18

VCC[32]

E7

VCC[33]

E9

VCC[34]

E10

VCC[35]

E12

VCC[36]

E13

VCC[37]

E15

VCC[38]

E17

VCC[39]

E18

VCC[40]

E20

VCC[41]

F7

VCC[42]

F9

VCC[43]

F10

VCC[44]

F12

VCC[45]

F14

VCC[46]

F15

VCC[47]

F17

VCC[48]

F18

VCC[49]

F20

VCC[50]

AA7

VCC[51]

AA9

VCC[52]

AA10

VCC[53]

AA12

VCC[54]

AA13

VCC[55]

AA15

VCC[56]

AA17

VCC[57]

AA18

VCC[58]

AA20

VCC[59]

AB9

VCC[60]

AC10

VCC[61]

AB10

VCC[62]

AB12

VCC[63]

AB14

VCC[64]

AB15

VCC[65]

AB17

VCC[66]

AB18

VCC[67]

SOCKET479P

12G04600479A

VCCSENSE

VSSSENSE

VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
VCC[77]
VCC[78]
VCC[79]
VCC[80]
VCC[81]
VCC[82]
VCC[83]
VCC[84]
VCC[85]
VCC[86]
VCC[87]
VCC[88]
VCC[89]
VCC[90]
VCC[91]
VCC[92]
VCC[93]
VCC[94]
VCC[95]
VCC[96]
VCC[97]
VCC[98]
VCC[99]

VCC[100]

VCCP[1]
VCCP[2]
VCCP[3]
VCCP[4]
VCCP[5]
VCCP[6]
VCCP[7]
VCCP[8]

VCCP[9]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26

AD6
AF5
AE5
AF4
AE3
AF2
AE2

AF7

AE7

YUNAH FSB667
Min Typ Max
VCCP 0.997V 1.05V 1.102V
Min Typ Max
ICCP 2.5A

+VCORE

+VCCP_AGTL+

+VCCA

120mA / 20mil
Close to Pin B26

12

10UF/10V

H_VID0

1 2

H_VID1

H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

VCCSENSE

VSSSENSE

0Ohm

3 4

0Ohm

5 6

0Ohm

7 8

0Ohm

1 2

0Ohm

3 4

0Ohm

5 6

0Ohm

12

R300
100Ohm

7 8

C325

GND

RN301A
RN301B
RN301C
RN301D
RN302A
RN302B
RN302C

R301

1 2

100Ohm

RN302D

0Ohm

12

C300

0.01UF/16V

checklist suggests
10uF POSCAP

VR_VID0 50
VR_VID1 50
VR_VID2 50
VR_VID3 50
VR_VID4 50
VR_VID5 50
VR_VID6 50

+VCORE
VCCSENSE 50

VSSSENSE 50

U200D

A4

VSS[1]

A8

VSS[2]

A11

VSS[3]

A14

VSS[4]

A16

VSS[5]

A19

VSS[6]

A23

VSS[7]

A26

VSS[8]

B6

VSS[9]

B8

VSS[10]

B11

VSS[11]

B13

VSS[12]

B16

VSS[13]

B19

VSS[14]

B21

VSS[15]

B24

VSS[16]

C5

VSS[17]

C8

VSS[18]

C11

VSS[19]

C14

VSS[20]

C16

VSS[21]

C19

VSS[22]

C2

VSS[23]

C22

VSS[24]

C25

VSS[25]

D1

VSS[26]

D4

VSS[27]

D8

VSS[28]

D11

VSS[29]

D13

VSS[30]

D16

VSS[31]

D19

VSS[32]

D23

VSS[33]

D26

VSS[34]

E3

VSS[35]

E6

VSS[36]

E8

VSS[37]

E11

VSS[38]

E14

VSS[39]

E16

VSS[40]

E19

VSS[41]

E21

VSS[42]

E24

VSS[43]

F5

VSS[44]

F8

VSS[45]

F11

VSS[46]

F13

VSS[47]

F16

VSS[48]

F19

VSS[49]

F2

VSS[50]

F22

VSS[51]

F25

VSS[52]

G4

VSS[53]

G1

VSS[54]

G23

VSS[55]

G26

VSS[56]

H3

VSS[57]

H6

VSS[58]

H21

VSS[59]

H24

VSS[60]

J2

VSS[61]

J5

VSS[62]

J22

VSS[63]

J25

VSS[64]

K1

VSS[65]

K4

VSS[66]

K23

VSS[67]

K26

VSS[68]

L3

VSS[69]

L6

VSS[70]

L21

VSS[71]

L24

VSS[72]

M2

VSS[73]

M5

VSS[74]

M22

VSS[75]

M25

VSS[76]

N1

VSS[77]

N4

VSS[78]

N23

VSS[79]

N26

VSS[80]

P3

VSS[81]

SOCKET479P

12G04600479A

VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24

+VCORE

+VCCP_AGTL+

+VCORE

+1.5VS

+VCCP_AGTL+ 2,5,6,9
+VCORE 50

+1.5VS 9,10,20,26,36,42,52

Place these caps on North of Secondary side

12

C301

22UF/6.3V

12

C302

22UF/6.3V

12

C303

22UF/6.3V

12

C304

22UF/6.3V

12

C305

22UF/6.3V

12

C306

22UF/6.3V

12

C307

22UF/6.3V

GNDGNDGNDGNDGNDGNDGNDGND

12

C308
22UF/6.3V

c0805

Place these caps on North of Primary side

12

C310

22UF/6.3V

12

C321

22UF/6.3V

12

22UF/6.3V

12

22UF/6.3V

GND

C311

C322

22UF/6.3V

GNDGND GNDGNDGND

12

22UF/6.3V

GND

C312

C323

GNDGNDGND

C313
22UF/6.3V

c0805

12

C324
22UF/6.3V

c0805

+VCCP_AGTL+

12

C314

c0402

0.1UF/10V

+1.05V Decoupling Capacitor
Place near CPU

12

12

12

C315

c0402

0.1UF/10V

12

C316

c0402

0.1UF/10V

C317

c0402

0.1UF/10V

C318

c0402

0.1UF/10V

12

0.1UF/10V

C319

c0402

GND

12

+

CE301
470UF/2.5V

c7343d_h75

12

C309

22UF/6.3V

Place these caps on South of Primary side

12

C320

22UF/6.3V

12

12

Place these caps on South of Secondary side

12

C327

C326

22UF/6.3V

22UF/6.3V

GNDGND

GND

GNDGND

C329

C328

22UF/6.3V

22UF/6.3V

GND GND GND GND

12

12

12

12

C330

22UF/6.3V

12

C331

22UF/6.3V

12

C332

22UF/6.3V

GND

12

C333
22UF/6.3V

c0805

GND

Layout Note:
VCCSENSE/VSSSENSE lines between the
CPU and the VR should have a trace width of

A A

5

18 mils on 7 mils spacing, with trace
impedance of Zo=27.4 Ohm.
The VCCSENSE/VSSSENSE should be
length matched to within 25 mils.
These resistors should be placed within 2
inch of the CPU.

Title :

ASUSTeK COMPUTER INC

Size Project Name

A3

4

3

2

Date: Sheet of

A6F

Monday, March 06, 2006

Engineer:

1

Yonah CPU (2)

Jack Wang

363

Rev

1.0

5

4

3

2

1

+12V
+5VS
+3VS

+V5S_FAN

45

HOLD1

1
2
3

HOLD2

GND

12G170000039

R412

1 2

330Ohm

+3VA

CON9

WTOB_CON_3P

GND

1219

CPU_THRM_DA 2

CPU_THRM_DC 2

Fan Speed Control

D D

KBC will issue a
analog ( a voltage
level ) signal.

SW: FAN_DA1 must
be low during S3

R404

Q402
2N7002

+3VS

/

1

1

G

RN400A
RN400B

1 2

14.7KOhm

32

3

D

S

2

GND GND

1 2

10KOhm

3 4

10KOhm

FAN0_DA28

DLY_OP_SD22

C C

OVER_TEMP#28

B B

Route H_THERMDA and H_THERMDC
on the same layer

------------------OTHER SIGNALS
12 mils
===============GND
10 mils
=========H_THERMDA(10 mils)
10 mils

A A

=========H_THERMDC(10 mils)
10 mils
=========GND
12 mils

---------------------OTHER SIGNALS

1%

R406
10KOhm

r0402
/

THERM#

+V5S_FAN

12

GND

GND

Using a OP AMP and fine-tuning
the level, we can improve the fan
speed accuracy.

12

12

R401
10KOhm

r0402

FAN_A1
FAN_A2

GND

R407
15KOhm

1%

U402

A

1

B

2
3 4

GND

NC7SZ08P5X

06G004600811

1 2

THRM_CPU#28

R410

0Ohm

r0402
/

C401 1000PF/50V

1 2

c0402

+12V

U401

A+

3

8

VCC

+

1

A-

AO

2

-

B+

5

+

BO

7

B-

4

6

-

GND

VCC

LM358MX

5

Y

+3VS

+3VS

AND_OVER_TEMP#

+3VA_EC

R413
10KOhm

r0402

1 2

GND

3 2

GND

Q400

3

D

2N7002

12

R405
10KOhm

r0402
/

RN400C

5 6

10KOhm

AND_OVER_TEMP#

+5VS

1

1

G

2

S

1 2

+3VS

+5VS

12

C400

0.1UF/10V

c0402

GND GND

R402

FAN_PWR_GFAN_OP

330Ohm

FAN_PWR_G2

Q404B
UM6K1N

5

SMB1_CLK28
SMB1_DAT28

1 2

R414

4.7KOhm

r0402

Q401

SI2301BDS_T1_E3

2 3

S

2

2

34

GND

GND

78

RN400D
10KOhm

+3VS

R400

1 2

0Ohm

r0402

SMB1_CLK
SMB1_DAT
SMBALERT#

D

3

G

1

1

61

Q404A
UM6K1N

12

C402
22UF/6.3V

c0805

+3VS_THM

12

C405

0.1UF/10V

c0402

U400

8
7
6
5

MAX6657MSA

SCLK
SDA
ALERT#
GND

+V5S_FAN

D400

1N4148W

1 2

GND

When fan speed is very slow, after RC
integrator the level of FANSP1 will be
very low that may make south bridge do the
wrong detection.

+3VS_THM

Standby Mode: 3uA(Max. 10uA)
Full Active: 0.5 mA(Max. 1mA)

1

VCC

2

DXP

3

DXN

4

OVERT#

+3VS_THM

CPU_THRM_DA
CPU_THRM_DC

THERM#

CPU FAN

FANSP1

12

C403

c0402

100PF/50V

GND

PM_THRMTRIP#2,7,17

4"-8"

12

C406
2200PF/50V

4"-8"

Avoid BPSB,Power

5

4

3

2

+12V 32,36,61
+5VS 13,19,20,21,22,27,28,36,37,38,44,50,61
+3VS 5,7,9,11,12,13,14,15,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61
+3VA 12,20,28,37,39,54,59,63

+3VS

12

FANSPFANSP1

+3VA

12

32

3

D

S

2

GND

A6F

PMBS3904

R409
10KOhm

r0402
/

VSUS_ON

Q405
2N7002

Q403

B

1

GND

Engineer:

TRIP_R

Q406

B

1

PMBS3904

R408

1 2

22kOhm

r0402

11/29

+3VS

12

R411
1MOhm

VSUS_ON_G

3

C

E
2

GND

ASUSTeK COMPUTER INC

Date: Sheet of

1

1

G

12

C404

0.22UF/6.3V

GND

Size Project Name

A3

Monday, March 06, 2006

R403
10KOhm

r0402

3
C

E
2

VSUS_ON 28,51

Title :

THER-SENSOR,FAN

1

FAN0_TACH 28

Jack Wang

Rev

463

1.0

5

+VCCP_AGTL+

Request

PCIE_REQ1# PCIE0(#),PCIE6(#)

PCIE_REQ2#

PCIE_REQ3#

D D

PCIE_REQ4#

C C

B B

CLK_MINIPCI

SELPCIE0_LCD#:
0-->pin17,pin18=LCDCLK(96MHz) or
27M/27M_SS

A A

SELLCD_27#/PCICLK_F1:
1-->pin17,pin18=LCDCLK(96MHz)

Control net

PCIE1(#),PCIE8(#)

PCIE2(#),PCIE4(#)

PCIE3(#),PCIE5(#),
PCIE7(#)

CLK_LCD_SSCG7
CLK_LCD_SSCG#7
CLK_USB4819

CPU_BSEL02
CPU_BSEL12

CLK_LAN_PCI33
CLK_CBPCI30
CLK_SIOPCI25
CLK_ECPCI28

CLK_ICHPCI18
SMB_CLK_S14,15,19,26
SMB_DAT_S14,15,19,26

R562
10Ohm

12

R561

4.7OHM

2/23/06

Net name

None

None

CLK_PCIE_MINICARD(#)

CLK_MCH_3GPLL(#)

X500

14.318Mhz

12

12

C515

27PF/50V

GND

CLK_MINIPCI

CLK_MINIPCI_D 38

CLK_DEBUG 41

GND

12

12

C513

C514

10UF/10V

0.1UF/10V

12

27PF/50V

C520 10PF/50V

/

1 2

GND

C516

/

C518 10PF/50V

C519 10PF/50V

/

1 2

1 2

GND

GND

+3VS_CLK

+3VS_CLK
+3VS_CLK

C522 10PF/50V

C517 10PF/50V

C523 10PF/50V

C521 10PF/50V

/

/

/

/

1 2

1 2

1 2

1 2

Realtek:Mount R519,Remove R550 R534

4

R501

/

12

/

12

/

12

/

12

+3VS_CLK

12

GND

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

R519

1 2

0Ohm r0402 /

R553
475Ohm

GND

1KOhm
R503

1KOhm
R504

1KOhm
R505

1KOhm

R516

2.2Ohm

R529 33Ohm

1 2

R530 33Ohm

1 2

R533 33Ohm

1 2

R534 2.2KOhm

1 2

R535 33Ohm

1 2

R536 10KOhm

1 2

R546 33Ohm

1 2

R540 33Ohm

1 2

R542 33Ohm

1 2

R544 10KOhm

1 2

R548 10KOhm

1 2

R549 33Ohm

1 2

R550 10KOhm

1 2

+3VS_VDDA

ICS_X1
ICS_X2
LCD_SSCG
LCD_SSCG#
FSA

PCICLK5
PCICLK4
PCICLK3
PCICLK2

PCICLK_F1
PCICLK_F0

ICS_IREF

1 2

ICS_34

R502 0Ohm

1 2

R500 0Ohm

1 2

R506 0Ohm

1 2

GND

MCH_BSEL0 7

MCH_BSEL1 7

MCH_BSEL2 7

+3VS

12

12

C501

0.1UF/10V

GND

C502

0.1UF/10V

Pin34 is PWRSAVE#

U500

21

VDDPCIEX1

28

VDDPCIEX2

42

VDDPCIEX3

34

VDD

50

VDDCPU

45

VDDA

46

GNDA

58

X1

57

X2

17

27FIX/LCD_SSCGT/PCIEX0T

18

27SS/LCD_SSCGC/PCIEX0C

12

FSLA/USB_48MHz

16

FSLB/TEST_MODE

5

SELPCIEX0_LCD#PCICLK5

4

PCICLK4

3

PCICLK3

64

PCICLK2/REQ_SEL

9

SELLCD_27#/PCICLK_F1

8

ITP_EN/PCICLK_F0

54

SCLK

55

SDATA

47

IREF

2

GND1

6

GND2

13

GND3

29

GND4

37

GND5

53

GND6

59

GND7

3

120Ohm/100Mhz

21

L501
120Ohm/100Mhz

+3VS_VDDPCI

1

7

VDDPCI1

VDDPCI2

CPUCLKT2_ITP/PCIEXT8

CPUCLKC2_ITP/PCIEXC8

internal
pull high

REF1/FSLC/TEST_SEL

Bclk BSEL0FSB

133

533
667

166

L500

21

12

12

C507

0.1UF/10V

0.1UF/10V

VDD48

VDDREF

PCI/PCIEX_STOP#

CPU_STOP#

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

PEREQ1#/PCIEXT7
PEREQ2#/PCIEXC7

PCIEXT6
PCIEXC6

PCIEXT5
PCIEXC5

PCIEXT4
PCIEXC4

PCIEXT3
PCIEXC3

PCIEXT2
PCIEXC2

PCIEXT1
PCIEXC1

SATACLKT
SATACLKC

DOTT_96MHz
DOTC_96MHz

PEREQ3#
PEREQ4#

Vtt_PwrGd#/PD

FSLC FSLB FSLA

BSEL1

BSEL2

L
LHHLH

+3VS_CLK

12

12

12

C504

0.1UF/10V

0.1UF/10V

C509

R512

2.2Ohm

+3VS_VDD48
+3VS_VDDREF
STP_PCI#
STP_CPU#

CLK_MCH

R522 33Ohm

CLK_MCH#

R523 33Ohm

CLK_CPU

R525 33Ohm

CLK_CPU#

R526 33Ohm

PCIE7

R531 10KOhm

PCIE#7

R532 10KOhm

PCIE4

R538 33Ohm

PCIE#4

R539 33Ohm

PCIE3

R541 33Ohm

PCIE#3

R543 33Ohm

PCIE2

R545 56Ohm

PCIE#2

R547 56Ohm

DOT96

R551 33Ohm

DOT96#

R552 33Ohm

R554 10KOhm

PEREQ4#

R557 10KOhm

R558 2.2KOhm

REF1

R559 33Ohm

REF0

R560 33Ohm

REF0

10UF/10V

C508

C503

11
56
63
62

49
48

52
51

44
43

41
40

39
38

36
35

30
31

24
25

22
23

19
20

26
27

14
15

32
33

10

61
60

GND

12

10UF/10V

12

C505

0.1UF/10V

12

0.1UF/10V

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

2/23/06

1 2
1 2

R556 0Ohm

1 2

1 2
1 2

+3VS_CLK

C500

GND

C510

GND

STP_PCI# 19
STP_CPU# 19,50

12

/

12
12

/

+VCCP_AGTL+

12

C506

0.1UF/10V

12

C511

10UF/6.3V

GND

+3VS

+3VS

2

+3VS

R513
1Ohm

1 2

CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6

CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2

CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7

CLK_PCIE_MINICARD 26
CLK_PCIE_MINICARD# 26

CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18

CLK_UMA_96M 7
CLK_UMA_96M# 7

MCH_CLK_REQ# 7
CLKREQ# 26

CPU_BSEL2 2

CLK_14_SIO 25
CLK_ICH14 19

+VCCP_AGTL+ 2,3,6,9
+3VS 4,7,9,11,12,13,14,15,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61

C512

1 2

0.1UF/10V

+3VS_CLK

12

R555
10KOhm

/

GND

Layout Note:
Place termination close to source IC

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_LCD_SSCG
CLK_LCD_SSCG#

CLK_UMA_96M
CLK_UMA_96M#

CLK_PCIE_MINICARD
CLK_PCIE_MINICARD#

PREQ#1
0=PCIEX 6/0 Not Controlled
1=PCIEX 6/0 Controlled

PREQ#2
0=PCIEX 8/1 Not Controlled
1=PCIEX 8/1 Controlled

PREQ#3
0=PCIEX 4/2 Not Controlled
1=PCIEX 4/2 Controlled

PREQ#4
0=PCIEX 7/5/3 Not Controlled
1=PCIEX 7/5/3 Controlled

CLK_EN# 50

1

R507 49.9Ohm

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

r0402
r0402

r0402
r0402

r0402
r0402

r0402
r0402

r0402
r0402

r0402
r0402

r0402
r0402

R508 49.9Ohm

R509 49.9Ohm
R510 49.9Ohm

R511 49.9Ohm
R514 49.9Ohm

R515 49.9Ohm
R517 49.9Ohm

R518 49.9Ohm
R520 49.9Ohm

R521 49.9Ohm
R524 49.9Ohm

R527 49.9Ohm
R528 49.9Ohm

GND

Internal Pull-Up Resistor

PCICLK2/REQ_SEL:
1-->pin40,pin41=PREQ1#,PREQ2#

ITP_EN/PCICLK_F0:
1-->CPU_ITP pair

5

Internal Pull-Down Resistor

4

3

2

ASUSTeK COMPUTER INC

Size Project Name

Custom

Date: Sheet

A6F

Title :

Engineer:

1

CLOCK GEN

Jack Wang

563Monday, March 06, 2006

of

Rev

1.1

5

H_D#[0..63]2 H_A#[31..3] 2

H_D#0
H_D#1
H_D#2
H_D#3

5

H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

CLK_MCH_BCLK
CLK_MCH_BCLK#

D D

C C

B B

CLK_MCH_BCLK5

A A

CLK_MCH_BCLK#5

U600A

F1
J1
H1
J6
H3

K2
G1
G2
K9
K1
K7

J8
H4

J3

K11

G4

T10

W11

T3
U7
U9

U11
T11

W9

T1

T8

T4

W7

U5

T9

W6

T5

AB7
AA9

W4
W3

Y3
Y7

W5
Y10
AB8

W2
AA4
AA7
AA2
AA6

AA10

Y8
AA1
AB4

AC9
AB11
AC11

AB3

AC2

AD1

AD9

AC1

AD7

AC6

AB5
AD10

AD4

AC8

E1
E2
E4

Y1
U1

W1

AG2
AG1

CALISTOGA_Q137

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_XRCOMP
H_XSCOMP
H_XSWING

H_YRCOMP
H_YSCOMP
H_YSWING

H_CLKIN
H_CLKIN#

HOST

4

H_ADSTB#_0
H_ADSTB#_1

H_CPURST#

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_SLPCPU#

4

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_ADS#

H_AVREF

H_BNR#

H_BPRI#

H_BREQ#0

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#
H_DVREF

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_TRDY#

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13

J7
W8
U3
AB10

K4
T7
Y5
AC4

K3
T6
AA5
AC5

D3
D4
B3

D8
G8
B8
F8
A8

B4
E6
D6

E3
E7

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_HIT#
H_HITM#
H_LOCK#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

N_CPUSLP#
H_TRDY#

H_ADS# 2
H_ADSTB#0 2
H_ADSTB#1 2

H_BNR# 2
H_BPRI# 2
H_BR0# 2
H_CPURST# 2
H_DBSY# 2
H_DEFER# 2
H_DPWR# 2
H_DRDY# 2

H_DINV#0 2
H_DINV#1 2
H_DINV#2 2
H_DINV#3 2

H_DSTBN#0 2
H_DSTBN#1 2
H_DSTBN#2 2
H_DSTBN#3 2

H_DSTBP#0 2
H_DSTBP#1 2
H_DSTBP#2 2
H_DSTBP#3 2

H_HIT# 2
H_HITM# 2
H_LOCK# 2

R600
0Ohm

12

3

+VCCP_AGTL+

<500 mil (55 Ohm)
T/B trace 5.5 ,
Space 25

12

C601

0.1UF/10V

GND

GND

R605
100Ohm

1%

1 2

R606
200Ohm

1%

1 2

Layout Note:

0.1uF should be placed 100mils or
less from GMCH pin.

H_REQ#[4..0] 2

H_RS#[0..2] 2

H_CPUSLP# 2,17
H_TRDY# 2

3

2

+VCCP

1 2

1 2

GND

+VCCP

1 2

1 2

GND

+VCCP

1 2

1 2

GND

2

R601

54.9Ohm

1%

H_XSCOMP

H_XRCOMP

R603

24.9Ohm

1%

R607
221Ohm

1%

R608
100Ohm

1%

R609
221Ohm

1%

R610
100Ohm

1%

+VCCP

+VCCP_AGTL+

+VCCP

R602

54.9Ohm

1%

H_YSCOMP

1 2

H_YRCOMP

R604

24.9Ohm

1%

1 2

GND

10/20mils

12

GND

5.5/20 mils

10/20mils

H_XSWING

C602

0.1UF/10V

Signal voltage level =

0.3125*VCCP
Trace should be 10 mil wide
with 20 mil spacing

H_YSWING

12

C600

0.1UF/10V

GND

ASUSTeK COMPUTER INC

Size Project Name

B

Date: Sheet

Monday, March 06, 2006

A6F

1

+VCCP 2,9,20,52
+VCCP_AGTL+ 2,3,5,9

Title :

Engineer:

1

Calistoga MCH (1)

Jack Wang

663

Rev

1.0

of

5

4

3

2

1

+3VS

L_BKLTCTL12

R702 10KOhm

1 2

R703 10KOhm

1 2

R704 10KOhm

1 2

R705 10KOhm

1 2

D D

1 2

GND

C C

GND

B B

A A

DAC_HSYNC_GM
DAC_VSYNC_GM

R700

1.5KOhm

1%

L_BKLTEN

R708
100KOhm

R713 150Ohm
R714 150Ohm
R715 150Ohm

GND

R718 150Ohm
R719 150Ohm
R720 150Ohm

GND

LVDS_L0N
LVDS_L2N
LVDS_L0P

LVDS_L1P
LVDS_L2P

LVDS_U0N
LVDS_U1N
LVDS_U2N

LVDS_U0P
LVDS_U1P
LVDS_U2P

12

GND

1 2
1 2

T702

GND

R716

4.99KOhm

1%

R721
39Ohm

R722
39Ohm

5

L_BKLTCTL
L_BKLTEN
L_CTLA_CLK
L_CTLB_DATA
EDID_CLK
EDID_DAT
L_IBG
L_VBG

1

L_VDDEN

LVDS_LCLKN
LVDS_LCLKP
LVDS_UCLKN
LVDS_UCLKP

LVDS_L0N
LVDS_L1N
LVDS_L2N

LVDS_L0P
LVDS_L1P
LVDS_L2P

LVDS_U0N
LVDS_U1N
LVDS_U2N

LVDS_U0P
LVDS_U1P
LVDS_U2P

TV_DACA_OUT_L

12

TV_DACB_OUT_L

12

TV_DACC_OUT_L

12

1%

TV_IREF

12

BLUE_L

12

1%

GREEN_L

12

1%

RED_L

12

1%

CRT_DDC_CLK
CRT_DDC_DATA

N_HSYNC
N_VSYNC

R723
255Ohm

1%

LVDS_L0N 12
LVDS_L1N 12
LVDS_L2N 12

LVDS_L0P 12
LVDS_L1P 12
LVDS_L2P 12

LVDS_U0N 12
LVDS_U1N 12
LVDS_U2N 12

LVDS_U0P 12
LVDS_U1P 12
LVDS_U2P 12

GND

CRT_IREF

12

GND

U600C

D32

J30
H30
H29
G26
G25
B38
C35
F32
C33
C32

A33
A32
E27
E26

C37
B35
A37

B37
B34
A36

G30
D30
F29

F30
D29
F28

A16
C18
A19

J20
B16
B18
B19

E23
D23
C22
B22
A21
B21

GND

C26
C25
G23

J22
H23

CALISTOGA_Q137

L_BKLTCTL
L_BKLTEN
L_CLK_CTLA
L_DATA_CTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL

LA_CLK#
LA_CLK
LB_CLK#
LB_CLK

LA_DATA#_0
LA_DATA#_1
LA_DATA#_2

LA_DATA_0
LA_DATA_1
LA_DATA_2

LB_DATA#_0
LB_DATA#_1
LB_DATA#_2

LB_DATA_0
LB_DATA_1
LB_DATA_2

TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT

TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC

LVDS_LCLKN
LVDS_LCLKPLVDS_L1N
LVDS_UCLKN
LVDS_UCLKP

L_BKLTEN
EDID_CLK

EDID_DAT
L_VDDEN

DAC_HSYNC_GM
DAC_VSYNC_GM

CRT_DDC_CLK
CRT_DDC_DATA

LVDS

TV

VGA

LVDS_LCLKN 12
LVDS_LCLKP 12
LVDS_UCLKN 12
LVDS_UCLKP 12

L_BKLTEN 12
EDID_CLK 12

EDID_DAT 12
L_VDDEN 12

EXP_A_COMPI

EXP_A_COMPO

EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8

EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15

EXP_A_RXP_0

EXP_A_RXP_1

EXP_A_RXP_2

EXP_A_RXP_3

EXP_A_RXP_4

EXP_A_RXP_5

EXP_A_RXP_6

EXP_A_RXP_7

EXP_A_RXP_8

EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15

EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8

EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12

PCI-EXPRESS GRAPHICS

EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15

EXP_A_TXP_0

EXP_A_TXP_1

EXP_A_TXP_2

EXP_A_TXP_3

EXP_A_TXP_4

EXP_A_TXP_5

EXP_A_TXP_6

EXP_A_TXP_7

EXP_A_TXP_8

EXP_A_TXP_9

EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15

CRT_DDC_CLK 13
CRT_DDC_DATA 13

4

D40
D38

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

EXP_A_COMP

TV_DACA_OUT_L

TV_DACB_OUT_L

TV_DACC_OUT_L

RED_L

GREEN_L

BLUE_L

+1.5VS_PCIE

R701

1 2

24.9Ohm

1%

PM_DPRSLPVR19,50

MCH_ICH_SYNC#18
MCH_CLK_REQ#5

put at pin1
of 150 Ohm

JP701 SHORT_PIN

1 2

JP702 SHORT_PIN

1 2

JP703 SHORT_PIN

1 2

JP704 SHORT_PIN

1 2

JP705 SHORT_PIN

1 2

JP706 SHORT_PIN

1 2

PM_BMBUSY#19

PM_THRMTRIP#2,4,17
ICH7_PWROK19,28

PLT_RST#18,19,27,28

+3VS

MCH_BSEL05
MCH_BSEL15
MCH_BSEL25

MCH_CFG_511
MCH_CFG_711
MCH_CFG_911
MCH_CFG_1111

MCH_CFG_1611
MCH_CFG_1811

MCH_CFG_1911

R706

1 2

10KOhm
R707

1 2

10KOhm

R724 0Ohm

TV_DACA_OUT

TV_DACB_OUT

TV_DACC_OUT

RED

GREEN

BLUE

PM_EXTTS#0

PM_EXTTS#1

1 2

/

3

T703

1

T704

1

T705

1

T706

1

T707

1

T708

1

T700

1

T709

1

T710

1

T711

1

T712

1

12

R717 100Ohm

MCH_ICH_SYNC#
MCH_CLK_REQ#

RED 13

GREEN 13

BLUE 13

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
PM_THRMTRIP#
ICH7_PWROK

RST_IN#_MCH

TV_DACA_OUT 13

TV_DACB_OUT 13

TV_DACC_OUT 13

AG11

AF11

AH33
AH34

BA41
BA40
BA39

AY41

AW41

AW1

T32
R32

J19
K30
J29
A41
A35
A34
D28
D27

K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26

G28
F25
H26

H28
H27
K28
H32

C41

BA3
BA2
BA1
B41

AY1

A40
A39

F3
F7

H7

G6

D1
C1

B2

A4
A3

U600B

RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
TV_DCONSEL_0
TV_DCONSEL_1
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#

SDVO_CTRLCLK
SDVO_CTRLDATA
ICH_SYNC#
CLK_REQ#

NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18

CALISTOGA_Q137

DAC_VSYNC_GM

DAC_HSYNC_GM

RSVD

CFG

PM

MISC NC

DDR MUXINGCLK

DMI

2

+3VS

M_VREF_MCH

+1.5VS

+1.5VS_PCIE

+1.8V

SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3

SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3

SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_OCDCOMP_0
SM_OCDCOMP_1

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP#

SM_RCOMP
SM_VREF_0

SM_VREF_1

G_CLKIN#

G_CLKIN

D_REFCLKIN#

D_REFCLKIN

D_REFSSCLKIN#

D_REFSSCLKIN

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

U700
74LVC1G32GV

B

1

VCC

A

2
3 4

GND

Y

B

1

VCC

A

2
3 4

GND

Y

U701
74LVC1G32GV

5

5

+3VS 4,5,9,11,12,13,14,15,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61
M_VREF_MCH 14,15,16
+1.5VS 9,10,20,26,36,42,52

+1.5VS_PCIE 9
+1.8V 10,14,15,36,53

M_CLK_DDR0

AY35

M_CLK_DDR1

AR1

M_CLK_DDR2

AW7

M_CLK_DDR3

AW40

M_CLK_DDR#0

AW35

M_CLK_DDR#1

AT1

M_CLK_DDR#2

AY7

M_CLK_DDR#3

AY40

M_CKE0

AU20

M_CKE1

AT20

M_CKE2

BA29

M_CKE3

AY29

M_CS#0

AW13

M_CS#1

AW12

M_CS#2

AY21

M_CS#3

AW21

M_OCDCOMP0

AL20

M_OCDCOMP1

AF10

M_ODT0

BA13

M_ODT1

BA12

M_ODT2

AY20

M_ODT3

AU21

M_RCOMP#

AV9

M_RCOMP

AT9

M_VREF_MCH

AK1
AK41

CLK_MCH_3GPLL#

AF33

CLK_MCH_3GPLL

AG33

CLK_UMA_96M#

A27

CLK_UMA_96M

A26

CLK_LCD_SSCG#

C40

CLK_LCD_SSCG

D41

DMI_TXN0

AE35

DMI_TXN1

AF39

DMI_TXN2

AG35

DMI_TXN3

AH39

DMI_TXP0

AC35

DMI_TXP1

AE39

DMI_TXP2

AF35

DMI_TXP3

AG39

DMI_RXN0

AE37

DMI_RXN1

AF41

DMI_RXN2

AG37

DMI_RXN3

AH41

DMI_RXP0

AC37

DMI_RXP1

AE41

DMI_RXP2

AF37

DMI_RXP3

AG41

+3VS

CRT_VSYNC

+3VS

CRT_HSYNC

ASUSTeK COMPUTER INC

Size Project Name

A3

Monday, March 06, 2006

Date: Sheet of

M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 14
M_CLK_DDR3 14

M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 14
M_CLK_DDR#3 14

Layout Note:
Route as short as
possible

R709 40.2Ohm /

12
12

R710 40.2Ohm /

R711 80.6Ohm 1%

1 2
1 2

R712 80.6Ohm 1%

CLK_MCH_3GPLL# 5
CLK_MCH_3GPLL 5
CLK_UMA_96M# 5
CLK_UMA_96M 5
CLK_LCD_SSCG# 5
CLK_LCD_SSCG 5

DMI_TXN[0..3] 18

DMI_TXP[0..3] 18

DMI_RXN[0..3] 18

DMI_RXP[0..3] 18

CRT_VSYNC 13

CRT_HSYNC 13

A6F

M_CKE[0..3] 14,15,16
M_CS#[0..3] 14,15,16
M_ODT[0..3] 14,15,16

GND

+1.8V

GND

Title :

Engineer:

1

Calistoga PCI-E (2)

Jack Wang

Rev

1.0

637

5

D D

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23

C C

B B

M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AJ35

AJ34
AM31
AM33

AJ36

AK35

AJ32

AH31
AN35
AP33
AR31
AP31

AN38
AM36
AM34

AN33

AK26

AL27

AM26

AN24

AK28

AL28

AM24

AP26

AP23

AL22
AP21
AN20

AL23
AP24
AP20

AT21
AR12
AR14
AP13
AP12

AT13

AT12

AL14

AL12

AW2

AG7
AG4
AG9

AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2

AP1
AN2
AV2
AT3
AN1
AL2

AF9
AF6
AH6

AF4
AF8

U600D

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

CALISTOGA_Q137

DDR SYSTEM MEMORY A

4

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

AU12
AV14
BA20

AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4

AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5

AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12

AW14
AK23
AK24
AY14

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CAS#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_RAS#
M_A_RCVENIN#
M_A_RCVENOUT#
M_A_WE#

M_A_DM[0..7] 15
M_A_DQS[0..7] 15
M_A_DQS#[0..7] 15
M_A_A[0..13] 15,16
M_A_DQ[0..63] 15

M_A_BS#0 15,16
M_A_BS#1 15,16
M_A_BS#2 15,16

M_A_CAS# 15,16

T801

1

T803

1

M_A_WE# 15,16

3

AK39

AJ37
AP39
AR41

AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40

AW38

AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31

AW31

AV29

AW29

AM19

AL19
AP14
AN14
AN17
AM16
AP15

AL15

AJ11
AH10

AN10
AK13
AH11
AK10

BA10

AW10

BA4

AW4
AY10

AY9

AW5

AY5
AV4
AR5
AK4
AK3

AK5

AJ9

AJ8

AT4
AJ5

AJ3

U600E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

CALISTOGA_Q137

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

2

M_B_BS#0

AT24

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVENIN#

DDR SYSTEM MEMORY B

SB_RCVENOUT#

SB_WE#

AV23
AY28

AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4

AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5

AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23

AU23
AK16
AK18
AR27

M_B_BS#1
M_B_BS#2

M_B_CAS#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_RAS#
M_B_RCVENIN#
M_B_RCVENOUT#
M_B_WE#

M_B_BS#0 14,16
M_B_BS#1 14,16
M_B_BS#2 14,16

M_B_CAS# 14,16

M_B_RAS# 14,16M_A_RAS# 15,16

T802

1

T800

1

M_B_WE# 14,16

M_B_DM[0..7] 14
M_B_DQS[0..7] 14
M_B_DQS#[0..7] 14
M_B_A[0..13] 14,16
M_B_DQ[0..63] 14

1

A A

Title :

ASUSTeK COMPUTER INC

Size Project Name

A3

5

4

3

2

Date: Sheet of

A6F

Monday, March 06, 2006

Engineer:

Calistoga DDR2 (3)

Jack Wang

1

Rev

1.0

638

5

Layout Note:
Place filter components

+1.5VS

close to GMCH

L901

120Ohm/100Mhz

D D

L902

30Ohm/100Mhz

L900

80Ohm/100Mhz

L903

30Ohm/100Mhz

C C

L905

30Ohm/100Mhz

L906

120Ohm/100Mhz

L907

120Ohm/100Mhz

B B

+2.5VS

VCC_SYNC
Pin H22

12

C931

0.1UF/10V

R904

10Ohm

A A

70 mA

L908

120Ohm/100Mhz

Layout Note:
Caps should be on Top layer

21

12

+

CE900
150UF/4V

/

GND

21

12

C903

0.1UF/10V

GND

21

12

+

CE902

470UF/2.5V

GND

21

12

+

CE903

/

470UF/2.5V

GND

21

12

+

CE904

/

470UF/2.5V

GND

21

12

C922

22UF/6.3V

GND

21

12

C926
22UF/6.3V

GND

VCCA_LVDS
Pin A38 10 mA

12

C900

0.01UF/25V

GND GNDGND

+VCCP_GMCH_R

12

VCCA_CRTDAC
Pin E21 F21

21

12

C944

0.022UF/25V

GND GND

5

12

C901
10UF/10V

GND

12

C904

10UF/10V

GND

12

C908

0.1UF/10V

GND

12

C911

0.1UF/10V

GND

12

C917

0.1UF/10V

GND

12

C923

0.1UF/10V

GND

12

C927

0.1UF/10V

GND

GND GND

3

12

C945

0.1UF/10V

GND

VCCA_3GPLL

+1.5VS_VCCAUX

VCCAUX
1900 mA

+1.5VS_DPLLA

VCCA_DPLLA
50 mA

+1.5VS_DPLLB

VCCA_DPLLB
50 mA

+1.5VS_HPLL

VCCA_HPLL
45 mA

VCCA_MPLL
45 mA

12

C932

0.1UF/10V

D901

BAT54C

+1.5VS_PCIE

VCC3G

12

C902
10UF/10V

+1.5VS_3GPLL

1500 mA

+1.5VS_MPLL

Layout Note:

0.1uF caps in 1.5VS_xPLL
need to be located as
edge caps within 200 mils.

VCCA_3GBG
Pin G41 2 mA

12

C933

0.1UF/10V

GND

1

+VCCP_GMCH

2

+2.5VS_CRTDAC

Layout Note:
These Caps should
be within 250 mils of
edge of GMCH

+VCCP

+1.5VS

VCCD_LVDS 20 mA
Pin A28 B28 C28

12

C909

0.1UF/10V

GND

+1.5VS

VCCD_TVDAC
Pin D21

12

C912

0.022UF/25V

GND

+1.5VS

VCCD_QTVDAC
H19 C28

12

C918

0.022UF/25V

GND

Layout Note:
These Caps should be within
250 mils of edge of GMCH

VCCTX_LVDS 60 mA
Pin A30 B30 C30

12

C934

0.1UF/10V

4

GMCH VCORE

+1.05VS
3500 mA

GND

12

C910
10UF/10V

12

C913

0.1UF/10V

GND

12

C919

0.1UF/10V

GND

12

C935

4.7UF/10V

JP900

1 2

SHORT_PIN

/

JP901

1 2

SHORT_PIN

/

24 mA

Layout Note:
These 0.1uF caps should
be placed within 200 mils
of edge

+3VS

VCC_HV 40 mA
Pin A23 B23 B25

12

C942
10UF/10V

GND

4

+VCCP_GMCH+VCCP

+2.5VS_CRTDAC

GND

12

C943

0.1UF/10V

GND

+1.5VS_PCIE

+1.5VS_3GPLL

+2.5VS

+1.5VS_DPLLA
+1.5VS_DPLLB

+1.5VS_HPLL

+2.5VS

+1.5VS_MPLL

+3VS_TVBG

+3VS_TVDACA
+3VS_TVDACB
+3VS_TVDACC

+1.5VS

+1.5VS

+1.5VS

+3VS

+1.5VS

+1.5VS_VCCAUX

GND

+2.5VS

GND

GND

U600H

H22
C30

B30
A30

AJ41

AB41

Y41
V41
R41
N41

L41

AC33

G41
H41

F21
E21
G21

B26
C39
AF1

A38
B39

AF2
H20

G20

E19
F19
C20
D20
E20
F20

AH1
AH2

A28
B28
C28

D21
A23

B23
B25

H19

AK31
AF31
AE31

AC31

AL30
AK30

AJ30
AH30
AG30

AF30

AE30
AD30
AC30
AG29

AF29

AE29
AD29
AC29
AG28

AF28

AE28
AH22

AJ21

AH21

AJ20
AH20
AH19

P19
P16

AH15

P15
AH14
AG14

AF14
AE14

Y14

AF13
AE13
AF12
AE12

AD12

CALISTOGA_Q137

VCCSYNC
VCC_TXLVDS0

VCC_TXLVDS1
VCC_TXLVDS2

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG

VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL

VCCA_LVDS
VSSA_LVDS

VCCA_MPLL
VCCA_TVBG

VSSA_TVBG

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCD_HMPLL0
VCCD_HMPLL1

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCD_TVDAC
VCC_HV0

VCC_HV1
VCC_HV2

VCCD_QTVDAC
VCCAUX0

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40

3

+VCCP_AGTL+

AC14

VTT_0

AB14

VTT_1

W14

VTT_2

V14

VTT_3

T14

VTT_4

R14

VTT_5

P14

VTT_6

N14

VTT_7

M14

VTT_8

L14

VTT_9

AD13

VTT_10

AC13

VTT_11

AB13

VTT_12

AA13

VTT_13

Y13

VTT_14

W13

VTT_15

V13

VTT_16

U13

VTT_17

T13

VTT_18

R13

VTT_19

N13

VTT_20

M13

VTT_21

L13

VTT_22

AB12

VTT_23

AA12

VTT_24

Y12

VTT_25

W12

VTT_26

V12

VTT_27

U12

VTT_28

T12

VTT_29

R12

VTT_30

P12

VTT_31

N12

VTT_32

M12

VTT_33

L12

VTT_34

R11

VTT_35

P11

VTT_36

N11

VTT_37

M11

VTT_38

R10

VTT_39

P10

VTT_40

N10

VTT_41

M10

VTT_42

P9

VTT_43

POWER

3

VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76

N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1

NOTE:0.1UF CAPS USED IN +1.5VS,
+3.3VS
+2.5VS should be placed within
200 mils of edge.

2

+VCCP_AGTL+
+VCCP_GMCH

+1.5VS_PCIE

+3VS
+2.5VS
+1.5VS

+VCCP_AGTL+

12

12

C905

2.2UF/6.3V

4.7UF/10V

Layout Note:
Place in cavity

+3VS_DAC+3VS

R900
0Ohm

/

1 2

Layout Note:
These Caps used in +3VS_TVDACx
should be within 250 mils of edge of
GMCH

VTTLF_CAP3

VTTLF_CAP2
VTTLF_CAP1

C928

0.47UF/16V

C936

0.47UF/16V

GND

GND

2

12

12

0.22UF/6.3V

12

C937

GND

+3VS

12

12

GND

R902

10KOhm

3VS_DAC_EN

C938

0.1UF/50V

+VCCP_AGTL+ 2,3,5,6

+VCCP_GMCH 10,42
+1.5VS_PCIE 7

+3VS 4,5,7,11,12,13,14,15,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61
+2.5VS 13,36,54
+1.5VS 10,20,26,36,42,52

Layout Note:
Place on the edge

800 mA

12

+

R901
10Ohm

21

C914
10UF/10V

+5V

12

C939

4.7UF/16V

GND GND

12

0.22UF/6.3V

12

C907

+1.5VS_DAC

GND

CE901

330UF/2.5V

D900

3

BAT54C

Total Power Consumption 120 mA

12

12

12

C915

0.022UF/25V

0.1UF/10V

GNDGND GND

12

12

C920

0.022UF/25V

0.1UF/10V

GNDGND

12

12

C924

0.022UF/25V

0.1UF/10V

GNDGND

12

12

C929

0.022UF/25V

0.1UF/10V

GND GND

12/1

U900

1

VIN

2

GND

3

SD#

VOUT

SI9183DT

5
4

FB

+1.5VS

1
2

C916

C921

C925

C930

3VS_DAC_ADJ

12

C940

0.1UF/50V

GND GND GND

C906

L904
180Ohm/100Mhz

Title :

ASUSTeK COMPUTER INC

Size Project Name

A3

Date: Sheet of

A6F

Monday, March 06, 2006

Engineer:

1

+3VS_TVBG

VCCA_TVBG
Pin H20

+3VS_TVDACA

VCCA_TVDACA
Pin E19 F19

+3VS_TVDACB

VCCA_TVDACB
Pin C20 D20

+3VS_TVDACC

VCCA_TVDACC
Pin E20 F20

1 2

35.7KOhm

20KOhm

R905

/

1 2

Calistoga Power (4)

Jack Wang

1

R903



+3VS_DAC

12

639

Rev

1.0

C941

4.7UF/16V

5

U600F

AA33

VCC_0

W33

VCC_1

P33

VCC_2

N33

VCC_3

L33

VCC_4

J33

VCC_5

AA32

VCC_6

Y32

VCC_7

W32

VCC_8

V32

D D

C C

B B

A A

P32
N32
M32

L32

J32

AA31

W31

V31

T31
R31

P31
N31
M31

AA30

Y30
W30

V30
U30

T30
R30

P30
N30
M30

L30

AA29

Y29
W29

V29
U29
R29

P29
M29

L29

AB28
AA28

Y28

V28
U28

T28
R28

P28
N28
M28

L28

P27
N27
M27

L27

P26
N26

L26
N25
M25

L25

P24
N24
M24

AB23
AA23

Y23

P23
N23
M23

L23

AC22
AB22

Y22
W22

P22
N22
M22

L22

AC21
AA21

W21
N21
M21

L21

AC20
AB20

Y20
W20

P20
N20
M20

L20

AB19
AA19

Y19
N19
M19

L19
N18
M18

L18

P17
N17
M17
N16
M16

L16

CALISTOGA_Q137

VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110

VCC

VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107

5

VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8

VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99

AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1

VCC_SM_1
VCC_SM_2

C1001

0.47UF/16V

VCC_SM_3

VCC_SM_4

+1.8V

VCC_SM_5
VCC_SM_6

C1012

0.47UF/16V

12

GND GND

12

C1003

0.47UF/16V

GND

12

C1004

0.47UF/16V

GND

12

4

12

C1002

0.47UF/16V

12

C1013

0.47UF/16V

GNDGND

4

+VCCP_GMCH+VCCP_GMCH

+VCCP_GMCH

12

+

U600G

AD27

VCC_NCTF0

AC27

VCC_NCTF1

AB27

VCC_NCTF2

AA27

VCC_NCTF3

Y27

VCC_NCTF4

W27

VCC_NCTF5

V27

VCC_NCTF6

U27

VCC_NCTF7

T27

VCC_NCTF8

R27

VCC_NCTF9

AD26

VCC_NCTF10

AC26

VCC_NCTF11

AB26

VCC_NCTF12

AA26

VCC_NCTF13

Y26

VCC_NCTF14

W26

VCC_NCTF15

V26

VCC_NCTF16

U26

VCC_NCTF17

T26

VCC_NCTF18

R26

VCC_NCTF19

AD25

VCC_NCTF20

AC25

VCC_NCTF21

AB25

VCC_NCTF22

AA25

VCC_NCTF23

Y25

VCC_NCTF24

W25

VCC_NCTF25

V25

VCC_NCTF26

U25

VCC_NCTF27

T25

VCC_NCTF28

R25

VCC_NCTF29

AD24

VCC_NCTF30

AC24

VCC_NCTF31

AB24

VCC_NCTF32

AA24

VCC_NCTF33

Y24

VCC_NCTF34

W24

VCC_NCTF35

V24

VCC_NCTF36

U24

VCC_NCTF37

T24

VCC_NCTF38

R24

VCC_NCTF39

AD23

VCC_NCTF40

V23

VCC_NCTF41

U23

VCC_NCTF42

T23

VCC_NCTF43

R23

VCC_NCTF44

AD22

VCC_NCTF45

V22

VCC_NCTF46

U22

VCC_NCTF47

T22

VCC_NCTF48

R22

VCC_NCTF49

AD21

VCC_NCTF50

V21

VCC_NCTF51

U21

VCC_NCTF52

T21

VCC_NCTF53

R21

VCC_NCTF54

AD20

VCC_NCTF55

V20

VCC_NCTF56

U20

VCC_NCTF57

T20

VCC_NCTF58

R20

VCC_NCTF59

AD19

VCC_NCTF60

V19

VCC_NCTF61

U19

VCC_NCTF62

T19

VCC_NCTF63

AD18

VCC_NCTF64

AC18

VCC_NCTF65

AB18

VCC_NCTF66

AA18

VCC_NCTF67

Y18

VCC_NCTF68

W18

VCC_NCTF69

V18

VCC_NCTF70

U18

VCC_NCTF71

T18

VCC_NCTF72

CALISTOGA_Q137

VCC(GMCH Core)

+1.5VS (5500 mA) or +1.05VS (3500 mA)

12

+

CE1001

220UF/4V

+1.8V

12

10UF/10V

12

10UF/10V

C1010

C1005

CE1000

220UF/4V

12

C1006

10UF/10V

Layout Note:
Place in cavity

12

C1011

10UF/10V

NCTF

12

+

CE1002

330UF/2.5V

12

C1007

1UF/10V

/

12

C1008

0.22UF/6.3V

3200 mA

12

+

CE1003

330UF/2.5V

3

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8

VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12

VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8

VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57

12

C1000

0.22UF/6.3V

12

+

/

CE1004

330UF/2.5V

GND

3

12

C1009

0.22UF/6.3V

GND

AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17

AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15

GND

+1.5VS

GND

U600J

J11

D11

B11
AV10
AP10
AL10
AJ10

AG10
AC10

W10
U10
BA9

AW9

AR9
AH9
AB9

Y9
R9
G9
E9

A9
AG8
AD8
AA8

U8

K8

C8
BA7
AV7
AP7

AL7

AJ7
AH7
AF7
AC7

R7
G7

D7
AG6
AD6
AB6

Y6

U6

N6

K6

H6

B6
AV5
AF5
AD5
AY4
AR4
AP4

AL4
AJ4

Y4

U4

R4

J4
F4
C4

AY3

AW3

AV3

AL3
AH3
AG3
AF3
AD3
AC3
AA3

G3
AT2
AR2
AP2
AK2

AJ2
AD2
AB2

Y2
U2
T2
N2

J2
H2
F2
C2

AL1

CALISTOGA_Q137

VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360

+1.5VS

+1.8V

+VCCP_GMCH

2

VSS

+1.5VS 9,20,26,36,42,52
+1.8V 7,14,15,36,53
+VCCP_GMCH 9,42

2

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272

AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11

GND

U600I

AK34

VSS_97

AG34

VSS_98

AF34

VSS_99

AE34

VSS_100

AC34

VSS_101

C34

VSS_102

AW33

VSS_103

AV33

VSS_104

AR33

VSS_105

AE33

VSS_106

AB33

VSS_107

Y33

VSS_108

V33

VSS_109

T33

VSS_110

R33

VSS_111

M33

VSS_112

H33

VSS_113

G33

VSS_114

F33

VSS_115

D33

VSS_116

B33

VSS_117

AH32

VSS_118

AG32

VSS_119

AF32

VSS_120

AE32

VSS_121

AC32

VSS_122

AB32

VSS_123

G32

VSS_124

B32

VSS_125

AY31

VSS_126

AV31

VSS_127

AN31

VSS_128

AJ31

VSS_129

AG31

VSS_130

AB31

VSS_131

Y31

VSS_132

AB30

VSS_133

E30

VSS_134

AT29

VSS_135

AN29

VSS_136

AB29

VSS_137

T29

VSS_138

N29

VSS_139

K29

VSS_140

G29

VSS_141

E29

VSS_142

C29

VSS_143

B29

VSS_144

A29

VSS_145

BA28

VSS_146

AW28

VSS_147

AU28

VSS_148

AP28

VSS_149

AM28

VSS_150

AD28

VSS_151

AC28

VSS_152

W28

VSS_153

J28

VSS_154

E28

VSS_155

AP27

VSS_156

AM27

VSS_157

AK27

VSS_158

J27

VSS_159

G27

VSS_160

F27

VSS_161

C27

VSS_162

B27

VSS_163

AN26

VSS_164

M26

VSS_165

K26

VSS_166

F26

VSS_167

D26

VSS_168

AK25

VSS_169

P25

VSS_170

K25

VSS_171

H25

VSS_172

E25

VSS_173

D25

VSS_174

A25

VSS_175

BA24

VSS_176

AU24

VSS_177

AL24

VSS_178

AW23

VSS_179

GND

CALISTOGA_Q137

ASUSTeK COMPUTER INC

Size Project Name

Custom

Monday, March 06, 2006

Date: Sheet

VSS

A6F

1

Title :

Engineer:

1

AC41

VSS_0

AA41

VSS_1

W41

VSS_2

T41

VSS_3

P41

VSS_4

M41

VSS_5

J41

VSS_6

F41

VSS_7

AV40

VSS_8

AP40

VSS_9

AN40

VSS_10

AK40

VSS_11

AJ40

VSS_12

AH40

VSS_13

AG40

VSS_14

AF40

VSS_15

AE40

VSS_16

B40

VSS_17

AY39

VSS_18

AW39

VSS_19

AV39

VSS_20

AR39

VSS_21

AN39

VSS_22

AJ39

VSS_23

AC39

VSS_24

AB39

VSS_25

AA39

VSS_26

Y39

VSS_27

W39

VSS_28

V39

VSS_29

T39

VSS_30

R39

VSS_31

P39

VSS_32

N39

VSS_33

M39

VSS_34

L39

VSS_35

J39

VSS_36

H39

VSS_37

G39

VSS_38

F39

VSS_39

D39

VSS_40

AT38

VSS_41

AM38

VSS_42

AH38

VSS_43

AG38

VSS_44

AF38

VSS_45

AE38

VSS_46

C38

VSS_47

AK37

VSS_48

AH37

VSS_49

AB37

VSS_50

AA37

VSS_51

Y37

VSS_52

W37

VSS_53

V37

VSS_54

T37

VSS_55

R37

VSS_56

P37

VSS_57

N37

VSS_58

M37

VSS_59

L37

VSS_60

J37

VSS_61

H37

VSS_62

G37

VSS_63

F37

VSS_64

D37

VSS_65

AY36

VSS_66

AW36

VSS_67

AN36

VSS_68

AH36

VSS_69

AG36

VSS_70

AF36

VSS_71

AE36

VSS_72

AC36

VSS_73

C36

VSS_74

B36

VSS_75

BA35

VSS_76

AV35

VSS_77

AR35

VSS_78

AH35

VSS_79

AB35

VSS_80

AA35

VSS_81

Y35

VSS_82

W35

VSS_83

V35

VSS_84

T35

VSS_85

R35

VSS_86

P35

VSS_87

N35

VSS_88

M35

VSS_89

L35

VSS_90

J35

VSS_91

H35

VSS_92

G35

VSS_93

F35

VSS_94

D35

VSS_95

AN34

VSS_96

GND

Clistoga GND (5)

Jack Wang

of

Rev

1.0

6310

5

4

3

2

1

MCH_CFG_57

12

R1102

2.2KOhm

GND

GND

GND

GND

r0402_h16

12

R1103

2.2KOhm

r0402_h16

12

R1104

2.2KOhm

r0402_h16

12

R1106

2.2KOhm

r0402_h16

D D

MCH_CFG_77

C C

B B

MCH_CFG_97

MCH_CFG_117

CFG5 : DMI X2 Select

LOW = DMI X 2

/

HIGH = DMI X 4 (Default)

CFG7 : CPU STRAP

LOW = Reserved

/

HIGH = Mobility CPU (Default)

CFG9 : PCIE GRAPHIC LANE

LOW = REVERSE LANES

/

HIGH = NORMAL OPERATION (Default)

CFG11 : Reserved but need to be pull lo w

/

MCH_CFG_167

12

R1101

2.2KOhm

r0402_h16

GND

+3VS

12

R1100
1KOhm

r0402

MCH_CFG_187

+3VS

12

MCH_CFG_197

CFG16 : FSB DYNAMIC ODT

LOW = Dynamic ODT Disabled

/

HIGH = Dynamic ODT Enabled (Default)

CFG18 : GMCH Core Voltage Level

LOW = 1.05V

HIGH = 1.5V (default)

/

CFG19 : DMI LANE REVERSAL

LOW = NORMAL

HIGH = LANES REVERSED

R1105

/

1KOhm

r0402

CFG

2:0
4:3

5
6

7
8

9
11:10

13:12

15:14

16
17

SDVO_C
TRLDATA

18

19

20

CFG[17..3] have internal pullup r es i st o rs .
CFG[19..18] have internal pulldown resi s to r s.
SDVOCRTL_DATA has internal pulldown
resistors.

All are sampled with respect to the
leading edge of the GMCH PWROK

FSB Freq select

DMI X 2 Select

CPU Strap

PCIE Graphics
Lane Reversal

XOR/ALLZ

FSB Dynamic ODT

SDVO Present

VCC select
DMI Lane

Reversal
SDVO/PCIE

concurrent

001 = FSB533
011 = FSB667

0 = DMI X 2
1 = DMI X 4 (Default)

0 = Reserved
1 = Mobile CPU (Default)

0 = Reverse Lanes
1 = Normal (Default)

00 = Partial Clock Gating Disable
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal operation (Default)

0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)

0 = No SDVO Card Present (Default)
1 = SDVO Card Present

0 = 1.05V (Default)
1 = 1.5V

0 = Normal (Default)
1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is
operational(Default)
1 = SDVO and PCIE x1 are operating
simultaneously via the PEG port

A A

5

4

+2.5VS

3

+2.5VS 9,13,36,54

Calistoga Strapping

Title :

1

Jack Wang

11 63Monday, March 06, 2006

Rev

1.0

of

ASUSTeK COMPUTER INC

Size Project Name

Custom

2

Date: Sheet

A6F

Engineer:

5

LCD Panel Power

3

2

GND

12

32

D

S

1209

R1202
22kOhm

+3VSLCD_G

Q1202
2N7002

+3VSLCD_DG

SI3865: US$0.22

12

C1202

1UF/25V

GND

1

1

G

GND

R1201
100KOhm

+12VS

1

1

G

Q1200
2N7002

R1204
100KOhm

+3V

12

32

3

D

1

1

G

S

2

GND

D D

L_VDDEN7

12

GND

1
2
3

+3VSLCD_DC

32

3

D

Q1203
2N7002

S

2

4

Q1201

D

G

SI3456BDV

6
5

S

4

1 2

R1203
100Ohm

r0402

+3VSLCD

3~3.6V
Full Active: 410 mA(Max. 500 mA)

3~3.6V
S0-S1 M: 410 mA(Max. 500 mA)

12

0.1UF/10V

L1201
80Ohm/100Mhz

21

12

0.1UF/10V

GND

C1203

12

10UF/10V

C1201

C1204

+3VS

12

C1200

0.01UF/16V

GND

12

C1205

1UF/10V

+3VS_LCD

12

0.1UF/10V

GND

C1206

3

2

1

LCD LVDS Interface

GND

3132

GND

CON10

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

BTOB_CON_30P

GND

SIDE1SIDE2

2

2

LVDS_UCLKP

4

4

LVDS_UCLKN

6

6

8

8

LVDS_U2P

10

10
12
14
16
18
20
22
24
26
28
30

LVDS_U2N

12
14

LVDS_U1P

16

LVDS_U1N

18
20

LVDS_U0P

22

LVDS_U0N

24
26
28
30

GND

GND

12

C1207

0.1UF/10V

c0402

+3VS
+3VS_LCD

LVDS_UCLKP 7
LVDS_UCLKN 7

LVDS_U2P 7
LVDS_U2N 7

LVDS_U1P 7
LVDS_U1N 7

LVDS_U0P 7
LVDS_U0N 7

LVDS_LCLKP7
LVDS_LCLKN7

LVDS_L2P7
LVDS_L2N7

LVDS_L1P7
LVDS_L1N7

LVDS_L0P7
LVDS_L0N7

EDID_CLK7
EDID_DAT7

+3VS_LCD

Cable Requirement:
Impedence: 100 ohm +/- 10%
Length Mismatch <= 10 mils
Twisted Pair(Not Ribbon)
Maximum Length <= 16"

LVDS_LCLKP
LVDS_LCLKN

LVDS_L2P
LVDS_L2N

LVDS_L1P
LVDS_L1N

LVDS_L0P
LVDS_L0N

EDID_CLK
EDID_DAT

C C

L1202

2 1

80Ohm/100Mhz

l0805_h43

+5V_USB67+5V

12

CE1200
22UF/6.3V

c0805

12

C1208

c0402

0.1UF/10V

12

C1209

c0402

1000PF/50V

LCD Backlight Control

Inverter Board

BIOS
LCD_BACKOFF#
When user push "Fn+F7" button
BIOS active this pin to turn On/Off backlight

EC
INVTER_DA:
EC output D/A signal ( adjust voltage level) to
adjust backlight

B B

LCD_BACKOFF#28

5,26,30,33,38

A A

PCI_RST#
L_BKLTEN7
LID_SW#28

L_BKLTCTL7

INVTER_DA28

BRIGHT_PWM28

INTMIC_A22

LCD_BACKOFF#
PCI_RST#
L_BKLTEN
LID_SW#

L1208

21

120Ohm/100Mhz

L1207

N/A

21

120Ohm/100Mhz

L1211

/

21

120Ohm/100Mhz

12

C1211

c0402

1000PF/50V

D1202 RB717F

1
2
1
2

D1203 RB717F

L1200

120Ohm/100Mhz

L1209 120Ohm/100Mhz

INTMIC_A_GND_CON

21

INTMIC_A_CON

21

L1210 120Ohm/100Mhz

3

3

21

+3VS +3VAAC_BAT_SYS

12

R1205

12

C1212

c0402

1000PF/50V

10KOhm

r0402

120Ohm/100Mhz

2 1

12

C1213

c0402

1000PF/50V

BL_EN_L

L1206

built in 14.1W
LCD Panel

L1204

l0805_h43

80Ohm/100Mhz

2 1

12

C1215
1UF/25V

12

C1216

c0402

1000PF/50V

12

C1214

0.1UF/25V

L1205

l0805_h43

80Ohm/100Mhz

2 1

INVERTER Interface

AC_INV

LID_SW#_CON

ADJ_BL_CON

BL_EN_CON

+3VA_CON

12

C1217

0.1UF/10V

c0402

CON11

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

WTOB_CON_20P

GND GND

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

2122

SIDE1SIDE2

USB_WLAN_ON#

+5V_USB67

USB4-_B
USB4+_B

USB4
For
CMOS
Camera

1 2

12

C1210

c0402 N/A

1000PF/50V

GND

R1200

/

0Ohm r0402

USB_PN4_B18

USB_PP4_B18

WLAN_ON# 19,26,38

L1203

N/A

90Ohm/100Mhz

09G091090000

1 4

RN1200A

1 2

0OHM

3 4

0OHM

RN1200B

2 3

GND

12

D1200

EGA10603V05A1

/

USB4-_B

USB4+_B

12

D1201

EGA10603V05A1

ESD Guard
Close to
USB Port

GND

/

GND_MIC

5

4

GND

700V rms@5 mA rms
(Min. 3 mA rms)6 mA rms(Max. 6.5 mA rms)

3

ASUSTeK COMPUTER INC

Size Project Name

A3

2

Date: Sheet

A6F

Title :

Engineer:

1

LVDS & INVERTER

Jack Wang

12 63Monday, March 06, 2006

of

Rev

1.1

5

4

3

2

1

CRT OUT

JP1304 SHORT_PIN

R1301
150Ohm

r0402

1 2

JP1305 SHORT_PIN

GREEN

1 2

JP1306 SHORT_PIN

BLUE

1 2

1 2

R1302
150Ohm

r0402

1 2

R1306
150Ohm

r0402

1 2

CRT_HSYNC

CRT_VSYNC

RED7

GREEN7

BLUE7

CRT_HSYNC7

CRT_VSYNC7

GND

12G14101107D

CON2

2

CVBS1

7

CVBS2

4

Y

6

C

5

NC

1

GND0

3

GND1

HC1 HC2

MINI_DIN_7P

8 9

12-141011072

GND

GND

D D

TV_DACA_OUT7

TV_DACB_OUT7

TV_DACC_OUT7

C C

B B

TV OUT

TV_DACA_OUT TV_DACA_OUT_R

JP1301

1 2

SHORT_PIN

12

R1303
150Ohm

r0402

+3VS

+3VS

+3VS

JP1302 SHORT_PIN

1 2

JP1303 SHORT_PIN

12

GND

GND

GND

1 2

12

R1304

R1305

150Ohm

150Ohm

r0402

r0402

Place Terminator
close to

GND

Connector

D1301

2

3

1

BAV99

D1303

2

3

1

BAV99

D1305

2

3

1

BAV99

PLACE ESD Diodes
near TV port

TV_DACB_OUT_R

12

C1305

c0402

5.6PF/50V

TV_DACA_OUT_R

TV_DACB_OUT_R

TV_DACC_OUT_R

checklist suggests
150ohm/100MHz &
6pF

TV_DACC_OUT_RTV_DACC_OUT

12

12

5.6PF/50V

C1307

C1306

c0402

c0402

5.6PF/50V

GND GND

21

21

21

+2.5VS

+2.5VS

+2.5VS

L1300120Ohm/100Mhz

L1302120Ohm/100Mhz

L1304120Ohm/100Mhz

12

C1308

c0402

5.6PF/50V

TV_CVBS_CON

TV_Y_CONTV_DACB_OUT

TV_C_CON

12

12

C1309

c0402

5.6PF/50V

5.6PF/50V

D1302

2
1

GND

2
1

GND

2
1

GND

3

BAV99

D1304

3

BAV99

D1306

3

BAV99

PLACE ESD Diodes
near VGA port

C1310

c0402

CRT_RED_R

CRT_GREEN_R

CRT_BLUE_R

CRT_RED_RRED

12

C1302
10PF/50V

c0402

GND

CRT_GREEN_R

12

C1304
10PF/50V

c0402

GND

CRT_BLUE_R

12

GND

checklist suggests 47ohm/100MHz

L1301

0.068uH

L1303

0.068uH

L1305

0.068uH
C1300
10PF/50V

c0402

1 2

1 2

R1307

39Ohm

r0402

R1308

39Ohm

r0402

21

21

GND

21

GND

GND

GND

GND

12

12

12

1 2

1 2

CRT_R_CON

C1301
22PF/25V

c0402

CRT_G_CON

C1303
22PF/25V

c0402

CRT_B_CON

C1311
22PF/25V

c0402

HSYNC_CON

C1312
47PF/50V

c0402

VSYNC_CON

C1313
47PF/50V

c0402

CON3

1

RED

2

GREEN

3

BLUE

13

/

HSYNC

CRT

14

/

VSYNC

15

PIN

1

VCC

NC1
NC2

9

4
11

D1300

+5VS

A A

5

1 2

+5VS_CRT

+3VS

1N4148W

R1310 6.8KOhm

1 2

R1311 6.8KOhm

1 2

R1312 2.2KOhm

1 2

R1313 2.2KOhm

1 2

+5VS_CRT

DDC2BD_5
DDC2BC_5

CRT_DDC_DATA
CRT_DDC_CLK

+3VS

1

BAV99

GND

D1308

2

+3VS

DDC2BD_5
DDC2BC_5

4

GND

1

BAV99

CRT_HSYNC

3

CRT_VSYNC

3

3

D1307

2

CRT_DDC_DATA7

+5VS

CRT_DDC_CLK7

DDC2BD_5

61

Q1300A
UM6K1N

2

Q1300B

5

UM6K1N

DDC2BC_5

34

2

R1309

1 2

0Ohm

R1300

1 2

0Ohm

DDC_DAT_CON

C1314
47PF/50V

c0402

1 2

GND

DDC_CLK_CON

C1315
47PF/50V

c0402

1 2

GND

ASUSTeK COMPUTER INC

Size Project Name

A3

Date: Sheet

12G101102152

A6F

12

DATA

15

DCLK

D_SUB_15P

SIDE_G16
SIDE_G17

GND2

GND3

GND4

GND5

6

7

8

10

GND

Title :

Engineer:

1

16
17

GND1

5

CRT & TV OUT

Jack Wang

13 63Monday, March 06, 2006

GND

Rev

1.0

of

5

M_B_DQ[0..63]8
M_B_A[0..13]8,16

4

M_VREF_DIMM1

+1.8V

+3VS

3

M_VREF_DIMM1 7,15,16
+1.8V 7,10,15,36,53
+3VS 4,5,7,9,11,12,13,15,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61

2

1

M_B_A0
M_B_A1
M_B_A2
M_B_A3

r0402

1 2

GND

GND

R1402
10KOhm

12

C1405

0.1UF/10V

12

C1407

0.1UF/10V

M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_BS#2
M_B_BS#0
M_B_BS#1
M_CS#2
M_CS#3
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR2
M_CLK_DDR#2
M_CKE2
M_CKE3
M_B_CAS#
M_B_RAS#
M_B_WE#

r0402

SMB_CLK_S
SMB_DAT_S

M_ODT2
M_ODT3

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

GND

+1.8V

D D

M_B_BS#28,16
M_B_BS#08,16
M_B_BS#18,16
M_CS#27,16
M_CS#37,16
M_CLK_DDR37
M_CLK_DDR#37
M_CLK_DDR27
M_CLK_DDR#27
M_CKE27,16
M_CKE37,16
M_B_CAS#8,16

GND

M_VREF_DIMM1

M_B_RAS#8,16
M_B_WE#8,16

R1401

1 2

10KOhm

SMB_CLK_S5,15,19,26
SMB_DAT_S5,15,19,26

M_ODT27,16
M_ODT37,16

For Data Swap

+3VS

12

C1404

2.2UF/6.3V

GND

VREF -> 10/10 mils

12

C1406

2.2UF/6.3V

GND

11/14

+3VS

C C

+1.8V

12

C1403

0.1UF/10V

+1.8V

12

C1400

0.1UF/10V

GND

12

C1412

2.2UF/6.3V

+1.8V

12

C1408

0.1UF/10V

12

2.2UF/6.3V

C1413

Layout Note:
Place these
Caps near
SO DIMM 1

12

12

C1411

C1409

0.1UF/10V

0.1UF/10V

12

12

C1414

2.2UF/6.3V

2.2UF/6.3V

4

C1415

12

C1410

0.1UF/10V

GND

12

2.2UF/6.3V

GND

C1416

12

12

0.1UF/10V

Layout Note:
Place these resistors
near the GMCH

B B

A A

M_B_DM[0..7]8
M_B_DQS[0..7]8
M_B_DQS#[0..7]8

5

C1401

C1402

0.1UF/10V

B102
B101
B100

B99
B98
B97
B94
B92
B93
B91

B105

B90
B89

B116

B86
B84

B85
B107
B106
B110
B115

B30

B32
B164
B166

B79

B80
B113
B108
B109
B198
B200
B197
B195

B114
B119

B10

B26

B52

B67
B130
B147
B170
B185

B13

B31

B51

B70
B131
B148
B169
B188

B11

B29

B49

B68
B129
B146
B167
B186

B111
B117

B95

B81

B87
B103

B47
B133
B183

B77

B71
B121
B193

B41

B53

B59

B65
B199

3

B1

CON8B

B:A0
B:A1
B:A2
B:A3
B:A4
B:A5
B:A6
B:A7
B:A8
B:A9
B:A10/AP
B:A11
B:A12
B:A13
B:A14
B:A15
B:A16_BA2
B:BA0
B:BA1
B:S0#
B:S1#
B:CK0
B:CK0#
B:CK1
B:CK1#
B:CKE0
B:CKE1
B:CBS#
B:RAS#
B:WE#
B:SA0
B:SA1
B:SCL
B:SDA

B:ODT0
B:ODT1

B:DM0
B:DM1
B:DM2
B:DM3
B:DM4
B:DM5
B:DM6
B:DM7

B:DQS0
B:DQS1
B:DQS2
B:DQS3
B:DQS4
B:DQS5
B:DQS6
B:DQS7
B:DQS0#
B:DQS1#
B:DQS2#
B:DQS3#
B:DQS4#
B:DQS5#
B:DQS6#
B:DQS7#

B:VDD2
B:VDD3
B:VDD5
B:VDD7
B:VDD9
B:VDD10

B:VSS1
B:VSS2
B:VSS3
B:VSS4
B:VSS9
B:VSS11
B:VSS14
B:VSS18
B:VSS19
B:VSS22
B:VSS23

B:VDDSPD
B:VREF

DDR_DIMM_331P

B:DQ0
B:DQ1
B:DQ2
B:DQ3
B:DQ4
B:DQ5
B:DQ6
B:DQ7
B:DQ8

B:DQ9
B:DQ10
B:DQ11
B:DQ12
B:DQ13
B:DQ14
B:DQ15
B:DQ16
B:DQ17
B:DQ18
B:DQ19
B:DQ20
B:DQ21
B:DQ22
B:DQ23
B:DQ24
B:DQ25
B:DQ26
B:DQ27
B:DQ28
B:DQ29
B:DQ30
B:DQ31
B:DQ32
B:DQ33
B:DQ34
B:DQ35
B:DQ36
B:DQ37
B:DQ38
B:DQ39
B:DQ40
B:DQ41
B:DQ42
B:DQ43
B:DQ44
B:DQ45
B:DQ46
B:DQ47
B:DQ48
B:DQ49
B:DQ50
B:DQ51
B:DQ52
B:DQ53
B:DQ54
B:DQ55
B:DQ56
B:DQ57
B:DQ58
B:DQ59
B:DQ60
B:DQ61
B:DQ62
B:DQ63

B:VSS26
B:VSS27
B:VSS29
B:VSS30
B:VSS31
B:VSS33
B:VSS34
B:VSS37
B:VSS38
B:VSS39
B:VSS40
B:VSS47
B:VSS48
B:VSS49
B:VSS50
B:VSS51
B:VSS52

B:NC1

B:NC2

B:NC3

B:NC4

B:NCTEST

B5
B7
B17
B19
B4
B6
B14
B16
B23
B25
B35
B37
B20
B22
B36
B38
B43
B45
B55
B57
B44
B46
B56
B58
B61
B63
B73
B75
B62
B64
B74
B76
B123
B125
B135
B137
B124
B126
B134
B136
B141
B143
B151
B153
B140
B142
B152
B154
B157
B159
B173
B175
B158
B160
B174
B176
B179
B181
B189
B191
B180
B182
B192
B194

B127
B139
B145
B165
B171
B177
B187
B9
B21
B33
B155
B3
B15
B27
B39
B149
B161

B83
B120
B50
B69
B163

M_B_DQ1
M_B_DQ4
M_B_DQ7
M_B_DQ3
M_B_DQ5
M_B_DQ0
M_B_DQ2
M_B_DQ6
M_B_DQ8
M_B_DQ9
M_B_DQ14
M_B_DQ15
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ10
M_B_DQ21
M_B_DQ16
M_B_DQ22
M_B_DQ23
M_B_DQ17
M_B_DQ20
M_B_DQ19
M_B_DQ18
M_B_DQ29
M_B_DQ25
M_B_DQ31
M_B_DQ30
M_B_DQ26
M_B_DQ24
M_B_DQ28
M_B_DQ27
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ41
M_B_DQ40
M_B_DQ46
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ42
M_B_DQ47
M_B_DQ53
M_B_DQ49
M_B_DQ54
M_B_DQ51
M_B_DQ48
M_B_DQ52
M_B_DQ50
M_B_DQ55
M_B_DQ63
M_B_DQ57
M_B_DQ62
M_B_DQ61
M_B_DQ56
M_B_DQ60
M_B_DQ58
M_B_DQ59

GND

Group0

Group1

Group2

Group3

Group4

Group5

Group6

Group7

Title :

ASUSTeK COMPUTER INC

Size Project Name

A3

2

Date: Sheet

A6F

Engineer:

DDR2_SO-DIMM(1)

Jack Wang

1

Rev

14 63Monday, March 06, 2006

1.0

of

5

M_A_DQ[0..63]8
M_A_A[0..13]8,16

Green Part Number:12G025122006

4

3

+1.8V

+3VS

M_VREF_DIMM0

+1.8V 7,10,14,36,53
+3VS 4,5,7,9,11,12,13,14,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61
M_VREF_DIMM0 7,14,16

2

1

M_A_A0
M_A_A1
M_A_A2

D D

M_A_BS#28,16
M_A_BS#08,16

M_A_BS#18,16
M_CS#07,16
M_CS#17,16
M_CLK_DDR07
M_CLK_DDR#07
M_CLK_DDR17
M_CLK_DDR#17
M_CKE07,16
M_CKE17,16
M_A_CAS#8,16
M_A_RAS#8,16

C C

12

R15001 10KOhm

R15002 10KOhm

GND GND

12

M_A_WE#8,16

SMB_CLK_S5,14,19,26
SMB_DAT_S5,14,19,26

M_ODT07,16
M_ODT17,16

For Data Swap

B B

A A

M_A_DM[0..7]8
M_A_DQS[0..7]8
M_A_DQS#[0..7]8

+1.8V

Layout Note:
Place these
Caps near

12

12

SO DIMM 0

C1509

C1508

2.2UF/6.3V

2.2UF/6.3V

GMCH=====>SODIMM1=>SODIMM0

+1.8V

Layout Note:
Place these
Caps near

12

SO DIMM 0

C1500

0.1UF/10V

12

C1510

2.2UF/6.3V

12

C1505

0.1UF/10V

12

C1511

2.2UF/6.3V

12

C1506

0.1UF/10V

GND

12

GND

12

C1512

2.2UF/6.3V

C1507

0.1UF/10V

+3VS

12

C1501

2.2UF/6.3V

GND GND

M_VREF_DIMM0

12

C1502

0.1UF/10V

M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

M_A_BS#2
M_A_BS#0

M_A_BS#1
M_CS#0
M_CS#1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
M_CKE0
M_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#

SMB_CLK_S
SMB_DAT_S

M_ODT0
M_ODT1

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

+1.8V

GND GND

VREF -> 10/10 mils

C1503

2.2UF/6.3V

GNDGND

12

C1504

0.1UF/10V

12

5

4

CON8A

A102

A:A0

A101

A:A1

A100

A:A2

A99

A:A3

A98

A:A4

A97

A:A5

A94

A:A6

A92

A:A7

A93

A:A8

A91

A:A9

A105

A:A10/AP

A90

A:A11

A89

A:A12

A116

A:A13

A86

A:A14

A84

A:A15

A85

A:A16_BA2

A107

A:BA0

A106

A:BA1

A110

A:S0#

A115

A:S1#

A30

A:CK0

A32

A:CK0#

A164

A:CK1

A166

A:CK1#

A79

A:CKE0

A80

A:CKE1

A113

A:CAS#

A108

A:RAS#

A109

A:WE#

A198

A:SA0

A200

A:SA1

A197

A:SCL

A195

A:SDA

A114

A:ODT0

A119

A:ODT1

A10

A:DM0

A26

A:DM1

A52

A:DM2

A67

A:DM3

A130

A:DM4

A147

A:DM5

A170

A:DM6

A185

A:DM7

A13

A:DQS0

A31

A:DQS1

A51

A:DQS2

A70

A:DQS3

A131

A:DQS4

A148

A:DQS5

A169

A:DQS6

A188

A:DQS7

A11

A:DQS0#

A29

A:DQS1#

A49

A:DQS2#

A68

A:DQS3#

A129

A:DQS4#

A146

A:DQS5#

A167

A:DQS6#

A186

A:DQS7#

A112

A:VDD1

A96

A:VDD4

A118

A:VDD6

A82

A:VDD8

A88

A:VDD11

A104

A:VDD12

A12

A:VSS5

A48

A:VSS6

A184

A:VSS7

A78

A:VSS8

A72

A:VSS10

A122

A:VSS12

A196

A:VSS13

A8

A:VSS15

A18

A:VSS16

A24

A:VSS17

A42

A:VSS20

A199

A:VDDSPD

A1

A:VREF

DDR_DIMM_331P

A:DQ0
A:DQ1
A:DQ2
A:DQ3
A:DQ4
A:DQ5
A:DQ6
A:DQ7
A:DQ8

A:DQ9
A:DQ10
A:DQ11
A:DQ12
A:DQ13
A:DQ14
A:DQ15
A:DQ16
A:DQ17
A:DQ18
A:DQ19
A:DQ20
A:DQ21
A:DQ22
A:DQ23
A:DQ24
A:DQ25
A:DQ26
A:DQ27
A:DQ28
A:DQ29
A:DQ30
A:DQ31
A:DQ32
A:DQ33
A:DQ34
A:DQ35
A:DQ36
A:DQ37
A:DQ38
A:DQ39
A:DQ40
A:DQ41
A:DQ42
A:DQ43
A:DQ44
A:DQ45
A:DQ46
A:DQ47
A:DQ48
A:DQ49
A:DQ50
A:DQ51
A:DQ52
A:DQ53
A:DQ54
A:DQ55
A:DQ56
A:DQ57
A:DQ58
A:DQ59
A:DQ60
A:DQ61
A:DQ62
A:DQ63

A:VSS21
A:VSS24
A:VSS25
A:VSS28
A:VSS32
A:VSS35
A:VSS36
A:VSS41
A:VSS42
A:VSS43
A:VSS44
A:VSS45
A:VSS46
A:VSS53
A:VSS54
A:VSS55
A:VSS56
A:VSS57

A:NC1

A:NC2

A:NC3

A:NC4

NP_NC4

GND1

205

GND2

206

GND3

208

A:NCTEST

GND4

207

NP_NC1

NP_NC2

NP_NC3

201

202

203

204

3

A7
A17
A19
A4
A6
A14
A16
A23
A25
A35
A37
A20
A22
A36
A38
A43
A45
A55
A57
A44
A46
A56
A58
A61
A63
A73
A75
A62
A64
A74
A76
A123
A125
A135
A137
A124
A126
A134
A136
A141
A143
A151
A153
A140
A142
A152
A154
A157
A159
A173
A175
A158
A160
A174
A176
A179
A181
A189
A191
A180
A182
A192
A194

A54
A60
A66
A128
A172
A178
A190
A34
A132
A144
A156
A168
A2
A28
A40
A138
A150
A162

A83
A120
A50
A69
A163

M_A_DQ7
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ0
M_A_DQ1
M_A_DQ14
M_A_DQ8
M_A_DQ10
M_A_DQ11
M_A_DQ13
M_A_DQ12
M_A_DQ15
M_A_DQ9
M_A_DQ16
M_A_DQ20
M_A_DQ18
M_A_DQ23
M_A_DQ21
M_A_DQ17
M_A_DQ19
M_A_DQ22
M_A_DQ28
M_A_DQ25
M_A_DQ31
M_A_DQ26
M_A_DQ24
M_A_DQ29
M_A_DQ30
M_A_DQ27
M_A_DQ34
M_A_DQ33
M_A_DQ39
M_A_DQ38
M_A_DQ36
M_A_DQ32
M_A_DQ37
M_A_DQ35
M_A_DQ45
M_A_DQ41
M_A_DQ47
M_A_DQ46
M_A_DQ44
M_A_DQ40
M_A_DQ43
M_A_DQ42
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ49
M_A_DQ48
M_A_DQ51
M_A_DQ50
M_A_DQ61
M_A_DQ63
M_A_DQ56
M_A_DQ62
M_A_DQ57
M_A_DQ60
M_A_DQ59
M_A_DQ58

Group0

Group1

Group2

Group3

Group4

Group5

Group6

Group7

1

DDR2 SO-DIMM(0)

Jack Wang

15 63Monday, March 06, 2006

of

Rev

1.0

Title :

ASUSTeK COMPUTER INC

Size Project Name

A3

2

Date: Sheet

A6F

Engineer:

M_A_DQ6

A5

5

+0.9VS

NEED TO SWAP

1 16

56Ohm

2 15

56Ohm

3 14

D D

C C

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

RN1601A
RN1601B
RN1601C
RN1601D
RN1601E
RN1601F
RN1601G
RN1601H

RN1602A
RN1602B
RN1602C
RN1602D
RN1602E
RN1602F
RN1602G
RN1602H

RN1603A
RN1603B
RN1603C
RN1603D
RN1603E
RN1603F
RN1603G
RN1603H

M_A_A2
M_A_A0

M_A_BS#1
M_A_RAS#
M_ODT0
M_CS#0
M_CS#2
M_ODT2

M_B_A11
M_B_A6
M_B_A7

M_B_A4
M_B_A2
M_B_A0
M_B_BS#1
M_B_RAS#

M_B_BS#0
M_B_A10
M_B_WE#
M_B_CAS#
M_CS#3
M_ODT3
M_ODT1
M_CS#1

4

M_A_A[0..13] 8,15
M_A_BS#[0..2] 8,15
M_A_CAS# 8,15

M_A_RAS# 8,15
M_A_WE# 8,15

M_B_A[0..13] 8,14
M_B_BS#[0..2] 8,14
M_B_CAS# 8,14

M_B_RAS# 8,14
M_B_WE# 8,14

M_CS#[0..3] 7,14,15
M_ODT[0..3] 7,14,15
M_CKE[0..3] 7,14,15

3

+0.9VS

L1600

120Ohm/100Mhz

2

21

M_VREF_DIMM0
M_VREF_DIMM1

M_VREF_MCH

+0.9VS

M_VREF_DIMM1
M_VREF_MCH
M_VREF_DIMM0

1

M_VREF_DIMM0 7,14,15
M_VREF_DIMM1 7,14,15
M_VREF_MCH 7,14,15
+0.9VS 36,53

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 16

56Ohm

2 15

56Ohm

B B

A A

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 16

56Ohm

2 15

56Ohm

3 14

56Ohm

4 13

56Ohm

5 12

56Ohm

6 11

56Ohm

7 10

56Ohm

8 9

56Ohm

1 2

56Ohm

3 4

56Ohm

5 6

56Ohm

7 8

56Ohm

5

RN1605A
RN1605B
RN1605C
RN1605D
RN1605E
RN1605F
RN1605G
RN1605H

RN1606A
RN1606B
RN1606C
RN1606D
RN1606E
RN1606F
RN1606G
RN1606H

RN1607A
RN1607B
RN1607C
RN1607D
RN1607E
RN1607F
RN1607G
RN1607H

RN1608A
RN1608B
RN1608C
RN1608D

M_B_A12
M_B_BS#2
M_A_A12
M_A_BS#0
M_A_BS#2
M_CKE2
M_CKE0
M_CKE3

M_B_A13
M_CKE1
M_A_A13
M_A_A4
M_A_A6
M_A_A7
M_A_A11
M_A_A9

M_A_A5
M_B_A1
M_B_A3
M_B_A5
M_B_A8
M_A_A3
M_A_A8
M_B_A9

M_A_CAS#
M_A_WE#
M_A_A10
M_A_A1

+0.9VS

12

+0.9VS

12

C1601

c0402

0.1UF/10V

C1613

c0402

0.1UF/10V

4

12

C1602

c0402

0.1UF/10V

12

C1603

c0402

0.1UF/10V

12

C1604

c0402

0.1UF/10V

12

C1605

c0402

0.1UF/10V

12

C1606

c0402

0.1UF/10V

12

C1607

c0402

0.1UF/10V

12

C1608

c0402

0.1UF/10V

12

C1609

c0402

0.1UF/10V

12

C1610

c0402

0.1UF/10V

Layout note:
Place one cap close to every 2 pull-up resistors terminated to +0.9VS

12

C1614

c0402

0.1UF/10V

12

C1615

c0402

0.1UF/10V

12

C1616

c0402

0.1UF/10V

12

3

C1617

c0402

0.1UF/10V

12

C1618

c0402

0.1UF/10V

12

C1619

c0402

0.1UF/10V

12

C1620

c0402

0.1UF/10V

12

C1621

c0402

0.1UF/10V

ASUSTeK COMPUTER INC

Size Project Name

A4

Date: Sheet

2

12

C1622

c0402

0.1UF/10V

A6F

12

C1600

c0402

0.1UF/10V

12

C1623

c0402

0.1UF/10V

Title :

Engineer:

12

C1611

c0402

0.1UF/10V

12

C1624

c0402

0.1UF/10V

DDR2 TERM

Jack Wang

1

12

GND

12

GND

16 63Monday, March 06, 2006

C1612

c0402

0.1UF/10V

C1625

c0402

0.1UF/10V

of

Rev

1.0

5

4

3

2

1

1 2

RTCX1
RTCX2

RTCRST#
INTRUDER#

INTVRMEN
EE_CS

EE_SHCLK
EE_DOUT
EE_DIN

LAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

ACZ_SDOUT
SATALED#
SATA0RXN

SATA0RXP
SATA0TXN
SATA0TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIASN
SATARBIASP

DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ

3

RTC_X1

R1701
10MOhm

RTC_X2

IDE

RTCLAN

CPU LPC

AC-97/AZALIASATA

+1.5VS_PCIE_ICH

LAD0
LAD1
LAD2
LAD3

LDRQ0#

LDRQ1#/GPIO23

LFRAME#
A20GATE

A20M#

CPUSLP#

TP1/DPRSTP#

TP2/DPSLP#

FERR#

GPIO49/CPUPWRGD

IGNNE#

INIT3_3V#

INIT#
INTR

RCIN#

NMI

SMI#

STPCLK#

THERMTRIP#

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0

DA1

DA2

DCS1#
DCS3#

+VCCP_ICH

+VCC_RTC

+VCCP

+1.5VS

+5VS
+3VS
+3VA

AA6
AB5
AC4
Y6

AC3
AA5

AB3
AE22

AH28
AG27
AF24

AH25
AG26
AG24

AG22
AG21
AF22
AF25

AG23
AH24

AF23
AH22
AF26

AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15

AH17
AE17
AF17

AE16
AD16

PD

PU

PU

PUGNT3#

PU

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_DRQ#0
LPC_DRQ#1

LPC_FRAME#
A20GATE

H_A20M#
S_CPUSLP#
S_DPRSTP#

H_DPSLP#
H_FERR#
H_PWRGD

H_IGNNE#
INIT3_3V#
H_INIT#
H_INTR

RCIN#
H_NMI

H_SMI#
H_STPCLK#
S_THRMTRIP#

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_PDA0
IDE_PDA1
IDE_PDA2

IDE_PDCS1#
IDE_PDCS3#

1

1 2
1 2

GPIO16
/DPRSLPVR

GPIO25

INTVRMEN

LINKALERT#

REQ[4:1]#

SATALED#

SPKR

TP3

2

+1.5VS_PCIE_ICH 18,20
+VCCP_ICH 20
+VCC_RTC 20
+VCCP 2,6,9,20,52
+1.5VS 9,10,20,26,36,42,52
+5VS 4,13,19,20,21,22,27,28,36,37,38,44,50,61
+3VS 4,5,7,9,11,12,13,14,15,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61
+3VA 4,12,20,28,37,39,54,59,63

LPC_AD0 25,28,38,41
LPC_AD1 25,28,38,41
LPC_AD2 25,28,38,41
LPC_AD3 25,28,38,41

LPC_DRQ#0 19,25

T1701

LPC_FRAME# 25,28,38,41
A20GATE 28

H_A20M# 2

R1705

/

0Ohm
R1700

/

0Ohm

H_DPSLP# 2

H_PWRGD 2

H_IGNNE# 2
H_INIT# 2

H_INTR 2
RCIN# 28
H_NMI 2

H_SMI# 2
H_STPCLK# 2

IDE_PDD[15:0] 27

IDE_PDA0 27
IDE_PDA1 27
IDE_PDA2 27

IDE_PDCS1# 27
IDE_PDCS3# 27

RSMRST# rising

PWROK rising

PWROK rising

PWROK rising

+VCCP_ICH

R1712

12

24.9Ohm

ASUSTeK COMPUTER INC

Date: Sheet

H_CPUSLP# 2,6
H_DPRSTP# 2,50

1

R1710
56Ohm

should not be pulled high

should not be pulled low

high: Enable integrated VccSus1_05 VRMALWAYS

REQUIRE an extenal pull-up R

should not be pulled low

high: "No reboot" mode

should not be pulled low unless
using XOR Chain testing

Size Project Name

Custom

+VCCP_ICH

R1706
56Ohm

H_FERR# 2

DPRSTP# routing from Intel 82801GBM to
Yonah processor is required. Routing to VR

T1702

must be done last and must have de-bounce
filtering to handle daisy chain topology.

PM_THRMTRIP# 2,4,7

24 ± 5% series termination resistor
placed within 2" from Intel 82801GBM,
56 ± 5% pull-up resistor has to be
within 2" from the series resistor

Title :

Engineer:

A6F

1

PD

PU

Need
PU

Conditional
PU

PD

PU

ICH7-M (1/4)

Jack Wang

Rev

1.0

of

17 63Monday, March 06, 2006

12

C1701 12PF/50V

+VCC_RTC

R1702

180KOhm

D D

C C

ACZ_BCLK_AUD21

ACZ_BCLK_MDC34

ACZ_SYNC_AUD21

ACZ_SYNC_MDC34

ACZ_RST#_AUD21,22

ACZ_RST#_MDC34

B B

ACZ_SDOUT_AUD21

ACZ_SDOUT_MDC34

A A

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

5

12

GND

R1707
39Ohm

R1708
39Ohm

R1709
39Ohm

R1711
39Ohm

R1713
39Ohm

R1715
39Ohm

R1717
39Ohm

R1719
39Ohm

12

C1700

0.1UF/10V

RTCRST#

1 2

12

JRST1

ACZ_BCLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

11/30

GND

+VCC_RTC

R1703

11/14

IDE_PDIOR#27
IDE_PDIOW#27
IDE_PDDACK#27
INT_IRQ1427
IDE_PIORDY27
IDE_PDDREQ27

4

1MOhm

1 2
1 2

R1704

330KOhm

ACZ_SDIN021
ACZ_SDIN134

T1703

T1704

R1714

1 2

0Ohm

T1700
T1705

R1716

1 2

0Ohm

T1706
T1707

R1718

1 2

0Ohm

R1720

0Ohm

GND

ACZ_SDOUT PWROK rising

ACZ_SYNC PWROK rising PD

EE_CS PD

EE_DOUT

GNT2#

GNT5#/GPIO17#
GNT4#/GPIO48

X1700

3

SIDE

32.768KHZ

12

C1702 12PF/50V

RTC_X1
RTC_X2

RTCRST#
INTRUNDER#

INTVRMEN

ACZ_BCLK
ACZ_SYNC

ACZ_RST#
ACZ_SDIN0

ACZ_SDIN1
ACZ_SDIN2

1

ACZ_SDOUT
SATALED#

1

SATA0_R
SATA0_TN

1

SATA0_TP

1

SATA2_R
SATA2_TN

1

SATA2_TP

1

SATA_CLK

SATA2_RBIAS

12

IDE_PDIOR#
IDE_PDIOW#
IDE_PDDACK#
INT_IRQ14
IDE_PIORDY
IDE_PDDREQ

PWROK rising

PWROK rising

2

2

1

1

U1700A

AB1
AB2

AA3

Y5

W4
W1

Y1
Y2

W3

V3
U3
U5

V4

T5
U7

V6

V7
U1

R6
R5

T2

T3

T1

T4

AF18

AF3

AE3
AG2
AH2

AF7

AE7
AG6
AH6

AF1

AE1

AH10
AG10

AF15

AH15

AF16
AH16
AG16
AE15

ICH7M

TP3 pull low: allow entrance to XOR Chain testing
TP3 not pull low: sets bit 1 of RPC.PC

sets bit 0 of RPC.PC

should not be pulled high

should not be pulled low

should not be pulled low

low: "top-block swap" mode

GNT5# GNT4#
0 1 SPI
1 0 PCI
1 1 LPC

5

PCI_AD[31:0]30,33,38

PCI Device

D D

Device

CardBus
LAN
Mini-PCI AD19 REQ3#/GNT3# E, F

C C

IDSEL# REQ#/GNT# Interrupts

AD17
AD23

REQ1#/GNT1#AB, C, D
REQ2#/GNT2#

PCI_INTA#19,33
PCI_INTB#19,30
PCI_INTC#19,30
PCI_INTD#19,30

T1802
T1804
T1806
T1808
T1810

1
1
1
1
1

4

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#

S_RSVD1
S_RSVD2
S_RSVD3
S_RSVD4
S_RSVD5

E18
C18
A16

E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10

AE5
AD5
AG4
AH4
AD9

U1700B

AD0
AD1
AD2

F18

AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20

F11

AD21

F10

AD22

E9

AD23

D9

AD24

B9

AD25

A8

AD26

A6

AD27

C7

AD28

B6

AD29

E6

AD30

D6

AD31

A3

PIRQA#

B4

PIRQB#

C5

PIRQC#

B5

PIRQD#

RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5

ICH7M

PCI

Interrupt I/F

MISC

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

REQ4#/GPIO22

GNT4#/GPIO48

GPIO1/REQ5#

GPIO17/GNT5#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#

RSVD_6
RSVD_7
RSVD_8
RSVD_9

MCH_SYNC#

3

D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8

B15
C12
D12
C15

A7
E10
B18
A12
C9
E11
B10
F15
F14
F16

C26
A9
B19

G8
F7
F8
G7

AE9
AG8
AH8
F21
AH20

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3
PCI_REQ#4
PCI_GNT#4
PCI_REQ#5
PCI_GNT#5

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_IRDY#
PCI_PAR
PCI_RST#_ICH
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLT_RST#_SB
CLK_ICHPCI
PCI_PME#

PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#

S_RSVD6

1

S_RSVD7

1

S_RSVD8

1

S_RSVD9

1

MCH_ICH_SYNC#

PCI_REQ#0 19
PCI_REQ#1 19,30

PCI_GNT#1 30
PCI_REQ#2 19,33
PCI_GNT#2 33
PCI_REQ#3 19,38
PCI_GNT#3 38
PCI_REQ#4 19

PCI_REQ#5 19

PCI_C/BE#0 30,33,38
PCI_C/BE#1 30,33,38
PCI_C/BE#2 30,33,38
PCI_C/BE#3 30,33,38

PCI_IRDY# 19,30,33,38
PCI_PAR 30,33,38

PCI_DEVSEL# 19,30,33,38
PCI_PERR# 19,30,33,38
PCI_LOCK# 19
PCI_SERR# 19,30,33,38
PCI_STOP# 19,30,33,38
PCI_TRDY# 19,30,33,38
PCI_FRAME# 19,30,33,38

CLK_ICHPCI 5
PCI_PME# 19,25,30,33,38

PCI_INTE# 19,38
PCI_INTF# 19,38
PCI_INTG# 19
PCI_INTH# 19

T1803
T1805
T1807
T1809

MCH_ICH_SYNC# 7

2

147

U1800C

VCC

T1801

1

R1801
1KOhm /

1 2
1 2

R1802
1KOhm /

GND

PCI_RST#_ICH

PLT_RST#_SB_R

PLT_RST#_SB

9

10

11

LPC
PCI 0

10
01SPI

N/A

12

1 2

C1800

0.01UF/16V

GND

SN74LV08APWR

GNT#4

GNT#5

1
1
0

1

+3V

147

VCC

1
2

GND

5
4

14 7

+3V

R1800

0Ohm

+3V

8

(default)1

U1800A

3

SN74LV08APWR

U1800B

GND

6

VCC

SN74LV08APWR

PLT_RST#_SB_R

Do not connect to reset on PCI
down devices.

1

147

U1800D

VCC

12
13

PCI_RST# 12,25,26,30,33,38

PLT_RST# 7,19,27,28

+3V

GND

SN74LV08APWR

C1801

0.1UF/10V

1 2

11

E28
E27

H26
H25
G28
G27

K26
K25

M26
M25

P26
P25
N28
N27

T25

T24
R28
R27

F26
F25

J28
J27

L28
L27

R2
P6
P1

P5
P2

D3
C4
D5
D4
E5
C3
A2
B3

U1700D

PERn1
PERp1
PETn1
PETp1

PERn2
PERp2
PETn2
PETp2

PERn3
PERp3
PETn3
PETp3

PERn4
PERp4
PETn4
PETp4

PERn5
PERp5
PETn5
PETp5

PERn6
PERp6
PETn6
PETp6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

ICH7M

V26

DMI0RXN

V25

DMI0RXP

U28

DMI0TXN

U27

DMI0TXP

Y26

DMI1RXN

Y25

DMI1RXP

W28

DMI1TXN

W27

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA28

DMI2TXN

AA27

DMI2TXP

AD25

PCI-ExpressSPI

DMI3RXN

AD24

DMI3RXP

AC28

DMI3TXN

AC27

DMI3TXP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USB

USBRBIAS#

3

DMI_CLKN
DMI_CLKP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

USBRBIAS

AE28
AE27

C25
D25

F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3

D2
D1

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_COMP

USB_PN0_B
USB_PP0_B
USB_PN1_B
USB_PP1_B
USB_PN2_B
USB_PP2_B
USB_PN3_B
USB_PP3_B
USB_PN4_B
USB_PP4_B
USB_PN5_B
USB_PP5_B
USB_PN6_B
USB_PP6_B
USB_PN7_B
USB_PP7_B

USBRBIAS

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PCIE_ICH# 5
CLK_PCIE_ICH 5

R1803 24.9Ohm 1%

1 2

USB_PN0_B 35
USB_PP0_B 35
USB_PN1_B 35
USB_PP1_B 35
USB_PN2_B 35
USB_PP2_B 35
USB_PN3_B 35
USB_PP3_B 35
USB_PN4_B 12
USB_PP4_B 12
USB_PN5_B 26
USB_PP5_B 26

USB_PN7_B 26
USB_PP7_B 26

R1804

1 2

22.6Ohm 1%

+1.5VS_PCIE_ICH

GND

Layout Note:
Pull-ups must be placed within 500
mils from Intel 82801GBM pins

T1838

1

T1839

1

ASUSTeK COMPUTER INC

Size Project Name

Custom

2

Date: Sheet

USB Devices

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7

A6F

Conn. 0
Conn. 1
Conn. 2
Conn. 3
CMOS Camera
Bluetooth

NC

Mini Card

ICH7-M (2/4)

Title :

Engineer:

Jack Wang

1

Rev

1.0

of

18 63Monday, March 06, 2006

T1811
T1812
T1813
T1814

PCIE_RXN2_MINICARD26
PCIE_RXP2_MINICARD26
PCIE_TXN2_MINICARD26

B B

A A

+3VSUS

RN1801A
RN1801B
RN1801C
RN1801D
RN1802A
RN1802B
RN1802C
RN1802D

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

1 2

10KOhm

3 4

10KOhm

5 6

10KOhm

7 8

10KOhm

5

USB_OC_0#
USB_OC_1#
USB_OC_7#
USB_OC_6#
USB_OC_5#
USB_OC_3#
USB_OC_4#
USB_OC_2#

PCIE_TXP2_MINICARD26

C1802 0.1UF/10V

1 2

C1803 0.1UF/10V

1 2

T1815
T1816
T1817
T1818

T1819
T1820
T1821
T1822

T1823
T1824
T1825
T1826

T1827
T1800
T1828
T1829

T1830
T1831
T1832

T1833
T1834

USB_OC_0#35
USB_OC_1#35

4

c0402

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1

1
1

PE_RN1
PE_RP1
PE_TN1
PE_TP1

PE_TN2
PE_TP2

PE_RN3
PE_RP3
PE_TN3
PE_TP3

PE_RN4
PE_RP4
PE_TN4
PE_TP4

PE_RN5
PE_RP5
PE_TN5
PE_TP5

PE_RN6
PE_RP6
PE_TN6
PE_TP6

SPI_CLK
SPI_CS#
SPI_ARB

SPI_MOSI
SPI_MISO

USB_OC_0#
USB_OC_1#
USB_OC_2#
USB_OC_3#
USB_OC_4#
USB_OC_5#
USB_OC_6#
USB_OC_7#

5

4

3

2

1

SMB_CLK
SMB_DAT
LINKALERT#
SM_LINK0
SM_LINK1

RING#

1

1
1

/

1

SPKR_SB
SUS_STAT#
SYS_RST#

PM_BMBUSY#
GPIO11
STP_PCI#

STP_CPU#
GPIO26
WLAN_ON#

BT_ON
PM_CLKRUN#
GPIO33

GPIO34
SB_WAKE#

INT_SERIRQ
PM_THERM#

VRMPWRGD
GPIO6

RF_OFF_SW#
EXTSMI#

D D

IMVPOK39

C C

SPKR_SB21

PM_BMBUSY#7

STP_PCI#5
STP_CPU#5,50

WLAN_ON#12,26,38
BT_ON26

PM_CLKRUN#30,33,38

SB_WAKE#26
INT_SERIRQ25,28,30,38
PM_THERM#28

EXTSMI#28

T1903

T1904
T1905

1 2

R1905 0Ohm

T1908

U1700C

C22

SMBCLK

B22

SMBDATA

A26

LINKALERT#

B25

SMLINK0

A25

SMLINK1

A28

RI#

A19

SPKR

A27

SUS_STAT#

A22

SYS_RST#

AB18

GPIO0/BM_BUSY#

B23

SMBALERT#/GPIO11

AC20

GPIO18/STPPCI#

AF21

GPIO20/STPCPU#

A21

GPIO26

B21

GPIO27

E23

GPIO28

AG18

GPIO32/CLKRUN#

AC19

GPIO33/AZ_DOCK_EN#

U2

GPIO34/AZ_DOCK_RST#

F20

WAKE#

AH21

SERIRQ

AF20

THRM#

AD22

VRMPWRGD

AC21

GPIO6

AC18

GPIO7

E21

GPIO8

ICH7M

SATA

SMB

Clocks

GPIO16/DPRSLPVR

SYS GPIO

Power MGT

GPIO

GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP

GPIO

GPIO37/SATA3GP

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

PWROK

TP0/BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

GPIO9

GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39

AF19
AH18
AH19
AE19

AC1
B2

C20
B24

D23
F22

AA4
AC22
C21
C23

C19
Y4
E20

A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20

GPIO21
GPIO19
BT_LED_EN#
PCB_ID0

CLK_ICH14
CLK_USB48

SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

ICH7_PWROK
PM_DPRSLPVR
PM_BATLOW#
PM_PWRBTN#

PLT_RST#
PM_RSMRST#
SATA_DET#0

USB_PWRSEL
KB_SCI#
SIO_SMI#
PR_IN#_SB
802_LED_EN#
GPIO24
CB_SD#
GPIO35
PCB_ID1
PCB_ID2

R1901 100Ohm

12

T1900

1

BT_LED_EN# 37

CLK_ICH14 5

T1901

1

R1902 0Ohm

12

R1900 0Ohm

12

1

PM_DPRSLPVR 7,50

PM_PWRBTN# 28

PM_RSMRST# 28

KB_SCI# 28
SIO_SMI# 25

802_LED_EN# 37

1

T1907

CB_SD# 30

1

T1909

T1902

PM_BATLOW#

GPIO Power Plane

CPU Vcore
5V Core

3.3V Core

3.3V Resume

B B

PCB_ID0
PCB_ID1
PCB_ID2

A A

GPIO[49]
GPIO[5:1]
GPIO[0][7:6][23:16][39:32][48]
GPIO[15:8][31:24]

SMB_CLK_S5,14,15,26

SMB_DAT_S5,14,15,26

+3VS

+3VS +3VS

12

12

5

R1933

8.2KOhm

/
r0402_h16

R1938

8.2KOhm

r0402_h16

GND

12

R1934

8.2KOhm

/
r0402_h16

12

R1939

8.2KOhm

r0402_h16

Q1902 2N7002

S

2

G

1

1

1

1

G

2

S

Q1900 2N7002

12

R1935

8.2KOhm

/
r0402_h16

12

R1940

8.2KOhm

r0402_h16

+5VS

Q1901

1

2N7002

1

G

3 2

3

D

D

SMB_CLK

32

3

+5VS

3

SMB_DAT

32

D

VRMPWRGDICH7_PWROK

2

S

R1912
10KOhm

1 2

GND

PCB_VID3 : PROJECT CODE
PCB_VID

MB V1.0

0 1 2
0 0 0

4

DPRSLPVR contains same information
as DPRSTP#.

GND

DPRSLPVR is preferred over DPRSTP#
if only one signal will be used.

PM_SUSB# 28
PM_SUSC# 28

PCI_PME#18,25,30,33,38

1 2

GND

R1903
10KOhm

1 2

GND

R1904
10KOhm

1 2

GND

D1900

1 2

1N4148W

checklist suggests
+3Vsus

3

CLK_USB48 5

C1900

/

10PF/50V

ICH7_PWROK 7,28

PLT_RST# 7,18,27,28 PCI_INTC#18,30

If ICH7M embedded Lan
controller was used
"LAN_RST#" should be
connected to "RSMRST#"

BAT_LL# 28

+3VSUS

USB_PWRSEL
KB_SCI#
SYS_RST#
GPIO11

RING#
PM_BATLOW#
SATA_DET#0
SIO_SMI#
802_LED_EN#
PR_IN#_SB

CB_SD#

Internal pull up

SMB_CLK
SMB_DAT

SB_WAKE#

SM_LINK1
SM_LINK0
LINKALERT#

SUS_STAT#

Internal pull up

R1906 10KOhm

1 2

R1907 10KOhm

1 2

R1909 10KOhm

1 2

R1911 10KOhm

1 2

R1914 8.2KOhm

1 2

R1916 8.2KOhm

12

R1918 8.2KOhm

1 2

R1920 8.2KOhm

1 2

R1922 8.2KOhm

1 2

R1924 8.2KOhm

1 2

R1926 8.2KOhm /

1 2

R1928 2.2KOhm

1 2

R1929 2.2KOhm

1 2

R1931 1KOhm

1 2

RN1900A 10KOhm

1 2

RN1900B

3 4

RN1900C
RN1900D

R1941 4.7KOhm

R1942 10KOhm

10KOhm

5 6

10KOhm

7 8

10KOhm

1 2

1 2

/

/

11/29

+3VSUS

2

PCI_TRDY#18,30,33,38
PCI_LOCK#18
PCI_SERR#18,30,33,38
PCI_PERR#18,30,33,38

PCI_REQ#518

PCI_REQ#018
PCI_IRDY#18,30,33,38
PCI_DEVSEL#18,30,33,38

PCI_INTB#18,30

PCI_INTA#18,33

PCI_INTD#18,30

PCI_INTG#18

PCI_INTF#18,38

PCI_INTH#18

PCI_INTE#18,38

PCI_REQ#418

PCI_REQ#118,30

PCI_REQ#218,33

PCI_REQ#318,38

PCI_FRAME#18,30,33,38
PCI_STOP#18,30,33,38

LPC_DRQ#017,25

ASUSTeK COMPUTER INC

Size Project Name

A3

Date: Sheet

PCI_TRDY#
PCI_LOCK#
PCI_SERR#
PCI_PERR#
PCI_REQ#5
PCI_REQ#0
PCI_IRDY#
PCI_DEVSEL#

PCI_INTB#
PCI_INTA#
PCI_INTC#
PCI_INTD#
PCI_INTG#
PCI_INTF#
PCI_INTH#
PCI_INTE#

PCI_REQ#4
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PM_CLKRUN#
PM_THERM#
PCI_FRAME#
PCI_STOP#

SMB_CLK_S
SMB_DAT_S

INT_SERIRQ
STP_PCI#
STP_CPU#

GPIO6
RF_OFF_SW#
GPIO19
BT_LED_EN#

LPC_DRQ#0

Internal pull up

BT_ON
WLAN_ON#

PM_RSMRST#

PM_DPRSLPVR

Internal pull down

A6F

RP1900A

1 5

8.2KOHM

RP1900B

2 5

8.2KOHM

RP1900C

3 5

8.2KOHM

RP1900D

4 5

8.2KOHM

RP1900E

6 5

8.2KOHM

RP1900F

7 5

8.2KOHM

RP1900G

8 5

8.2KOHM

RP1900H

9 5

8.2KOHM

RP1901A

1 5

8.2KOHM

RP1901B

2 5

8.2KOHM

RP1901C

3 5

8.2KOHM

RP1901D

4 5

8.2KOHM

RP1901E

6 5

8.2KOHM

RP1901F

7 5

8.2KOHM

RP1901G

8 5

8.2KOHM

RP1901H

9 5

8.2KOHM

RP1902A

1 5

8.2KOHM

RP1902B

2 5

8.2KOHM

RP1902C

3 5

8.2KOHM

RP1902D

4 5

8.2KOHM

RP1902E

6 5

8.2KOHM

RP1902F

7 5

8.2KOHM

RP1902G

8 5

8.2KOHM

RP1902H

9 5

8.2KOHM

R1908 2.2KOhm

12

R1910 2.2KOhm

12

R1913 10KOhm

1 2

R1915 10KOhm /

1 2

R1917 10KOhm /

1 2

<Optional>

R1919 8.2KOhm

12

R1921 8.2KOhm

12

R1923 8.2KOhm

12

R1925 8.2KOhm

1 2

R1927 8.2KOhm /

12

R1930 8.2KOhm

1 2

R1932 8.2KOhm

1 2

R1936 10KOhm

1 2

R1937 100KOhm/

1 2

Title :

Engineer:

1

+3VS

10
10
10
10
10
10
10
10

10
10
10
10
10
10
10
10

10
10
10
10
10
10
10
10

GND

ICH7-M (3/4)

Jack Wang

19 63Monday, March 06, 2006

of

Rev

1.0

5

+3VS

D2000

2

+1.5VS_DMIPLL

L2000

21

12

C2027

0.1UF/10V

+1.5VS

GND

3

12

C2001

0.1UF/10V

GND

3

12

C2005

0.1UF/10V

GND

12

C2007

0.1UF/10V

12

C2018

10UF/10V

+1.5VS

12

0.1UF/10V

GND

+3VSUS

GND

10 mA

12

C2032

c0402

0.1UF/10V

BAT54C

V5REF

D2001

BAT54C

V5REF_SUS

770 mA

12

C2008

0.1UF/10V

+3VS

GND

12

0.01UF/50V

GND

+1.5VS

C2023

12

C2030

0.1UF/10V

T2003

1

+3VSUS

2
1

12

C2014

0.1UF/10V

50 mA

C2000

50 mA

12

C2024

0.1UF/10V

GND

+1.5VS

1

30 mA

6 mA

10 mA

12

C2009

0.1UF/10V

640 mA

12

1UF/10V

GND

VCCLAN

+5VS

R2001

1 2

+5VSUS

1 2

+1.5VS_PCIE_ICH

L2001

21

GND

100Ohm

R2003

10Ohm

12

+

CE2000
220UF/4V

c7343d_h75

80Ohm/100Mhz

+3VS

GND

D D

Layout Note:
Place above Caps within 100 mils of
ICH7-M on the Bottom side or 140 mils
on the Top near pin D28, T28 & AD28

+1.5VS

C C

+1.5VS

R2004

1 2

1Ohm

Layout Note:
Place within 100 mils of ICH7-M

B B

A A

on the Bottom side or 140 mils
on the Top near pin AG5

Layout Note:
Place within 100 mils of
ICH7-M on the Bottom side or
140 mils on the Top

Layout Note:
Place within 100 mils of
ICH7-M on the Bottom side or
140 mils on the Top

Layout Note:
Place within 100 mils of ICH7-M
on the Bottom side or 140 mils
on the Top near pin AG9

80Ohm/100Mhz

Layout Note:
Place within 100 mils of ICH7-M
on the Bottom side or 140 mils
on the Top

+1.5VS_DMIPLL_L

5

C2031

4

U1700F

G10

V5REF_1

AD17

V5REF_2

F6

V5REF_Sus

AA22

Vcc1_5_B_1

AA23

Vcc1_5_B_2

AB22

Vcc1_5_B_3

AB23

Vcc1_5_B_4

AC23

Vcc1_5_B_5

AC24

Vcc1_5_B_6

AC25

Vcc1_5_B_7

AC26

Vcc1_5_B_8

AD26

Vcc1_5_B_9

AD27

Vcc1_5_B_10

AD28

Vcc1_5_B_11

D26

Vcc1_5_B_12

D27

Vcc1_5_B_13

D28

Vcc1_5_B_14

E24

Vcc1_5_B_15

E25

Vcc1_5_B_16

E26

Vcc1_5_B_17

F23

Vcc1_5_B_18

F24

Vcc1_5_B_19

G22

Vcc1_5_B_20

G23

Vcc1_5_B_21

H22

Vcc1_5_B_22

H23

Vcc1_5_B_23

J22

Vcc1_5_B_24

J23

Vcc1_5_B_25

K22

Vcc1_5_B_26

K23

Vcc1_5_B_27

L22

Vcc1_5_B_28

L23

Vcc1_5_B_29

M22

Vcc1_5_B_30

M23

Vcc1_5_B_31

N22

Vcc1_5_B_32

N23

Vcc1_5_B_33

P22

Vcc1_5_B_34

P23

Vcc1_5_B_35

R22

Vcc1_5_B_36

R23

Vcc1_5_B_37

R24

Vcc1_5_B_38

R25

Vcc1_5_B_39

R26

Vcc1_5_B_40

T22

Vcc1_5_B_41

T23

Vcc1_5_B_42

T26

Vcc1_5_B_43

T27

Vcc1_5_B_44

T28

Vcc1_5_B_45

U22

Vcc1_5_B_46

U23

Vcc1_5_B_47

V22

Vcc1_5_B_48

V23

Vcc1_5_B_49

W22

Vcc1_5_B_50

W23

Vcc1_5_B_51

Y22

Vcc1_5_B_52

Y23

Vcc1_5_B_53

B27

Vcc3_3_1

AG28

VccDMIPLL

AB7

Vcc1_5_A_1

AC6

Vcc1_5_A_2

AC7

Vcc1_5_A_3

AD6

Vcc1_5_A_4

AE6

Vcc1_5_A_5

AF5

Vcc1_5_A_6

AF6

Vcc1_5_A_7

AG5

Vcc1_5_A_8

AH5

Vcc1_5_A_9

AD2

VccSATAPLL

AH11

Vcc3_3_2

AB10

Vcc1_5_A_10

AB9

Vcc1_5_A_11

AC10

Vcc1_5_A_12

AD10

Vcc1_5_A_13

AE10

Vcc1_5_A_14

AF10

Vcc1_5_A_15

AF9

Vcc1_5_A_16

AG9

Vcc1_5_A_17

AH9

Vcc1_5_A_18

E3

VccSus3_3_19

C1

VccUSBPLL

AA2

VccSus1_05/VccLAN1_05_1

Y7

VccSus1_05/VccLAN1_05_2

ICH7M

4

Vcc1_05_1
Vcc1_05_2
Vcc1_05_3
Vcc1_05_4
Vcc1_05_5
Vcc1_05_6
Vcc1_05_7
Vcc1_05_8
Vcc1_05_9

Vcc1_05_10

CORE

Vcc1_05_11
Vcc1_05_12
Vcc1_05_13
Vcc1_05_14
Vcc1_05_15
Vcc1_05_16
Vcc1_05_17
Vcc1_05_18
Vcc1_05_19

VCCPAUX

Vcc1_05_20

VccSus3_3/VccLAN3_3_1
VccSus3_3/VccLAN3_3_2
VccSus3_3/VccLAN3_3_3
VccSus3_3/VccLAN3_3_4

Vcc3_3/VccHDA

VccSus3_3/VccSusHDA

V_CPU_IO1
V_CPU_IO2
V_CPU_IO3

IDEPCIUSB

USB CORE

Vcc3_3_3
Vcc3_3_4
Vcc3_3_5
Vcc3_3_6
Vcc3_3_7
Vcc3_3_8

Vcc3_3_9
Vcc3_3_10
Vcc3_3_11

Vcc3_3_12
Vcc3_3_13
Vcc3_3_14
Vcc3_3_15
Vcc3_3_16
Vcc3_3_17
Vcc3_3_18
Vcc3_3_19
Vcc3_3_20
Vcc3_3_21

VccRTC
VccSus3_3_1
VccSus3_3_2

VccSus3_3_3
VccSus3_3_4
VccSus3_3_5
VccSus3_3_6

VccSus3_3_7
VccSus3_3_8
VccSus3_3_9

VccSus3_3_10
VccSus3_3_11
VccSus3_3_12
VccSus3_3_13
VccSus3_3_14
VccSus3_3_15
VccSus3_3_16
VccSus3_3_17
VccSus3_3_18

Vcc1_5_A_19
Vcc1_5_A_20

Vcc1_5_A_21
Vcc1_5_A_22
Vcc1_5_A_23

Vcc1_5_A_24
Vcc1_5_A_25

VccSus1_05_1
VccSus1_05_2

VccSus1_05_3

Vcc1_5_A_26
Vcc1_5_A_27
Vcc1_5_A_28
Vcc1_5_A_29
Vcc1_5_A_30

VCCA3GP

ARX

ATX

L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

V5
V1
W2
W7

U6
R7
AE23

AE26
AH26

AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19

A5
B13
B16
B7
C10
D15
F9
G11
G12
G16

W5
P7
A24

C24
D19
D22
G19

K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7

AB17
AC17

T7
F17
G17

AB8
AC8

K7
C28

G20
A1

H6
H7
J6
J7

40 mA

10 mA

14 mA

270 mA

45 mA

940 mA

12

0.1UF/10V

GND

VCCSUS3

56 mA

12

0.1UF/10V

12

0.1UF/10V

GND

12

0.1UF/10V

GND

12

0.1UF/10V

GND

12

0.1UF/10V

+1.5VS

12

0.1UF/10V

GND

SUS1_05

+1.5VS

12

0.1UF/10V

GND

3

+VCCP_ICH

12

C2003

C2002

1UF/10V

R2000
0Ohm

1 2

R2002

1 2

0Ohm /

12

C2004

0.1UF/10V

GND

+3VSUS

C2010

C2013

C2015

C2021

C2025

C2029

C2033

+VCCP_ICH

12

C2011

0.1UF/10V

+3VS

12

C2016

0.1UF/10V

12

C2022

0.1UF/10V

+3VSUS

12

C2026

0.1UF/10V

GND

T2002

1

17 mA

Layout Note:
Place within 100 mils of
ICH7-M on the Bottom side
or 140 mils on the Top

3

+3VS

12

0.1UF/10V

GND

GND

+3VS

+3VSUS

12

+

CE2001
470UF/2.5V

c7343d_h75

+3VS

+3VSUS

C2006

12

C2012

4.7U/6.3V

12

C2017

0.1UF/10V

1 2

1 2

+VCCP

JP2001

SHORT_PIN

/

JP2000

SHORT_PIN

/

If ICH7 embedded Lan
controller was used, these
pins should connect to
+3VSUS for S3-S5 wake up.

Layout Note:
Place within 100 mils of ICH7-M
on the Bottom side or 140 mils
on the Top near pin

Layout Note:
Place within 100 mils of ICH7-M
on the Bottom side or 140 mils
on the Top near pin

Layout Note:
Distribute in PCI section

+VCC_RTC

12

12

C2019

C2020

0.1UF/10V

0.1UF/10V

GND

T2000

1

RTC_BAT

12

BAT1

BATT_HOLDER

GND

R2005

1KOhm

RTC_BAT_R

12

T2001

2

+3VA +VCC_RTC

D2002

2

3

1

1

2

RB715F

12

1UF/10V

1

U1700E

C2028

A4

Vss1

A23

Vss2

B1

Vss3

B8

Vss4

B11

Vss5

B14

Vss6

B17

Vss7

B20

Vss8

B26

Vss9

B28

Vss10

C2

Vss11

C6

Vss12

C27

Vss13

D10

Vss14

D13

Vss15

D18

Vss16

D21

Vss17

D24

Vss18

E1

Vss19

E2

Vss20

E4

Vss21

E8

Vss22

E15

Vss23

F3

Vss24

F4

Vss25

F5

Vss26

F12

Vss27

F27

Vss28

F28

Vss29

G1

Vss30

G2

Vss31

G5

Vss32

G6

Vss33

G9

Vss34

G14

Vss35

G18

Vss36

G21

Vss37

G24

Vss38

G25

Vss39

G26

Vss40

H3

Vss41

H4

Vss42

H5

Vss43

H24

Vss44

H27

Vss45

H28

Vss46

J1

Vss47

J2

Vss48

J5

Vss49

J24

Vss50

J25

Vss51

J26

Vss52

K24

Vss53

K27

Vss54

K28

Vss55

L13

Vss56

L15

Vss57

L24

Vss58

L25

Vss59

L26

Vss60

M3

Vss61

M4

Vss62

M5

Vss63

M12

Vss64

M13

Vss65

M14

Vss66

M15

Vss67

M16

Vss68

M17

Vss69

M24

Vss70

M27

Vss71

M28

Vss72

N1

Vss73

N2

Vss74

N5

Vss75

N6

Vss76

N11

Vss77

N12

Vss78

N13

Vss79

N14

Vss80

N15

Vss81

N16

Vss82

N17

Vss83

N18

Vss84

N24

Vss85

N25

Vss86

N26

Vss87

P3

Vss88

P4

Vss89

P12

Vss90

P13

Vss91

P14

Vss92

P15

Vss93

P16

Vss94

P17

Vss95

P24

Vss96

P27

Vss97

ICH7M

GND GND

Vss98

Vss99
Vss100
Vss101
Vss102
Vss103
Vss104
Vss105
Vss106
Vss107
Vss108
Vss109
Vss110
Vss111
Vss112
Vss113
Vss114
Vss115
Vss116
Vss117
Vss118
Vss119
Vss120
Vss121
Vss122
Vss123
Vss124
Vss125
Vss126
Vss127
Vss128
Vss129
Vss130
Vss131
Vss132
Vss133
Vss134
Vss135
Vss136
Vss137
Vss138
Vss139
Vss140
Vss141
Vss142
Vss143
Vss144
Vss145
Vss146
Vss147
Vss148
Vss149
Vss150
Vss151
Vss152
Vss153
Vss154
Vss155
Vss156
Vss157
Vss158
Vss159
Vss160
Vss161
Vss162
Vss163
Vss164
Vss165
Vss166
Vss167
Vss168
Vss169
Vss170
Vss171
Vss172
Vss173
Vss174
Vss175
Vss176
Vss177
Vss178
Vss179
Vss180
Vss181
Vss182
Vss183
Vss184
Vss185
Vss186
Vss187
Vss188
Vss189
Vss190
Vss191
Vss192
Vss193
Vss194

P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27

Title :

ASUSTeK COMPUTER INC

Size Project Name

A3

Date: Sheet of

A6F

Monday, March 06, 2006

Engineer:

1

ICH7-M (4/4)

Jack Wang

Rev

1.0

6320