There is a possiblity that power amp
outputs may have to be connected to the
speaker terminals with flying leads.
Depends on board space available for
heavy tracks.
These caps on audio clock and data lines from
the Vaddis are not fitted to help improve the
video noise floor problems on CVBS. (In
conjunction with high value source resistance
NF
termination on the video board.)
NF
+3V3(STBY)
GND
P81
P82
P83
P84
P85
P86
P87
P88
SKT9
Zone2 / Record
SCRN
GND
P89
HS_TEMP
AMP_MUTE_LCR*
AMP_MUTE_SUR*
PWR_AMP_SR
PWR_AMP_R
PWR_AMP_C
PWR_AMP_L
PWR_AMP_SL
SKT3
SKT8
KYOYAKU GOLD
SKT4
KYOYAKU GOLD
PRE_OUT_CPRE_OUT_L
PRE_OUT_SUB
KYOYAKU
GOLD
Solo 2.1 only
NF Solo 5.1
Z2_OUT_L
Z2_OUT_R
CON4
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
MOLEX
52806
GND
1mm FFC - Molex / 52806-1610
Solo 5.1 only
NF Solo 2.1
SCRN
SCRN
GND
To L103AY (Power Amp Board)
PRE_OUT_R
PRE_OUT_SL
PRE_OUT_SR
Solo 2.1 only
NF Solo 5.1
GOLD
KUNMING
SKT7
GND
SCRN
To L108AY (Display Board)
L998CT - Solo Movie 5.1
Main/Audio PCB
QTYDESCRIPTIONPART No.NOTESITEM
ITEM31Blank PCB Solo5.1 Main BoardL998PB
DRAWING TITLE
Solo Movie Main PCB - Top level
Filename:
Top level Solo Movie 3.0.prj
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB25 9QR
Notes:
Contact Engineer:
markt@arcam.co.uk
Contact Tel:
AJD25/06/073.0Added connectors for Solo 2.1 options07_E129
07_E084MJT11/06/07
07_E045MJT07/03/07
07_E014MJT01/02/07No schematic changes. Layout change only (R620, R621 moved)2.0
06_E194MJT23/01/071.0
ECO No.DESCRIPTION OF CHANGE
01223 203210 (direct)Mark Tweedale
01223 203200 (reception)
INITIALS
Printed:
2-Aug-2007
None to this sheet.
Changed R442 - R445 for compatibility with revised VFD.
None to this sheet.
Changed C810, C851 to longer life parts due to heat.
SKT500 changed to common GND/EMC type, R338, R339,
R217, R647 added to PCB. Some caps on CON2 removed
06_E194 MJT23/01/071.0Full production. No changes to this sheet
ECO No.DESCRIPTION OF CHANGE
01223 203210 (direct)Mark Tweedale
01223 203200 (reception)
+3V3(H8)
C411
C415
10uF
10N
10V
50V
1206
0603
GND
+5V(D)+5V(D)+5V(D)
R439
1K0
0603
TR403
MMUN2211LT1
SOT-23
GNDGNDGND
PLL_CLK*
P440
PLL_CE*
PLL_DI*
TRIG_OUT*
+3V3(H8)
RST
GND
P451
P482
P483
P485
P486
P484
P487
VADDIS_PROG_UVADDIS_PROG
PATH_AD*
PATH_B*
PATH_C*
P441
P442
Choose a lower reset voltage?
VCC
GND
R416
4K7
0603
R442330R
P445
R443330R
P446
R444330R
P447
R445330R
P448
AJD25/06/073.007_E129None to this sheet.
DATE
INITIALS
2-Aug-2007
Printed:
C416
10N
50V
0603
P495
P496
P497
R427
R434
4K7
4K7
0603
0603
P449
P450
R437 1K0 0603
+3V3(H8)
GND
0603
0603
0603
0603
R424
1K0
0603
411Sheetof
C410
10uF
10V
1206
R440
1K0
0603
TR404
MMUN2211LT1
SOT-23
I2CDAB_SCLK
I2CDAB_SDA
I2CDAB_RES*
I2C_SCLK
I2C_SDA
I2C_RES*
CODEC_INT
R435
R436
4K7
4K7
0603
0603
C406
47P
50V
0603
TX_CMOS
P473
Notes for H8 uC
----------------------- ----RXD2/TXD2 (pins 98/97) are the
RS232 coms to the Vaddis
Set Real-time clock to use internal
trickle charge (single diode and 2k
resistor)
XTAL is now 25MHz. Is this a
problem for timing?
+3V3(H8)
C413
C436
10N
10uF
50V
10V
0603
1206
GND
These sigs should be high in standby
for minimum current draw
+3V3(H8)
R453
R454
4K7
4K7
0603
0603
PG4
P53
WDTOVF*
RES(in)*
PG5
PG6
RES*
GND
C407
C408
47P
47P
50V
50V
0603
0603
TX_CMOSRX_CMOS
VADDIS_PROG
P472
PATH_AD*
PATH_B*
P474
PATH_C*
DRAWING NO.
A2
C435
10N
50V
0603
R441
1K0
0603
TR405
MMUN2211LT1
SOT-23
NF
CON499
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3M
2500 series
C409
47P
50V
0603
GND
L998CT
PLL_CLK
PLL_CE
PLL_DI
TRIG_OUT*
Bodged for JTAG socket
DISP_BLK
DISP_LAT
DISP_CLK
DISP_DAT
ISSUE
SKT500
SAT
AV
KYOYAKU
GOLD
P549
1
VCC
O/P
GND
2
GND
1
VCC
O/P
GND
2
GND
DAB_DIGOP_SW
R500
75R
0W125
0805
GND
C501
100N
16V
0603
3
RX500
OC-0805R*007
C502
100N
16V
0603
3
RX501
OC-0805R*007
-3dB point at: 1/(2*Pi*[100+75]*47p) = 19.4MHz
P515P523
P516
C521
10uF
10V
1206
GND
P517P524
P518
C522
10uF
10V
1206
GND
P519P525
R506
1K8
0603
R505
100R
0603
+5V(D)
R501
10R
0W125
0805
R504
1K8
0603
+5V(D)
R502
10R
0W125
0805
R507
1K8
0603
Output approx 0.5V
R533
220R
0603
GND
GND
Output approx 0.5V
GND
Output approx 0.5V
GND
P526
Switched Input from DAB and possible streaming client card
+3V3(D)
C529
470N
16V
GND
0805
12
16
EN
CLK27M_VADDIS
OK to have
unconnected inputs
(produces HIGH output)
12M_CLK_EN*
24M_CLK_EN*
+5V(D)
R521
0R0
0603
GND
24M/22M*
RMCK
C550
27P
50V
0603
C551
27P
50V
0603
24M/22M*
DIN110DOUT1+
11
DIN2
2
RIN1+
NC
1
NC
RIN1-
3
NC
RIN2+
4
RIN2-
NC
R542
4K7
0603
R543
4K7
0603
REG500
LM1117MPX-3.3
SOT-223
P536
C517
100N
16V
0603
GNDGND
R527
10K
0603
DOUT1-
DOUT2+
DOUT2-
ROUT1
ROUT2
EN
9
13
GND
24M_CLK_EN_R*
+3V3
P520
X500
27MHz
HC49
P521
P522
VCC
GND
7
8
6
5
15
NC
14
NC
IC508
SN65LVDS049
TSSOP-16
P590
P527
NC
No output termination resistors:
Built-in 50 Ohm source impedance.
IC507C
56
74HC04D SO-14
+3V3(PLL)
C543
100UF
10V
YXF
1
7
XTI
8
XTO
14
FSEL
16
NC
2
C546
47P
50V
0603
R534
220R
0603
R535
220R
0603
RMCK+
RMCK-
CLK27M_VADDIS+
CLK27M_VADDIS-
DIV_2_EN12M_CLK_EN_R*
P589P588
VDD312VDD1
IC506
SM8707E
VSOP-16
VSS311VSS1
GND
C531
10N
50V
0603
C530
10N
50V
0603
C535
10N
50V
0603
C536
10N
50V
0603
C534
10N
50V
0603
C518
100N
16V
0603
5
6
To Vaddis 8
To Vaddis 8
To Vaddis 8
To Vaddis 8
VDD2
MO1
MO2
AO1
AO2
SO1
SO2
VSS2
GND
C519
100N
16V
0603
3
4
9
10
13
15
NC
NC
CLOCK GENERATOR
C537
10N
50V
0603
C520
100N
16V
0603
R529
56R 0603
P504
SPDIF data rate @ 96kHz 2-ch PCM:
96k x 32 bits x 2 channels = 6.144MHz
Bi-phase encoding has up to 2 symbols per bit.....
Therefore minimum bandwith is 12.288MHz
SPDIF_SAT_ELEC
SPDIF_SAT
SPDIF_AUX
C539
C538
10N
10N
50V
50V
0603
0603
ADC_PCM
CODEC_INT
CLK27M_VADDIS
P597
R509
P503
100R 0603
R510
P505
100R 0603
R511
100R 0603
SMPS_CLK_FAST
I2C_RES*
I2C_SCLK
I2C_SDA
R520
2K0
0603
GND
ADC_BUF_L+
ADC_BUF_L-
ADC_BUF_R+
ADC_BUF_R-
P507
Note about ground pins on CS42528:
The two DGND pins (5 & 52) have about 3.5 Ohms between
them in the device.
The two AGND pins (25 & 40) have several MegOhms
between them and DGND
Conclusion: AGND and DGND appear to be separate within
the chip
Ditch the parallel caps and just have the largest value?
14
C509
100N
16V
0603
7
C515
100N
16V
0603
C516
100N
16V
0603
VQ used to bias ADC input signals
VQ (nominal) = 2.7V
Max allowed VQ current = 10uA
Therefore smallest load = 270k Ohms!!!
Use FET input opamp, eg TL072 (cheap)
Low-pass filter output to reduce noise
(Spec is 50nV/RtHz with gain=10 : quite noisey!)
06_E194 MJT23/01/071.0Full production. No changes to this sheet
01223 203210 (direct)Mark Tweedale
01223 203200 (reception)
+5V(D)
R503
10R
0W125
0805
14
7
11
10
14
13
15
GND
C511
100N
16V
0603
-3dB = 159Hz
GND
IC507F
74HC04D
SO-14
DATE
2-Aug-2007
IC500A
1I021Y
3
1I1
5
2I0
6
2I1
3I0
3I1
4I0
4I1
1
S
EN
74HCT157D
SO-16
IC500B
VCC
GND
74HCT157D
SO-16
C549
100N
16V
0603
1213
VAD_DIGOP
DAB_DIGOP
DAB/VAD*
IC503C
VCC
GND
74LVC74AD
S0-14
R526
P552P553
10K
0603
R515 330R
P555
0603
P557
0603
AJD25/06/073.007_E129None to this sheet.
ECO No.DESCRIPTION OF CHANGE
INITIALS
Printed:
16
8
C554
10uF
10V
1206
VQ_BUF
2Y
3Y
4Y
+5V(D)
GND
511Sheetof
4
P559P560
7
9
NC
12
NC
C510
100N
16V
0603
IC504B
VCC
GND
74HC4040D
SO-16
R514 330R
0603
C525
10uF
10V
1206
GND
R508
100R
0603
P586
C553
10uF
10V
1206
16
C512
100N
16V
0603
8
GND
SMPS_SYNC
P565
SMPS_SYNC*
P566P556
A2
P558
C506
100N
16V
0603
1
I/P
GND
DAB_DIGOP_SW
+3V3(D)
2
D
3
CLK
GND
C528
10uF
10V
1206
P561
R538
0R0
0603
12
34
GND
R518
P563
1211
47K 0603
R519
P564
47K 0603
DRAWING NO.
TX500
2
OC-0805T*001
VCC
GND
3
IC503A
74LVC74AD
4
S0-14
5
Q
SD*
6
!Q
RD*
1
IC507G
14
VCC
7
GND
74HC04D
SO-14
IC507D
89
P562
74HC04D SO-14
IC507A
74HC04D SO-14
IC507B
74HC04D SO-14
IC507E
1011
74HC04D SO-14
IC502D
13
74LVC125AD
SO-14
98
IC502C
10
74LVC125AD
SO-14
SMPS_SYNC
SMPS_SYNC*
L998CT
NC
NC
NC
NC
NC
P587
C542
100N
16V
0603
NC
ISSUE
PRE_L
PRE_R
PRE_C
PRE_SUB
PRE_SL
PRE_SR
+7V(A)
C600
100N
16V
0603
84
3
2
-7V(A)
5
6
NFNF
R606
47K
0603
GND
R607
47K
0603
GND
GND
1
C601
100N
16V
0603
7
PRE_REC_L
PRE_REC_R
DAC_2DMIX_L
DAC_2DMIX_R
R604
47R
0603
R608
47R
0603
R600
1K0
0603
R605
1K0
0603
P600
IC604A
NJM2114M
DMP-8
P601
IC604B
NJM2114M
DMP-8
P621
P624
Z2_SEL_PRE
Z2_SEL_2D
Select preamp record out or 2-ch D.Mix
+5V(D)
R620
100K
0603
R621
100K
0603
R627
2R2
0W125
0805
Note:
When headphones are inserted while a
DD5.1 or similar soundtrack is playing,
the 5.1 outputs mute and the preamp
routes the 2chDmix to L/R.
PRE_L
PRE_R
PREAMP_MUTE
P642
P643
R615
0R00603
9
R639
0R00603
8
1
16
C624
470UF
25V
YK
GND
P607
P608
C636
100UF
10V
YXF
C637
100UF
10V
YXF
1011
NF
IC602C
DG412DY
SO-16
67
NF
IC602B
DG412DY
SO-16
23
NF
IC602A
DG412DY
SO-16
1415
NF
IC602D
DG412DY
SO-16
GND
C602
100N
50V
0805
P640
P641
R640
47K
0603
GND
P604
P605
PREAMP_CLK
PREAMP_DA
PREAMP_MUTE
P606
C628
1UF 50V YK
C629
1UF 50V YK
C627
10UF
50V
YK
SURR_SEL_0
SURR_SEL_1
R641
47R 0603
R642
47R 0603
SCART audio output
R646
47K
goes via mutes on Preamp.sch page
0603
10V
C603
100UF
YXF
10V
C604
100UF
YXF
+7V(A)
R613
10K
0603
Pull-up on SEL to
+7V(A) sets address
for Z2 volume:
D2 = 1
D1 = 1
to use same control
lines as main vol
chip.
P613
C622
33P
50V
NF
0603
P615
P616
P617
C623
33P
50V
NF
0603
P619
R622
1K0
0603
P602
P603
R623
75K
0603
R624
75K
0603
P612
P620
+7V(A)
R601
47K
0603
P609
FIXED_VOL_L
FIXED_VOL_R
Zone 2 volume
May not need in and out coupling caps
Don't think we need these output coupling caps
P610
P611
12
10
HEADPHONE AMP
100mW 20-30 ohms
8
2
3
6
4
5
1
IN1
3
IN2
SEL
8
CL
9
DA
MUTE
DGND
11
GNDGND
IC607
1
7
LM4880M
SO-8
NF
R614
1K0
0603
+7V(A)
7
AGND12AGND24AGND3
C625
470UF
25V
YK
C626
470UF
25V
YK
GND
C607
100N
16V
0603
VCC
OUT1
OUT2
VEE
6
5
-7V(A)
P614
R625
2K2
0603
R626
2K2
0603
P618
P622
P623
R603
R602
1K0
1K0
0603
0603
GND
C612
100UF
10V
WL
GND
14
P625
13
P627
IC606
BD3812F
SO-14
GND
C613
C608
100UF
100N
10V
16V
WL
0603
R629
4R7
1W
CF
Note re: Update PCB process and HP_OUT_L and
HP_OUT_R
For some reason, the update PCB process has always
wanted to disconnect and then re-connect these two
nets. I cannot find the cause for this oddity, however
ignoring it seems to be the right thing to do!
(Mark T 08/12/06)
R630
4R7
1W
CF
R643
47R 0603
R644
47R 0603
HP_OUT_L
HP_OUT_R
GND
To Power Amps--------------------- To Pre-out Phonos ---------------------
PWR_AMP_L
PWR_AMP_R
PWR_AMP_C
PWR_AMP_SL
+7V(A)
14
4
X0
V+
5
X1
6
X2
7
X3
13
Y1
12
Y2
11
Y3
10
Y4
2
EN
1
A0
16
A1
15
GND
P644
P645
-7V(A)
COMX
COMY
V-
3
GND
8
9
IC605
DG409DY
SO-16
IN0: Default - mute on power up
IN1: Biamp mode - LS amp = L, RS amp = R
IN2: Zone2 amps - LS amp = Z2 L, RS amp = Z2 R
IN3: Normal 5.1 - LS amp = LS, RS amp = RS
Note: want Normal 5.1 on IN3 as this has the worst
non-selected X-talk to the output as this input pin is
closest to the output pin.
C609
100N
16V
0603
C610
100N
16V
0603
R647
1M0
0W063
0603
NC
NC
D600
BAT54S
SOT-23
C630
100UF
25V
YK
D601
BAT54S
SOT-23
PREOUT_MUTE*
P629
P630
+7V(A)
-7V(A)
+7V_MUTES
R645
1M0
0603
-7V_MUTES
67
IC600B
DG412DY
PREOUT_MUTE*
PREOUT_MUTE*
PREOUT_MUTE*
PREOUT_MUTE_Z2*
+5V(SW) currents:
Zenner = (7-5.1) / 620 = 3mA
P631
+5V(SW)
QTYDESCRIPTIONPART No.NOTESITEM
DG412 = 5 x 5uA max
Resistor Pd @ 3mA= 5.6mW
C611
100N
16V
0603
+7V(A)
R628
620R
0W125
0805
DZ600
BZX84C
5V1
SOT-23
GND
ITEM60014.1m m I/D, 7.3mm O/D O-RingF275Place over C630, halfway down.
DRAWING TITLE
8
SO-16
23
IC600A
DG412DY
1
SO-16
1415
IC600D
DG412DY
16
SO-16
1011
IC600C
DG412DY
9
SO-16
67
IC601B
DG412DY
8
SO-16
23
IC601A
DG412DY
1
SO-16
1415
IC601D
DG412DY
16
SO-16
1011
IC601C
DG412DY
9
SO-16
P633
P634
P635
P636
P637
P638
P639
47R
0603
R632
47R
0603
R633
47R
0603
R634
47R
0603
R635
47R
0603
R636
47R
0603
R637
47R
0603
R638
47R
0603
IC600E
DG412DY
SO-16
V+
VL
GND
V-
R631
P632
Solo Movie Main PCB - Audio Switch & Mute
Filename:
Audio switch and mute.sch
A & R Cambridge Ltd.
Pembroke Avenue
Waterbeach
Cambridge CB25 9QR
06_E194 MJT23/01/071.0Full production. Added adhesive under C833. Changed R816.
01223 203210 (direct)Mark Tweedale
01223 203200 (reception)
TR808
R848
1K0
0603
BD180
TO-126
P856P860
R849
1K0
0603
P857P861
P855P859
TR809
MMUN2211LT1
SOT-23
+5V(STBY)
In Clock Standby or On, uC is active so +3V3(STBY) is
enabled.
In Hard Standby uC is put into 'Software Standby' mode,
where uC clock stops but outputs are fixed at their last
value. +3V3(STBY) is disabled by setting HARD_STBY*
low.
N.B. Default power up state should be with +3V3(STBY)
enabled so there is power to drive the RS232 chip and
switching to program the H8 via cable.
From Audio board to Video board
GND
Discharge Diode if > 1000uF?
REG804
LM1117MPX-5.0/NOPB
+7V(SMPS)
+7V(SMPS)
+7V(SMPS)
P865
P869
ECO No.DESCRIPTION OF CHANGE
L801
600R@100MHz
L803
600R@100MHz
P864
C838
10N
0603
L800
50V
47uH
1.8A
SM
P866
D807
DFLS230LH
PowerDI 123
P868
D808
DFLS230LH
PowerDI 123
P867
C839
10N
0603
L802
50V
15uH
3A
SM
P870
P871
AJD25/06/073.007_E129None to this sheet.
DATE
INITIALS
2-Aug-2007
Printed:
SOT-223
P862
C805
1uF
25V
1206
REG807
LM1117MPX-3.3/NOPB
SOT-223
P863
C804
1uF
25V
1206
REG805
LM1117MPX-5.0/NOPB
SOT-223
C806
1uF
25V
1206
+7V_SMPS_X
R822
13K
0603
C840
1uF
25V
R823
1206
2K7
0603
+3V3_SMPS_X
R825
4K7
0603
C842
10uF
10V
1206
R824
2K7
0603
Place over C818, halfway down.
811Sheetof
+3V3
+5
+5
P877
P879
CON801
JST
PH
C841
220UF
25V
WB
C843
220UF
25V
WB
1
2
3
4
5
6
7
8
3V3 digital for the audio section
A2
+3V3(SMPS)
+5V(VID)
+7V(SMPS)
GND
For CODEC analogue side
+5V(A)
P872
C821
220UF
16V
YXF
GND
For CODEC digital side
+3V3(D)
P873
C820
470UF
25V
YK
GND
For Video board
Locally reg'd to +3V3_VDAC
+5V(D)
P875
C823
470UF
25V
YK
R842
680R
0W125
0805
R843
680R
0W125
0805
DRAWING NO.
For this board
Mostly around CODEC
GND
SP803
P878
Dissipation = 75mW
SP804
P880
Dissipation = 16mW
L998CT
+7V(SMPS)
+3V3(SMPS)
ISSUE
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