Apple iPad Mini 2 (Retina) Schematics
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCH AND BOARD PART NUMBERS
QTY
PART#
D
820-4124
C
B
DESCRIPTION
1
SCH,MLB-C1,X200
1
PCBF,MLB-C1,X200
PDF CSA
TABLE_TABLEOFCONTENTS_HEAD
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13
14
17
18
19
20
21
22
24
26
CONTENTS
TABLE OF CONTENTS
BLOCK DIAGRAM: SYSTEM
BOM TABLES
SOC: MAIN
SOC: I/OS
SOC: NAND
SOC: DP,MIPI
SOC: SRAM, IO PWRS
SOC: VDD, SRAM, CPU, GPU PWRS
SOC: MISC & ALIASES
IO: TRISTAR
NAND STORAGE
TOUCH: SUPPORT CKT & CONN
AUDIO: HP FLEX CONN
AUDIO: L81 CODEC
AUDIO: CS35L19A AMPS
BUTTON: CONN
VIDEO: EDP SUPPORT & CONN
SENSOR: OSCAR
CAMERA: FF-ALS CONN & FILTERS
7
REFERENCE DESIGNATOR(S)
SCH1051-0886
PCB1
BOM OPTION
3456
REV ECN
MLB-C1
X200
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
SYNC MASTER
N/A N/A
J85_MLB_B
J72_MLB_C
N/A
N/A
N/A
MLB
N/A
N/A
N/A
N/A N/A
MLB
N/A
N/A
KAVITHA
KAVITHA
N/A N/A
J85 MLB_C
J72_MLB_C
J85 MLB_C
DATE
04/02/2013
11/26/2012
04/18/2011
05/05/2011
04/18/2011
05/04/2012
04/18/2011
04/18/2011
04/11/2011
05/04/2012
06/21/2010
03/31/2011
01/18/2012
01/18/2012
12/05/2012
11/26/2012
12/03/2012
LAST_MODIFIED=Tue Oct 29 15:52:27 2013
TABLE_TABLEOFCONTENTS_HEAD
21
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22
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23
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24
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25
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26
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28
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29
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30
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32
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33
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34
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37
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TABLE_TABLEOFCONTENTS_ITEM
CSAPDF
CONTENTS
27
SENSOR: ACCEL, COMPASS, GYRO
28
SENSOR: PROX
29
CAMERA: REAR CONN & FILTERS
30
CELL:AP INTERFACE & DEBUG CONNECTORS
32
CELL: BASEBAND PMU (1 0F 2)
33
CELL: BASEBAND PMU (2 OF 2)
34
CELL: BASEBAND (1 OF 2)
35
CELL: BASEBAND (2 OF 2)
36
CELL: RF TRANSCEIVER (1 0F 2)
37
CELL: RF TRANSCEIVER (2 OF 2)
38
CELL: RX MATCHING
39
CELL: RF TRANSCEIVER (3 OF 4)
40
CELL: PENTABAND PA
41
CELL: BAND 2/3 PAD
42
CELL: BAND 7/20 PAD
43
CELL: BAND 5/8 PAD
44
CELL: 2G PA
45
CELL: PA DCDC CONVERTER
46
CELL: ASM AND HB LTE FRONT-END
47
CELL: RX DIVERSITY
48
CELL: GPS
49
CELL: ANTENNA FEEDS
57
IO: FILTERS & HOTBAR CONN
58
WIFI/BT: MODULE
75
POWER: BATTERY CONNECTOR
81
PMU: ANYA PAGE 1
82
PMU: ANYA PAGE 2
83
PMU: ANYA PAGE 3
84
PMU: ANYA PAGE 4
85
POWER: PP1V8_SW
90
SEP: EEPROM & SOC DEBUG
93
TEST: TP/HOLES/FIDUCIALS
94
TEST: EE TP/PP
121
POWER: ALIASES
SYNC MASTER
N/A N/A
J85 MLB_C
N/A N/A
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
N/A
WIFI_DEV
N/A N/A
J72_MLB_C
J85 MLB_C
J72_MLB_C
J72_MLB_C
J85 MLB_C
J72_MLB_C
J85 MLB_C
J72_MLB_C
J72_MLB_C
DATE
12/05/12
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
04/18/2011
05/20/2013
11/26/2012
12/03/2012
11/26/2012
11/26/2012
11/26/2012
11/26/2012
12/03/12
11/26/2012
11/26/2012
A
0002535199
DESCRIPTION OF REVISION
PRODUCTION RELEASED
12
CK
APPD
DATE
2014-01-13
D
C
B
A
DRAWING
8 7 6 5 4 2 1
3
DRAWING TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SCH,MLB-C1,X200
Apple Inc.
R
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
1 OF 121
SHEET
1 OF 54
SIZE
A
D
8 7 6 5 4 3
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12
ISP1_I2C
GRAPE
SPI1
MIPI1C
ISP0_I2C
CUMULUS
CUMULUS
D
MIPI0C
HSIC2
UART1
FRONT CAMERA
REAR CAMERA
D
MIMO
WIFI/BT ANT
WIFI/BT
UART2
I2S3
BT_I2S
CSA 58
WIFI/BT ANT
NOT ON
ALCATRAZ
DISPLAY/
TOUCH PANEL
EDP
C
BACKLIGHT
HSIC1
I2S4
UART3
CELLULAR/
HSIC1
JTAG
USART
USB
CSA 31-46
GPS
WIFI-ONLY CONFIG
PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT
GPS ANT
C
SIM CARD
UART5
BUTTON FLEX
HOME BUTTON
B
PMU
ANYA
CSA 81-84
HALL EFF
1-3
BATTERY
CSA 75
OSCAR
CSA 24
DWI
I2C0
UART4
I2C1
USB2.0
UART0
UART6
I2C0
I2C2
TRISTAR
CSA 13
B
I2S1
COMPASS
CSA 17
SPI BUS
ACCELEROMETER
CSA 27CSA 27CSA 27
GYRO
I2C3
FMI0
FMI1
SPI2
I2S0
I2S2
SPI
ASP
XSP
AMP
CSA 20
MBUS
AMP
CSA 20
RIGHT
SPEAKER
LEFT
SPEAKER
L81
A
PROX SENSOR
ALS
CSA 28
AUDIO
CODEC
NAND FLASH
CSA 14
6 3
HP
MIC1 MIC2
CSA 19
SYNC_MASTER=J85_MLB_B
PAGE TITLE
BLOCK DIAGRAM: SYSTEM
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/02/2013
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
2 OF 121
SHEET
2 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
12
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
SOC
PART#
339S0207
PART NUMBER
DESCRIPTION
QTY
H6P + 1GB ELPIDA
1
ALTERNATE FOR
PART NUMBER
339S0207339S0208
BOM OPTION
REFERENCE DESIGNATOR(S)
U0652
REF DES
COMMENTS:
HYNIX DDR
U0652
CRITICAL BOM OPTION
CRITICAL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
BOM options provided by this page:
D
C
BOM OPTIONS
COMMON
ALTERNATE
16GB_PROD
32GB_PROD
64GB_PROD
128GB_PROD
DEVELOPMENT_JTAG_TAP
JTAG_DAP
MLB (WDOG TO PMU)
WIFI BOM OPTIONS
ANDGATE_TI
FERRITE_TY
FERRITE_TDK
BOM GROUP
BASIC
BOM OPTIONS
COMMON,ALTERNATE
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
PMU
PART#
343S0656
FLASH CONFIGURATIONS
PART#
335S0922 32GB
335S0924
PART NUMBER
335S0931 335S0922
335S0932
DESCRIPTION
QTY
1
IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342
QTY
DESCRIPTION
1
TOS,19NM,PPN1.5,C,DDP,16GB
TOS,19NM,PPN1.5,C,QDP,32GB
1
1
TOS,19NM,PPN1.5,C,ODP,64GB
1
TOS,19NM,PPN1.5,C,12DP,64GB
1
TOS,19NM,PPN1.5,C,16DP,128GB
ALTERNATE FOR
PART NUMBER
335S0921335S0930
335S0923
BOM OPTION
16GB
32GB
64GB
REFERENCE DESIGNATOR(S)
U8100
REFERENCE DESIGNATOR(S)
U1400
U1400
U1400
U1400
U1400
REF DES
COMMENTS:
U1400
HYNIX 20NM PPN1.5 16GB
HYNIX 20NM PPN1.5 32GB
U1400
HYNIX 20NM PPN1.5 64GB
U1400
CRITICAL BOM OPTION
CRITICAL
BOM OPTION
16GB335S0921
64GB335S0923
96GB335S0929
128GB
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
D
C
U2200
TABLE_5_HEAD
TABLE_5_ITEM
WIFI
PART NUMBER
ALTERNATE FOR
PART NUMBER
339S0213339S0223
BOM OPTION
REF DES
U5800
COMMENTS:
QTY
PART#
353S4272
NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES)
TABLE_ALT_HEAD
TABLE_ALT_ITEM
4.3UF CAP
PART NUMBER
DESCRIPTION
IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8
1
ALTERNATE FOR
PART NUMBER
138S0657138S0702
BOM OPTION
REFERENCE DESIGNATOR(S)
U2200
REF DES
COMMENTS:
RDAR #13988471
C1009,C1015,...
BOM OPTION
TABLE_ALT_HEAD
TABLE_ALT_ITEM
MECHANICAL PARTS
PART#
B
806-6207
806-7613
DESCRIPTION
QTY
1
FENCE,TALL,MLB,X221
FENCE,RADIO,MLB,C BRD,X221
1
REFERENCE DESIGNATOR(S)
PD_FENCE_MLB
PD_CAN_RADIO
CRITICAL BOM OPTION
CRITICAL
CRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
B
GYRO
PART#
338S1192
BARCODE LABEL/EEEE CODES
PART#
825-7639
825-7639
825-7639
825-7639
825-7639
825-7639
825-7639
A
825-7639
825-7639
825-7639
DESCRIPTION
QTY
EEEE FOR 639-5393 (X200C1 GOOD)
1
EEEE FOR 639-5394 (X200C1 BETTER)
1
EEEE FOR 639-5385 (X200C1 BEST)
1
EEEE FOR 639-5386 (X200C1 BEST+)
1
EEEE FOR 639-5387 (X200C1 ULTIMATE)
1
EEEE FOR 639-5388 (X200C1 GOOD IVS)
1
EEEE FOR 639-5389 (X200C1 BETTER IVS)
1
EEEE FOR 639-5390 (X200C1 BEST IVS)
1
EEEE FOR 639-5391 (X200C1 BEST+ IVS)
1
EEEE FOR 639-5392 (X200C1 ULTIMATE IVS)
1
REFERENCE DESIGNATOR(S)
FNJD
FNJ5
FNJ9
FNJH
FNJ6
FNJ8
FNJF
FNJC
FNJ7
FNJG
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
EEEE_X200C_GOOD
EEEE_X200C_BETTER
EEEE_X200C_BEST
EEEE_X200C_BEST+
EEEE_X200C_ULTIMATE
EEEE_X200C_GOOD_IVS
EEEE_X200C_BETTER_IVS
EEEE_X200C_BEST_IVS
EEEE_X200C_BEST+_IVS
EEEE_X200C_ULTIMATE_IVS
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
132S0391 CRITICAL
132S0288
ACCEL
PART#
PART NUMBER
DESCRIPTION
QTY
1
GYRO, ST MICRO
1
GYRO, INVENSENSE
CAP 0.01UF 25V 0201
1
CAP 0.1UF 16V 0201
1
DESCRIPTION
QTY
1
IC,ACCEL,3-AXIS,DIG,BMA282,LGA14
ALTERNATE FOR
PART NUMBER
338S1233 ST MICRO - DISQUAL’ED
338S1114 OLD ACCEL - ST MICRO
338S1191 OLD ACCEL - ST MICRO
BOM OPTION
REFERENCE DESIGNATOR(S)
U2720
U2720
C2726
C2726
REFERENCE DESIGNATOR(S)
U2700
REF DES
COMMENTS:
CRITICAL BOM OPTION
CRITICAL
CRITICAL338S1218
CRITICAL
CRITICAL BOM OPTION
CRITICAL338S1163
TABLE_ALT_HEAD
GYRO_STMICRO
GYRO_INVENSENSE
GYRO_STMICRO
GYRO_INVENSENSE
6 3
TABLE_5_HEAD
TABLE_5_ITEM
338S1158 OLD GYRO - ST MICRO
TABLE_5_ITEM
OLDER INVENSENSE P/N 338S1135
OLD INVENSENSE P/N 338S1200 (3/22/13)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
SYNC_MASTER=J72_MLB_C
PAGE TITLE
BOM TABLES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=11/26/2012
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
4 OF 121
SHEET
3 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
WWW.AliSaler.Com
H6P: JTAG, USB, PLL, HSIC, XTAL
12
D
NOTE: CANDIDATE FOR COST-SAVINGS
(REPLACE WITH XW LATER?)
=PP1V8_PLL_SOC
54
R0622
1 2
0.00
=PP1V2_HSIC_SOC
54
C0690
0.22UF
20%
6.3V
X5R
0201
01005
1
2
1
C0651
0.1UF
20%
6.3V
2
X5R-CERM
C0691
0.22UF
6.3V
0201
20%
X5R
C
=PP1V8_SOC
4 5 7
10 18 54
JTAG_SOC_TDI
4
52
JTAG_SOC_TMS
4
11 52
JTAG_SOC_TCK
4
11 52
B
1
R0647
100K
1%
1/32W
MF
01005
2
1
R0646
100K
1%
1/32W
MF
01005
2
10 11 24 48 52
10 18 54
8
1
2
4 5 7
IN
R0645
100K
1%
1/32W
MF
01005
=PP1V8_SOC
RESET_SOC_L
1
R0617
100K
1%
1/32W
MF
01005
2
1
C0618
1000PF
10%
6.3V
2
X5R-CERM
01005
HSIC2_BB_DATA
24 27 53
BI
HSIC2_BB_STB
24 27 53
BI
HSIC1_WLAN_DATA
44 53
BI
HSIC1_WLAN_STB
44 53
BI
1.8V TOLERANT
10 52
10 52
4
52
4
11 52
4
11 52
10
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
JTAG_SOC_SEL
IN
JTAG_SOC_TRST_L
IN
JTAG_SOC_TDI
IN
JTAG_SOC_TMS
IN
JTAG_SOC_TCK
IN
SOC_HOLD_RESET
IN
NC_HSIC0_DATA
NC_HSIC0_STB
HSIC1_BB_DATA
HSIC1_BB_STB
HSIC2_WLAN_DATA
HSIC2_WLAN_STB
NC_JTAG_SOC_TRTCK
TP_JTAG_SOC_TDO
52
1
2
PP1V8_PLL_SOC_F
52
1
C0648
0.01UF
10%
6.3V
2
X5R
0100501005
A26
HSIC0_DATA
B26
HSIC0_STB
A27
HSIC1_DATA
B27
HSIC1_STB
AM33
HSIC2_DATA
AM34
HSIC2_STB
D28
JTAG_SEL
D27
JTAG_TRTCK
E28
JTAG_TRST*
E27
JTAG_TDO
F27
JTAG_TDI
F28
JTAG_TMS
C28
JTAG_TCK
F29
RESET*
E29
CFSB
D29
HOLD_RESET
H16
FUSE1_FSRC
1
C0608
2
G22
G23
AM31
(3X 13MA)
HSIC_VDD120
HSIC_VDD122
HSIC_VDD121
0.01UF
10%
6.3V
X5R
01005
HSIC_VDD120
HSIC_VDD121
HSIC_VDD122
VDDIO18_GRP3
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 1 OF 13
VDDIO18_GRP1
F24
U16
AE20
(1MA)
(6X 1MA)
VDD_ANA_PLL
VDD_ANA_PLL_CCC
VDDIO18_GRP4
ANALOGMUXOUT
USB_ANALOGTEST
TST_CLKOUT
FAST_SCAN_CLK
(25MA)
F23
(25MA)
USB_DVDD
USB_VDD330
(5.4MA)
USB_DP
USB_DM
USB_VBUS
USB_ID
USB_REXT
WDOG
TESTMODE
XI0
XO0
F25
E25
E26
B29
A29
D26
D23
E24
E23
AD4
AC3
AD3
AB3
NC_USB_ANALOGTEST
=PP1V0_USB_SOC
1
C0627
0.01UF
10%
6.3V
2
X5R
01005
=PP3V3_USB_SOC
1
C0630
0.1UF
20%
6.3V
2
X5R-CERM
01005
XTAL_SOC_24M_I
XTAL_SOC_24M_O
NC_ANALOGMUXOUT
USB_VBUS_DETECT_R
NC_USB_ID
WDOG_SOC
SOC_TEST_CLKOUT
SOC_FAST_SCAN_CLK
SOC_TESTMODE
54
54
TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD
1
R0655
OUT
IN
IN
USB_SOC_P
USB_SOC_N
10
TP0600
TP
TP-P55
10
10 52
1.00M
1%
1/32W
MF
01005
11 52
BI
11 52
BI
R0651
68.1K
1%
1/32W
MF
01005
24.000MHZ-30PPM-9.5PF-60OHM
USB_REXT
R0640
1.33K
1 2
1%
1/32W
USB_VBUS_DETECT
1
2
2
R0642
200
1%
1/32W
MF
01005
01005
Y0602
1.60X1.20MM-SM
SOC_24M_O
MF
USBHS ON/OFF TOLERANCE 5V/1.98V
46
IN
NOTE: NEW USB_REXT
VALUE FOR H6 = 200 OHM
OLD (H5) VALUE: 44.2 OHM
42
1 3
C0607
12PF
1 2
5%
16V
CERM
01005
C0613
12PF
1 2
5%
16V
CERM
01005
D
C
B
A
HSIC_VSS120
HSIC_VSS121
HSIC_VSS122
H20
H21
AM32
USB_VSSA0
H23
6 3
SYNC_MASTER=N/A
PAGE TITLE
SOC: MAIN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/18/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
6 OF 121
SHEET
4 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
SOC I/OS
12
R0720
33.2
1%
1/32W
MF
01005
I2S0_CODEC_ASP_MCK
15 53
OUT
D
I2S1_SPKAMP_MCK
16 53
OUT
1 2
R0721
33.2
1%
1/32W
MF
01005
1 2
I2S0_CODEC_ASP_MCK_R
I2S0_CODEC_ASP_BCLK
15
OUT
I2S0_CODEC_ASP_LRCK
15
OUT
I2S0_CODEC_ASP_DIN
15
IN
I2S0_CODEC_ASP_DOUT
15
OUT
I2S1_SPKAMP_MCK_R
I2S1_SPKAMP_BCLK
16 53
OUT
I2S1_SPKAMP_LRCK
16 53
OUT
I2S1_SPKAMP_DIN
16 53
IN
I2S1_SPKAMP_DOUT
16 53
OUT
NC_GPIO_GYRO_IRQ1
I2S2_CODEC_XSP_BCLK
15
OUT
I2S2_CODEC_XSP_LRCK
15 53
OUT
I2S2_CODEC_XSP_DIN
15
IN
I2S2_CODEC_XSP_DOUT
15 53
OUT
GPIO_SPKAMP_RIGHT_IRQ_L
16
IN
I2S3_SOC2BT_BCLK
10
OUT
I2S3_SOC2BT_LRCK
10
OUT
I2S3_BT2SOC_DATA
10
IN
I2S3_SOC2BT_DATA
10
OUT
BB_JTAG_TCK
24 27 52
OUT
BB_JTAG_TMS
24 27 52
OUT
BB_JTAG_TDI
24 27 52
OUT
BB_JTAG_TDO
24 27 52
IN
BB_JTAG_TRST_L
24 27 52
OUT
AL32
AL31
AJ31
AK31
AL33
AL34
AK33
AJ32
AK34
AJ33
AJ34
AH31
AH34
AG31
AG32
AH33
AF31
AG34
AE31
AF33
AE32
AD31
AE33
C30
E30
I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT
I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT
I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT
I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT
I2S4_MCK
I2S4_BCLK
I2S4_LRCK
I2S4_DIN
I2S4_DOUT
C
AV10
AN12
AT10
AP11
AN6
AP5
AT5
AV5
AU5
AV4
AU4
AR5
AU6
AR6
AP7
AN8
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
10
IN
10
IN
10
IN
13 52
IN
13 52
OUT
13
OUT
13 52
OUT
15 53
IN
15 53
OUT
15 53
OUT
15
OUT
GPIO_BOARD_ID2
GPIO_BOARD_ID1
GPIO_BOARD_ID0
NC_SPI0_SSIN
SPI1_GRAPE_MISO
SPI1_GRAPE_MOSI
SPI1_GRAPE_SCLK
SPI1_GRAPE_CS_L
SPI2_CODEC_MISO
SPI2_CODEC_MOSI
SPI2_CODEC_SCLK
SPI2_CODEC_CS_L
NC_SPI1_NAVAJO_MISO
NC_SPI1_NAVAJO_MOSI
NC_SPI1_NAVAJO_SCLK
NC_GPIO_NAVAJO2SOC_INT
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 3 OF 13
CRITICAL
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
SEP_7816UART0_RST
SEP_7816UART0_SCL
SEP_7816UART0_SDA
VDDIO18_GRP1
SEP_7816UART1_RST
SEP_7816UART1_SCL
SEP_7816UART1_SDA
SIO_7816UART0_RST
SIO_7816UART0_SCL
SIO_7816UART0_SDA
SIO_7816UART1_RST
SIO_7816UART1_SCL
VDDIO18_GRP2
SIO_7816UART1_SDA
DISP_VSYNC
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
I2C3_SCL
I2C3_SDA
DWI_CLK
DWI_DI
DWI_DO
SOCHOT0
SOCHOT1
AV6
AR7
AP8
AU7
AT11
AR11
W30
W32
AP19
AT18
AT19
AR1
AP3
AP2
AR4
AR2
AP4
AB33
AA31
AB31
AA33
AA32
AA34
AP18
AP17
AN17
I2C0_SCL_1V8
I2C0_SDA_1V8
I2C1_SOC2OSCAR_SWDCLK_1V8
I2C1_SOC2OSCAR_SWDIO_1V8
I2C2_SCL_1V8
I2C2_SDA_1V8
I2C3_SCL_1V8
I2C3_SDA_1V8
TP_SOC_TST_CPUSWITCH_OUT
NC_SEP_7816UART0_RST
SEP_I2C0_SCL
SEP_I2C0_SDA
NC_SEP_7816UART1_RST
NC_SEP_7816UART1_SCL
NC_SEP_7816UART1_SDA
HSIC1_WLAN2SOC_REMOTE_WAKE
HSIC1_WLAN2SOC_DEVICE_RDY
HSIC1_SOC2WLAN_HOST_RDY
HSIC2_BB2SOC_REMOTE_WAKE
HSIC2_BB2SOC_DEVICE_RDY
HSIC2_SOC2BB_HOST_RDY
DISPLAY_SYNC
DWI_AP_CLK
DWI_AP_DO
SOCHOT0_L
SOCHOT1_L
24 28
5
OUT
BI
OUT
BI
OUT
BI
IN
OUT
OUT
BI
5
28
24 28
49 52
OUT
OUT
44 53
44 53
5
5
5
48 52
48 53
5
44 53
5
13
11 48 52
5
11 48 52
16 52
5
16 52
20 22
5
20 22
51
5
51
48
TRISTAR
PMU
5
OUT
5
BI
SPK AMPS
ALS
PROX
19
19
GPIO_BTN_HOME_L
5
13 48
IN
GPIO_BTN_ONOFF_L
5
17 48
IN
GPIO_BTN_VOL_UP_L
17
IN
GPIO_BTN_VOL_DOWN_L
17
IN
GPIO_BTN_SRL_L
5
17 48
IN
GPIO_SOC2BEACON_EN
OUT
GPIO_SOC2AJ_HS4_SHUNT_EN
GPIO_SOC2AJ_HS3_SHUNT_EN
14
OUT
GPIO_BOARD_REV0
10
IN
GPIO_BOARD_REV1
10
IN
GPIO_BOARD_REV2
10
IN
GPIO_CODEC_IRQ_L
15 52
IN
GPIO_SOC2BB_WAKE_MODEM
28 52
OUT
GPIO_GRAPE_IRQ_L
13 52
IN
BB_IPC_GPIO
28
IN
GPIO_ALS_IRQ_L
20
IN
GPIO_BOARD_ID3
10
IN
GPIO_BB2SOC_RESET_DET_L
24 28
IN
GPIO_BOOT_CONFIG0
10
IN
GPIO_PMU2SOC_IRQ_L
48
IN
GPIO_SOC2PMU_KEEPACT
5
48
OUT
GPIO_GRAPE_RST_L
13 52
OUT
GPIO_BB2SOC_GPS_SYNC
28
IN
GPIO_SOC2BB_RADIO_ON_L
24 26 52
IN
NC_GPIO_BB_HSIC_DEV_RDY
GPIO_BOOT_CONFIG1
10
IN
GPIO_FORCE_DFU
5
52
IN
TP_GPIO_DFU_STATUS
GPIO_BOOT_CONFIG2
10
IN
GPIO_BOOT_CONFIG3
10
IN
GPIO_SOC2OSCAR_DBGEN
19
OUT
GPIO_SOC2BB_RST_L
24 26 52
OUT
GPIO_PROX_IRQ_L
22
IN
GPIO_BB2SOC_GSM_TXBURST
28
IN
GPIO_SPKAMP_RST_L
5
16
OUT
GPIO_BT_WAKE
44 53
OUT
GPIO_TS2SOC2PMU_INT
11 48
IN
GPIO_SPKAMP_LEFT_IRQ_L
16
IN
GPIO_SOC2LCD_PWREN
18
OUT
AC5
AB1
AB2
AD1
AD5
AE4
AF1
AE2
AE5
AF3
AF4
AF2
AG1
AG3
AG4
AH3
AH2
AH4
AG5
AJ5
AJ4
AK2
AP13
AP12
AR13
AN14
AT12
AT13
AV13
AP14
AU13
AP15
AR14
AT14
AT15
AP16
AR16
AT16
AT17
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
POP-1GB-DDR
SYM 2 OF 13
CRITICAL
VDDIO18_GRP1
OMIT
U0652
H6P
FCMSP
TMR32_PWM0
TMR32_PWM1
TMR32_PWM2
UART0_RXD
UART0_TXD
UART1_CTSN
UART1_RTSN
UART1_RXD
UART1_TXD
UART2_CTSN
UART2_RTSN
UART2_RXD
UART2_TXD
VDDIO18_GRP1
UART3_CTSN
UART3_RTSN
UART3_RXD
UART3_TXD
UART4_CTSN
UART4_RTSN
UART4_RXD
UART4_TXD
UART5_RTXD
UART6_RXD
UART6_TXD
VDDIO18_GRP2 VDDIO18_GRP2
AC31
AD34
AC32
AR19
AR18
AL2
AL4
AK4
AK3
AL5
AM3
AM2
AM1
AN3
AN4
AP1
AN1
AV3
AU3
AT3
AT2
AM5
W31
Y31
OSCAR_TIME_SYNC_HOST_INT
GPIO_SPKAMP_KEEPALIVE
CLK_32K_SOC2CUMULUS
UART0_SOC_RXD
UART0_SOC_TXD
UART1_BT2SOC_RTS_L
UART1_SOC2BT_RTS_L
UART1_BT2SOC_TX
UART1_SOC2BT_TX
NC_UART2_CTS
NC_UART2_RTS
UART2_WLAN2SOC_TX
UART2_SOC2WLAN_TX
UART3_BB2SOC_RTS_L
UART3_SOC2BB_RTS_L
UART3_BB2SOC_TX
UART3_SOC2BB_TX
PMU_GPIO_OSCAR2PMU_HOST_WAKE
GPIO_OSCAR_RESET_L
UART4_OSCAR2SOC_RXD
UART4_SOC2OSCAR_TXD
UART5_BATT_RTXD
UART6_TS_ACC_RXD
UART6_TS_ACC_TXD
IN
OUTOUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
BI
IN
OUT
19
5
16 52 14
13 52
11 52
11 52
44
44
44 53
44 53
44 53
44 53
24 28
24 28
11 24 28 52
11 24 28 52
19 48
19
19 53
19 53
45 48
11 52
11 52
D
C
=PP1V8_S2R_MISC
5
B
A
51 54
=PP1V8_ALWAYS
54
=PP1V8_S2R_MISC
5
51 54
=PP1V8_SOC
4 5 7
10 18 54
=PP1V8_S2R_MISC
5
51 54
R0771
220K
1 2
5%
1/32W
MF
01005
R0770
220K
1 2
5%
1/32W
MF
01005
R0765
220K
1 2
5%
1/32W
MF
01005
R0754
100K
1 2
5%
1/32W
MF
01005
R0755
100K
1 2
5%
1/32W
MF
01005
GPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
GPIO_BTN_SRL_L
(SCREEN ROTATION LOCK)
SOCHOT0_L
SOCHOT1_L
=PP1V8_SOC
4 5 7
5
13 48
5
17 48
5
17 48
5
49 52
5
48
6 3
10 18 54
I2C0_SDA_1V8
5
11 48 52
I2C0_SCL_1V8
5
11 48 52
I2C2_SDA_1V8
5
16 52
I2C2_SCL_1V8
5
16 52
I2C3_SDA_1V8
5
20 22
I2C3_SCL_1V8
5
20 22
SEP_I2C0_SDA
5
51
SEP_I2C0_SCL
5
51
I2C1_SOC2OSCAR_SWDIO_1V8
5
19
I2C1_SOC2OSCAR_SWDCLK_1V8
5
19
1
1
R0700
2.2K
5%
1/32W
MF
01005MF01005
2
2
R0701
2.2K
5%
1/32W
1
R0702
1.8K
5%
1/32W
MF
01005
2
1
R0703
1.8K
5%
1/32W
MF
01005
2
1
2.2K
5%
1/32W
MF
01005
2
1
R0705R0704
2.2K
5%
1/32W
MF
01005
2
1
R0750
2.2K
5%
1/32W
MF
01005
2
1
R0751
2.2K
5%
1/32W
MF
01005
2
NOSTUFF
1
R0752
2.2K
5%
1/32W
MF
01005
2
NOSTUFF
1
R0753
2.2K
5%
1/32W
MF
01005
2
1
R0739
100K
1%
1/32W
MF
01005
2
1
100K
1%
1/32W
MF
01005
2
GPIO_SPKAMP_RST_L
GPIO_SOC2PMU_KEEPACT
HSIC1_SOC2WLAN_HOST_RDY
GPIO_FORCE_DFU
GPIO_SPKAMP_KEEPALIVE
1
R0736R0735
100K
1%
1/32W
MF
01005
2
1
R0737
100K
1%
1/32W
MF
01005
2
SYNC_MASTER=N/A
PAGE TITLE
1
R0738
100K
1%
1/32W
MF
01005
2
SOC: I/OS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
16
5
48
5
44 53
5
52
5
16 52
SYNC_DATE=05/05/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
7 OF 121
SHEET
5 OF 54
124578
SIZE
B
A
D
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
OUT
OUT
OUT
OUT
PPN0_ALE
PPN0_CEN0
PPN0_CEN1
PPN0_CLE
PPN0_DQS
PPN0_IO0
PPN0_IO1
PPN0_IO2
PPN0_IO3
PPN0_IO4
PPN0_IO5
PPN0_IO6
PPN0_IO7
PPN0_REN
PPN0_VREF
PPN0_WEN
PPN0_ZQ
PPN1_ALE
PPN1_CEN0
PPN1_CEN1
PPN1_CLE
PPN1_IO0
PPN1_IO1
PPN1_IO2
PPN1_IO3
PPN1_IO4
PPN1_IO5
PPN1_IO6
PPN1_REN
PPN1_VREF
PPN1_WEN
PPN1_ZQ
PPN1_DQS
PPN1_IO7
SYM 4 OF 13
VSS
VSS
SYM 11 OF 13
VSS
VSS
SYM 12 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
VDDIO18_GRP3
12 52
12
12
12
12
12
12
12
12 53
12
12
12
12
100K
1/32W
1%
MF
01005
R0831
MF
R0832
100K
1%
1/32W
01005
12 52
12
12
12
12
12
12
12
12
12 53 12
12
12
12
12
10%
0.01UF
X5R
01005
6.3V
C0860
C0861
10%
0.01UF
X5R
01005
6.3V
R0860
50K
MF
1/32W
01005
1%
R0861
50K
MF
1/32W
1%
01005
U0652
POP-1GB-DDR
H6P
FCMSP
OMIT
CRITICAL
01005
R0870
1%
240
1/32W
MF
01005
R0871
1%
240
MF
1/32W
FCMSP
POP-1GB-DDR
H6P
U0652
OMIT
CRITICAL
FCMSP
POP-1GB-DDR
H6P
U0652
OMIT
CRITICAL
SYNC_DATE=04/18/2011
SYNC_MASTER=N/A
SOC: NAND
NC_PPN1_CEN1NC_PPN0_CEN1
FMI1_CE0_L
PPVREF_FMI_SOC
FMI0_AD<4>
FMI0_AD<0>
FMI0_CE0_L
FMI0_WE_L
FMI0_AD<7>
FMI0_AD<6>
FMI0_AD<5>
FMI0_AD<2>
FMI0_AD<1>
FMI0_DQS
FMI0_ALE
FMI1_AD<1>
FMI1_AD<0>
FMI1_AD<2>
FMI1_AD<4>
FMI1_AD<3>
FMI1_AD<7>
FMI1_AD<6>
FMI1_AD<5>
FMI1_CLE
FMI1_ALE
FMI1_DQS
=PP1V8_NAND_SOC
FMI0_ZQ FMI1_ZQ
FMI1_WE_L
FMI1_RE_LFMI0_RE_L
FMI0_CLE
FMI0_AD<3>
=PP1V8_NAND_SOC
051-0886
A.0.0
8 OF 121
6 OF 54
1
2
1
2
2
1
2
1
1
2
1
2
A31
G32
H31
B31
D34
B32
C32
C33
C34
F32
F33
F34
G34
D33
D31
A32
E33
N34
R32
P32
P31
M34
M33
L32
M32
K32
J32
H33
L31
N31
N32
K33
L34
H34
1 2 1 2
A11
A1
AA3
AF29
AJ30
A3
A4
A5
A7
A9
A13
A14
A16
A18
A25
A28
A30
A33
A34
AA1
AA2
AA4
AA8
AA10
AA12
AA14
AA16
AA18
AA22
AA24
AA26
AA28
AA30
AB5
AB7
AB9
AB11
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AB29
AB32
AC4
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AC30
AC34
AD2
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD25
AD29
AD32
AE3
AE8
AE10
AE12
AE16
AE18
AE22
AE24
AE26
AE28
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF32
AG2
AG8
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AG30
AH5
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AH29
AH32
AJ1
AJ3
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ22
AJ24
AJ26
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK32
AL3
AL6
AL8
AL10
AL12
AL14
AL16
AL18
AL20
AL22
AL24
AL26
AL28
AL30
AM4
AM7
AM18
AM30
AN2
AN5
AN7
AB6
AM9
AM11
AM13
AN16
AM15
AN19
AN20
AN21
AN22
AN23
AN24
AJ28
A2
AB13
AE14
AN31
AP25
AP26
E10
E11
E12
G28
G26
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G1
F31
F30
F26
F15
F14
F13
F12
F10
F9
F8
F7
F6
F5
F4
F3
F2
E34
E32
E31
E22
E21
E20
E19
E18
E15
E14
E13
E8
E7
E5
E4
E3
E1
D22
D21
D20
D19
D18
D17
D15
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
C31
C29
C27
C26
C23
C22
C19
C18
C17
C16
C15
C13
C11
C10
C9
C7
C6
C5
C3
C2
C1
B34
B33
B30
B28
B25
B19
B18
B17
B16
B15
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B2
B1
AV34
AV33
AV20
AV18
AV16
AV14
AV11
AV9
AV2
AV1
AU34
AU33
AU21
AU18
AU16
AU11
AU2
AU1
AT32
AT31
AT30
AT29
AT28
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
AT6
AT4
AT1
AR32
AR20
AR17
AR15
AR12
AR8
AR3
AP28
AP27
AP24
AN33
AN32
AR29
AR28
AR25
AR24
AR22
AR21
E9
C12
AP21
AP20
AP6
AN34
AP32
AR23
E6
C24
AP30
AP31
D32
D16
AP29
6
54
6
54
WWW.AliSaler.Com
OUT
OUT
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
IN
IN
IN
IN
DP_PAD_AUXN
DP_PAD_AUXP
DP_PAD_AVDD_AUX
DP_PAD_AVDD0
DP_PAD_AVDD1
DP_PAD_AVDD2
DP_PAD_AVDD3
DP_PAD_AVDDP0
DP_PAD_AVDDX
DP_PAD_AVSS_AUX
DP_PAD_AVSS0
DP_PAD_AVSS1
DP_PAD_AVSS2
DP_PAD_AVSS3
DP_PAD_AVSSP0
DP_PAD_AVSSX
DP_PAD_DC_TP
DP_PAD_DVDD
DP_PAD_DVSS
DP_PAD_R_BIAS
DP_PAD_TX0N
DP_PAD_TX0P
DP_PAD_TX1N
DP_PAD_TX1P
DP_PAD_TX2N
DP_PAD_TX2P
DP_PAD_TX3N
DP_PAD_TX3P
EDP_HPD
SYM 6 OF 13
MIPI0C_DPDATA0
SENSOR1_RST
SENSOR1_CLK
MIPI1C_DPDATA0
SENSOR0_RST
SENSOR0_ISTRB
SENSOR0_CLK
MIPI1D_VREG_0P4V
MIPI1D_VDD18
MIPI1C_DPDATA1
MIPI1C_DPCLK
MIPI1C_DNDATA1
MIPI1C_DNDATA0
MIPI1C_DNCLK
MIPI0D_VREG_0P4V
MIPI0D_VDD18
MIPI0D_DPCLK
MIPI0D_DNCLK
MIPI0C_DPDATA2
MIPI0C_DPDATA1
MIPI0C_DNDATA2
MIPI0C_DNDATA1
MIPI_VSS
ISP0_SDA
ISP0_SCL
ISP1_SCL
MIPI0C_DPDATA3
MIPI0C_DNDATA3
MIPI0C_DPCLK
MIPI0D_DNDATA3
MIPI0D_DPDATA3
MIPI0D_DNDATA2
MIPI0D_DPDATA2
MIPI0D_DNDATA1
MIPI0D_DPDATA1
MIPI0C_DNCLK
MIPI0D_DPDATA0
MIPI0D_DNDATA0
MIPI_VDD10
SENSOR1_ISTRB
MIPI0C_DNDATA0
ISP1_SDA
SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN
SYM 5 OF 13
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(2MA)
(2MA)
(55MA)
VDDIO18_GRP1
VDDIO18_GRP1
MIPI_VDD10
(50MA)
(50MA)
(1MA)
(50MA)
(14MA)
(50MA)
VDDIO18_GRP3
(14MA)
(10MA)
DISPLAYPORT
20 52
20 52
20 52
20 52
20 53
20 53
R0940
49.9
01005
01005
5%
2.2K
1/32W
MF
R0932
1/32W
R0933
01005
5%
2.2K
MF
20 53
20 53
R0941
01005
100
23 52
23 52
01005
5%
2.2K
1/32W
MF
R0931
01005
2.2K
5%
1/32W
MF
R0930
23 52
23 52
23 53
23 53
23 53
23 53
23 53
23 53
CRITICAL
OMIT
U0652
FCMSP
POP-1GB-DDR
H6P
C0962
20%
0.1UF
X5R-CERM
6.3V
01005
20%
0204
1UF
4V
X6S
C0930
CRITICAL
OMIT
U0652
POP-1GB-DDR
H6P
FCMSP
C0957
1.0UF
0201-1
6.3V
X5R
20%
18 53
18 53
18 53
18 53
18 53
18 53
18
18
18
18 53
18 53
R0900
01005
MF
1/32W
4.99K
1%
NOSTUFF
01005
6.3V
X5R
0.01UF
10%
C0950
C0958
01005
16V
NP0-C0G-CERM
8.2PF
+/-0.5PF
1/32W
0%
0.00
MF
R0901
01005
C0951
16V
01005
5%
56PF
NP0-C0G
C0952
01005
16V
NP0-C0G-CERM
8.2PF
+/-0.5PF
01005
NP0-C0G
C0953
56PF
5%
16V
0201
20%
X5R
6.3V
C0954
0.22UF
C0955
0201-1
6.3V
X5R
1.0UF
20%
C0956
0201-1
6.3V
X5R
1.0UF
20%
SOC: DP,MIPI
SYNC_MASTER=MLB
SYNC_DATE=05/04/2012
=PP1V8_MIPI_SOC
NC_MIPI1D_VREG
NC_MIPI0D_VREG
NC_SENSOR1_XSHUTDOWN
NC_SENSOR1_ISTRB
NC_SENSOR0_ISTRB
NC_SENSOR0_XSHUTDOWN
NC_MIPI0C_CAM_REAR_DATA_P2
NC_MIPI0C_CAM_REAR_DATA_N2
MIPI0C_CAM_REAR_DATA_P<0>
EDP_DATA_P<1>
PP1V8_EDP_AVDD_AUX
=PP1V8_SOC
ISP0_CAM_REAR_SCL
ISP0_CAM_REAR_SDA
ISP0_CAM_REAR_CLK
ISP1_CAM_FRONT_CLK_R
MIPI1C_CAM_FRONT_DATA_P<0>
ISP0_CAM_REAR_CLK_R
NC_MIPI1C_CAM_FRONT_DATA_P1
MIPI1C_CAM_FRONT_CLK_P
NC_MIPI1C_CAM_FRONT_DATA_N1
MIPI1C_CAM_FRONT_DATA_N<0>
MIPI1C_CAM_FRONT_CLK_N
NC_MIPI0D_DPCLK
NC_MIPI0D_DNCLK
MIPI0C_CAM_REAR_DATA_P<1>
MIPI0C_CAM_REAR_DATA_N<1>
NC_MIPI0C_CAM_REAR_DATA_P3
NC_MIPI0C_CAM_REAR_DATA_N3
MIPI0C_CAM_REAR_CLK_P
NC_MIPI0D_DNDATA3
NC_MIPI0D_DPDATA3
NC_MIPI0D_DNDATA2
NC_MIPI0D_DPDATA2
NC_MIPI0D_DNDATA1
NC_MIPI0D_DPDATA1
MIPI0C_CAM_REAR_CLK_N
NC_MIPI0D_DPDATA0
NC_MIPI0D_DNDATA0
MIPI0C_CAM_REAR_DATA_N<0>
=PP1V0_MIPI_SOC
=PP1V8_EDP_SOC
SOC_EDP_R_BIAS
EDP_AUX_N
EDP_AUX_P
TP_EDP_PAD_DC_TP
EDP_DATA_N<0>
EDP_DATA_P<0>
EDP_DATA_N<1>
EDP_DATA_N<2>
EDP_DATA_P<2>
EDP_DATA_N<3>
EDP_DATA_P<3>
EDP_HPD
ISP1_CAM_FRONT_SDA
ISP1_CAM_FRONT_SCL
ISP0_CAM_REAR_SHUTDOWN_L
ISP1_CAM_FRONT_CLK
ISP1_CAM_FRONT_SHUTDOWN_L
=PP1V0_EDP_PAD_DVDD_SOC
051-0886
A.0.0
9 OF 121
7 OF 54
1 2
1
2
1
2
1 2
1
2
1
2
B20
A20
F18
F19
F20
F21
F22
G18
F17
G17
H19
G19
G20
G21
H18
H17
E16
F16
G16
E17
B21
A21
B22
A22
B23
A23
B24
A24
D30
2
1
2
1
AU27
AT9
AU9
AT33
AN28
AT8
AN10
AV8
AR30
AR31
AP33
AR33
AP34
AT34
AR34
AR27
AR26
AU30
AV30
AU24
AU26
AV24
AV26
AM28
AM27
AM26
AM25 AN29
AV7
AT7
AU8
AU23
AV23
AU25
AV28
AU28
AV29
AU29
AV31
AU31
AV25
AU32
AV32
AN25
AN26
AN27
AM29
AL25
AR10
AV27
AP9
AR9
AP10
2
1
1
2
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
2
1
54
4 5
10 18 54
54
54
54
DDR1_VREF_CA
DDR0_VREF_CA
DDR1_RREF_DQ
VSS
DDR0_CKEIN
DDR0_VDD_CKE
DDR1_RREF_CA
DDR0_RREF_CA
DDR0_RREF_DQ
DDR0_VREF_DQ
DDR1_VREF_DQ
VDDCA
VDD2
VDD1
VDDQ
DDR1_VDD_CKE
DDR1_CKEIN
SYM 7 OF 13
VDDIOD_DDR1CA
VDDIOD_DDR0CA
VDDIO18_GRP4
VSS
VDDIO18_GRP2
VDDIO18_GRP1
VDDIOD_DDRDQ
VDDIO18_GRP3
SYM 9 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(DDR IMPEDANCE CONTROL)
ON 5/6/12, BY MANU G
NOTE: CKEIN CONFIRMED 1.8V TOLERANT
CAPS FOR VDDIOD ARE SHARED WITH VDDQ
(45MA)
(500MA)
SHARED WITH VDDIOD)
(CURRENT CONSUMPTION
(CURRENT CONSUMPTION
SHARED WITH VDDIOD)
(<1MA)
(<1MA)
(1000MA)
(20MA)
(31MA)
(2MA)
(65MA)
(GPIO,UART,SPI,I2C)
(SENSOR,SOCHOT,PMU)
CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX
NOSTUFF
0.01UF
10%
6.3V
C1056
X5R
01005
R1056
01005
1.00K
MF
1%
1/32W
R1055
01005
1/32W
MF
1%
1.00K
X5R
6.3V
01005
NOSTUFF
C1054
0.01UF
10%
R1053
01005
MF
1%
1.00K
1/32W
R1054
01005
1%
1/32W
1.00K
MF
0204
1UF
20%
4V
X6S
C1007
1UF
0204
20%
4V
X6S
C1006
R1031
MF
01005
240
1%
1/32W
01005
MF
R1001
240
1/32W
1%
01005
0.1UF
C1000
20%
6.3V
X5R-CERM
C1009
0610
4V
4.3UF
X5R-CERM
20%
20%
4V
X7S
0204
0.47UF
C1004
20%
4V
X5R-CERM
0610
4.3UF
C1015
0610
4V
20%
X5R-CERM
4.3UF
C1027
OMIT
CRITICAL
U0652
H6P
POP-1GB-DDR
FCMSP
4V
0204
20%
X6S
1UF
C1029
4V
0204
X7S
20%
0.47UF
C1026
X6S
1UF
4V
0204
20%
C1028
20%
0.47UF
X7S
0204
4V
C1031
X6S
0204
1UF
20%
4V
C1071
20%
4V
X7S
0.47UF
0204
C1073
402
4.7UF
X5R
6.3V
20%
C1070
X6S
4V
20%
1UF
0204
C1072
H6P
POP-1GB-DDR
FCMSP
OMIT
CRITICAL
U0652
0201
FL1000
1KOHM-25%-0.2A
X5R-CERM
10V
20%
1.0UF
0201-1
C1042
01005
MF
R1000
240
1/32W
1%
R1030
MF
01005
240
1%
1/32W
NOSTUFF
X5R
10%
01005
0.01UF
6.3V
C1002
R1005
01005
1/32W
MF
2.21K
1%
R1006
01005
MF
2.21K
1%
1/32W
NOSTUFF
6.3V
C1052
0.01UF
X5R
10%
01005
01005
MF
2.21K
1%
1/32W
R1051
R1052
01005
MF
1/32W
1%
2.21K
SOC: SRAM, IO PWRS
SYNC_MASTER=N/A
SYNC_DATE=04/18/2011
DDR0_CA_ZQ
DDR0_DQ_ZQ
DDR1_CA_ZQ
=PP1V2_S2R_DDR_SOC
PPVREF_DDR1_DQ
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
PPVREF_DDR1_CA
VOLTAGE=0.6V
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM
PPVREF_DDR0_DQ
MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
PPVREF_DDR0_CA
=PP1V2_VDDQ_DDR
=PP1V2_S2R_DDR
=PP1V2_VDDQ_DDR
=PP1V2_S2R_DDR
PPVREF_DDR1_DQ
PPVREF_DDR0_DQ
=PP1V2_VDDQ_DDR
=PP1V8_S2R_DDR
RESET_SOC_L
=PP1V8_VDDIO18_SOC
=PP1V2_VDDIOD_SOC
PP1V8_XTAL
PPVREF_DDR1_CA
=PP1V2_S2R_DDR
DDR1_DQ_ZQ
PPVREF_DDR0_CA
051-0886
A.0.0
10 OF 121
8 OF 54
NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=PWR
2
1
1
2
1
2
2
1
1
2
1
2
2
1
2
1
1
2
1
2
2
1
2
1
2
1
2
1
2
1
Y33
AU17
T4
H27
K9
H25
J31
J20
G30
G31
G33
H1
H2
H3
H4
H5
H29
H32
J2
J3
J4
J5
J10
J12
J18
J22
J24
J26
J28
J30
K1
K3
K4
K7
K11
K13
K15
K17
K19
K21
K23
K25
K27
K29
K31
K34
L2
J6
J8
J14
K5
AP22
AP23
AC33
AU15
F11
D14
U4
AB34
AF34
AV12
AV15
R34
W34
AC2
AD33
C20
G2
J33
L3
P33
U2
U33
Y34
AJ2
AG33
AU10
AU14
AU22
AV17
AU20
C8
C4
C14
D24
AK1
AE34
B3
D25
B14
E2
J34
P34
V33
U1
AU12
AV22
AU19
A6
A8
C25
C21
J1
F1
L1
R1
N1
V1
A10
A12
A15
A17
A19
AE1
AC1
AH1
AL1
Y1
K2
J16
U31
U32
AV21
AV19
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
AG6
AE6
AC6
Y30
AM17
Y19
Y21
Y23
Y27
Y29
Y32
AM8
AM12
Y17
Y15
Y13
Y9
Y5
Y4
Y2
W33
W28
W26
W24
W22
W20
W18
W16
W12
W8
W5
W3
V34
V32
V30
V27
V25
V15
V13
V9
V7
V5
V4
V3
V2
U34
U30
V29
U29
T29
R29
AM24
AM23
AM22
AM21
AM20
Y6
W10
W14
U6
T6
G29
G24
P30
H30
K30
M30
W2
T11
T9
T7
V23
V21
V19
V17
U22
U20
U18
U14
U12
U10
U8
U5
U3
T34
T33
T32
T31
T30
T27
T25
T23
T21
T19
T17
T15
T13
T5
T3
T2
T1
R33
AH30
AD30
AM19
AM10
AH6
AD6
V11
Y3
Y7
Y11
AA6
H10
H11
H12
H13
H14
H15
M6
N6
P6
R6
V6
W6
AM14
AM16
H9
W4
W1
U28
U26
H6
H7
H8
U24
G27
G25
AJ6
AE30
21
2
1
1
2
1
2
2
1
1
2
1
2
2
1
1
2
1
2
54
8
8
8
8
8
54
8
54
8
54
8
54
8
8
8
54
54
4
10 11 24 48 52
9
54
54
52
8
8
54
8
WWW.AliSaler.Com
VDD_SENSE
VDDVDD
SYM 10 OF 13
SYM 8 OF 13
VDD_ANA_TMPSADC0
VDD_ANA_TMPSADC1
VDD_ANA_TMPSADC2
VDD_ANA_TMPSADC3
VDD_SRAM_SOC
VSS
VDD_SRAM_CPU
VDD_GPUVDD_CPU
VDD_GPU_SENSE
VDD_SENSE_CPU
SYM 13 OF 13
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(VDD BALLS = VDD_SOC PWR DOMAIN)
7,500MA FOR G3 GPU
@125C
@1.1V/1.2GHZ
10,800MA FOR CPU0+1
@1.1V
@125C
(2.5MA)
(2.5MA)
(2.5MA)
(2.5MA)
@125C
@1.0V
(1500MA)
1,500MA FOR CYCLONE + M$ SRAM
(THERMAL VIRUS)
@1.0V
@125C
2,500MA FOR VDD_SOC
POP-1GB-DDR
H6P
FCMSP
U0652
OMIT
CRITICAL
20%
4V
0610
4.3UF
X5R-CERM
C1148
20%
C1151
1UF
4V
X6S
0204
4V
0.47UF
20%
C1153
X7S
0204
0204
X6S
C1150
1UF
20%
4V
X7S
4V
20%
0204
C1152
0.47UF
FCMSP
POP-1GB-DDR
H6P
U0652
OMIT
CRITICAL
C1160
20%
0.1UF
01005
6.3V
X5R-CERM
OMIT
POP-1GB-DDR
H6P
U0652
CRITICAL
FCMSP
CRITICAL
C1103
4V
X5R-CERM
4.3UF
0610
20%
C1102
X5R-CERM
4.3UF
0610
20%
4V
CRITICAL
C1101
4V
20%
X5R-CERM
4.3UF
0610
CRITICALCRITICAL
C1100
0610
20%
4V
X5R-CERM
4.3UF
C1109
CRITICAL
0204
X6S
4V
20%
1UF
C1114
+/-0.5PF
8.2PF
01005
NP0-C0G-CERM
16V
C1108
CRITICAL
1UF
20%
4V
X6S
0204
C1107
CRITICAL
1UF
20%
4V
X6S
0204
0201
0.22UF
20%
X5R
6.3V
C1113
C1106
20%
1UF
4V
0204
X6S
CRITICAL
4V
20%
1UF
C1105
0204
X6S
CRITICAL
0201
0.22UF
20%
X5R
6.3V
C1112
C1111
0.47UF
20%
0204
X7S
4V
CRITICAL
0204
X6S
20%
C1104
1UF
4V
CRITICAL
0204
20%
0.47UF
C1110
CRITICAL
X7S
4V
C1118
CRITICAL
4V
X5R-CERM
0610
4.3UF
20%
C1117
CRITICAL
4.3UF
4V
20%
0610
X5R-CERM
C1122
4V
20%
X5R-CERM
4.3UF
0610
CRITICAL
C1126
20%
1UF
4V
0204
X6S
CRITICAL
C1121
CRITICAL
4V
20%
X5R-CERM
4.3UF
0610
C1125
1UF
20%
4V
X6S
0204
CRITICAL
C1116
20%
X5R
4V
0402
15UF
C1115
20%
X5R
4V
0402
15UF
4.3UF
0610
X5R-CERM
20%
4V
CRITICAL
C1120
C1124
20%
1UF
4V
X6S
0204
CRITICAL
4.3UF
X5R-CERM
0610
20%
4V
CRITICAL
C1119
C1123
20%
1UF
4V
0204
X6S
CRITICAL
C1130
20%
1UF
4V
X6S
0204
CRITICAL
C1129
20%
1UF
4V
X6S
0204
CRITICAL
C1134
01005
8.2PF
NP0-C0G-CERM
16V
+/-0.5PF
0201
0.22UF
20%
C1133
6.3V
X5R
C1128
20%
1UF
4V
0204
X6S
CRITICAL
C1127
1UF
20%
4V
0204
X6S
CRITICAL
C1132
CRITICAL
0204
X6S
4V
20%
1UF
C1131
CRITICAL
0204
X6S
4V
20%
1UF
C1138
4V
0204
0.47UF
20%
CRITICAL
X7S
0.47UF
4V
20%
0204
CRITICAL
C1142
X7S
C1137
4V
20%
0204
0.47UF
CRITICAL
X7S
CRITICAL
4V
20%
0204
C1141
0.47UF
X7S
0201
6.3V
X5R
C1145
0.22UF
20%
C1136
20%
0204
4V
0.47UF
CRITICAL
X7S
C1140
CRITICAL
4V
0204
0.47UF
20%
X7S
20%
CRITICAL
C1135
0.47UF
4V
X7S
0204
C1139
CRITICAL
20%
0.47UF
0204
4V
X7S
01005
20%
6.3V
X5R
0.22UF
C1144
01005
20%
6.3V
0.22UF
X5R
C1143
CRITICAL
C1187
X7S
4V
20%
0.47UF
0204
CRITICAL
C1186
20%
4V
0204
0.47UF
X7S
CRITICAL
C1185
0.47UF
20%
0204
X7S
4V
CRITICAL
C1184
20%
0204
X7S
4V
0.47UF
CRITICAL
C1183
0204
4V
1UF
20%
X6S
CRITICAL
C1182
4V
1UF
20%
X6S
0204
C1194
8.2PF
+/-0.5PF
01005
NP0-C0G-CERM
16V
0.22UF
X5R
6.3V
20%
01005
C1193C1192
01005
20%
6.3V
X5R
0.22UF
C1191
01005
20%
6.3V
X5R
0.22UF
C1190
01005
20%
6.3V
X5R
0.22UF
CRITICAL
20%
1UF
4V
0204
X6S
C1181
CRITICAL
20%
0204
1UF
4V
X6S
C1180
CRITICAL
20%
1UF
4V
X6S
C1179
0204
CRITICAL
X6S
4V
20%
1UF
0204
C1178
CRITICAL
0610
4V
20%
X5R-CERM
4.3UF
C1177
CRITICAL
4V
X5R-CERM
4.3UF
0610
20%
C1176
CRITICAL
20%
X5R-CERM
4.3UF
0610
4V
C1175
CRITICAL
4.3UF
0610
4V
20%
X5R-CERM
C1174
CRITICAL
4V
20%
4.3UF
0610
X5R-CERM
C1173
CRITICAL
X5R-CERM
4V
20%
4.3UF
0610
C1172
15UF
0402
4V
X5R
20%
C1171
15UF
0402
4V
20%
X5R
C1170
0.47UF
0204
4V
X7S
20%
C1189
CRITICAL
0204
4V
X7S
20%
0.47UF
CRITICAL
C1188
SOC: VDD, SRAM, CPU, GPU PWRS
SYNC_MASTER=N/A
SYNC_DATE=04/18/2011
=PPVDD_CPU
=PPVDD_GPU
PPVDD_CPU_SOC_SENSE
PPVDD_GPU_SOC_SENSE
=PP1V8_VDDIO18_SOC
=PPVDD_SRAM_SOC
PPVDD_SOC_SOC_SENSE
=PPVDD_SOC
051-0886
A.0.0
11 OF 121
9 OF 54
P20
P22
K10
K8
K18
K16
K14
K12
K6
J29
J27
J23
J21
J19
J17
J15
J13
J11
AK6
AK20
R7
V31
R17
U23
R25
V22
J25
N27
N17
N15
N13
AN11
Y20
Y18
Y16
W19
W17
W7
V28
V26
V24
V20
V18
V16
V14
U27
U25
U21
U19
U17
U7
T28
T26
T24
T22
T20
T18
T16
T14
R27
R23
R21
R19
R15
R13
P28
P24
P18
P16
P14
P12
P10
P8
N29
N25
N23
N21
N19
N11
N9
N7
M26
M24
M22
M20
M18
M16
M14
M12
M10
L27
L25
L23
L21
L19
L17
L15
L13
L11
L9
L7
K28
J9
J7
H28
H24
AN9
AL23
AK30
AN18
AF30
AF20
AF6
AE21
AN15
AD20
AN13
AB20
AB14
AA17
K20
AA7
U15
P26
M28
L29
AA19
R11
R9
K26
K24
K22
H26
AH20
AB30
M8
2
1
2
1
2
1
2
1
2
1
R28
R30
R31
AJ20
AA20
AB4
H22
AA9
AA11
AA13
AA15
AB8
T10
T12
U11
L4
L5
L6
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
L30
L33
M1
M2
M3
M4
M5
M7
M9
M11
M13
M15
M17
M19
M21
N3
N5
N8
N10
N12
N14
N16
N18
N20
N22
N24
N26
N28
N30
P1
P2
P3
P4
P7
P9
P11
P13
P17
P19
P21
P23
P25
P27
P29
R2
R3
R4
R5
R8
R10
R16
R18
R24
R26
T8
U9
W13
V10
V8
U13
W15
W11
W9
V12
Y8
AD24
AD26
AD28
AE23
AE25
AE27
AF24
AF26
AF28
AK25
Y25
M23
M25
M27
M29
M31
N2
N4
N33
P5
P15
R12
R22
R14
R20
Y14
Y12
Y10
2
1
AL29
AL9
AL7
AL19
AC29
AD22
AL13
AL11
AK8
AK14
AK10
AJ9
AJ19
AJ17
AJ15
AH8
AH16
AH12
AG13
AB18
AF8
AF18
AF10
AE9
AE7
AE19
AE17
AB16
AE13
AE11
AD8
AD18
AD16
AD14
AD12
AD10
AB10
AB26
AB24
Y28
Y26
Y24
Y22
W27
W25
W21
AA29
AL27
AL21
AK28
AJ29
AJ25
AJ23
AA27
AJ21
AH26
AH24
AH22
AG21
AB12
AC9
AC19
AF27
AF25
AC27
AC25
AB28
AC23
AC21
AE15
AG9
AG7
AC11
AA25
AA23
AC17
AC15
AC13
AF12
AF14
AF16
AG23
AG27
AF22
AE29
AD27
AK12
AJ7
AJ13
AH18
AH14
AH10
AG15
AC7
AA21
AB22
AG11
AG17
AJ11
AK16
AK18
AL15
AL17
AA5
AM6
AN30
AG19
AG25
AG29
AH28
AJ27
AK22
AK24
AK26
W29
W23
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
54
54
53
8
54
54
53
54
OUT
CLK
RESET
DETGND
GND
GND
GND
GND
GND
I/O
DETECT
VCC VPP
OUT
BIIN
IN
SCHEMATIC DEFINED CONSTRAINTS (YES/NO)
CKPLUS RULE EXCEPTIONS
TABLE_DASHBOARD_INFO
REQUIRED
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
EVT101
BOARD_ID[1]
MLB_C
SIM CARD
SPI0 TEST MODE
MLB
BOARD REVISION
S/W READ FLOW
2. DISABLE PU AND ENABLE PD
1. SET GPIO AS INPUT
BOARD_ID[0]
ID[3-0] SYSTEM
1. SET GPIO AS INPUT
BOOT_CONFIG[3-0]
2. DISABLE PU AND ENABLE PD
BOOT_CONFIG[3] (GPIO29)
S/W READ FLOW
BOOT_CONFIG[0] (GPIO18)
BOOT_CONFIG[2] (GPIO28)
BOARD ID
3. READ
BOARD_ID[3]
BOARD_ID[2]
BRD_REV[2-0]
3. READ
1. SET GPIO AS INPUT
S/W READ FLOW
3. READ
BOOT_CONFIG[1] (GPIO25)
BOOT CONFIG ID
1010 J85 AP
1011 J85 DEV
1100 J86 AP
1101 J86 DEV
1110 J87 AP
1111 J87 DEV
MLB_B
0000
0010
JTAG
SPI0
0011
0001
2. ENABLE PU AND DISABLE PD
NAND <-- SELECTED
NAND TEST MODE
ID_J85_J87
2.2K
5%
01005
1/32W
MF
R1205
01005
5%
MF
1/32W
2.2K
R1201
NOSTUFFNOSTUFF
2.2K
1/32W
5%
R1200
MF
01005 01005
5%
2.2K
1/32W
MF
R1203
NOSTUFF
MF
1/32W
2.2K
5%
R1206
ID_DEV
01005
ID_J86_J87
5%
2.2K
01005
1/32W
MF
R1204
R1260
5%
100
MF
1/32W
01005
01005
1/32W
2.2K
5%
MF
R1213
4
52
100
5%
1/32W
MF
01005
R1210
01005
R1250
0%
0.00
1/32W
MF
NOSTUFF
SIM-CARD-X113-X223
F-ST-SM
CELL
J3000
24 28 52
24 28 52 24 28 52
24 28 52
C3002
CELL
CERM
6.3V
5%
100PF
01005
01005
MF
1/32W
1%
CELL
15.00K
R3000
C3001
0402
X5R
10%
16V
1.0UF
CELL
01005
MF
1/32W
5%
2.2K
R1202
1/32W
5%
100
R1211
01005
MF
NOSTUFF
2.2K
01005
5%
MF
R1207
1/32W
2.2K
MF
5%
R1208
01005
1/32W
NOSTUFF
5%
2.2K
01005
1/32W
MF
R1209
NO
SYNC_DATE=04/11/2011
SYNC_MASTER=N/A
SOC: MISC & ALIASES
GPIO_BOOT_CONFIG2
SIMCRD_CLK_CONN
SIMCRD_RST_CONN
PP_LDO6_RUIM_1V8
NC_J3000_5
SIMCRD_IO_CONN
SIM_TRAY_DETECT
MAKE_BASE=TRUE
WDOG_SOC
WDOG_SOC2PMU_RESET_IN
MAKE_BASE=TRUE
I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA
I2S3_SOC2BT_DATA
MAKE_BASE=TRUE
I2S4_SOC2BT_DATA
I2S3_SOC2BT_BCLK
MAKE_BASE=TRUE
I2S4_SOC2BT_BCLK
I2S3_SOC2BT_LRCK
MAKE_BASE=TRUE
I2S4_SOC2BT_LRCK
RESET_SOC_L
JTAG_SOC_TRST_L
JTAG_SOC_SEL
GPIO_BOARD_ID1
GPIO_BOARD_REV1
SOC_FAST_SCAN_CLK
GPIO_BOARD_ID2
GPIO_BOARD_REV2
GPIO_BOOT_CONFIG3
GPIO_BOARD_REV0
GPIO_BOARD_ID3
SOC_HOLD_RESET
SOC_TESTMODE
=PP1V8_SOC
=PP1V8_SOC
GPIO_BOARD_ID0
GPIO_BOOT_CONFIG0
GPIO_BOOT_CONFIG1
051-0886
A.0.0
12 OF 121
10 OF 54
1
2
1
2
1
2
1
2
1
2
1
2
1 2
1
2
1
2
1 2
3
2
8
111012
4
9
6
7
1
5
2
1
1
2
2
1
1
2
1
2
1
2
1
2
1
2
5
24 25 27 52
4
48
5
44
5
44
5
44
5
44
4 8
11 24 48 52
4
52
5
5
4
5
5
5
5
5
4
4
52
4 5 7
10 18 54
4 5 7
10 18 54
5
5
5
WWW.AliSaler.Com
OUT
IN
OUT
OUT
OUT
DIG_DP
DVSS
DVSS
DVSS
DIG_DN
USB1_DP
USB1_DN
USB0_DP
UART0_TX
USB0_DN
UART1_TX
UART0_RX
UART2_TX
UART1_RX
JTAG_CLK
UART2_RX
JTAG_DIO
ACC_PWR
VDD_3V0
VDD_1V8
P_IN
ACC1
ACC2
DP1
DN1
DP2
DN2
CON_DET_L
HOST_RESET
SWITCH_EN
SDA
INT
SCL
BYPASS
POW_GATE_EN*
BRICK_ID
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
343S0658 = TRISTAR 2, A1
TRISTAR
343S0614 = TRISTAR 1
TO USB BB MUX
(T’S OFF TO H4A UART4)
AP USB
ACCESSORY UART
AP DEBUG UART
TRISTAR BYPASS FOR 3V LDO
BB DEBUG UART
343S0639 = TRISTAR 2, A0
998-5855 = TRISTAR 2, TC
46
4 8
10 24 48 52
48
CRITICAL
C1303
1.0UF
X5R-CERM
10V
20%
0201-1
0.1UF
6.3V
C1302
10%
CERM-X5R
0201
0.1UF
X5R-CERM
C1300
01005
6.3V
20%
0.1UF
20%
6.3V
X5R-CERM
01005
C1301
5
48
+/-0.5PF
16V
01005
8.2PF
C1321
NP0-C0G-CERM
C1320
16V
01005
NP0-C0G-CERM
8.2PF
+/-0.5PF
C1322
16V
NP0-C0G-CERM
01005
+/-0.5PF
8.2PF
R1370
MF
0.00
0%
1/32W
01005
15
C1360
10V
20%
X5R-CERM
1.0UF
0201-1
CRITICAL
C1361
10%
1UF
402
X5R
25V
CBTL1610A1UK
U1300
CRITICAL
WLCSP
SYNC_DATE=N/A
SYNC_MASTER=N/A
IO: TRISTAR
MIKEY_TS_P
MIKEY_TS_N
USB_BB_P
USB_BB_N
USB_SOC_P
UART6_TS_ACC_TXD
USB_SOC_N
UART0_SOC_TXD
UART6_TS_ACC_RXD
UART3_BB2SOC_TX
UART0_SOC_RXD
JTAG_SOC_TCK
UART3_SOC2BB_TX
JTAG_SOC_TMS
=PP3V0_S2R_TRISTAR
PPVBUS_PROT
PPOUT_E75_ACC_ID1
PPOUT_E75_ACC_ID2
E75_DPAIR1_P
E75_DPAIR1_N
E75_DPAIR2_P
E75_DPAIR2_N
TS_CON_DET_L
TS2PMU_RESET_IN
RESET_SOC_L
I2C0_SDA_1V8
GPIO_TS2SOC2PMU_INT
I2C0_SCL_1V8
TRISTAR_BYPASS
NET_SPACING_TYPE=PWR
VOLTAGE=3V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=0.5MM
OVP_SW_EN_L
PMU_USB_BRICKID
L81_MBUS_REF
=PP1V8_S2R_TRISTAR
=PP3V3_ACC
051-0886
A.0.0
13 OF 121
11 OF 54
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1 2
2
1
2
1
C3
F5C1A6
C4
A1
B1
A3
E2
B3
F2
E1
D2
F1
A5
D1
B5
D5
F4
F3
F6
C5
E5
A2
B2
A4
B4
E3
B6
E4
D3
C6
D4
E6
D6
C2
15 52
15 52
24 52 53
24 52 53
4
52
5
52
4
52
5
52
5
52
5
24 28 52
5
52
4
52
5
24 28 52
4
52
54
46 52
43
43
43
43
43
43
43
5
48 52
5
48 52
48
54 54
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1
WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQ
VSS
VCCQ
VDDI
TMSC
TCKC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
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NOTICE OF PROPRIETARY PROPERTY:
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D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
ENSURE TRACE INDUCTANCE < 2NH
LAYOUT NOTE FOR U1400 VDDI:
C1413
2.2UF
X5R-CERM
0201
20%
4V
20%
C1412
15UF
4V
0402
X5R
20%
C1411
15UF
4V
0402
X5R
20%
C1410
4V
X5R
15UF
0402
C1404
20%
4V
X7S
0.47UF
0204
C1407
1UF
20%
X5R
6.3V
02010204
20%
C1405
X6S
4V
1UF
6
52
6
6
6
6
6
53
6
52
6
6
6
6
6
R1454
MF
1%
243
1/32W
01005
0201
20%
4V
C1450
2.2UF
X5R-CERM
6
6
6
6
53
6
6
6
6
6
6
6
6
6
6
6
6
OMIT
LGA-12X17
U1400
CRITICAL
XXNM-XGBX8-MLC-PPN1.5-ODP
R1460
01005
1%
1/32W
MF
50K
R1461
01005
1%
1/32W
MF
50K
6.3V
01005
C1460
X5R
0.01UF
10%
6.3V
01005
C1461
X5R
0.01UF
10%
16V
5%
01005
NP0-C0G
C1491
27PF
16V
5%
01005
NP0-C0G
27PF
C1490
27PF
16V
5%
01005
NP0-C0G
C1492
NP0-C0G
01005
5%
16V
27PF
C1494
27PF
NP0-C0G
01005
5%
16V
C1493
10UF
6.3V
CERM-X5R
0402-2
20%
C1402
20%
CERM-X5R
6.3V
0402-2
10UF
C1401
6.3V
20%
10UF
CERM-X5R
0402-2
C1400
20%
0402-2
CERM-X5R
6.3V
10UF
C1480
1UF
20%
C1406
6.3V
X5R
0201
SYNC_DATE=05/04/2012
NAND STORAGE
SYNC_MASTER=MLB
=PP3V3_NAND
FMI1_AD<3>
FMI1_AD<4>
FMI0_AD<4>
FMI0_CE0_L
NC_U1400_RE0
FMI1_CE0_L
FMI_ZQ_U1400
FMI0_AD<5>
FMI0_RE_L
PPVREF_FMI_NAND
=PP1V8_NAND
FMI1_AD<0>
FMI1_AD<7>
FMI1_AD<6>
FMI1_AD<5>
FMI1_AD<1>
FMI0_AD<7>
FMI0_AD<6>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<1>
FMI0_AD<0>
FMI1_CLE
FMI0_CLE
FMI0_WE_L
FMI0_ALE
FMI0_DQS
FMI1_ALE
FMI1_WE_L
NC_U1400_RE1
FMI1_RE_L
FMI1_DQS
NC_U1400_DQS1
TP_TMSC_U1400
TP_TCKC_U1400
TP_U1400_RB0
NC_U1400_DQS0
TP_U1400_RB1
=PP1V8_NAND
PPVDDI_NAND
FMI1_AD<2>
051-0886
A.0.0
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2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
G1
G7
J7
N3
N5
L7
J1
L1
H6
K6
J5
L5
J3
K2
H2
G3
F2M6B6
C3
C5
A3
A5
E3
C1
B4
C7
F4
E5
H4
D2
E1
D4
D6
M4
K4
E7
A1
G5
OA8
OF8G0OE0
OD8
OC8
N7
OE8
OD0
OC0
A7M2L3F6B2
OF0
G8
N1
OB8
OB0
OA0
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
54
12 48 54
53
53
53
53
12 48 54
WWW.AliSaler.Com
CAP
ON S
D
VDD
GND
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TOUCH SUBSYSTEM
(PLUG - FLEX 998-4527)
RCPT - MLB 998-4526 -> 516S1054
LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION
0.38 DCR
1/32W
MF
R1752
0.00
0%
01005
J1700
503304-2010
CRITICAL
F-ST-SM-1
MF
R1790
1/32W
1.00K
1%
01005
R1753
0.00
01005
MF
0%
1/32W
NOSTUFF
C1761
27PF
5%
NP0-C0G
16V
01005
0201
C1702
X7R-CERM
16V
1000PF
10%
X5R
10V
10%
1UF
402
C1701
27PF
01005
16V
NP0-C0G
5%
C1700
L1700
0201
240OHM-350MA
1000PF
16V
X7R-CERM
0201
C1705
10%
C1704
0201
X5R
6.3V
20%
1UF
0201
10%
1000PF
X7R-CERM
C1708
16V
X5R
6.3V
20%
1UF
0201
C1707
5%
27PF
NP0-C0G
C1703
16V
01005
240OHM-350MA
0201
L1701
0201-2
240-OHM-0.2A-0.8-OHM
L1702
01005
5%
27PF
NP0-C0G
16V
C1706
6.3V
X5R
1UF
20%
0201
C1752
CRITICAL
SLG5AP302
U1700
TDFN
CRITICAL
C1750
0201
10%
0.1UF
X5R-CERM
16V
CRITICAL
C1751
10%
X7R
10V
4700PF
201
CRITICAL
1%
100K
R1751
MF
1/32W
01005
X5R-CERM
10UF
C1753
20%
0402-2
10V
CRITICAL
01005
150OHM-25%-200MA-0.7DCR
L1760
C1760
27PF
5%
NP0-C0G
16V
01005
TOUCH: SUPPORT CKT & CONN
SYNC_MASTER=N/A
SYNC_DATE=06/21/2010
PP1V8_GRAPE_SW
GPIO_BTN_HOME_L
GPIO_BTN_HOME_FILT_L
GPIO_BTN_HOME_R_L
PP3V0_S2R_HALL_FILT
DISPLAY_SYNC_R
SPI1_GRAPE_MOSI
SPI1_GRAPE_MISO
GPIO_GRAPE_IRQ_L
CLK_32K_SOC2CUMULUS
SPI1_GRAPE_CS_L
PP1V8_GRAPE_FILT
GPIO_GRAPE_RST_L
GPIO_BTN_HOME_FILT_L
NC_PMU_GPIO_HALL_IRQ_4
PMU_GPIO_MB_HALL3_IRQ
PMU_GPIO_MB_HALL2_IRQ
PMU_GPIO_MB_HALL1_IRQ
PP5V25_GRAPE_FILT
SPI1_GRAPE_SCLK_R
SPI1_GRAPE_SCLK
DISPLAY_SYNC
=PP3V0_S2R_HALL
PP3V0_S2R_HALL_FILT
VCC_MAIN_GRAPE_RAMP
=PP1V8_GRAPE
=PPVCC_MAIN_GRAPE
=PP1V8_S2R_GRAPE
=PP5V25_GRAPE
PP5V25_GRAPE_FILT
PP1V8_GRAPE_FILT
051-0886
A.0.0
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1 2
13
17
24
23
19
11
15
9
7
5
1
3
18
20
12
14
16
8
10
6
4
2
22
21
1 2
1 2
2
1
2
1
2
1
2
1
21
2
1
2
1
2
1
2
1
2
1
21
21
2
1
2
1
7
2 5
3
18
2
1
2
1
1
2
2
1
21
2
1
52
5
48 13 52
13 52
52
5
52
5
52
5
52
5
52
5
52
13 52
5
52
13 52
48
48
48
13 52
52
5
5
54 13 52
54
54
54
54 13 52
13 52
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
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NOTICE OF PROPRIETARY PROPERTY:
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SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
(P/N 510S0761 - FLEX)
P/N 510S0760 - MLB
AUDIO_JACK_FLEX RET1
AUDIO_JACK_FLEX MIC2
AUDIO_JACK_FLEX MIC1
AUDIO_JACK_FLEX RET2
PER DAVE BREECE
J1800
CRITICAL
AA07A-S016VA1
F-ST-SM-COMBO
0201-2
L1800
240-OHM-0.2A-0.8-OHM
C1800
NP0-C0G
16V
27PF
5%
01005
0.1UF
10%
6.3V
C1801
CERM-X5R
0201
NP0-C0G
16V
27PF
5%
01005
C1802
R1850
0%
0.00
MF
1/32W
01005
NOSTUFF
NP0-C0G
16V
5%
C1850
01005
27PF
01005
5%
16V
NP0-C0G
56PF
C1821
5%
16V
NP0-C0G
56PF
C1820
01005 01005
C1822
56PF
NP0-C0G
16V
5%5%
16V
NP0-C0G
56PF
01005
C1830
AUDIO: HP FLEX CONN
SYNC_DATE=03/31/2011
SYNC_MASTER=N/A
MIN_NECK_WIDTH=0.06 MM
VOLTAGE=2.65V
PP_LDO14_2V65
LAT_SW2_CTL
GPIO_SOC2AJ_HS3_SHUNT_EN
PP1V8_DMIC_FILT
LAT_SW1_CTL
CONN_HP_LEFT_FILT
CONN_HP_RIGHT_FILT
CONN_HP_HS3_FILT
CONN_HP_HEADSET_DET_FILT
CONN_HP_HS3_REF_FILT
GPIO_SOC2AJ_HS4_SHUNT_EN
DMIC1_FF_SCLK_FILT
DMIC1_FF_SD
CONN_HP_HS4_REF_FILT
CONN_HP_HS4_FILT
DMIC1_FF_SCLK
=PP1V8_DMIC
051-0886
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20
19
18
17
15
13
11
9
7
1
16
14
12
10
8
6
4
2
5
3
21
2
1
2
1
2
1
1 2
2
1
2
1
2
1
2
1
2
1
25 32 33 39 40
28 52
5
24 28 52
15
15
15
15
15
5
15
15
15
15
54
WWW.AliSaler.Com
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
BI
BI
OUT
OUT
SYM 2 OF 2
DMIC1_SCLK
DMIC2_SD
MCLK
GND13
GND0
TSTI2
TSTI1
TSTI0
GND18
GND17
GND16
GND15
GND14
GND12
GND11
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
RESET*
WAKE*
INT*
CDOUT
CDIN
CCLK
XSP_SDOUT
XSP_SDIN_DAC2_MUTE
XSP_LRCK_FSYNC
XSP_SCLK
ASP_SDOUT
ASP_SDIN
ASP_LRCK
ASP_SCLK
DMIC2_SCLK
DMIC1_SD
CS*
MBUS_REF
SYM 1 OF 2
FLYP
MIC4_BIAS_FILT
AIN3+
AIN1-
FLYN
GNDA
MIC1_BIAS
MIC2_BIAS_FILT_IN
MIC2_BIAS_FILT
MIC2_BIAS
AIN2+
AIN2M
MIC2_BIAS_IN
AIN3-
MIC3_BIAS
MIC3_BIAS_FILT
AIN4+
AIN4-
MIC4_BIAS
GNDP
GNDD
GNDHS
+VCP_FILT
FILT-
FILT+
LINEOUT_REF
LINEOUTB
LINEOUTA
HPDETECT
HS4_REF
HS3_REF
HS4
HS3
HPOUTB
HPOUTA
DN
DP
AOUT2-
AOUT2+
AOUT1_M
AOUT1+
GNDCP
-VCP_FILT
VA
VCP1
VD
VP0VLVP1
VPROG_CP
VPROG_MB
SPEAKER_VQ
AIN1+
MIC1_BIAS_FILT
GNDHS
FLYC
VCP0
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
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8 7 6 5 4 3
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NOTICE OF PROPRIETARY PROPERTY:
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PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
TABLE_ALT_ITEM
TABLE_ALT_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
DIGITAL MIC
TO HEADPHONE JACK
TO THE HP CONNECTOR
U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846
NOTE:
PLACE R1930 & R1931 CLOSE TO U3600
MIKEY BUS FILTER
PLACE L1900 TO 1905 CLOSE
14
0402
10UF
CERM-X5R
CRITICAL
20%
6.3V
C1910
XW1900
SHORT-8L-0.25MM-SM
NOSTUFF
CRITICAL
20%
X5R
4.7UF
C1907
402
6.3V
CRITICAL
4.7UF
X5R
20%
402
6.3V
C1908
22
01005
5%
1/32W
MF
R1912
22
MF
1/32W
5%
01005
R1913
14
14
5
5
22
01005
MF5%
1/32W
R1910
MF
01005
5%
22
R1911
1/32W
5
5
5
5
53
5
53
5
5
5
53
5
53
5
53
5
53
5
52
48 52
48
C1912
X5R
6.3V
402
20%
4.7UF
MF
1/20W
2.21K
1%
R1901
201
0201-1
20%
1.0UF
C1911
X5R
6.3V
1.00K
5%
1/32W
MF
01005
NOSTUFF
R1940
14
14
11
XW1902
NOSTUFF
SHORT-8L-0.25MM-SM
0201 CERM-X5R
0.1UF
10%
6.3V
C1916
0201 CERM-X5R
0.1UF
10%
6.3V
C1917
SHORT-8L-0.25MM-SM
XW1903
NOSTUFF
R1931
5%
MF
12
201
1/20W
R1930
5%
MF
201
1/20W
12
C1932
5%
25V
0201
NP0-CERM
100PF
SIGNAL_MODEL=EMPTY
C1931
5%
100PF
0201
NP0-CERM
25V
NOSTUFF
C1930
5%
NP0-CERM
25V
100PF
0201
SIGNAL_MODEL=EMPTY
11 52
11 52
L1900
FERR-33-OHM-0.8A-0.09-OHM
0201
L1901
FERR-33-OHM-0.8A-0.09-OHM
0201
L1902
FERR-33-OHM-0.8A-0.09-OHM
0201
L1903
FERR-33-OHM-0.8A-0.09-OHM
0201
L1904
01005
120-OHM-210MA
L1905
120-OHM-210MA
01005
14
14
C1990
01005
16V
NP0-C0G
100PF
5%
C1991
5%
100PF
NP0-C0G
16V
01005
0201
R1950
1.00
1%
1/20W
MF-LF
0201-1
1.0UF
20%
6.3V
CRITICAL
X5R
C1951
X5R
C1950
4.7UF
CRITICAL
20%
402
6.3V
0201
R1951
1/20W
1%
1.00
MF-LF
MF
1/20W
1%
R1952
255K
201
C1913
0.1UF
10%
0201
X5R-CERM
10V
5%
1/20W
MF
0
R1953
201
U1900
WLCSP
CS42L81-CWZR-A1
CRITICAL
WLCSP
U1900
CS42L81-CWZR-A1
0.1UF
0201
X5R-CERM
10V
C1914
10%
CRITICAL
X5R-CERM
4.7UF
20%
10V
0402
C1909C1904
10V
X5R-CERM
0201
10%
0.1UF
20%
6.3V
X5R-CERM
01005
C1915
0.1UF
20%
01005
X5R-CERM
6.3V
0.1UF
C1902
0201
10%
0.1UF
X5R-CERM
10V
CRITICAL
C1903
4.7UF
CRITICAL
6.3V
C1901
X5R
402
20%
4.7UF
C1905
X5R
6.3V
20%
402
C1906
20%
4.7UF
6.3V
402 X5R
14
L1920
240-OHM-0.2A-0.8-OHM
0201-2
C1920
4700PF
10%
10V
X7R
201
NOSTUFF
R1920
01005
3.3K
1/32W
5%
MF
14
SYNC_DATE=01/18/2012
AUDIO: L81 CODEC
SYNC_MASTER=KAVITHA
338S1213 338S1116
RADAR:13373870 SSMC FAB
U1900
155S0773 155S0453
L1904,L1905
RADAR:11100717
=PP1V7_VA_VCP
NO_TEST=TRUE
NC_MIC4_BIAS
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
CODEC_HP_HS4_REF
=PP1V8_AUDIO
L81_FLYP
0.15MM
0.3MM
L81_FLYC
0.15MM
0.3MM
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PP1V7_VCP
VOLTAGE=1.7V
NO_TEST=TRUE
AIN1P
NO_TEST=TRUE
AIN1N
L81_MIC2_BIAS
L81_MIC2_BIAS_FILT_IN
HP_MIC_POS
MIC1_BIAS_FILT
NO_TEST=TRUE
SPI2_CODEC_MISO
SPI2_CODEC_MOSI
SPI2_CODEC_SCLK
SPI2_CODEC_CS_L
L81_MBUS_REF
I2S2_CODEC_XSP_DOUT
L81_FILT
0.30MM
L81_PVCP
0.15MM
GND_AUDIO_CODEC
L81_NVCP
0.30MM
0.15MM
NO_TEST=TRUE
NC_RIGHT_CH_OUT_N
NO_TEST=TRUE
NC_RIGHT_CH_OUT_P
L81_AIN2_POS
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PPVCC_VPROG_CP
=PPVCC_MAIN_AUDIO
GND_AUDIO_CODEC
MIC4_BIAS_FILT
NO_TEST=TRUE
MIN_NECK_WIDTH=0.15MM
PPVCC_VPROG_MB
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
L81_FLYN
0.15MM
0.3MM
PPVCC_VPROG_MB_F
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=4.2V
0.15MM
0.20MM
GND_AUDIO_CODEC
VOLTAGE=0V
I2S2_CODEC_XSP_SDOUT
I2S2_CODEC_XSP_DIN
DMIC1_FF_SCLK
DMIC1_FF_SD
I2S0_CODEC_ASP_SDOUT
I2S0_CODEC_ASP_DIN
L81_DMIC1_FF_SD
NC_DMIC2_SCLK
NO_TEST=TRUE
I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT
I2S2_CODEC_XSP_BCLK
I2S2_CODEC_XSP_LRCK
GPIO_CODEC_IRQ_L
PMU_GPIO_CODEC_HS_INT_L
I2S0_CODEC_ASP_MCK
L81_DMIC1_FF_SCLK
PMU_GPIO_CODEC_RST_L
=PP1V8_AUDIO
CODEC_MIC_BIAS_FILT
MAKE_BASE=TRUE
NC_MIC3_BIAS
NO_TEST=TRUE
NO_TEST=TRUE
NC_MIC1_BIAS
AIN4P
AIN4N
MAKE_BASE=TRUE
CODEC_AIN
AIN3P
AIN3N
AIN1N
AIN1P
MIC1_BIAS_FILT
MIC4_BIAS_FILT
MIC3_BIAS_FILT
L81_MIC2_BIAS_IN
L81_AIN2_NEG
CODEC_HP_HS3
CODEC_HP_RIGHT
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
CODEC_HP_HS3
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
CODEC_HP_HS4
MIN_NECK_WIDTH=0.15MM
CODEC_HP_LEFT
MIN_LINE_WIDTH=0.20MM
L81_MBUS_P
CONN_HP_HS3_FILT
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
CONN_HP_RIGHT_FILT
MIN_LINE_WIDTH=0.20MM
CONN_HP_LEFT_FILT
MIN_NECK_WIDTH=0.15MM
CODEC_HP_DET_R
MIN_LINE_WIDTH=0.50MM
CONN_HP_HS4_FILT
MIN_NECK_WIDTH=0.20MM
L81_MBUS_N
AIN4N
NO_TEST=TRUE
MIC3_BIAS_FILT
NO_TEST=TRUE
NO_TEST=TRUE
AIN3N
NO_TEST=TRUE
AIN3P
CONN_HP_HEADSET_DET_FILT
CODEC_HP_DET
NO_TEST=TRUE
NC_LEFT_CH_OUT_N
CODEC_HP_DET
CODEC_HP_HS4
HP_MIC_NEG
NO_TEST=TRUE
AIN4P
NO_TEST=TRUE
NC_LEFT_CH_OUT_P
NO_TEST=TRUE
NC_CODEC_LINE_OUT_R
NC_CODEC_LINE_OUT_L
NO_TEST=TRUE
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
CONN_HP_HS3_REF_FILT
MIN_NECK_WIDTH=0.1MM
CONN_HP_HS4_REF_FILT
MIN_LINE_WIDTH=0.15MM
L81_MIC2_BIAS_FILT
CODEC_HP_HS3_REF
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.15MM
L81_MBUS_N
L81_MBUS_P MIKEY_TS_P
MIKEY_TS_N
NC_SPEAKER_VQ
051-0886
A.0.0
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1
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1
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B2
B7
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G5
C6
D4
C7
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H5
G7
G6
F8
F7
F6
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E6
E5
D8
D7
D6
D5
D3
C9
B10
B9
A7
B8
A6
A4
A5
B5
B4
A1
A2
B3
A3
B6
B1
C5
K5
H10
F2
C3
E4
K10
G2
H2
K3
F3
G4
C1
D1
J3
C2
H4
G3
D2
E2
F4
E10
A10
J2
H9
F1
E1
H6
J6
K6
H8
J7
K7
K1
J1
K8
J8
K4
J4
D9
D10
F9
F10
J9
K9
G1
G9
A9E8A8
E9
G10
H1
C10
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H3
K2
J10
G8
2
1
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1
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15
FILT+
SCL
VP
SDA
VA
ADO
VBST
SW
GNDA
IREF+
OUT+
OUT-
ISENSE+
ISENSE-
VSENSE+
VSENSE-
LDO_FILT
GNDP
INT*
RESET*
ALIVE
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
VER1
FILT+
SCL
VP
SDA
VA
ADO
VBST
SW
GNDA
IREF+
OUT+
OUT-
ISENSE+
ISENSE-
VSENSE+
VSENSE-
LDO_FILT
GNDP
INT*
RESET*
ALIVE
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
VER1
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
SPEAKER CONNECTOR
UPDATED: DEC 13
BY MARCH 2013. C0 FIXES PROCESS ISSUES.
2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0
REMOVED BASED ON PERFORMANCE ON J65
1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN
I2C ADDRESS: 1000000X
PLACE XWS CLOSE TO CONNECTOR
LEFT SPEAKER AMP
I2C ADDRESS: 1000001X
RIGHT SPEAKER AMP
TFA302610A-SM
2.2UH-20%-3.3A-0.115OHM
L2050
U2040
WLCSP
CS35L19B-CWZR/C0
WLCSP
U2050
CS35L19B-CWZR/C0
CRITICAL
0402-1
X5R-CERM
20%
10V
10UF
C2094C2092
0.1UF
10%
10V
X5R-CERM
0201
C2093
10V
10%
0.1UF
X5R-CERM
0201
X5R-CERM
10UF
CRITICAL
C2095
10V
20%
0402-1
CRITICAL
X5R-CERM
0402-1
20%
10V
10UF
C2091
CRITICAL
C2090
10V
20%
0402-1
X5R-CERM
10UF
10V
C2042
CRITICAL
X5R-CERM
4.7UF
0402
20%
SIGNAL_MODEL=EMPTY
SM
XW2051
SIGNAL_MODEL=EMPTY
SM
XW2050
SIGNAL_MODEL=EMPTY
SM
XW2040
SIGNAL_MODEL=EMPTY
SM
XW2041
C2054
10V
0201
10%
0.1UF
X5R-CERM
C2055
603
X5R
10V
20%
10UF
CRITICAL
R2051
201
MF
1%
44.2K
1/20W
6.3V
CERM-X5R
0.1UF
10%
C2056
0201
4.7UF
X5R-CERM1
CRITICAL
C2058
6.3V
20%
402
402
C2057
20%
CRITICAL
4.7UF
X5R-CERM1
6.3V
R2041
201
MF
1%
1/20W
44.2K
X5R-CERM1
4.7UF
C2048
402
20%
6.3V
CRITICAL
20%
0402
10V
X5R-CERM
C2041
CRITICAL
4.7UF
CRITICAL
C2051
0402
10V
20%
4.7UF
X5R-CERM
C2043
0402
X5R-CERM
10V
CRITICAL
4.7UF
20%
CRITICAL
TFA302610A-SM
L2040
2.2UH-20%-3.3A-0.115OHM
10%
C2044
X5R-CERM
0.1UF
10V
0201
CRITICAL
10UF
C2045
20%
10V
X5R
603
CERM-X5R
10%
6.3V
0.1UF
C2046
0201
X5R-CERM1
CRITICAL
C2047
20%
6.3V
4.7UF
402
MF
1%
1/4W
0.100
R2050
CRITICAL
0402
1%
MF
1/4W
CRITICAL
0.100
R2040
0402
CRITICAL
C2052
X5R-CERM
4.7UF
0402
10V
20%
CRITICAL
C2053
20%
10V
0402
4.7UF
X5R-CERM
SIGNAL_MODEL=EMPTY
XW2077
SM
XW2076
SM
SIGNAL_MODEL=EMPTY
XW2075
SIGNAL_MODEL=EMPTY
SM
SIGNAL_MODEL=EMPTY
SM
XW2074
SYNC_MASTER=KAVITHA
AUDIO: CS35L19A AMPS
SYNC_DATE=01/18/2012
GPIO_SPKAMP_KEEPALIVE
I2C2_SDA_1V8
I2S1_SPKAMP_MCK
SPKR_L_CONN_P
SPKR_L_CONN_P
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
I2S1_SPKAMP_DIN
SPKR_R_VSENSE_N
SPKR_R_VSENSE_N
SPKR_R_CONN_P
SPKR_R_CONN_P
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
=PP1V7_VA_VCP
SPKR_R_SES_P
SPKR_L_SES_P
SPKR_L_VSENSE_N
SPKR_L_VSENSE_N
=PPVCC_MAIN_AUDIO
SPKR_L_VSENSE_P
SPKR_L_VSENSE_P
SPKR_R_VSENSE_P
SPKR_R_VSENSE_P
L19_R_SWITCH
PP1V7_VA_VCP
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_LRCK
GPIO_SPKAMP_RIGHT_IRQ_L
L19_L_LDO_FILT
L19_R_LDO_FILT
GPIO_SPKAMP_RST_L
NET_SPACING_TYPE=PWR
L19_L_VBOOST
L19_R_IREF
L19_L_FILT
L19_L_SWITCH
L19_L_IREF
GPIO_SPKAMP_LEFT_IRQ_L
I2S1_SPKAMP_BCLK
I2S1_SPKAMP_LRCK
I2S1_SPKAMP_DOUT
I2C2_SDA_1V8
GPIO_SPKAMP_KEEPALIVE
I2C2_SCL_1V8
GPIO_SPKAMP_RST_L
I2S1_SPKAMP_MCK
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
SPKR_L_CONN_N
SPKR_L_CONN_N
SPKR_L_P
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SPKR_L_SES_N
MIN_LINE_WIDTH=0.5 MM
SPKR_R_CONN_N
MIN_NECK_WIDTH=0.2 MM
SPKR_R_CONN_N
SPKR_R_P
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
L19_R_FILT
I2C2_SCL_1V8
I2S1_SPKAMP_DIN
I2S1_SPKAMP_DOUT
NET_SPACING_TYPE=PWR
L19_R_VBOOST
=PPVCC_MAIN_AUDIO
SPKR_R_SES_N
=PP1V7_VA_VCP
20 OF 121
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051-0886
4 OF 4
16 OF 54
21
F2
D1D6A4
B1
C1
D5
F5
C7
A5
A1
A2
D4
F4
F3
B5
B6
C6
E4
C4
C3
B4
B3
B7
D2
C2
E1
F1
E2
E3
C5
D3
A3
A7
A6
D7
E7
E6
F6
F7
E5
B2
F2
D1D6A4
B1
C1
D5
F5
C7
A5
A1
A2
D4
F4
F3
B5
B6
C6
E4
C4
C3
B4
B3
B7
D2
C2
E1
F1
E2
E3
C5
D3
A3
A7
A6
D7
E7
E6
F6
F7
E5
B2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
1 2
1 2
1
2
1 2
2
1
2
1
2
1
21
2
1
2
1
2
1
1 2
1 2
1 2
2
1
2
1
1 2
1 2
1 2
1 2
5
16 52
5
16 52
5
16 53
16 43 52 16 43
52
5
16 53
16
16
16 43 52 16 43
52
15 16 54
16
16
15 16 54
16
16
16
16
47 52 54
5
16 53
5
16 53
5
5
16
5
5
16 53
5
16 53
5
16 53
5
16 52
5
16 52
5
16 52
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16 43 52 16 43
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16 43
52
16 43 52
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15 16 54 15 16 54
WWW.AliSaler.Com
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
8 7 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
PAGE
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
SIZE
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
BUTTON CONNECTOR
(MOVED HERE TO SUPPORT COST FORMAT)
(REF DES PRESERVED FOR LAYOUT)
516S0828
01005
MF
1%
1/32W
1.00K
R2900
01005
MF
1/32W
1%
1.00K
R2901
01005
MF
1%
1/32W
1.00K
R2902
01005
1/32W
MF
1%
1.00K
R2903
12.8V-100PF
201-1
DZ2960
12.8V-100PF
201-1
DZ2961
201-1
12.8V-100PF
DZ2962
12.8V-100PF
201-1
DZ2963
CRITICAL
J2960
F-ST-SM
503548-1010
25V
0201
CERM
82PF
5%
C2963
0201-2
240-OHM-0.2A-0.8-OHM
L2963
82PF
5%
25V
0201
CERM
C2962
0201-2
240-OHM-0.2A-0.8-OHM
L2962
82PF
25V
0201
CERM
5%
C2961
0201-2
240-OHM-0.2A-0.8-OHM
L2961
CERM
0201
25V
82PF
5%
C2960
0201-2
240-OHM-0.2A-0.8-OHM
L2960
BUTTON: CONN
SYNC_DATE=N/A
SYNC_MASTER=N/A
GPIO_BTN_ONOFF_R_L
GPIO_BTN_VOL_UP_R_L
GPIO_BTN_VOL_DOWN_R_L
GPIO_BTN_SRL_R_L
GPIO_BTN_VOL_DOWN_L
GPIO_BTN_VOL_UP_L
GPIO_BTN_ONOFF_L
GPIO_BTN_SRL_L
GPIO_BTN_ONOFF_L_FILT
GPIO_BTN_VOL_UP_L_FILT
GPIO_BTN_SRL_L_FILT
GPIO_BTN_VOL_DOWN_L_FILT
051-0886
A.0.0
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1 2
1 2
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1
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3
10
8
6
4
9
7
2
13
11 12
14
2
1
21
2
1
21
2
1
21
2
1
21
5
5
5
48
5
48
52
52
52
52
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