Apple iPad Mini 2 Schematic PCB layout

8

7

6

5

4

3

2

1

D

D

MAIN LOGIC BOARD

C

SL9304

R4300

C4073

C4033 C4034

L4314L4315

C4326

C4327

C4322

C4323

C4317

C4318

C4316

C4074

C4319

C2971

L2901

XW2951

*

C2905

C2903

XW2950

C2901 C2904

U4358

C2902

C2900

L2900

C2908

C2970

C2906

C2980

L2911 L2910 L2912

L2902

J2950

C2972

C2907

C4485

L2950

L2807

L2808

J2800

*

C4488

C2911

C2909

C2973

L2903

*

L2800

C2800

R2800

C2802

C2807

C2806

C2801

*

U2800

L2802

L2804

L2801

L2803

L4803

FL4801

L4801

L4802

L4438L4437

C2910

R2801

C2804

U4410

C2805

C2803

*

C4472

C4487

C4484

C4486

C4483

L4436

L4440

C4471

C4467

C4489

L4435

R4605

L4613

L4807

C4805

*

C4807

L4806

*
L4805

*

U4801

*

C4804

C4803

L4804
*

C4809

FL4802

R4065

C4039

C4052

C4053

C4038

C4042

L4029

L4044

L4030

L4045

L4020

C4037

C4040

*

C4002

FL3901

L3909

R3901

L3908

*

C4049

C4071

C3811

L3819

L3817

C3809

C3808

R4064

C4230

U4215

C4231

FL4211

C4216

R4437

L3907

*

C4054

C3902

FL3902

C3905

C3904

C3903

L3903

L3902

C3901

L3901

*

L3906

C3914

L3904

C3913

L3905

C3912

C3908

C3706

*

C3721

C3716

C3907

C4064

C3906

C3909

U3901

L3824

C4047

L3823

L3822

*

C4046

C4023

L4012

U4000

*

C4012

C4076

C4075

C4072

C4232

*

C4234

C4239

L4254

C4228

C4227

L4253

C4229

*

C4218 C4219

U3600

C3911

C3910

L3810

*

L3809

L3811

L3812

*

R3600

L3808

L3807

C3801

C3800

L3800L3802

C3804

C3805 C3802

C3803

L3803 L3801

L3805

L3804

L3806

L3815

L3813

*

C4008

C3807

C3806

U3803

L3814

L3825

L3840

U4714

R4739

*

L4743

R4701

C4794

C4737

C4736

C4235

C4710

*

C4508

*

C4507

L4500

U4500

C4001

C4325 C4324

C4043

U4025

U4027

C4041

*

*

C4060

C4061

L4316

C4320

L4071

C4056

L4317

C4058

C4048

C4055

L4070

C4321

L4097

R4607

R4608

L4072

L4439

C4639

C4663

C4664

C4665

U4617

C4666

C4622

C4641

*

C4150

L4136

C4154

U4123

C4148

C4102

C4100

*

FL4012

*

C4063

L4083

L3821

*

U3802

L3820

C3810

C4668 C4669

*

SW4601

L4228

C4640

U3801

C4236

L4642

*

R4139

L4138

L4229

C4151

C4155

R8327

C4101

*

C4149

L4182

L4122

R3603

L4123

L4257

C4146

R3602

C4103

C4233

C4104

C4147

R3601

C4207

C4208

L4200

C3602

R3002

R3502

C3434

R3003

C3426

R3700

R3702

C3231

C3715

C3701

C3413

C3414

C3708

C3707

C3709

C3720

C3718

C3717

C3719

C3409

R3604

C3600

C3601

C4500

R4500

C3412

C3700

C3402

C3704

C3400

C3702

C3703

C3401

C3714

C3403

C3705

C3421

C3713

C3712

C3404

*

C3500

C3710

C3711

C3424

C3425

C4756

C4755

L4742

L4740

L4746

C4797

C4799

*

C3207

U4722

L4701

XW3303

L4747

C3225

R4711

L4765

C4708

C3206

C4798

C4739

C4738

XW3302

R4534

C4545

C3226

C3227

C4502

C4503

C4504

J2960

*

C3431

R3402

R3400

R3403

C3432

XW3002

XW3003

U3400

XW3301

XW3300

C3228

C3229

C3219

L3200

*

L3203

C3218

U3300

*

C3215

C3216

L3202

R3304

C3204

C3205

R3305 R3307

*

L3201

*

C3213

C3221

*

XW3200

L3204

XW3305

*

C3222

C3212

C3300

C3209

C3211

C3203

C3230

Y3300

C3210

R3303

C3214

C3217

DZ2963

DZ2960

MH9302

DZ2961

DZ2962

SL9303

L2962

C1400

C1411

U3520

R3401

L3520

C3423

C3520

C3422

C3407

C3433

C3406

C3410

C3411

R3530 R3531

C3416 C3408

C3415

C3417 C3405

C3420

C3419

C3418

R3306

R3300

R3301

C3223

C3220

C3208

XW3304

C1450

C3224

C1492

C3202

C1413

C3201

R8330

C3200

SL9300

PP9424

R1911

R2903

L2963

C2963

R1910

C2960

R1913

L2960

*

C1916

XW1902

R2900

R1912

XW1903

R2901

C1917

C2961

L2961

XW1900

C1910

R2902
PP9425

U1900

C1991 C1990

C2962

PP9406

C1901

C1903

R1460

C1460

C1461

C1913

R1953

R1952

R1461

C1930

R1930

C1404

C1480

C1931

C1932

C1407

R1931

C1491

U1400

C2701

L2700

R2747

U2700

R2757

R2405

C1920

*
U2400

C2401

C1412

C1494C0607

C1410

C1402

C1026

C1102

R1454

C1009

C1490 C1493

C1406

*

C1405

C2723

L2741

C2725

C2700

C2711

XW2700

U2710

C2750

*

*

C2710

R2406

U2720

L2701

XW2701

R2727

R0753

R0752

C2400

R2450

PP9403

R0870

R0871

R0720

R0646

R0831

R0655

R0640

C0613

Y0602

*

C1103

*

C1401

R8323

C1015

C1100

R0832

L2702

C2721

C1027

C2045

C2726

C2047

R2750

R1211

R1250

C0618

C1101

R0617

U0652

C1004

C2094

R2040

C2091

*

XW2041

XW2040

C2044 C2092

C2046

R0702

R0703

R0739

U2040

R0738

C2043

C2041 C2042

C2048

R0705

R0704

PP9423

PP9417

R1051

PP9419

R1052

PP9420

PP9416

C1070

R0721

R1000

C1052

C1007

R0750

R1209

R1208

R0770

R0765

R1207

U9000

R1213

R1260

C1148

C1915

C1902

R1940

C1909

C1951

C1904

*

R1951

C1914

C1905

R1950

C1906

C1950

R1920

C1907

C1908

C1912

R2400

R1901

C1911

C2055

L2040

*

C2093

C8352

C2095

*

XW2050

XW2051

C2090

C2057

C2054

C2056

U2050

PP9421

C2053

PP9422

R2051R2041

C2058

C8190

R8324

C1120

C1116

C8105

C1121

L8100

*

C1118

C1119

C8109

C8110

C1117

L8103

*

C1122

R1006

R1005

C1002

C1115 C8111

R1001

C1174

R1201

L8104

*

C1177

R0940

R0941

C8118

C1175

R0933

R0930

R0931

R0701

C1171

C1173

C8112

C8114C8116

C1176

C1170

C1172

R1205

R1206

C8120

R0751

C9000

*

C8356

C8550

C8350

U8550

U8350

*

R8352

C81A1

L2050

C81A7

C2052

C2051

C81A2

*

L8111

*

C8104

C8160

*

L8101

XW8101

C8102 C8103

C8101

C8107

*

L8102

C8100 C8106

C8171

C8108

C8117

L8105

C8113

C8172

C8119

XW8102

C8150

*

L8106

C8131

XW8106

C8132

C8115

C8130

C8127

C8126

C8128

C8555

C8355

C8129

C8125

XW8104

C8124

XW8105

L8108

L8109

*

*

C8152

C8151

C8166

C8162

C8170

C8167

C8165

C8139

C81A3 C81A0 C81A5 C81A6

XW8107

C81A4

*

C8178 C8175 C8157

U8100

C8183 C8181 C8179 C8177 C8176

*

C8161 C8158 C8184 C8182 C8180

L8110

C8235

C8188

C8186

C8168

C8185

C8187

C8156

C8159

C8242

C8307

C8154

C8234

C8164

R0735

*

*

C8153

C8212

L8107

C8122

R8425

U8400

C8123

C8121

R8420

C8460

XW8103

C8142

C8226

C8141

*

R0771

C8144

C8200

C8203

C8201

C8238

C8231

C8135

C8138

C8137

D8230

C8290

C8210

C8239

C81A9

C8196

C81A8

C8136

*

L8229

R0651

XW8114

C8145

C8148

C8147

C8308

R8172

R8173

C8149

C8233

C8230

C8237

C8241

C8216

C8215

C8305

R8303

C8240

C8232

Y8200

C8310

C8211

C8306

C8169

C8143

*

C8140

Q8104

C8400

R8430

C8163

R8445

R8411

R8410

*

Q8440

*

R8451

R8435

R8450

XW8410

D8100

L8225

*

*

C1752

C1750

U1700

R1751

C8254

C1751

C1753

C8250

C8253

C8252

D8228

C8259

C8251

L2200

Q8123

*

DZ8120

R8130

R8116

R3000

C3000

U3000

U3003

C3001

U3001

L8112

R2290

R2291

U2201

C2270

*

R8322

C2240

R2205

C8155

C8301

*

R8399

U1300

R1370

C1321

C1301

*

U2200

C2239

C1302

C1322

R8170

C2230

C2203

R8146

C8146

C1303

C2241

C2202

C1361

C1360

C1320

C1300

SL9305

MH9300

J3000

C3002

U3002

C5880

C5882

*

C5827

J5820

C5817

R5820

C5826

U5820

*

C5825

C5822

C5821

C5824

C5823

C5820

*

XW5891

XW5890

*

J5810

R5810

C5816

U5810

*

U5811

C5815

R5830

L5811

C5814

C5810

C5811

C5813

U5800

XW5897

R0736

C5881

PP9483 PP9482

XW5892

R5805

R5802

R5800

R5801

R5804

R5803

PP9469

PP9468

SP*

STD9302

L1702

R1752

R1753

C1761

C2233

C8280

R8227

C8281

*

R8231

C8282

R8232

R8235

*

C8283

L5810

R8239

C8284

R8240

C8285

L2201

C5800

C5801

*

STD9300

PP9472

XW5896

R2242

R2250

XW5895

PP9471

L2240

XW5893

XW5894

DZ5700

C5702

C5700

L5700

C5703

R5700

C7522

C5701

FL7500

C7523

C7525

C7526

C7524

C8193

C8194

R8100

C1708

C2221

R2241

C1707

C2250

C1706

C2251

R1790

R2243

C1760

C2242

L1760

C2243

L2212 L2242L2232L2202 L2222

L1701

*

C1704

C2245

C2244

C1705

C1703

J1700

* *

C2247

C1700

J2201

C2232

C2246

L1700

C1702

C2249

C2248

C2260

R8321

*

XW7520

*

J7500

C1701

D5701D5703

L5704

DZ5702

C5704

R5790

R5791

R5706 R5705

DZ5710

STD9301

L5701

C5705

DZ5703

L5702

C5707

DZ5704

D5702

L5703

D5700

C

*

J4910

*

L2602

C2606

C2608

L2660

C2607

B

L2600

C2601

C2600

L2611

C2602

J2601

XW2600

C2605

L2610

C2603

C2604

L2601

R2601

U2601

U2600

*

*

*

R1850

C1850

L1903

L1905

L1800

L1904

C1800

L1902

L1901

C1830

C1821 C1820

L1900

L1920

J1800

C1802

C1801

C1822

SP*

*

J4802

*

R4801

C4801

C4802

J4800

A

DRAWING

schemu

820-4124-A TOP

B

A

8 7 6 5 4 2 1

3

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

SCH AND BOARD PART NUMBERS

QTY

PART#

D

820-4124

C

B

DESCRIPTION

1

SCH,MLB-C1,X200

1

PCBF,MLB-C1,X200

PDF CSA

TABLE_TABLEOFCONTENTS_HEAD

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2

4

6
7

8
9

10

11
12

13
14

17
18

19

20
21

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26

CONTENTS
TABLE OF CONTENTS
BLOCK DIAGRAM: SYSTEM
BOM TABLES
SOC: MAIN
SOC: I/OS
SOC: NAND
SOC: DP,MIPI
SOC: SRAM, IO PWRS
SOC: VDD, SRAM, CPU, GPU PWRS
SOC: MISC & ALIASES
IO: TRISTAR
NAND STORAGE
TOUCH: SUPPORT CKT & CONN
AUDIO: HP FLEX CONN
AUDIO: L81 CODEC
AUDIO: CS35L19A AMPS
BUTTON: CONN
VIDEO: EDP SUPPORT & CONN
SENSOR: OSCAR
CAMERA: FF-ALS CONN & FILTERS

7

REFERENCE DESIGNATOR(S)

SCH1051-0886

PCB1

BOM OPTION

3456

REV ECN

MLB-C1

X200

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

SYNC MASTER

N/A N/A

J85_MLB_B

J72_MLB_C

N/A

N/A

N/A

MLB

N/A

N/A

N/A

N/A N/A

MLB

N/A

N/A

KAVITHA

KAVITHA

N/A N/A

J85 MLB_C

J72_MLB_C

J85 MLB_C

DATE

04/02/2013

11/26/2012

04/18/2011

05/05/2011

04/18/2011

05/04/2012

04/18/2011

04/18/2011

04/11/2011

05/04/2012

06/21/2010

03/31/2011

01/18/2012

01/18/2012

12/05/2012

11/26/2012

12/03/2012

LAST_MODIFIED=Tue Oct 29 15:52:27 2013

TABLE_TABLEOFCONTENTS_HEAD

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TABLE_TABLEOFCONTENTS_ITEM

CSAPDF

CONTENTS

27

SENSOR: ACCEL, COMPASS, GYRO

28

SENSOR: PROX

29

CAMERA: REAR CONN & FILTERS

30

CELL:AP INTERFACE & DEBUG CONNECTORS

32

CELL: BASEBAND PMU (1 0F 2)

33

CELL: BASEBAND PMU (2 OF 2)

34

CELL: BASEBAND (1 OF 2)

35

CELL: BASEBAND (2 OF 2)

36

CELL: RF TRANSCEIVER (1 0F 2)

37

CELL: RF TRANSCEIVER (2 OF 2)

38

CELL: RX MATCHING

39

CELL: RF TRANSCEIVER (3 OF 4)

40

CELL: PENTABAND PA

41

CELL: BAND 2/3 PAD

42

CELL: BAND 7/20 PAD

43

CELL: BAND 5/8 PAD

44

CELL: 2G PA

45

CELL: PA DCDC CONVERTER

46

CELL: ASM AND HB LTE FRONT-END

47

CELL: RX DIVERSITY

48

CELL: GPS

49

CELL: ANTENNA FEEDS

57

IO: FILTERS & HOTBAR CONN

58

WIFI/BT: MODULE

75

POWER: BATTERY CONNECTOR

81

PMU: ANYA PAGE 1

82

PMU: ANYA PAGE 2

83

PMU: ANYA PAGE 3

84

PMU: ANYA PAGE 4

85

POWER: PP1V8_SW

90

SEP: EEPROM & SOC DEBUG

93

TEST: TP/HOLES/FIDUCIALS

94

TEST: EE TP/PP

121

POWER: ALIASES

SYNC MASTER

N/A N/A
J85 MLB_C
N/A N/A

RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87

RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87

RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87

RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87

RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87

RADIO_MLB_87
N/A
WIFI_DEV
N/A N/A

J72_MLB_C
J85 MLB_C
J72_MLB_C
J72_MLB_C

J85 MLB_C
J72_MLB_C
J85 MLB_C

J72_MLB_C
J72_MLB_C

DATE

12/05/12

10/29/2013
10/29/2013
10/29/2013
10/29/2013

10/29/2013
10/29/2013
10/29/2013

10/29/2013
10/29/2013
10/29/2013
10/29/2013

10/29/2013
10/29/2013
10/29/2013
10/29/2013

10/29/2013
10/29/2013
10/29/2013

10/29/2013
04/18/2011
05/20/2013

11/26/2012
12/03/2012
11/26/2012
11/26/2012

11/26/2012
11/26/2012
12/03/12

11/26/2012
11/26/2012

A

0002535199

DESCRIPTION OF REVISION

PRODUCTION RELEASED

12

CK
APPD

DATE

2014-01-13

D

C

B

w w w . c h i n a f i x . c o m

A

DRAWING

8 7 6 5 4 2 1

3

DRAWING TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SCH,MLB-C1,X200

Apple Inc.

R

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

1 OF 121

SHEET

1 OF 54

SIZE

A

D

8 7 6 5 4 3

12

ISP1_I2C

GRAPE

SPI1

MIPI1C

ISP0_I2C

CUMULUS

CUMULUS

D

MIPI0C

HSIC2
UART1

FRONT CAMERA

REAR CAMERA

D

MIMO

WIFI/BT ANT

WIFI/BT

UART2

I2S3

BT_I2S

CSA 58

WIFI/BT ANT

NOT ON

ALCATRAZ

DISPLAY/

TOUCH PANEL

EDP

C

BACKLIGHT

HSIC1

I2S4

UART3

CELLULAR/

HSIC1

JTAG
USART

USB

CSA 31-46

GPS

WIFI-ONLY CONFIG

PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT

GPS ANT

C

SIM CARD

UART5

BUTTON FLEX

HOME BUTTON

B

PMU

ANYA

CSA 81-84

HALL EFF

1-3

BATTERY

CSA 75

OSCAR

CSA 24

DWI
I2C0

UART4
I2C1

USB2.0

UART0
UART6

I2C0

I2C2

TRISTAR

CSA 13

B

I2S1

COMPASS

CSA 17

SPI BUS

ACCELEROMETER

GYRO

CSA 27CSA 27CSA 27

I2C3

FMI0

FMI1

SPI2

I2S0
I2S2

SPI
ASP

XSP

MBUS

AMP

CSA 20

AMP

CSA 20

w w w . c h i n a f i x . c o m

RIGHT

SPEAKER

LEFT
SPEAKER

L81

AUDIO

A

HP

PROX SENSOR

CSA 28

NAND FLASH

ALS

CSA 14

6 3

CODEC

CSA 19

MIC1 MIC2

SYNC_MASTER=J85_MLB_B

PAGE TITLE

BLOCK DIAGRAM: SYSTEM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/02/2013

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

2 OF 121

SHEET

2 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

SOC

Page Notes

Power aliases required by this page:
(NONE)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:

D

C

BOM OPTIONS

COMMON
ALTERNATE

16GB_PROD
32GB_PROD
64GB_PROD
128GB_PROD

DEVELOPMENT_JTAG_TAP
JTAG_DAP
MLB (WDOG TO PMU)

WIFI BOM OPTIONS

ANDGATE_TI
FERRITE_TY
FERRITE_TDK

BOM GROUP

BASIC

BOM OPTIONS

COMMON,ALTERNATE

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

PART#

339S0207

PART NUMBER

PMU

PART#

343S0656

FLASH CONFIGURATIONS

PART#

335S0922 32GB

335S0924

PART NUMBER

335S0931 335S0922

335S0932

DESCRIPTION

QTY

H6P + 1GB ELPIDA

1

ALTERNATE FOR
PART NUMBER

339S0207339S0208

DESCRIPTION

QTY

1

IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342

QTY

DESCRIPTION

1

TOS,19NM,PPN1.5,C,DDP,16GB

TOS,19NM,PPN1.5,C,QDP,32GB

1

1

TOS,19NM,PPN1.5,C,ODP,64GB

1

TOS,19NM,PPN1.5,C,12DP,64GB

1

TOS,19NM,PPN1.5,C,16DP,128GB

ALTERNATE FOR
PART NUMBER

335S0921335S0930

335S0923

BOM OPTION

BOM OPTION

16GB

32GB

64GB

REFERENCE DESIGNATOR(S)

U0652

REF DES

COMMENTS:

HYNIX DDR

U0652

REFERENCE DESIGNATOR(S)

U8100

REFERENCE DESIGNATOR(S)

U1400

U1400

U1400

U1400

U1400

REF DES

COMMENTS:

U1400

HYNIX 20NM PPN1.5 16GB

HYNIX 20NM PPN1.5 32GB

U1400

HYNIX 20NM PPN1.5 64GB

U1400

CRITICAL BOM OPTION

CRITICAL

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL BOM OPTION

CRITICAL

BOM OPTION

16GB335S0921

64GB335S0923

96GB335S0929

128GB

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

D

TABLE_5_HEAD

TABLE_5_ITEM

C

U2200

TABLE_5_HEAD

TABLE_5_ITEM

WIFI

PART NUMBER

ALTERNATE FOR
PART NUMBER

339S0213339S0223

BOM OPTION

REF DES

U5800

COMMENTS:

QTY

PART#

353S4272

NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES)

TABLE_ALT_HEAD

TABLE_ALT_ITEM

4.3UF CAP

PART NUMBER

DESCRIPTION

IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8

1

ALTERNATE FOR
PART NUMBER

138S0657138S0702

BOM OPTION

REFERENCE DESIGNATOR(S)

U2200

REF DES

COMMENTS:

RDAR #13988471

C1009,C1015,...

BOM OPTION

TABLE_ALT_HEAD

TABLE_ALT_ITEM

MECHANICAL PARTS

PART#

B

806-6207

806-7613

DESCRIPTION

QTY

1

FENCE,TALL,MLB,X221

FENCE,RADIO,MLB,C BRD,X221

1

REFERENCE DESIGNATOR(S)

PD_FENCE_MLB

PD_CAN_RADIO

CRITICAL BOM OPTION

CRITICAL

CRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

B

GYRO

PART#

338S1192

BARCODE LABEL/EEEE CODES

PART#

825-7639

825-7639

825-7639

825-7639

825-7639

825-7639

825-7639

A

825-7639

825-7639

825-7639

DESCRIPTION

QTY

EEEE FOR 639-5393 (X200C1 GOOD)

1

EEEE FOR 639-5394 (X200C1 BETTER)

1

EEEE FOR 639-5385 (X200C1 BEST)

1

EEEE FOR 639-5386 (X200C1 BEST+)

1

EEEE FOR 639-5387 (X200C1 ULTIMATE)

1

EEEE FOR 639-5388 (X200C1 GOOD IVS)

1

EEEE FOR 639-5389 (X200C1 BETTER IVS)

1

EEEE FOR 639-5390 (X200C1 BEST IVS)

1

EEEE FOR 639-5391 (X200C1 BEST+ IVS)

1

EEEE FOR 639-5392 (X200C1 ULTIMATE IVS)

1

REFERENCE DESIGNATOR(S)

FNJD

FNJ5

FNJ9

FNJH

FNJ6

FNJ8

FNJF

FNJC

FNJ7

FNJG

CRITICAL BOM OPTION

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

EEEE_X200C_GOOD

EEEE_X200C_BETTER

EEEE_X200C_BEST

EEEE_X200C_BEST+

EEEE_X200C_ULTIMATE

EEEE_X200C_GOOD_IVS

EEEE_X200C_BETTER_IVS

EEEE_X200C_BEST_IVS

EEEE_X200C_BEST+_IVS

EEEE_X200C_ULTIMATE_IVS

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

w w w . c h i n a f i x . c o m

132S0391 CRITICAL

132S0288

ACCEL

PART#

PART NUMBER

DESCRIPTION

QTY

1

GYRO, ST MICRO

1

GYRO, INVENSENSE

CAP 0.01UF 25V 0201

1

CAP 0.1UF 16V 0201

1

DESCRIPTION

QTY

1

IC,ACCEL,3-AXIS,DIG,BMA282,LGA14

ALTERNATE FOR
PART NUMBER

338S1233 ST MICRO - DISQUAL’ED
338S1114 OLD ACCEL - ST MICRO
338S1191 OLD ACCEL - ST MICRO

BOM OPTION

REFERENCE DESIGNATOR(S)

U2720

U2720

C2726

C2726

REFERENCE DESIGNATOR(S)

U2700

REF DES

COMMENTS:

CRITICAL BOM OPTION

CRITICAL

CRITICAL338S1218

CRITICAL

CRITICAL BOM OPTION

CRITICAL338S1163

TABLE_ALT_HEAD

GYRO_STMICRO

GYRO_INVENSENSE

GYRO_STMICRO

GYRO_INVENSENSE

6 3

TABLE_5_HEAD

TABLE_5_ITEM

338S1158 OLD GYRO - ST MICRO

TABLE_5_ITEM

OLDER INVENSENSE P/N 338S1135
OLD INVENSENSE P/N 338S1200 (3/22/13)

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

SYNC_MASTER=J72_MLB_C

PAGE TITLE

BOM TABLES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

4 OF 121

SHEET

3 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

H6P: JTAG, USB, PLL, HSIC, XTAL

12

D

NOTE: CANDIDATE FOR COST-SAVINGS

(REPLACE WITH XW LATER?)

=PP1V8_PLL_SOC

54

R0622

1 2

0.00

=PP1V2_HSIC_SOC

54

C0690

0.22UF

20%

6.3V
X5R

0201

01005

1

2

1

C0651

0.1UF

20%

6.3V

2

X5R-CERM

C0691

0.22UF

6.3V
0201

20%
X5R

C

=PP1V8_SOC

4 5 7

10 18 54

JTAG_SOC_TDI

4

52

JTAG_SOC_TMS

4

11 52

JTAG_SOC_TCK

4

11 52

B

1

R0647

100K

1%
1/32W
MF
01005

2

1

R0646

100K

1%
1/32W
MF
01005

2

10 11 24 48 52

10 18 54

8

1

2

4 5 7

IN

R0645

100K

1%
1/32W
MF
01005

=PP1V8_SOC

RESET_SOC_L

1

R0617

100K

1%
1/32W
MF
01005

2

1

C0618

1000PF

10%

6.3V

2

X5R-CERM
01005

HSIC2_BB_DATA

24 27 53

BI

HSIC2_BB_STB

24 27 53

BI

HSIC1_WLAN_DATA

44 53

BI

HSIC1_WLAN_STB

44 53

BI

1.8V TOLERANT

10 52

10 52

4

52

4

11 52

4

11 52

10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_SOC_SEL

IN

JTAG_SOC_TRST_L

IN

JTAG_SOC_TDI

IN

JTAG_SOC_TMS

IN

JTAG_SOC_TCK

IN

SOC_HOLD_RESET

IN

NC_HSIC0_DATA
NC_HSIC0_STB

HSIC1_BB_DATA
HSIC1_BB_STB

HSIC2_WLAN_DATA
HSIC2_WLAN_STB

NC_JTAG_SOC_TRTCK

TP_JTAG_SOC_TDO

52

1

2

PP1V8_PLL_SOC_F

52

1

C0648

0.01UF

10%

6.3V

2

X5R
0100501005

A26

HSIC0_DATA

B26

HSIC0_STB

A27

HSIC1_DATA

B27

HSIC1_STB

AM33

HSIC2_DATA

AM34

HSIC2_STB

D28

JTAG_SEL

D27

JTAG_TRTCK

E28

JTAG_TRST*

E27

JTAG_TDO

F27

JTAG_TDI

F28

JTAG_TMS

C28

JTAG_TCK

F29

RESET*

E29

CFSB

D29

HOLD_RESET

H16

FUSE1_FSRC

1

C0608

0.01UF

10%

6.3V

2

X5R
01005

G22

G23

AM31

(3X 13MA)

HSIC_VDD120

HSIC_VDD122

HSIC_VDD121

HSIC_VDD120

HSIC_VDD121

HSIC_VDD122

VDDIO18_GRP3

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 1 OF 13

VDDIO18_GRP1

U16

AE20

(1MA)

(6X 1MA)

VDD_ANA_PLL

VDD_ANA_PLL_CCC

VDDIO18_GRP4

ANALOGMUXOUT

USB_ANALOGTEST

TST_CLKOUT

FAST_SCAN_CLK

(25MA)

F23

F24

USB_DVDD

USB_VDD330

(5.4MA)

USB_DP
USB_DM

USB_VBUS

USB_ID

USB_REXT

TESTMODE

(25MA)

XI0
XO0

WDOG

F25
E25

E26

B29
A29

D26

D23

E24

E23

AD4

AC3

AD3

AB3

NC_USB_ANALOGTEST

=PP1V0_USB_SOC

1

C0627

0.01UF

10%

6.3V

2

X5R
01005

=PP3V3_USB_SOC

1

C0630

0.1UF

20%

6.3V

2

X5R-CERM
01005

XTAL_SOC_24M_I
XTAL_SOC_24M_O

NC_ANALOGMUXOUT

USB_VBUS_DETECT_R

NC_USB_ID

WDOG_SOC

SOC_TEST_CLKOUT

SOC_FAST_SCAN_CLK

SOC_TESTMODE

54

54

TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD

1

R0655

OUT

IN

IN

USB_SOC_P
USB_SOC_N

10

TP0600

TP

TP-P55

10

10 52

1.00M

1%

1/32W

MF

01005

11 52

BI

11 52

BI

R0651

68.1K

1%

1/32W

MF

01005

24.000MHZ-30PPM-9.5PF-60OHM

USB_REXT

R0640

1.33K

1 2

1%

1/32W

USB_VBUS_DETECT

1

R0642

2

2

200

1%
1/32W
MF
01005

01005

Y0602

1.60X1.20MM-SM

SOC_24M_O

MF

USBHS ON/OFF TOLERANCE 5V/1.98V

46

IN

NOTE: NEW USB_REXT
VALUE FOR H6 = 200 OHM
OLD (H5) VALUE: 44.2 OHM

42

1 3

C0607

12PF

1 2

5%

16V

CERM

01005

C0613

12PF

1 2

5%

16V

CERM

01005

D

C

B

HSIC_VSS120

HSIC_VSS121

HSIC_VSS122

H20

H21

AM32

USB_VSSA0

H23

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=N/A

PAGE TITLE

SOC: MAIN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

6 OF 121

SHEET

4 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

SOC I/OS

12

R0720

33.2

1%

1/32W

MF

01005

I2S0_CODEC_ASP_MCK

15 53

OUT

D

I2S1_SPKAMP_MCK

16 53

OUT

1 2

R0721

33.2

1%

1/32W

MF

01005

1 2

I2S0_CODEC_ASP_MCK_R
I2S0_CODEC_ASP_BCLK

15

OUT

I2S0_CODEC_ASP_LRCK

15

OUT

I2S0_CODEC_ASP_DIN

15

IN

I2S0_CODEC_ASP_DOUT

15

OUT

I2S1_SPKAMP_MCK_R
I2S1_SPKAMP_BCLK

16 53

OUT

I2S1_SPKAMP_LRCK

16 53

OUT

I2S1_SPKAMP_DIN

16 53

IN

I2S1_SPKAMP_DOUT

16 53

OUT

NC_GPIO_GYRO_IRQ1

I2S2_CODEC_XSP_BCLK

15

OUT

I2S2_CODEC_XSP_LRCK

15 53

OUT

I2S2_CODEC_XSP_DIN

15

IN

I2S2_CODEC_XSP_DOUT

15 53

OUT

GPIO_SPKAMP_RIGHT_IRQ_L

16

IN

I2S3_SOC2BT_BCLK

10

OUT

I2S3_SOC2BT_LRCK

10

OUT

I2S3_BT2SOC_DATA

10

IN

I2S3_SOC2BT_DATA

10

OUT

BB_JTAG_TCK

24 27 52

OUT

BB_JTAG_TMS

24 27 52

OUT

BB_JTAG_TDI

24 27 52

OUT

BB_JTAG_TDO

24 27 52

IN

BB_JTAG_TRST_L

24 27 52

OUT

C30
AL32
AL31
AJ31
AK31

AL33
AL34
AK33
AJ32
AK34

E30
AJ33
AJ34
AH31
AH34

AG31
AG32
AH33
AF31
AG34

AE31
AF33
AE32
AD31
AE33

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

I2S4_MCK
I2S4_BCLK
I2S4_LRCK
I2S4_DIN
I2S4_DOUT

C

AV10
AN12
AT10
AP11

AN6

AP5

AT5

AV5

AU5

AV4

AU4

AR5

AU6

AR6

AP7

AN8

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

GPIO_BOARD_ID2

10

IN

GPIO_BOARD_ID1

10

IN

GPIO_BOARD_ID0

10

IN

SPI1_GRAPE_MISO

13 52

IN

SPI1_GRAPE_MOSI

13 52

OUT

SPI1_GRAPE_SCLK

13

OUT

SPI1_GRAPE_CS_L

13 52

OUT

SPI2_CODEC_MISO

15 53

IN

SPI2_CODEC_MOSI

15 53

OUT

SPI2_CODEC_SCLK

15 53

OUT

SPI2_CODEC_CS_L

15

OUT

NC_SPI0_SSIN

NC_SPI1_NAVAJO_MISO
NC_SPI1_NAVAJO_MOSI
NC_SPI1_NAVAJO_SCLK
NC_GPIO_NAVAJO2SOC_INT

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 3 OF 13

CRITICAL

VDDIO18_GRP2

VDDIO18_GRP2

VDDIO18_GRP1

VDDIO18_GRP1

VDDIO18_GRP1

SEP_7816UART0_RST
SEP_7816UART0_SCL
SEP_7816UART0_SDA

VDDIO18_GRP1

SEP_7816UART1_RST
SEP_7816UART1_SCL
SEP_7816UART1_SDA

SIO_7816UART0_RST
SIO_7816UART0_SCL
SIO_7816UART0_SDA
SIO_7816UART1_RST
SIO_7816UART1_SCL

VDDIO18_GRP2

SIO_7816UART1_SDA

DISP_VSYNC

I2C0_SCL
I2C0_SDA

I2C1_SCL
I2C1_SDA

I2C2_SCL
I2C2_SDA

I2C3_SCL
I2C3_SDA

DWI_CLK

DWI_DI
DWI_DO

SOCHOT0
SOCHOT1

AV6
AR7

AP8
AU7

AT11
AR11

W30
W32

AP19
AT18
AT19

AR1
AP3
AP2
AR4
AR2
AP4

AB33
AA31
AB31
AA33
AA32
AA34

AP18
AP17

AN17

I2C0_SCL_1V8
I2C0_SDA_1V8

I2C1_SOC2OSCAR_SWDCLK_1V8

I2C1_SOC2OSCAR_SWDIO_1V8

I2C2_SCL_1V8
I2C2_SDA_1V8

I2C3_SCL_1V8
I2C3_SDA_1V8

TP_SOC_TST_CPUSWITCH_OUT

NC_SEP_7816UART0_RST

SEP_I2C0_SCL
SEP_I2C0_SDA

NC_SEP_7816UART1_RST
NC_SEP_7816UART1_SCL
NC_SEP_7816UART1_SDA

HSIC1_WLAN2SOC_REMOTE_WAKE
HSIC1_WLAN2SOC_DEVICE_RDY
HSIC1_SOC2WLAN_HOST_RDY
HSIC2_BB2SOC_REMOTE_WAKE
HSIC2_BB2SOC_DEVICE_RDY
HSIC2_SOC2BB_HOST_RDY

DISPLAY_SYNC

DWI_AP_CLK

DWI_AP_DO

SOCHOT0_L
SOCHOT1_L

24 28

5

OUT

OUT

OUT

OUT

OUT

5

24 28

49 52

OUT

OUT

BI

BI

BI

IN

BI

28

44 53

44 53

5

5

5

48 52

48 53

5

44 53

5

13

11 48 52

5

11 48 52

16 52

5

16 52

20 22

5

20 22

51

5

51

48

TRISTAR
PMU

5

OUT

BI

SPK AMPS

ALS
PROX

19

5

19

GPIO_BTN_HOME_L

5

13 48

IN

GPIO_BTN_ONOFF_L

5

17 48

IN

GPIO_BTN_VOL_UP_L

17

IN

GPIO_BTN_VOL_DOWN_L

17

IN

GPIO_BTN_SRL_L

5

17 48

IN

GPIO_SOC2BEACON_EN

OUT

GPIO_SOC2AJ_HS4_SHUNT_EN
GPIO_SOC2AJ_HS3_SHUNT_EN

14

OUT

GPIO_BOARD_REV0

10

IN

GPIO_BOARD_REV1

10

IN

GPIO_BOARD_REV2

10

IN

15 52

IN

28 52

OUT

GPIO_GRAPE_IRQ_L

13 52

IN

28

IN

20

IN

GPIO_BOARD_ID3

10

IN

GPIO_BB2SOC_RESET_DET_L

24 28

IN

GPIO_BOOT_CONFIG0

10

IN

GPIO_PMU2SOC_IRQ_L

48

IN

GPIO_SOC2PMU_KEEPACT

5

48

OUT

GPIO_GRAPE_RST_L

13 52

OUT

GPIO_BB2SOC_GPS_SYNC

28

IN

GPIO_SOC2BB_RADIO_ON_L

24 26 52

IN

NC_GPIO_BB_HSIC_DEV_RDY

GPIO_BOOT_CONFIG1

10

IN

GPIO_FORCE_DFU

5

52

IN

TP_GPIO_DFU_STATUS

GPIO_BOOT_CONFIG2

10

IN

GPIO_BOOT_CONFIG3

10

IN

GPIO_SOC2OSCAR_DBGEN

19

OUT

GPIO_SOC2BB_RST_L

24 26 52

OUT

GPIO_PROX_IRQ_L

22

IN

GPIO_BB2SOC_GSM_TXBURST

28

IN

GPIO_SPKAMP_RST_L

5

16

OUT

GPIO_BT_WAKE

44 53

OUT

GPIO_TS2SOC2PMU_INT

11 48

IN

GPIO_SPKAMP_LEFT_IRQ_L

16

IN

GPIO_SOC2LCD_PWREN

18

OUT

GPIO_CODEC_IRQ_L

GPIO_SOC2BB_WAKE_MODEM

BB_IPC_GPIO
GPIO_ALS_IRQ_L

AC5
AB1
AB2
AD1
AD5
AE4
AF1
AE2
AE5
AF3
AF4
AF2
AG1
AG3
AG4
AH3
AH2
AH4
AG5
AJ5
AJ4

AK2
AP13
AP12
AR13
AN14
AT12
AT13
AV13
AP14
AU13
AP15
AR14
AT14
AT15
AP16
AR16
AT16
AT17

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38

POP-1GB-DDR

SYM 2 OF 13

CRITICAL

VDDIO18_GRP1

OMIT

U0652

H6P

FCMSP

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART0_RXD
UART0_TXD

UART1_CTSN
UART1_RTSN

UART1_RXD
UART1_TXD

UART2_CTSN
UART2_RTSN

UART2_RXD
UART2_TXD

VDDIO18_GRP1

UART3_CTSN
UART3_RTSN

UART3_RXD
UART3_TXD

UART4_CTSN
UART4_RTSN

UART4_RXD
UART4_TXD

UART5_RTXD

UART6_RXD
UART6_TXD

VDDIO18_GRP2 VDDIO18_GRP2

AC31
AD34
AC32

AR19
AR18

AL2
AL4
AK4
AK3

AL5
AM3
AM2
AM1

AN3
AN4
AP1
AN1

AV3
AU3
AT3
AT2

AM5

W31
Y31

OSCAR_TIME_SYNC_HOST_INT

GPIO_SPKAMP_KEEPALIVE

CLK_32K_SOC2CUMULUS

UART0_SOC_RXD
UART0_SOC_TXD

UART1_BT2SOC_RTS_L

UART1_SOC2BT_RTS_L
UART1_BT2SOC_TX
UART1_SOC2BT_TX

NC_UART2_CTS
NC_UART2_RTS

UART2_WLAN2SOC_TX
UART2_SOC2WLAN_TX

UART3_BB2SOC_RTS_L

UART3_SOC2BB_RTS_L
UART3_BB2SOC_TX
UART3_SOC2BB_TX

PMU_GPIO_OSCAR2PMU_HOST_WAKE
GPIO_OSCAR_RESET_L

UART4_OSCAR2SOC_RXD

UART4_SOC2OSCAR_TXD

UART5_BATT_RTXD

UART6_TS_ACC_RXD
UART6_TS_ACC_TXD

IN
OUTOUT
OUT

IN
OUT

IN
OUT

IN
OUT

IN
OUT

IN
OUT

IN
OUT

IN
OUT

IN
OUT

BI

IN
OUT

19

5

16 52 14

13 52

11 52

11 52

44

44

44 53

44 53

44 53

53

44

24 28

24 28

11 24

28 52

11 24 28 52

19 48

19

19 53

19 53

45 48

11 52

11 52

D

C

=PP1V8_S2R_MISC

5

B

51 54

=PP1V8_ALWAYS

54

=PP1V8_S2R_MISC

5

51 54

R0771

220K

1

5%

1/32W

MF

01005

R0770

220K

1 2

5%

1/32W

MF

01005

R0765

220K

1 2

5%

1/32W

MF

01005

2

GPIO_BTN_HOME_L

GPIO_BTN_ONOFF_L

GPIO_BTN_SRL_L

(SCREEN ROTATION LOCK)

=PP1V8_SOC

4 5 7

5

13 48

5

17 48

5

17 48

10 18 54

I2C0_SDA_1V8

5

11 48 52

I2C0_SCL_1V8

5

11 48 52

I2C2_SDA_1V8

5

16 52

I2C2_SCL_1V8

5

16 52

I2C3_SDA_1V8

5

20 22

I2C3_SCL_1V8

5

20 22

SEP_I2C0_SDA

5

51

SEP_I2C0_SCL

5

51

I2C1_SOC2OSCAR_SWDIO_1V8

5

19

I2C1_SOC2OSCAR_SWDCLK_1V8

5

19

1

1

R0700

2.2K

5%
1/32W
MF
01005MF01005

2

2

R0701

2.2K

5%
1/32W

1

R0702

1.8K

5%
1/32W
MF
01005

2

1

R0703

1.8K

5%
1/32W
MF
01005

2

1

2.2K

5%

1/32W
MF
01005

2

1

R0705R0704

2.2K

5%
1/32W
MF
01005

2

1

R0750

2.2K

5%
1/32W
MF
01005

2

1

R0751

2.2K

5%
1/32W
MF
01005

2

NOSTUFF

1

R0752

2.2K

5%
1/32W
MF
01005

2

NOSTUFF

1

R0753

2.2K

5%
1/32W
MF
01005

2

1

R0739

100K

1%
1/32W
MF
01005

2

1

100K

1%
1/32W
MF
01005

2

1

R0736R0735

100K

1%
1/32W
MF
01005

2

1

R0737

100K

1%
1/32W
MF
01005

2

GPIO_SPKAMP_RST_L
GPIO_SOC2PMU_KEEPACT
HSIC1_SOC2WLAN_HOST_RDY
GPIO_FORCE_DFU
GPIO_SPKAMP_KEEPALIVE

1

R0738

100K

1%
1/32W
MF
01005

2

5

16

5

48

5

44 53

5

52

5

16 52

B

w w w . c h i n a f i x . c o m

=PP1V8_SOC

4 5 7

10 18 54

A

=PP1V8_S2R_MISC

5

51 54

R0754

100K

1 2

5%

1/32W

MF

01005

R0755

100K

1 2

5%

1/32W

MF

01005

SOCHOT0_L

SOCHOT1_L

5

49 52

SIZE

A

D

SYNC_MASTER=N/A

PAGE TITLE

5

48

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SOC: I/OS

Apple Inc.

R

6 3

SYNC_DATE=05/05/2011

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

7 OF 121

SHEET

5 OF 54

124578

8 7 6 5 4 3

12

AN32
AN33
AN34

AP6
AP20
AP21
AP24

D

C

B

A

AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32

AR3

AR8
AR12
AR15
AR17
AR20
AR21
AR22
AR23
AR24
AR25
AR28
AR29
AR32

AT1

AT4

AT6
AT20
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31
AT32

AU1

AU2
AU11
AU16
AU18
AU21
AU33
AU34

AV1

AV2

AV9
AV11
AV14
AV16
AV18
AV20
AV33
AV34

B10

B11

B12

B13

B15

B16

B17

B18

B19

B25

B28

B30

B33

B34

VSS

B1
B2
B4
B5
B6
B7
B8
B9

C1
C2
C3
C5
C6
C7
C9

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 12 OF 13

CRITICAL

VSS

C10
C11
C12
C13
C15
C16
C17
C18
C19
C22
C23
C24
C26
C27
C29
C31
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D15
D16
D17
D18
D19
D20
D21
D22
D32
E1
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E18
E19
E20
E21
E22
E31
E32
E34
F2
F3
F4
F5
F6
F7
F8
F9
F10
F12
F13
F14
F15
F26
F30
F31
G1
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G26
G28

AA10
AA12
AA14
AA16
AA18
AA22
AA24
AA26
AA28
AA30

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AB29
AB32

AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AC30
AC34

AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD25
AD29
AD32

AE10
AE12
AE14
AE16
AE18
AE22
AE24
AE26
AE28

AF11
AF13
AF15
AF17
AF19

A11
A13
A14
A16
A18
A25
A28
A30
A33
A34
AA1
AA2
AA3
AA4
AA8

AB5
AB7
AB9

AC4
AC8

AD2
AD7
AD9

AE3
AE8

AF5
AF7
AF9

A1
A2
A3
A4
A5
A7
A9

VSS

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 11 OF 13

CRITICAL

AF21
AF23
AF29
AF32
AG2
AG8
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AG30
AH5
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AH29
AH32
AJ1
AJ3
AJ8
AJ10
AJ12

VSS

AJ14
AJ16
AJ18
AJ22
AJ24
AJ26
AJ28
AJ30
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK32
AL3
AL6
AL8
AL10
AL12
AL14
AL16
AL18
AL20
AL22
AL24
AL26
AL28
AL30
AM4
AM7
AM18
AM30
AN2
AN5
AN7
AB6
AM9
AM11

w w w . c h i n a f i x . c o m

AM13
AN16
AM15
AN19
AN20
AN21
AN22
AN23
AN24
AN31

=PP1V8_NAND_SOC

6

54

R0831

1

100K

1%
1/32W
MF
01005

2

FMI0_CE0_L

12 52

OUT

G32
H31

PPN0_CEN0
PPN0_CEN1

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 4 OF 13

PPN1_CEN0
PPN1_CEN1

R32
P32

NC_PPN1_CEN1NC_PPN0_CEN1

CRITICAL

FMI0_AD<0>

12

BI

FMI0_AD<1>

12

BI

FMI0_AD<2>

12

BI

FMI0_AD<3>

12 53

BI

FMI0_AD<4>

12

BI

FMI0_AD<5>

12

BI

FMI0_AD<6>

12

BI

FMI0_AD<7>

12

BI

FMI0_ALE

12

OUT

FMI0_CLE

12

OUT

FMI0_WE_L

12

OUT

12

OUT

FMI0_DQS

12 53 12

BI BI

R0870

240

1 2 1 2

1%

1/32W

MF

01005

FMI0_ZQ FMI1_ZQ

B32
C32
C33
C34
F32
F33
F34
G34

A31
B31
A32
D33
D34
E33

D31

PPN0_IO0
PPN0_IO1
PPN0_IO2
PPN0_IO3
PPN0_IO4
PPN0_IO5
PPN0_IO6
PPN0_IO7

PPN0_ALE
PPN0_CLE
PPN0_WEN
PPN0_REN
PPN0_DQS
PPN0_ZQ

PPN0_VREF

VDDIO18_GRP3

PPVREF_FMI_SOC

PPN1_IO0
PPN1_IO1
PPN1_IO2
PPN1_IO3
PPN1_IO4
PPN1_IO5
PPN1_IO6
PPN1_IO7

PPN1_ALE
PPN1_CLE
PPN1_WEN
PPN1_REN
PPN1_DQS

PPN1_VREF

PPN1_ZQ

M34
M33
L32
M32
K32
J32
H33
H34

N34
P31
N32
L31
L34
K33

N31

6 3

R0832

1

100K

1%
1/32W
MF
01005

2

FMI1_CE0_L

FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>

FMI1_ALE

FMI1_CLE
FMI1_WE_L
FMI1_RE_LFMI0_RE_L

FMI1_DQS

R0871

240

1%

1/32W

MF

01005

=PP1V8_NAND_SOC

1

R0860

50K

1%
1/32W
MF
01005

2

1

R0861

50K

1%
1/32W
MF
01005

2

SYNC_MASTER=N/A

PAGE TITLE

1

2

1

2

OUT

BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT

C0860

0.01UF

10%

6.3V
X5R
01005

C0861

0.01UF

10%

6.3V
X5R
01005

12 52

12

12

12

12

12

12

12

12

12

12

12

12

6

54

SOC: NAND

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

8 OF 121

SHEET

6 OF 54

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

=PP1V8_MIPI_SOC

D

=PP1V0_MIPI_SOC

54

NC_SENSOR0_ISTRB
NC_SENSOR0_XSHUTDOWN

NC_SENSOR1_ISTRB
NC_SENSOR1_XSHUTDOWN

MIPI0C_CAM_REAR_DATA_P<0>

23 53

IN

MIPI0C_CAM_REAR_DATA_N<0>

23 53

IN

MIPI0C_CAM_REAR_DATA_P<1>

23 53

IN

MIPI0C_CAM_REAR_DATA_N<1>

23 53

IN

DISPLAYPORT

C

=PP1V8_EDP_SOC

54

54

1

2

=PP1V0_EDP_PAD_DVDD_SOC

B

C0951

56PF

5%
16V
NP0-C0G
01005

R0901

0.00

1 2

0%

1/32W

MF

01005

1

C0952

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

1

C0957

1.0UF

20%

6.3V

2

X5R
0201-1

1

C0953

56PF

5%
16V

2

NP0-C0G
01005

1

C0958

8.2PF

+/-0.5PF

16V

2

NP0-C0G-CERM
01005

1

C0954

0.22UF

20%

6.3V

2

X5R
0201

PP1V8_EDP_AVDD_AUX

1

C0955

1.0UF

20%

6.3V

2

X5R
0201-1

F20

G18

F17

F16

(14MA)

(14MA)

(10MA)

DP_PAD_DVDD

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

DP_PAD_AVDDX

DP_PAD_AVDDP0

(50MA)

DP_PAD_AVDD1

1

C0956

1.0UF

20%

6.3V

2

X5R
0201-1

F18

F19

DP_PAD_AVDD0

DP_PAD_AVDD_AUX

(50MA)

(1MA)

F21

F22

DP_PAD_AVDD2

DP_PAD_AVDD3

(50MA)

(50MA)

23 53

OUT

23 53

OUT

NC_MIPI0C_CAM_REAR_DATA_P2
NC_MIPI0C_CAM_REAR_DATA_N2

NC_MIPI0C_CAM_REAR_DATA_P3
NC_MIPI0C_CAM_REAR_DATA_N3

MIPI0C_CAM_REAR_CLK_P
MIPI0C_CAM_REAR_CLK_N

NC_MIPI0D_DPDATA0
NC_MIPI0D_DNDATA0

NC_MIPI0D_DPDATA1
NC_MIPI0D_DNDATA1

NC_MIPI0D_DPDATA2
NC_MIPI0D_DNDATA2

NC_MIPI0D_DPDATA3
NC_MIPI0D_DNDATA3

NC_MIPI0D_DPCLK
NC_MIPI0D_DNCLK

1

C0930

1UF

20%
4V

2

X6S
0204

AN10

SENSOR0_ISTRB

AR9

SENSOR0_XSHUTDOWN

AR10

SENSOR1_ISTRB

AP10

SENSOR1_XSHUTDOWN

AU27

MIPI0C_DPDATA0

AV27

MIPI0C_DNDATA0

AU26

MIPI0C_DPDATA1

AV26

MIPI0C_DNDATA1

AU24

MIPI0C_DPDATA2

AV24

MIPI0C_DNDATA2

AU23

MIPI0C_DPDATA3

AV23

MIPI0C_DNDATA3

AU25

MIPI0C_DPCLK

AV25

MIPI0C_DNCLK

AU32

MIPI0D_DPDATA0

AV32

MIPI0D_DNDATA0

AU31

MIPI0D_DPDATA1

AV31

MIPI0D_DNDATA1

AU29

MIPI0D_DPDATA2

AV29

MIPI0D_DNDATA2

AU28

MIPI0D_DPDATA3

AV28

MIPI0D_DNDATA3

AU30

MIPI0D_DPCLK

AV30

MIPI0D_DNCLK

AN25

AN26

AN27

MIPI_VDD10

(55MA)

AN28

AM25 AN29

VDDIO18_GRP1

U0652

POP-1GB-DDR

SYM 5 OF 13

CRITICAL

MIPI_VDD10

MIPI_VSS

AM29

AM28

AM27

AM26

OMIT

H6P

FCMSP

AL25

AR26

MIPI0D_VDD18

(2MA)

VDDIO18_GRP1

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

AR30

AR31

AR27

MIPI1D_VDD18

MIPI1D_VREG_0P4V

MIPI0D_VREG_0P4V

(2MA)

ISP0_SCL
ISP0_SDA

ISP1_SCL
ISP1_SDA

SENSOR0_CLK
SENSOR0_RST

SENSOR1_CLK
SENSOR1_RST

NC_MIPI0D_VREG
NC_MIPI1D_VREG

AT7
AV7

AU8
AP9

AV8
AT8

AU9
AT9

AT33
AT34

AP33
AP34

AR33
AR34

54

1

C0962

0.1UF

20%

6.3V

2

X5R-CERM
01005

ISP0_CAM_REAR_CLK_R

ISP1_CAM_FRONT_CLK_R

NC_MIPI1C_CAM_FRONT_DATA_P1
NC_MIPI1C_CAM_FRONT_DATA_N1

1

R0931

2.2K

5%
1/32W
MF
01005

2

1

R0930

2.2K

5%
1/32W
MF
01005

2

100

01005

1 2

49.9

01005

1 2

=PP1V8_SOC

1

1

R0932

R0933

2.2K

2.2K

5%

5%

1/32W

1/32W

MF

MF

01005

01005

2

2

ISP0_CAM_REAR_SCL
ISP0_CAM_REAR_SDA

ISP1_CAM_FRONT_SCL
ISP1_CAM_FRONT_SDA

R0941

R0940

MIPI1C_CAM_FRONT_DATA_P<0>
MIPI1C_CAM_FRONT_DATA_N<0>

ISP0_CAM_REAR_CLK

ISP0_CAM_REAR_SHUTDOWN_L

ISP1_CAM_FRONT_CLK

ISP1_CAM_FRONT_SHUTDOWN_L

MIPI1C_CAM_FRONT_CLK_P
MIPI1C_CAM_FRONT_CLK_N

4 5

10 18 54

D

23 52

BI

23 52

OUT

20 52

BI

20 52

OUT

23 52

OUT

23 52

OUT

20 52

OUT

20 52

OUT

20 53

IN

20 53

IN

20 53

OUT

20 53

OUT

C

B

TP_EDP_PAD_DC_TP

SOC_EDP_R_BIAS

NOSTUFF

1

C0950

0.01UF

10%

6.3V

2

X5R
01005

1

R0900

4.99K

1%
1/32W
MF
01005

2

A

E16

DP_PAD_DC_TP

E17

DP_PAD_R_BIAS

DP_PAD_DVSS

DP_PAD_AVSS2

DP_PAD_AVSS3

G20

G21

G16

SYM 6 OF 13

CRITICAL

DP_PAD_AVSSX

DP_PAD_AVSSP0

H18

H17

DP_PAD_AVSS0

DP_PAD_AVSS1

DP_PAD_AVSS_AUX

G17

H19

G19

D30

A20
B20

A21
B21

A22
B22

A23
B23

A24
B24

EDP_HPD

EDP_AUX_P
EDP_AUX_N

EDP_DATA_P<0>
EDP_DATA_N<0>

EDP_DATA_P<1>
EDP_DATA_N<1>

EDP_DATA_P<2>
EDP_DATA_N<2>

EDP_DATA_P<3>
EDP_DATA_N<3>

18

IN

18

BI

18

BI

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

VDDIO18_GRP3

EDP_HPD

DP_PAD_AUXP
DP_PAD_AUXN

DP_PAD_TX0P
DP_PAD_TX0N

w w w . c h i n a f i x . c o m

DP_PAD_TX1P
DP_PAD_TX1N

DP_PAD_TX2P
DP_PAD_TX2N

DP_PAD_TX3P
DP_PAD_TX3N

6 3

SYNC_MASTER=MLB

PAGE TITLE

SOC: DP,MIPI

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/04/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

9 OF 121

SHEET

7 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

=PP1V2_VDDIOD_SOC

54

CAPS FOR VDDIOD ARE SHARED WITH VDDQ

D

AM20
AM21
AM22
AM23
AM24

R29
T29
U29
V29

AA6

H10
H11
H12
H13
H14
H15

H6
H7
H8
H9

M6
N6
P6
R6
T6
U6
V6
W6
Y6

VDDIOD_DDR0CA

VDDIOD_DDR1CA

VDDIOD_DDRDQ

(1000MA)

SYM 9 OF 13

C

CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX

=PP1V8_VDDIO18_SOC

9

54

1

C1070

4.7UF

20%

6.3V

2

X5R
402

1

C1072

1UF

20%
4V

2

X6S

B

0204

1

C1071

1UF

20%
4V

2

X6S
0204

1

C1073

0.47UF

20%
4V

2

X7S
0204

FL1000

1KOHM-25%-0.2A

0201

PP1V8_XTAL

52

1

C1042

1.0UF

20%
10V

2

X5R-CERM
0201-1

AD6
AH6
AM8

AM10

VDDIO18_GRP1

AM12
AM14
AM16
AM19

AD30
AH30

21

G25
G27
H30
K30
M30
P30
G29

G24

VDDIO18_GRP4

(65MA)

(GPIO,UART,SPI,I2C)
(SENSOR,SOCHOT,PMU)

VDDIO18_GRP2

(20MA)

VDDIO18_GRP3

(31MA)

(2MA)

A

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

CRITICAL

R33
T1
T2

VSS

T3
T5
T7
T9
T11
T13
T15
T17
T19
T21
T23
T25
T27
T30
T31
T32
T33
T34
U3
U5
U8
U10
U12
U14
U18
U20
U22
U24
U26
U28
U30
U34
V2
V3
V4
V5
V7
V9
V11
V13
V15
V17
V19
V21
V23
V25
V27
V30
V32
V34
W1
W2
W3
W4
W5
W8
W10
W12
W14
W16
W18
W20
W22
W24
W26
W28
W33
Y2
Y3
Y4
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y27
Y29
Y32
AM17
Y30
AC6
AE6
AG6
AJ6
AE30

=PP1V2_S2R_DDR

8

54

1

R1005

2.21K

1%
1/32W
MF
01005

2

PPVREF_DDR0_CA

NOSTUFF

1

0.01UF

10%

6.3V

2

X5R

01005

C1002

=PP1V2_VDDQ_DDR

8

54

1

R1006

2.21K

1%
1/32W
MF
01005

2

1

R1053

1.00K

1%
1/32W
MF
01005

2

PPVREF_DDR0_DQ

NOSTUFF

1

0.01UF

10%

6.3V

2

X5R

01005

C1054

=PP1V2_S2R_DDR

8

54

1

R1054

1.00K

1%
1/32W
MF
01005

2

1

R1051

2.21K

1%
1/32W
MF
01005

2

PPVREF_DDR1_CA

NOSTUFF

1

0.01UF

10%

6.3V

2

X5R

01005

C1052

=PP1V2_VDDQ_DDR

8

54

1

R1052

2.21K

1%
1/32W
MF
01005

2

1

R1055

1.00K

1%
1/32W
MF
01005

2

PPVREF_DDR1_DQ

1

R1056

1.00K

1%
1/32W
MF
01005

w w w . c h i n a f i x . c o m

2

NOSTUFF

1

2
01005

C1056

0.01UF

10%

6.3V
X5R

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

8

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

8

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

8

VOLTAGE=0.6V

MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM

NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

8

=PP1V2_S2R_DDR_SOC

54

1

C1000

0.1UF

20%

6.3V

X5R-CERM

2

01005

1

2

R1001

240

1%
1/32W
MF
01005

6 3

1

R1000

240

1%
1/32W
MF
01005

2

NOTE: CKEIN CONFIRMED 1.8V TOLERANT

DDR0_CA_ZQ
DDR1_CA_ZQ
DDR0_DQ_ZQ

1

1

R1030

240

1%
1/32W
MF
01005

2

2

(DDR IMPEDANCE CONTROL)

=PP1V2_S2R_DDR

8

54

R1031

240

1%
1/32W
MF
01005

1

C1009

4.3UF

20%
4V

2

X5R-CERM
0610

=PP1V8_S2R_DDR

54

54

DDR1_DQ_ZQ

=PP1V2_VDDQ_DDR

8

RESET_SOC_L

4

10 11 24 48 52

ON 5/6/12, BY MANU G

PPVREF_DDR0_CA

8

PPVREF_DDR1_CA

8

PPVREF_DDR0_DQ

8

PPVREF_DDR1_DQ

8

C1006

1UF

20%
4V
X6S
0204

1

C1015

4.3UF

20%
4V

2

X5R-CERM
0610

C1028

1UF

20%
4V
X6S
0204

1

C1007

1UF

20%
4V

2

X6S
0204

1

C1004

20%
4V

2

X7S
0204

1

2

1

2

1

C1026

0.47UF

20%
4V

2

X7S
0204

1

2

1

2

1

C1031

0.47UF

20%
4V

2

X7S
0204

0.47UF

C1027

4.3UF

20%
4V
X5R-CERM
0610

C1029

1UF

20%
4V
X6S
0204

AP22

DDR0_CKEIN

U32

DDR1_CKEIN

AP23

DDR0_VDD_CKE

U31

DDR1_VDD_CKE

AU15

DDR0_RREF_CA

AC33

DDR1_RREF_CA

F11

DDR0_RREF_DQ

T4

DDR1_RREF_DQ

AU17

DDR0_VREF_CA

Y33

DDR1_VREF_CA

D14

DDR0_VREF_DQ

U4

DDR1_VREF_DQ

AB34

AF34

AV12

(CURRENT CONSUMPTION

SHARED WITH VDDIOD)

AV15

AV19

VDDCA

AV21

R34
W34

AC2

AD33

C20

G2

J33

L3

P33

U2

(500MA)

U33
Y34

VDD2

AG33

AJ2
AU10
AU14
AU20
AU22
AV17

C4

C8
C14
D24

AE34

AK1

B3
B14
D25

E2

(45MA)

J34

VDD1

P34

U1
V33

AU12
AU19
AV22

A6

A8
C21
C25

F1

J1

L1

(CURRENT CONSUMPTION

SHARED WITH VDDIOD)

N1

R1

V1

VDDQ

A10
A12
A15
A17
A19
AC1
AE1
AH1
AL1

Y1

SYNC_MASTER=N/A

PAGE TITLE

(<1MA)
(<1MA)

POP-1GB-DDR

CRITICAL

SYM 7 OF 13

OMIT

U0652

H6P

FCMSP

SOC: SRAM, IO PWRS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

G30
G31
G33
H1
H2
H3
H4
H5
H25
H27
H29
H32
J2
J3
J4
J5
J6
J8
J10
J12
J14
J16
J18
J20
J22
J24
J26
J28
J30
J31

VSS

K1
K2
K3
K4
K5
K7
K9
K11
K13
K15
K17
K19
K21
K23
K25
K27
K29
K31
K34
L2

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

10 OF 121

SHEET

8 OF 54

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

=PPVDD_GPU

54

C1170

15UF

20%
4V
X5R
0402

C1116

15UF

20%
4V
X5R
0402

CRITICAL

C1122

4.3UF

20%
4V
X5R-CERM
0610

CRITICAL

C1128

1UF

20%
4V
X6S
0204

C1134

8.2PF

+/-0.5PF
16V
NP0-C0G-CERM
01005

CRITICAL

1

C1141

0.47UF

20%
4V

2

X7S
0204

1

C1171

15UF

20%
4V

2

X5R
0402

1

2

1

2

CRITICAL

C1140

0.47UF

20%
4V
X7S
0204

1

2

1

2

1

2

1

2

1

2

=PPVDD_SOC

54

1

C1100

4.3UF

20%
4V

2

X5R-CERM
0610

D

CRITICAL

1

C1104

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1110

0.47UF

20%
4V

2

X7S
0204

CRITICAL

1

C1105

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1111

0.47UF

20%
4V

2

X7S
0204

C

B

A

PPVDD_SOC_SOC_SENSE

53

CRITICAL

1

C1106

1UF

20%
4V

2

X6S
0204

1

2

AA7
AA17
AA19

L29

M28

N27

P26

R25

U15

V22
AB30
AH20

H26

J25

K20

K22

K24

K26

K28

L7

L9
L11
L13
L15
L17
L19
L21
L23
L25
L27

(VDD BALLS = VDD_SOC PWR DOMAIN)

M8
M10
M12
M14
M16
M18
M20
M22
M24
M26

N7

N9
N11
N13
N15
N17
N19
N21
N23
N25
N29

P8
P10
P12
P14
P16
P18
P20
P22
P24
P28

R7

R9
R11
R13
R15
R17
R19
R21

V31

VDD_SENSE

CRITICALCRITICAL

1

C1101

4.3UF

20%
4V

2

X5R-CERM
0610

CRITICAL

1

C1107

1UF

20%
4V

2

X6S
0204

C1112

0.22UF

20%

6.3V
X5R
0201

1

2

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 10 OF 13

CRITICAL

2,500MA FOR VDD_SOC
@125C
@1.0V
(THERMAL VIRUS)

C1113

0.22UF

20%

6.3V
X5R
0201

OMIT

CRITICAL

1

C1102

4.3UF

20%
4V

2

X5R-CERM
0610

CRITICAL

1

C1108

1UF

20%
4V

2

X6S
0204

1

C1114

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

CRITICAL

1

C1103

4.3UF

20%
4V

2

X5R-CERM
0610

CRITICAL

1

C1109

1UF

20%
4V

2

X6S
0204

R23
R27
T14
T16
T18
T20
T22
T24
T26
T28
U7
U17
U19
U21
U23
U25
U27
V14
V16
V18
V20
V24
V26
V28
W7
W17
W19
Y16
Y18
Y20
AN11
AB14

VDDVDD

AB20
AN13
AD20
AN15
AE21
AF6
AF20
AF30
AN18
AK6
AK20
AK30
AL23
AN9
H24
H28
J7
J9
J11
J13
J15
J17
J19
J21
J23
J27
J29
K6
K8
K10
K12
K14
K16
K18

=PPVDD_SRAM_SOC

54

1

C1150

1UF

20%
4V

2

X6S
0204

1

C1152

0.47UF

20%
4V

2

X7S
0204

=PP1V8_VDDIO18_SOC

8

54

1

C1160

0.1UF

20%

6.3V

2

X5R-CERM
01005

AD24

1

C1148

4.3UF

20%
4V

2

X5R-CERM
0610

1

C1151

1UF

20%
4V

2

X6S
0204

1

C1153

0.47UF

20%
4V

2

X7S
0204

w w w . c h i n a f i x . c o m

AD26
AD28
AE23
AE25
AE27

VDD_SRAM_CPU

1,500MA FOR CYCLONE + M$ SRAM

AF24

@125C

AF26

@1.0V

AF28
AK25

Y25

AA9
AA11
AA13
AA15

(1500MA)

AB8

T8
T10
T12

U9
U11
U13

VDD_SRAM_SOC

V8
V10
V12

W9
W11
W13
W15

Y8
Y10
Y12
Y14

AJ20

VDD_ANA_TMPSADC0

AA20

VDD_ANA_TMPSADC1

AB4

VDD_ANA_TMPSADC2

H22

VDD_ANA_TMPSADC3

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 8 OF 13

CRITICAL

(2.5MA)
(2.5MA)
(2.5MA)
(2.5MA)

VSS

L4
L5
L6
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
L30
L33
M1
M2
M3
M4
M5
M7
M9
M11
M13
M15
M17
M19
M21
M23
M25
M27
M29
M31
N2
N3
N4
N5
N8
N10
N12
N14
N16
N18
N20
N22
N24
N26
N28
N30
N33
P1
P2
P3
P4
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
P29
R2
R3
R4
R5
R8
R10
R12
R14
R16
R18
R20
R22
R24
R26
R28
R30
R31

CRITICAL

1

C1139

0.47UF

20%
4V

2

X7S
0204

1

C1115

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C1121

4.3UF

20%
4V

2

X5R-CERM
0610

CRITICAL

1

C1127

1UF

20%
4V

2

X6S
0204

1

C1133

0.22UF

20%

6.3V

2

X5R
0201

1

2

CRITICAL

C1117

4.3UF

20%
4V
X5R-CERM
0610

CRITICAL

C1123

1UF

20%
4V
X6S
0204

CRITICAL

1

C1129

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1135

0.47UF

20%
4V

2

X7S
0204

CRITICAL

1

C1142

0.47UF

20%
4V

2

X7S
0204

CRITICAL

1

C1172

4.3UF

20%
4V

2

X5R-CERM
0610

1

2

1

2

CRITICAL

C1118

4.3UF

20%
4V
X5R-CERM
0610

CRITICAL

C1124

1UF

20%
4V
X6S
0204

CRITICAL

1

C1130

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1136

0.47UF

20%
4V

2

X7S
0204

1

C1143

0.22UF

20%

6.3V

2

X5R
01005

CRITICAL

1

C1173

4.3UF

20%
4V

2

X5R-CERM
0610

1

2

CRITICAL

C1188

0.47UF

20%
4V
X7S
0204

54

1

2

1

2

CRITICAL

1

C1174

4.3UF

20%
4V

2

X5R-CERM
0610

CRITICAL

1

C1181

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1189

2

=PPVDD_CPU

CRITICAL

C1119

4.3UF

20%
4V
X5R-CERM
0610

CRITICAL

C1125

1UF

20%
4V
X6S
0204

CRITICAL

1

C1131

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1137

0.47UF

20%
4V

2

X7S
0204

1

C1144

0.22UF

20%

6.3V

2

X5R
01005

PPVDD_CPU_SOC_SENSE

53

CRITICAL

1

C1182

1UF

20%
4V

2

X6S
0204

0.47UF

20%
4V
X7S
0204

CRITICAL

1

C1120

4.3UF

20%
4V

2

X5R-CERM
0610

CRITICAL

1

C1126

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1132

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1138

0.47UF

20%
4V

2

X7S
0204

1

C1145

0.22UF

20%

6.3V

2

X5R
0201

CRITICAL

1

C1175

4.3UF

20%
4V

2

X5R-CERM
0610

1

2

CRITICAL

1

C1183

1UF

2

C1190

0.22UF

20%

6.3V
X5R
01005

20%
4V
X6S
0204

CRITICAL

1

C1176

4.3UF

20%
4V

2

X5R-CERM
0610

AA21
AA23
AA25
AA27
AA29
AB22
AB24
AB26
AB28
AC21
AC23
AC25
AC27
AC29
AD22
AD27
AE29
AF22
AF25
AF27
AG21
AG23
AG25
AG27
AG29
AH22
AH24
AH26
AH28
AJ21
AJ23
AJ25
AJ27
AJ29
AK22
AK24
AK26
AK28
AL21
AL27

W21
W23
W25
W27
W29
Y22
Y24
Y26
Y28

AL29

AN30

CRITICAL

1

C1177

4.3UF

20%
4V

2

X5R-CERM
0610

CRITICAL

1

C1184

0.47UF

20%
4V

2

X7S
0204

1

C1191

0.22UF

20%

6.3V

2

X5R
01005

10,800MA FOR CPU0+1
@125C
@1.1V/1.2GHZ

VDD_SENSE_CPU

SYNC_MASTER=N/A

PAGE TITLE

SOC: VDD, SRAM, CPU, GPU PWRS

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

1

C1178

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1185

0.47UF

20%
4V

2

X7S
0204

1

0.22UF

20%

6.3V

2

X5R
01005

OMIT

U0652

H6P

POP-1GB-DDR

FCMSP

SYM 13 OF 13

CRITICAL

7,500MA FOR G3 GPU

R

CRITICAL

1

C1179

1UF

20%
4V

2

X6S
0204

CRITICAL

1

C1186

0.47UF

20%
4V

2

X7S
0204

1

C1193C1192

0.22UF

20%

6.3V

2

X5R
01005

@125C
@1.1V

VDD_GPUVDD_CPU

VDD_GPU_SENSE

Apple Inc.

1

2

1

2

1

C1194

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

6 3

12

CRITICAL

C1180

1UF

20%
4V
X6S
0204

CRITICAL

C1187

0.47UF

20%
4V
X7S
0204

AB10
AB12
AB16
AB18
AC11
AC13
AC15
AC17
AC19
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE7
AE9
AF10
AF12
AF14
AF16
AF18
AF8
AG11
AG13
AG15
AG17
AG19
AG7
AG9
AH10
AH12
AH14
AH16
AH18
AH8
AJ11
AJ13
AJ15
AJ17
AJ19
AJ7
AJ9
AK10
AK12
AK14
AK16
AK18
AK8
AL11
AL13
AL15
AL17
AL19
AL7
AL9
AM6

PPVDD_GPU_SOC_SENSE

AA5

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-0886

REVISION

BRANCH

PAGE

11 OF 121

SHEET

9 OF 54

124578

A.0.0

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

D

BOARD ID

C

BOOT CONFIG ID

BOOT_CONFIG[3] (GPIO29)

BOOT_CONFIG[2] (GPIO28)

BOOT_CONFIG[1] (GPIO25)

BOOT_CONFIG[0] (GPIO18)

BOARD_ID[3]

BOARD_ID[2]

BOARD_ID[1]

BOARD_ID[0]

10 18 54

MLB

MLB_B

MLB_C

=PP1V8_SOC

4 5 7

GPIO_BOARD_ID3

5

GPIO_BOARD_ID2

5

GPIO_BOARD_ID1

5

GPIO_BOARD_ID0

5

ID[3-0] SYSTEM

1010 J85 AP
1011 J85 DEV

1100 J86 AP
1101 J86 DEV

1110 J87 AP
1111 J87 DEV

=PP1V8_SOC

4 5 7

10 18 54

GPIO_BOOT_CONFIG3

5

GPIO_BOOT_CONFIG2

5

GPIO_BOOT_CONFIG1

5

GPIO_BOOT_CONFIG0

5

BOOT_CONFIG[3-0]

0000

SPI0
SPI0 TEST MODE

0001
0010

NAND <-- SELECTED

0011

NAND TEST MODE

1

R1213

2.2K

5%
1/32W
MF
01005

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

NOSTUFFNOSTUFF

1

R1200

2.2K

5%
1/32W
MF
01005 01005

2

ID_J86_J87

1

R1204

2.2K

5%
1/32W
MF
01005

2

1

R1201

2.2K

5%
1/32W
MF
01005

2

ID_J85_J87

1

R1205

2.2K

5%
1/32W
MF
01005

2

1

R1202

2.2K

5%
1/32W
MF
01005

2

S/W READ FLOW

1. SET GPIO AS INPUT

2. DISABLE PU AND ENABLE PD

3. READ

ID_DEV

1

R1206

2.2K

5%
1/32W
MF
01005

2

NOSTUFF

1

R1203

2.2K

5%
1/32W
MF

2

JTAG

JTAG_SOC_TRST_L

4

52

1

R1211

100

5%
1/32W
MF
01005

2

JTAG_SOC_SEL

1

R1210

100

5%
1/32W
MF
01005

2

1 2

R1260

100

5%

1/32W

MF

01005

NOSTUFF

R1250

0.00

1 2

0%

1/32W

MF

01005

4

52

OUT

SOC_TESTMODE

SOC_FAST_SCAN_CLK

SOC_HOLD_RESET

RESET_SOC_L

4

52

4

4

4 8

11 24 48 52

I2S3_SOC2BT_BCLK

5

I2S3_SOC2BT_LRCK

5

I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA

5

I2S3_SOC2BT_DATA

5

WDOG_SOC

4

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

I2S4_SOC2BT_BCLK
I2S4_SOC2BT_LRCK

I2S4_SOC2BT_DATA

WDOG_SOC2PMU_RESET_IN

D

44

44

44

44

48

C

BOARD REVISION

B

A

GPIO_BOARD_REV2

5

GPIO_BOARD_REV1

5

GPIO_BOARD_REV0

5

BRD_REV[2-0]

EVT101

NOSTUFF

1

R1207

2.2K

5%
1/32W
MF
01005

2

1. SET GPIO AS INPUT

2. ENABLE PU AND DISABLE PD

3. READ

CKPLUS RULE EXCEPTIONS

SCHEMATIC DEFINED CONSTRAINTS (YES/NO)

1

R1208

2.2K

5%
1/32W
MF
01005

2

S/W READ FLOW

REQUIRED

SIM CARD

NOSTUFF

1

R1209

2.2K

5%
1/32W
MF
01005

2

24 28 52

IN

PP_LDO6_RUIM_1V8

24 25 27 52

SIMCRD_RST_CONN
SIMCRD_CLK_CONN

CELL

1

C3001

1.0UF

10%
16V

2

X5R
0402

1

VCC VPP

CELL

J3000

SIM-CARD-X113-X223

RESET

CLK

F-ST-SM

GND

DETGND

9

8

2

3

GND

GND

111012

NC_J3000_5

5

I/O

DETECT

GND

GND

4

B

CELL

1

R3000

15.00K

1%
1/32W
MF
01005

2

6

7

SIMCRD_IO_CONN

SIM_TRAY_DETECT

CELL

1

C3002

100PF

5%

6.3V

2

CERM
01005

24 28 52 24 28 52

BIIN

24 28 52

OUT

w w w . c h i n a f i x . c o m

SIZE

A

D

SYNC_MASTER=N/A

PAGE TITLE

SOC: MISC & ALIASES

Apple Inc.

R

TABLE_DASHBOARD_INFO

NO

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=04/11/2011

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

12 OF 121

SHEET

10 OF 54

124578

8 7 6 5 4 3

343S0658 = TRISTAR 2, A1
998-5855 = TRISTAR 2, TC
343S0639 = TRISTAR 2, A0
343S0614 = TRISTAR 1

12

D

D

TRISTAR

=PP3V0_S2R_TRISTAR

54

C

TO USB BB MUX

AP USB

ACCESSORY UART

AP DEBUG UART

BB DEBUG UART

(T’S OFF TO H4A UART4)

1

C1320

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

54 54

MIKEY_TS_P

15 52

MIKEY_TS_N

15 52

USB_BB_P

24 52 53

USB_BB_N

24 52 53

PMU_USB_BRICKID

48

USB_SOC_P

4

52

USB_SOC_N

4

52

UART6_TS_ACC_TXD

5

52

UART6_TS_ACC_RXD

5

52

UART0_SOC_TXD

5

52

UART0_SOC_RXD

5

52

UART3_BB2SOC_TX

5

24 28 52

UART3_SOC2BB_TX

5

24 28 52

JTAG_SOC_TCK

4

52

JTAG_SOC_TMS

4

52

1

C1300

0.1UF

20%

6.3V

2

X5R-CERM
01005

=PP1V8_S2R_TRISTAR

1

C1321

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

1

2

1

2

C1301

C1360

1.0UF

20%
10V
X5R-CERM
0201-1

0.1UF

20%

6.3V
X5R-CERM
01005

CBTL1610A1UK

C3

DIG_DP

C4

DIG_DN

A1

USB1_DP

B1

USB1_DN

C2

BRICK_ID

A3

USB0_DP

B3

USB0_DN

E2

UART0_TX

E1

UART0_RX

F2

UART1_TX

F1

UART1_RX

D2

UART2_TX

D1

UART2_RX

A5

JTAG_CLK

B5

JTAG_DIO

F4

F3

VDD_3V0

VDD_1V8

U1300

WLCSP

CON_DET_L

POW_GATE_EN*

SWITCH_EN

HOST_RESET

DVSS

DVSS

F5C1A6

CRITICAL

D5

ACC_PWR

BYPASS

DVSS

P_IN
ACC1
ACC2

DP1
DN1

DP2
DN2

SDA
SCL
INT

1

C1302

0.1UF

10%

6.3V

2

CERM-X5R
0201

F6
C5

PPOUT_E75_ACC_ID1

E5

PPOUT_E75_ACC_ID2

A2

E75_DPAIR1_P

B2

E75_DPAIR1_N

A4

E75_DPAIR2_P

B4

E75_DPAIR2_N

E3

TS_CON_DET_L

D6

OVP_SW_EN_L

E4

RESET_SOC_L

B6

TS2PMU_RESET_IN

D3

I2C0_SDA_1V8

D4

I2C0_SCL_1V8

C6

GPIO_TS2SOC2PMU_INT

E6

TRISTAR_BYPASS

CRITICAL

1

C1303

1.0UF

20%
10V

2

X5R-CERM
0201-1

1

C1322

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

43

43

43

43

43

43

43

OUT

IN

OUT

5

48 52

5

48 52

OUT

VOLTAGE=3V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5MM

TRISTAR BYPASS FOR 3V LDO

46

4 8

10 24 48 52

48

5

48

=PP3V3_ACC

PPVBUS_PROT

CRITICAL

1

C1361

1UF

10%
25V

2

X5R
402

46 52

C

B

L81_MBUS_REF

15

OUT

R1370

0.00

1 2

0%

1/32W

MF

01005

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=N/A

PAGE TITLE

IO: TRISTAR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

13 OF 121

SHEET

11 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

D

=PP3V3_NAND

54

OA0
OB0

1

2

C1404

G3
H2
J3
K2
L5
K6
J5
H6

G1
J1
L1
N3
N5
L7
J7
G7

0.47UF

20%
4V
X7S
0204

VDDI

IO0-0
IO1-0
IO2-0
IO3-0
IO4-0
IO5-0
IO6-0
IO7-0

IO0-1
IO1-1
IO2-1
IO3-1
IO4-1
IO5-1
IO6-1
IO7-1

TCKC
TMSC

OB8

F2M6B6

VCC

VSS

N1

OC8

N7

CRITICAL

OMIT

U1400

LGA-12X17

XXNM-XGBX8-MLC-PPN1.5-ODP

VSSQ

A7M2L3F6B2

OC0

OD8

VCCQ

OD0

OE8

OF8G0OE0

OF0

G8

OA8

CE0*
CLE0
ALE0
WE0*

RE0*

DQS0

DQS0*

R/B0*

CE1*
CLE1
ALE1
WE1*

RE1*

DQS1

DQS1*

R/B1*

VREF

RE0

RE1

A5
A3
C1
E3

B4
C7

H4
F4

E5

C5
C3
D2
E1

D4
D6

M4
K4

E7

G5

A1

ZQ

FMI0_CE0_L
FMI0_CLE
FMI0_ALE
FMI0_WE_L

NC_U1400_RE0

FMI0_RE_L

FMI0_DQS

NC_U1400_DQS0

TP_U1400_RB0

FMI1_CE0_L
FMI1_CLE
FMI1_ALE
FMI1_WE_L

NC_U1400_RE1

FMI1_RE_L

FMI1_DQS

NC_U1400_DQS1

TP_U1400_RB1

FMI_ZQ_U1400

1

2

C1410

15UF

20%
4V
X5R
0402

53

53

IN
IN
IN
IN

IN

IN

IN
IN
IN
IN

IN

IN

1

R1454

243

1%
1/32W
MF
01005

2

1

C1411

15UF

20%

4V

2

X5R
0402

6

52

6

6

6

6

6

53

6

52

6

6

6

6

6

PPVREF_FMI_NAND

1

2

C1412

15UF

20%
4V
X5R
0402

1

2

C1413

2.2UF

20%
4V
X5R-CERM
0201

1

2

C1493

27PF

5%
16V
NP0-C0G
01005

=PP1V8_NAND

1

C1494

27PF

5%
16V

2

NP0-C0G
01005

1

R1460

50K

1%
1/32W
MF
01005

2

1

R1461

50K

1%
1/32W
MF
01005

2

12 48 54

=PP1V8_NAND

1

C1460

0.01UF

10%

6.3V

2

X5R
01005

1

C1461

0.01UF

10%

6.3V

2

X5R
01005

12 48 54

C1401

10UF

20%

6.3V
CERM-X5R
0402-2

1

2

C1402

10UF

20%

6.3V
CERM-X5R
0402-2

1

C1480

10UF

20%

6.3V

2

CERM-X5R
0402-2

1

2

1

2

53

C1405

1UF

20%
4V
X6S

C1492

27PF

5%
16V
NP0-C0G
01005

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

1

C1406

1UF

20%

6.3V

2

X5R
0201

PPVDDI_NAND

1

C1450

2.2UF

20%
4V

2

X5R-CERM
0201

FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>

FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>

1

2

C1407

1UF

20%

6.3V
X5R
02010204

1

2

C1490

27PF

5%
16V
NP0-C0G
01005

1

2

C1491

27PF

5%
16V
NP0-C0G
01005

1

2

1

C1400

10UF

20%

6.3V
2

CERM-X5R
0402-2

LAYOUT NOTE FOR U1400 VDDI:
ENSURE TRACE INDUCTANCE < 2NH

C

B

TP_TCKC_U1400

53

TP_TMSC_U1400

53

D

C

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=MLB

PAGE TITLE

NAND STORAGE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=05/04/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

14 OF 121

SHEET

12 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

TOUCH SUBSYSTEM

12

L1700

1

R1751

100K

1%
1/32W
MF
01005

2

240OHM-350MA

0201

CRITICAL

1

C1750

0.1UF

10%
16V

2

X5R-CERM
0201

VCC_MAIN_GRAPE_RAMP

CRITICAL

1

C1751

4700PF

10%
10V

2

X7R
201

21

18

VDD

U1700

TDFN

GND

1

C1702

1000PF

10%
16V

2

X7R-CERM
0201

CRITICAL

D

3

1

C1700

27PF

5%
16V

2

NP0-C0G
01005

1

C1701

1UF

10%
10V

2

X5R
402

=PP1V8_S2R_GRAPE

54

SLG5AP302

7

CAP

2 5

ON S

PP5V25_GRAPE_FILT

CRITICAL

1

C1752

1UF

20%

6.3V

2

X5R
0201

PP1V8_GRAPE_SW

CRITICAL

1

C1753

10UF

20%
10V

2

X5R-CERM
0402-2

52

SPI1_GRAPE_SCLK

5

DISPLAY_SYNC

5

1 2

R1753

0.00

0%

1/32W

MF

01005

R1752

0.00

1/32W
01005

1 2

NOSTUFF

1

C1761

27PF

5%
16V

2

NP0-C0G
01005

0%
MF

PP3V0_S2R_HALL_FILT

13 52

52

SPI1_GRAPE_SCLK_R
SPI1_GRAPE_MISO

5

52

SPI1_GRAPE_MOSI

5

52

SPI1_GRAPE_CS_L

5

52

CLK_32K_SOC2CUMULUS

5

52

GPIO_GRAPE_IRQ_L

5

52

GPIO_GRAPE_RST_L

5

52

PP1V8_GRAPE_FILT

13 52

=PP5V25_GRAPE

D

54 13 52

=PPVCC_MAIN_GRAPE

54

=PP1V8_GRAPE

54

C

L1760

LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION

0.38 DCR

L1701

240OHM-350MA

0201

21

1

C1703

27PF

5%
16V

2

NP0-C0G
01005

1

C1704

1UF

20%

6.3V

2

X5R
0201

1

2

PP1V8_GRAPE_FILT

C1705

1000PF

10%
16V
X7R-CERM
0201

13 52

GPIO_BTN_HOME_L

5

48 13 52

150OHM-25%-200MA-0.7DCR

01005

21

RCPT - MLB 998-4526 -> 516S1054

(PLUG - FLEX 998-4527)

503304-2010

DISPLAY_SYNC_R

52

GPIO_BTN_HOME_R_L

1

C1760

27PF

5%
16V

2

NP0-C0G
01005

CRITICAL

J1700

F-ST-SM-1

2
4
6

8
10
12
14
16
18
20

22
21

1
3
5
7
9
11
13
15
17
19

23
24

R1790

1.00K

1 2

1%

1/32W

MF

01005

GPIO_BTN_HOME_FILT_L

NC_PMU_GPIO_HALL_IRQ_4

PMU_GPIO_MB_HALL3_IRQ
PMU_GPIO_MB_HALL2_IRQ
PMU_GPIO_MB_HALL1_IRQ

PP5V25_GRAPE_FILT

GPIO_BTN_HOME_FILT_L

13 52

48

48

48

D

13 52

C

B

=PP3V0_S2R_HALL

54 13 52

L1702

240-OHM-0.2A-0.8-OHM

0201-2

21

1

C1706

27PF

5%
16V

2

NP0-C0G
01005

1

C1707

1UF

20%

6.3V

2

X5R
0201

1

C1708

1000PF

10%
16V

2

X7R-CERM
0201

PP3V0_S2R_HALL_FILT

B

w w w . c h i n a f i x . c o m

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

TOUCH: SUPPORT CKT & CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/21/2010

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

17 OF 121

SHEET

13 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

D

R1850

0.00

1 2

0%

1/32W

MF

01005

DMIC1_FF_SD

15

GPIO_SOC2AJ_HS4_SHUNT_EN

5

GPIO_SOC2AJ_HS3_SHUNT_EN

5

LAT_SW2_CTL

28 52

PP_LDO14_2V65

25 32 33 39 40

LAT_SW1_CTL

24 28 52

=PP1V8_DMIC

54

L1800

0201-2

240-OHM-0.2A-0.8-OHM

DMIC1_FF_SCLK

15

C1800

27PF

5%
16V
NP0-C0G
01005

PP1V8_DMIC_FILT

21

1

2

C

DMIC1_FF_SCLK_FILT

NOSTUFF

1

C1850

27PF

5%
16V

2

NP0-C0G
01005

VOLTAGE=2.65V

1

C1820

56PF

5%
16V

2

NP0-C0G
01005 01005

1

C1830

56PF

16V

2

NP0-C0G
01005

1

C1821

56PF

5%
16V

2

NP0-C0G
01005

1

C1822

56PF

5%5%
16V

2

NP0-C0G

MIN_NECK_WIDTH=0.06 MM

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R
0201

P/N 510S0760 - MLB

(P/N 510S0761 - FLEX)

CRITICAL

J1800

AA07A-S016VA1

F-ST-SM-COMBO

2
4
6

8
10
12
14
16

1

C1802

27PF

5%
16V

2

NP0-C0G
01005

18
17

1
3
5
7
9
11
13
15

19
20

CONN_HP_HS4_FILT
CONN_HP_HS4_REF_FILT
CONN_HP_HS3_REF_FILT

CONN_HP_HS3_FILT

CONN_HP_RIGHT_FILT

CONN_HP_LEFT_FILT

CONN_HP_HEADSET_DET_FILT

15

15

15

15

15

15

15

AUDIO_JACK_FLEX RET2
AUDIO_JACK_FLEX MIC1
AUDIO_JACK_FLEX MIC2
AUDIO_JACK_FLEX RET1

PER DAVE BREECE

D

C

B

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=N/A

PAGE TITLE

AUDIO: HP FLEX CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=03/31/2011

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

14 OF 54

PAGE

18 OF 121

SHEET

124578

SIZE

A

D

8 7 6 5 4 3

=PPVCC_MAIN_AUDIO

16 54

=PP1V8_AUDIO

15 54

R1950

D

=PP1V7_VA_VCP

16 54

CRITICAL

1

C1901

4.7UF

20%

6.3V

2

X5R

GND_AUDIO_CODEC

15 52

R1901

2.21K

1 2

MF

1%

1/20W

C

C1911

1.0UF

6.3V

0201-1

1

20%

2

X5R

L81_MIC2_BIAS_FILT_IN

XW1902

SHORT-8L-0.25MM-SM

CODEC_HP_HS4

15 52

CODEC_HP_HS3

15 52

2 1

NOSTUFF

XW1903

SHORT-8L-0.25MM-SM

2 1

NOSTUFF

402

L81_MIC2_BIAS_IN

201

L81_MIC2_BIAS

C1912

4.7UF

1 2

20%

6.3V
X5R
402

HP_MIC_POS

HP_MIC_NEG

CRITICAL

1

C1903

0.1UF

10%
10V

2

X5R-CERM
0201

L81_MIC2_BIAS_FILT

C1916

0.1UF

1 2

10%

6.3V

0201 CERM-X5R

C1917

0.1UF

1 2

10%

6.3V

0201 CERM-X5R

15

15

15

15

15

15

15

15

15

1.00

1 2

MF-LF

1%

1/20W

GND_AUDIO_CODEC

15 52

C1905

4.7UF

12

6.3V

20%

402

X5R

C1906

4.7UF

12

20%

6.3V
402 X5R

NC_MIC1_BIAS
AIN1P
AIN1N
MIC1_BIAS_FILT

NC_MIC3_BIAS

AIN3P
AIN3N
MIC3_BIAS_FILT

NC_MIC4_BIAS

AIN4P
AIN4N
MIC4_BIAS_FILT

0201

L81_FLYP

0.3MM

0.15MM

L81_FLYC

0.3MM

0.15MM

L81_FLYN

0.3MM

0.15MM

L81_AIN2_POS
L81_AIN2_NEG

PP1V7_VCP

CRITICAL

1

C1950

4.7UF

20%

6.3V

2

X5R
402

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

1

2

VOLTAGE=1.7V
MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.15MM

NC_SPEAKER_VQ

C1902

0.1UF

20%

6.3V
X5R-CERM
01005

CRITICAL

1

C1951

1.0UF

20%

6.3V

2

X5R
0201-1

H10

FLYP

J10

FLYC

K10

FLYN

H2

MIC1_BIAS

E3

AIN1+

E4

AIN1-

H3

MIC1_BIAS_FILT

J3

MIC2_BIAS_IN

G4

MIC2_BIAS

K3

MIC2_BIAS_FILT_IN

F3

MIC2_BIAS_FILT

C1

AIN2+

D1

AIN2M

H4

MIC3_BIAS

C3

AIN3+

C2

AIN3-

G3

MIC3_BIAS_FILT

F4

MIC4_BIAS

D2

AIN4+

E2

AIN4-

F2

MIC4_BIAS_FILT

C10

SPEAKER_VQ

1

C1915

0.1UF

20%

6.3V

2

X5R-CERM
01005

G1

G9

A9E8A8

G8

VA

VCP0

VCP1

VD

CRITICAL

CS42L81-CWZR-A1

WLCSP

SYM 1 OF 2

GNDP

B

E10

VP0VLVP1

U1900

GNDA

GNDD

GNDHS

GNDHS

G2

K2

J2

A10

SHORT-8L-0.25MM-SM

0.1UF

10%
10V

X5R-CERM

0201

E9

LINEOUT_REF

NOSTUFF
XW1900

G10

VPROG_CP

+VCP_FILT

-VCP_FILT

HPDETECT

LINEOUTA
LINEOUTB

21

CRITICAL

1

1

C1909C1904

4.7UF

20%
10V

2

2

X5R-CERM
0402

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

PPVCC_VPROG_CP

1

C1914

0.1UF

10%
10V

2

X5R-CERM
0201

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

PPVCC_VPROG_MB_F

1

2

H1

VPROG_MB

H9
J9

GNDCP

K9

F10

AOUT1+

AOUT1_M

AOUT2+
AOUT2-

HPOUTA
HPOUTB

HS3_REF
HS4_REF

FILT+
FILT-

HS3
HS4

NO_TEST=TRUE

F9

NO_TEST=TRUE

D10

NO_TEST=TRUE

D9

NO_TEST=TRUE

J4

DP

K4

DN

J8
K8
J1
K1
K7
J7
H8

K6

NO_TEST=TRUE

J6

NO_TEST=TRUE

H6

L81_FILT

E1
F1

R1951

1.00

1 2

1/20W

0201

MF-LF

R1952

255K

1 2

1/20W

C1913

0.1UF

10%
10V
X5R-CERM
0201

L81_PVCP

L81_NVCP

NC_LEFT_CH_OUT_P
NC_LEFT_CH_OUT_N

NC_RIGHT_CH_OUT_P
NC_RIGHT_CH_OUT_N

L81_MBUS_P
L81_MBUS_N
CODEC_HP_LEFT

52

CODEC_HP_RIGHT

52

CODEC_HP_HS3

15 52

CODEC_HP_HS4

15 52

CODEC_HP_DET

NC_CODEC_LINE_OUT_L
NC_CODEC_LINE_OUT_R

CRITICAL

1

C1910

10UF

20%

6.3V

2

CERM-X5R
0402

VOLTAGE=0V

GND_AUDIO_CODEC

NOTE:

U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846

1%

1

R1953

0

5%
1/20W
MF
201

2

1%

201

MF

PPVCC_VPROG_MB

VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM

CRITICAL

C1907

4.7UF

1 2

0.30MM

0.15MM

0.15MM

MIN_LINE_WIDTH=0.20MM
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

0.15MM

0.20MM

15 52

0.30MM

15

15

20%
X5R

CRITICAL

C1908

4.7UF

1 2

15

6.3V
402

GND_AUDIO_CODEC

6.3V

20%
X5R

402

MIN_NECK_WIDTH=0.15MM

15 52

CODEC_HP_DET

15

CODEC_HP_HS3_REF

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

CODEC_HP_HS4_REF

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

MIKEY BUS FILTER

SIGNAL_MODEL=EMPTY

1

C1930

100PF

5%

PLACE R1930 & R1931 CLOSE TO U3600

R1930

12

1 2

5%

0201

0201

1/20W

MF

201

R1931

12

1 2

5%

1/20W

MF

201

L1920

21

0201-2

21

CONN_HP_LEFT_FILT

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

21

CONN_HP_RIGHT_FILT

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

21

CONN_HP_HS3_FILT

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

21

CONN_HP_HS4_FILT

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

21

CONN_HP_HS3_REF_FILT

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

21

CONN_HP_HS4_REF_FILT

MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM

L81_MBUS_P MIKEY_TS_P

15

L81_MBUS_N

15

R1920

3.3K

1 2

1/32W
01005

52

52

5%
MF

CODEC_HP_DET_R

52

NOSTUFF

1

C1920

4700PF

10%
10V

2

X7R
201

240-OHM-0.2A-0.8-OHM

PLACE L1900 TO 1905 CLOSE
TO THE HP CONNECTOR

FERR-33-OHM-0.8A-0.09-OHM

FERR-33-OHM-0.8A-0.09-OHM

FERR-33-OHM-0.8A-0.09-OHM

FERR-33-OHM-0.8A-0.09-OHM

L1900

L1901

L1902

0201

L1903

0201

L1904

120-OHM-210MA

01005

L1905

120-OHM-210MA

01005

25V

2

NP0-CERM
0201

NOSTUFF

1

C1931

100PF

5%
25V

2

NP0-CERM
0201

SIGNAL_MODEL=EMPTY

1

C1932

100PF

5%
25V

2

NP0-CERM
0201

CONN_HP_HEADSET_DET_FILT

IN

OUT

OUT

IN

IN

IN

IN

MIKEY_TS_N

14

14

14

14

14

14

14

12

11 52

BI

11 52

BI

TO HEADPHONE JACK

D

C

B

MIC1_BIAS_FILT

CODEC_MIC_BIAS_FILT

MAKE_BASE=TRUE

1

C1990

100PF

5%
16V

2

NP0-C0G
01005

MIC3_BIAS_FILT
MIC4_BIAS_FILT

AIN1P

CODEC_AIN

MAKE_BASE=TRUE

1

C1991

100PF

5%
16V

2

NP0-C0G

A

01005

AIN1N
AIN3P
AIN3N
AIN4P
AIN4N

15

15

15

5

53

15

15

15

15

15

15

=PP1V8_AUDIO

15 54

48

IN

w w w . c h i n a f i x . c o m

NOSTUFF

1

R1940

1.00K

5%
1/32W
MF
01005

2

IN

5

IN

5

IN

5

IN

5

IN

5

IN

53

5

IN

5

53

IN

5

IN

11

IN

5

OUT

5

53

OUT

5

53

IN

5

53

OUT

5

52

OUT

48 52

OUT

DIGITAL MIC

DMIC1_FF_SD

14

IN

DMIC1_FF_SCLK

14

IN

I2S0_CODEC_ASP_MCK
I2S0_CODEC_ASP_BCLK

I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_DIN

I2S2_CODEC_XSP_BCLK
I2S2_CODEC_XSP_LRCK
I2S2_CODEC_XSP_DOUT
I2S2_CODEC_XSP_DIN

L81_MBUS_REF
SPI2_CODEC_CS_L
SPI2_CODEC_SCLK
SPI2_CODEC_MOSI
SPI2_CODEC_MISO

GPIO_CODEC_IRQ_L
PMU_GPIO_CODEC_HS_INT_L
PMU_GPIO_CODEC_RST_L

R1910

1/32W

R1911

1/32W

R1912

1/32W

R1913

1/32W

5%

1 2

5%

1 2

5%

1 2

1 2

22

01005

MF

22

MF

01005

NC_DMIC2_SCLK

I2S0_CODEC_ASP_SDOUT

22

01005

MF5%

I2S2_CODEC_XSP_SDOUT

22

MF

01005

L81_DMIC1_FF_SD
L81_DMIC1_FF_SCLK

NO_TEST=TRUE

B1

DMIC1_SD

B2

DMIC1_SCLK

B7

DMIC2_SD

B6

DMIC2_SCLK

C8

MCLK

A3

ASP_SCLK

B3

ASP_LRCK

A2

ASP_SDIN

A1

ASP_SDOUT

B4

XSP_SCLK

B5

XSP_LRCK_FSYNC

A5

XSP_SDIN_DAC2_MUTE

A4

XSP_SDOUT

K5

MBUS_REF

C5

CS*

A6

CCLK

B8

CDIN

A7

CDOUT

B9

INT*

B10

WAKE*

C9

RESET*

U1900

CS42L81-CWZR-A1

WLCSP

SYM 2 OF 2

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18

TSTI0
TSTI1
TSTI2

C6
D3
D5
D6
D7
D8
E5
E6
E7
F5
F6
F7
F8
G5
G6
G7
H5
H7
J5

C4
C7

D4

PART NUMBER

155S0773 155S0453

338S1213 338S1116

ALTERNATE FOR
PART NUMBER

BOM OPTION

SYNC_MASTER=KAVITHA

PAGE TITLE

REF DES

L1904,L1905

U1900

COMMENTS:

RADAR:11100717

RADAR:13373870 SSMC FAB

AUDIO: L81 CODEC

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

SYNC_DATE=01/18/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

15 OF 54

PAGE

19 OF 121

SHEET

124578

SIZE

A

D

8 7 6 5 4 3

12

RIGHT SPEAKER AMP

=PPVCC_MAIN_AUDIO

15 16 54 15 16 54

CRITICAL

1

2

D

47 52 54

1

C2041

4.7UF

20%
10V

2

X5R-CERM

0402

PP1V7_VA_VCP

CRITICAL

C2042

4.7UF

20%
10V

X5R-CERM

0402

CRITICAL

C2043

4.7UF

20%
10V

X5R-CERM

0402

1

2

C2044

0.1UF

10%
10V

X5R-CERM

0201

1

2

2.2UH-20%-3.3A-0.115OHM

TFA302610A-SM

I2C2_SDA_1V8

5

16 52

I2C2_SCL_1V8

5

16 52

GPIO_SPKAMP_RIGHT_IRQ_L

5

GPIO_SPKAMP_RST_L

5

16

GPIO_SPKAMP_KEEPALIVE

5

16 52

I2S1_SPKAMP_MCK

5

16 53

I2S1_SPKAMP_BCLK

5

16 53

I2S1_SPKAMP_LRCK

5

16 53

I2S1_SPKAMP_DOUT

5

16 53

I2S1_SPKAMP_DIN

5

16 53

CRITICAL

L2040

1

2

0.1UF
10%
10V

X5R-CERM

0201

L19_R_VBOOST

CRITICAL

1

C2045

10UF

20%
10V

2

X5R
603

21

L19_R_SWITCH

CRITICAL

1

2

C

LEFT SPEAKER AMP

=PPVCC_MAIN_AUDIO

15 16 54

CRITICAL

1

2

B

C2051

4.7UF

20%
10V

X5R-CERM

0402

CRITICAL

1

C2052

4.7UF

20%
10V

2

X5R-CERM

0402

CRITICAL

1

C2053

1

C2054

4.7UF

0.1UF

20%

10%

10V

X5R-CERM

0402

2

10V

X5R-CERM

0201

2

2.2UH-20%-3.3A-0.115OHM

I2C2_SDA_1V8

5

16 52

I2C2_SCL_1V8

5

16 52

GPIO_SPKAMP_LEFT_IRQ_L

5

GPIO_SPKAMP_RST_L

5

16

GPIO_SPKAMP_KEEPALIVE

5

16 52

I2S1_SPKAMP_MCK

5

16 53

I2S1_SPKAMP_BCLK

5

16 53

I2S1_SPKAMP_LRCK

5

16 53

I2S1_SPKAMP_DOUT

5

16 53

I2S1_SPKAMP_DIN

5

16 53

TFA302610A-SM

1

C2093

0.1UF
10%
10V

2

X5R-CERM

0201

L2050

L19_L_VBOOST

CRITICAL

1

C2055

10UF

20%
10V

2

X5R
603

21

L19_L_SWITCH

CRITICAL

1

C2090

10UF

20%
10V

2

X5R-CERM

0402-1

I2C ADDRESS: 1000001X

NET_SPACING_TYPE=PWR

CRITICAL

1

C2094C2092

C2091

10UF

10UF

20%

20%

10V

10V

2

X5R-CERM

X5R-CERM

0402-1

0402-1

A2
B2

D5

A7

A6

D7

C7
E7

E6

F6

F7

E5

A1

SW

SDA

SCL

INT*

RESET*

ALIVE

ADO

MCLK

SCLK

LRCK/FSYNC

SDIN

SDOUT

B3

A3

B1

D1D6A4

C1

VBST

U2040

CS35L19B-CWZR/C0

WLCSP

GNDP

B4

C4

C3

D3

I2C ADDRESS: 1000000X

NET_SPACING_TYPE=PWR

CRITICAL

1

C2095

10UF

20%
10V

2

X5R-CERM

0402-1

A2
B2

D5

A7

A6

D7

C7
E7

E6

F6

F7

E5

A1

SW

SDA

SCL

INT*

RESET*

ALIVE

ADO

MCLK

SCLK

LRCK/FSYNC

SDIN

SDOUT

A3

B3

B1

D1D6A4

C1

VBST

U2050

CS35L19B-CWZR/C0

WLCSP

GNDP

B4

D3

C4

C3

VER1

D4

VER1

D4

=PP1V7_VA_VCP

1

C2046

0.1UF

10%

6.3V

2

F5

A5

VA

VP

F2

FILT+

C5

LDO_FILT

E3

VSENSE-

E2

VSENSE+

F1

ISENSE-

E1

ISENSE+

D2

OUT+

C2

OUT-

B7

IREF+

GNDA

B5

B6

F4

F3

C6

E4

CERM-X5R
0201

L19_R_FILT
L19_R_LDO_FILT

SPKR_R_SES_N
SPKR_R_SES_P

SPKR_R_P

L19_R_IREF

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

1

R2041

44.2K

1%
1/20W
MF
201

2

=PP1V7_VA_VCP

1

C2056

0.1UF

10%

6.3V

2

F5

A5

VA

VP

F2

FILT+

C5

LDO_FILT

E3

VSENSE-

E2

VSENSE+

F1

ISENSE-

E1

ISENSE+

D2

OUT+

C2

OUT-

B7

IREF+

GNDA

w w w . c h i n a f i x . c o m

B5

B6

F4

F3

C6

E4

CERM-X5R
0201

L19_L_FILT
L19_L_LDO_FILT

SPKR_L_SES_N
SPKR_L_SES_P

SPKR_L_P

L19_L_IREF

MIN_LINE_WIDTH=0.5 MM

1

MIN_NECK_WIDTH=0.2 MM

R2051

44.2K

1%
1/20W
MF
201

2

CRITICAL

C2047

4.7UF

1 2

20%

6.3V

CRITICAL

C2048

4.7UF

1 2

20%

6.3V

SM

XW2040

R2040

SIGNAL_MODEL=EMPTY

SPKR_R_CONN_N

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

CRITICAL

C2057

4.7UF

1 2

20%

6.3V

CRITICAL

C2058

4.7UF

1 2

20%

6.3V

SM

XW2050

R2050

SIGNAL_MODEL=EMPTY

1 2

X5R-CERM1

402

X5R-CERM1

402

CRITICAL

0.100

1 2

1%

1/4W

MF

0402

15 16 54

X5R-CERM1

402

X5R-CERM1

402

CRITICAL

0.100

1%

1/4W

MF

0402

SM

XW2041

SIGNAL_MODEL=EMPTY

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

SM

XW2051

SIGNAL_MODEL=EMPTY

MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM

SPKR_R_VSENSE_N

16

SPKR_R_VSENSE_P

16

SPKR_R_CONN_P

SPKR_L_VSENSE_N

16

SPKR_L_VSENSE_P

16

SPKR_L_CONN_P

SPKR_R_CONN_P

SPKR_R_VSENSE_P

16

SPKR_R_CONN_N

SPKR_R_VSENSE_N

16

SPKR_L_CONN_P

SPKR_L_VSENSE_P

16

SPKR_L_CONN_N

SPKR_L_VSENSE_N

16

SPEAKER CONNECTOR

XW2074

SM

SIGNAL_MODEL=EMPTY

1 2

XW2075

SM

SIGNAL_MODEL=EMPTY

1 2

XW2076

SM

SIGNAL_MODEL=EMPTY

1 2

XW2077

SM

SIGNAL_MODEL=EMPTY

1 2

PLACE XWS CLOSE TO CONNECTOR

UPDATED: DEC 13

1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN
REMOVED BASED ON PERFORMANCE ON J65

2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0
BY MARCH 2013. C0 FIXES PROCESS ISSUES.

16 43 52 16 43

52
16 43

16 43 52

52

16 43 52 16 43

52

16 43 52 16 43

52

D

C

B

A

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

SPKR_L_CONN_N

6 3

SYNC_MASTER=KAVITHA

PAGE TITLE

AUDIO: CS35L19A AMPS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/18/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

20 OF 121

SHEET

4 OF 4

16 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

D

D

BUTTON CONNECTOR

(MOVED HERE TO SUPPORT COST FORMAT)

(REF DES PRESERVED FOR LAYOUT)

L2960

GPIO_BTN_VOL_DOWN_L

5

GPIO_BTN_VOL_UP_L

C

5

GPIO_BTN_SRL_L

5

48

GPIO_BTN_ONOFF_L

5

48

240-OHM-0.2A-0.8-OHM

240-OHM-0.2A-0.8-OHM

240-OHM-0.2A-0.8-OHM

240-OHM-0.2A-0.8-OHM

0201-2

L2961

0201-2

L2962

0201-2

L2963

0201-2

21

21

21

21

GPIO_BTN_VOL_DOWN_R_L

GPIO_BTN_VOL_UP_R_L

GPIO_BTN_SRL_R_L

GPIO_BTN_ONOFF_R_L

1

2

C2960

82PF

5%
25V
CERM
0201

R2900

1.00K

1 2

1%

1/32W

MF

01005

1

2

C2961

82PF

R2901

1.00K

1 2

1%

1/32W

MF

01005

5%
25V
CERM
0201

1

2

R2902

1.00K

1 2

C2962

82PF

5%
25V
CERM
0201

1/32W
01005

52

GPIO_BTN_VOL_DOWN_L_FILT
GPIO_BTN_VOL_UP_L_FILT

52

52

GPIO_BTN_SRL_L_FILT

1%
MF

1

C2963

2

R2903

1.00K

1 2

82PF

5%
25V
CERM
0201

1%

1/32W

MF

01005

DZ2960

201-1

12.8V-100PF

2

12.8V-100PF

1

DZ2961

201-1

12.8V-100PF

2

1

DZ2962

201-1

2

1

DZ2963

201-1

12.8V-100PF

GPIO_BTN_ONOFF_L_FILT

52

2

1

516S0828

CRITICAL

J2960

503548-1010

F-ST-SM

11 12

1

2

3

4

5

6
8

7

10

9

13

14

C

B

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=N/A

PAGE TITLE

BUTTON: CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

21 OF 121

SHEET

17 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

EDP CONNECTOR SUPPORT

=PPVCC_MAIN_LCD

54

D

GPIO_SOC2LCD_PWREN

5

18

IN

1

R2205

100K

5%
1/32W
MF
01005

2

LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION

1

C2240

0.1UF

10%
16V

2

X5R-CERM
0201

U2200

SLG5AP304V

C2241

3900PF

10%
50V
X7R
0402

7

CAP

CRITICAL

LCD_RAMP

1

2

REVIEW: 4700PF 0201 132S0187
RDAR://PROBLEM/12579948

VDD

TDFN

GND

1

C2239

0.1UF

10%
16V

2

OMIT

X5R-CERM
0201

CRITICAL

3

D

52

SON

8 1

PPVCC_MAIN_LCD_SW

1

C2203

0.1UF

10%
16V

2

X5R-CERM
0201

CRITICAL

1

C2202

10UF

20%

6.3V

2

CERM-X5R
0402

L2201

FERR-120-OHM-1.5A

1

C2230

82PF

5%
25V

2

CERM
0201

0402A

21

PPVCC_MAIN_LCD_SW_CONN

1

C2232

15PF

5%
16V

2

NP0-C0G-CERM
01005

GPIO_SOC2LCD_PWREN

5

18

OUT

18 52

LCM_PWR_EN_RES

R2291

1 2

0.00

1/32W
01005

0%
MF

LCM_OFF_L

18

PPVCC_MAIN_LCD_SW_CONN

18 52

IN

PART NUMBER

155S0667 155S0583

BACK-UP DELAYED PWREN CKT

=PP1V8_SOC

4 5 7

CRITICAL

L2200

C

=PPLED_REG_A

54 18 52

220-OHM-1A

0402

21

1

C2233

8.2PF

+/-0.5PF
50V

2

C0G-CERM
201

PPLED_BACK_REG_A

1

C2221

56PF

2%
50V

2

NP0-C0G-CERM
0201

10 54

5

18

IN

LCM_PWR_EN_OR_GATE

1

C2270

0.1UF

20%

6.3V

2

X5R-CERM
01005

GPIO_SOC2LCD_PWREN

NC_U2201_5

LCM_PWR_EN_OR_GATE

6

2

U2201

1

NC

CRITICAL

74LVC1G32

SOT891

4

35

GATE2LCD_PWREN

LCM_PWR_EN_OR_GATE

R2290

1 2

0.00

0%

1/32W

MF

01005

LED_IO_6_A

47

IN

LED_IO_5_A

47

IN

LED_IO_4_A

47

IN

LED_IO_3_A

47

IN

LED_IO_2_A

47

IN

LED_IO_1_A

47

IN

PPLED_BACK_REG_A

18 52

IN

ALTERNATE FOR
PART NUMBER

BOM OPTION

REF DES

COMMENTS:

L2242,L2810,L2811,L2812,L2813,L2814,L2710,L2711,L2712,L6030,L6031

RDAR://PROBLEM/8616060, RADAR://PROBLEM/9015335

P/N 516S1056

CRITICAL

J2201

AA07A-S032-VA1

F-ST-SM-1

3334

2

1
3

4
6

5
7

8
10
12
14
16
18
20
22
24
26
28
30
32

9
11
13
15
17
19
21
23
25
27
29
31

3536

EDP_DATA_EMI_CONN_N<3>EDP_HPD_EMI
EDP_DATA_EMI_CONN_P<3>

EDP_DATA_EMI_CONN_N<2>
EDP_DATA_EMI_CONN_P<2>

EDP_DATA_EMI_CONN_N<1>
EDP_DATA_EMI_CONN_P<1>

EDP_DATA_EMI_CONN_N<0>
EDP_DATA_EMI_CONN_P<0>

TABLE_ALT_HEAD

TABLE_ALT_ITEM

EDP_AUX_EMI_CONN_N
EDP_AUX_EMI_CONN_P

D

18 53

IN

18 53

IN

18 53

IN

18 53

IN

18 53

IN

18 53

IN

18 53

IN

18 53

IN

18

IN

18

IN

C

REVIEW: CAN/SHOULD WE USE 132S0316, 0.1UF 20%, 01005
RDAR://PROBLEM/12579963

7

7

IN

IN

EDP_AUX_P

EDP_AUX_N

C2250

01005

C2251

01005

B

7

53

7

53

7

53

7

53

7

53

7

53

EDP_DATA_P<0>

IN

EDP_DATA_N<0>

IN

EDP_DATA_N<1>

IN

EDP_DATA_P<1>

IN

EDP_DATA_N<2>

IN

EDP_DATA_P<2>

IN

C2242

01005

C2243

01005

C2244

01005

C2245

01005

C2246

01005

C2247

01005

A

7

53

7

53

EDP_DATA_N<3>

IN

EDP_DATA_P<3>

IN

C2248

01005

C2249

01005

0.1UF

1 2

6.3V X5R-CERM

20%

0.1UF

1 2

6.3V

6.3V X5R-CERM

6.3V X5R-CERM

6.3V

6.3V X5R-CERM

6.3V X5R-CERM

6.3V X5R-CERM

6.3V X5R-CERM

6.3V X5R-CERM

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

20%

0.1UF

20%

0.1UF

20%

0.1UF

20%

0.1UF

20%

0.1UF

20%

0.1UF

20%

20%

20%

X5R-CERM

X5R-CERM

0.1UF

0.1UF

EDP_AUX_EMI_P

EDP_AUX_EMI_N

EDP_DATA_EMI_P<0>

53

EDP_DATA_EMI_N<0>

53

EDP_DATA_EMI_N<1>

53

EDP_DATA_EMI_P<1>

53

EDP_DATA_EMI_N<2>

53

EDP_DATA_EMI_P<2>

53

EDP_DATA_EMI_N<3>

53

EDP_DATA_EMI_P<3>

53

1

R2241

100K

5%
1/32W
MF
01005

2

1

R2243

100K

5%
1/32W
MF
01005

2

CRITICAL

L2212

1

SYM_VER-2

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

CRITICAL

L2222

1

SYM_VER-2

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

CRITICAL

L2232

1

SYM_VER-2

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

CRITICAL

L2202

1

SYM_VER-2

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

32

4

32

4

32

4

32

4

EDP_DATA_EMI_CONN_P<0>

EDP_DATA_EMI_CONN_N<0>

EDP_DATA_EMI_CONN_N<1>

EDP_DATA_EMI_CONN_P<1>

w w w . c h i n a f i x . c o m

EDP_DATA_EMI_CONN_N<2>

EDP_DATA_EMI_CONN_P<2>

EDP_DATA_EMI_CONN_N<3>

EDP_DATA_EMI_CONN_P<3>

6 3

CRITICAL

L2242

1

SYM_VER-2

TAM0605-4SM

3.25-OHM-0.1A-2.4GHZ

EDP_AUX_EMI_CONN_P

32

4

EDP_AUX_EMI_CONN_N

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

18 53

OUT

REVIEW: WILL THE DISPLAY INCLUDE A VOLTAGE DIVIDER

18

OUT

18

OUT

TO REDUCE THE 2.5V FROM THE TCON TO 1.8V TO THE AP?
RDAR://PROBLEM/12579981

L2240

18

240-OHM-25%-0.20A-1.0DCR

1

C2260

27PF

5%
16V

2

NP0-C0G
01005

01005

21

R2250

7.5K

EDP_HPD_2P5EDP_HPD_EMI

1 2

5%

1/32W

MF

01005

NOTE:
PER GREG DE MERCEY, EDP_HPD PIN IS 2.5V TOLERANT

HOWEVER TO BE CONSERVATIVE, DIVIDER CKT IS NOT REMOVED

SYNC_MASTER=J85 MLB_C

PAGE TITLE

1

R2242

20.0K

5%
1/32W
MF
01005

2

EDP_HPD

OUT

VIDEO: EDP SUPPORT & CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

7

SYNC_DATE=12/05/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

22 OF 121

SHEET

18 OF 54

SIZE

B

A

D

124578

8 7 6 5 4 3

12

D

GPIO_OSCAR_RESET_L

5

IN

OSCAR VDDIO = 1.8V HIBERNATE (NEED TO WAKE HOST)
OSCAR CORE = 1.2V HIBERNATE (NEED TO RUN IN S2R)

REVIEW:NEED PU ON CS?
RDAR://PROBLEM/12579997

=PP1V8_S2R_OSCAR

19 54

1

R2400

100K

5%
1/32W
MF
01005

2

SPI_OSCAR2ACCEL_CS_L

21

OUT

SPI_OSCAR2GYRO_CS_L

21

OUT

ACCEL2OSCAR_INT1

21

IN

GYRO2OSCAR_INT2

21

IN

GYRO2OSCAR_INT1

21

IN

ACCEL2OSCAR_INT2

21

IN

COMPASS2OSCAR_INT

21

IN

SPI_OSCAR2COMPASS_CS_L

21

OUT

OSCAR_TIME_SYNC_HOST_INT

5

OUT

PMU_GPIO_OSCAR2PMU_HOST_WAKE

5

48

OUT

NC_ISP0_CAM_REAR_SDA

=PP1V2_S2R_OSCAR

54 19 54

1

C2400

1.0UF

20%

6.3V

2

X5R

0201-1

C

REVIEW: N51 HAS OSCAR I2C CONNECTED TO RF CAM I2C
COMPARE SENSOR CONNECTIONS WITH N51, IDENTIFY AND UNDERSTAND DIFFERENCES
RDAR://PROBLEM/12580012

OSCAR

APN 337S4416

C1C2C6

VDDC

VDDC

CRITICAL

U2400

LPC18A1UK-CPA1

E3

P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P0_8
P0_9
P0_10

RESET*

WLCSP

VSS

B1

VSS

D6

E5
E6
C5
D5
E2
D3
D4
E1
A3
A2

E4

VDDIO

P0_11
P0_12
P0_13
P0_14
P0_15
P0_16
P0_17
P0_18
P0_19
P0_20
P0_21
P0_22

DBGEN

=PP1V8_S2R_OSCAR

1

C2401

1.0UF

20%

6.3V

2

X5R

0201-1

A1

NC_ISP0_CAM_REAR_SCL

B2

SPI_OSCAR_SCLK_R

A4

SPI_OSCAR_MISO

B3

SPI_OSCAR_MOSI_R

B4

UART4_OSCAR2SOC_RXD

A5

UART4_SOC2OSCAR_TXD

B5

OSCAR2RADIO_CONTEXT_A

C3

OSCAR2RADIO_CONTEXT_B

C4

I2C1_SOC2OSCAR_SWDIO_1V8

B6

I2C1_SOC2OSCAR_SWDCLK_1V8

D1

PMU_GPIO_CLK_32K_OSCAR

A6

TP_OSCAR_P0_22

D2

GPIO_SOC2OSCAR_DBGEN_R

21

IN

5

OUT

5

IN

28 44 52

OUT

28 44 52

OUT

5

BI

5

IN

48 52

IN

R2450

0.00

1 2

0%

1/32W

MF

01005

53

53

GPIO_SOC2OSCAR_DBGEN

R2405

15.0

1 2

5%

1/32W

MF

01005

R2406

15.0

1 2

5%

1/32W

MF

01005

NOTE: I2C1 IS ASSUMED TO USE PUSH-PULL INSTEAD OF OPEN-DRAIN

SPI_OSCAR_SCLK

SPI_OSCAR_MOSI

5

IN

21

OUT

21

IN

D

C

B

B

w w w . c h i n a f i x . c o m

A

6 3

SYNC_MASTER=J72_MLB_C

PAGE TITLE

SENSOR: OSCAR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

24 OF 121

SHEET

19 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

VGA FRONT CAMERA CONNECTOR

12

D

=PP2V9_CAM_FRONT

54

L2601

=PP1V8_CAM_FRONT

54

240OHM-350MA

0201

L2600

240OHM-350MA

0201

XW2600

SM

1 2

21

1

C2603

56PF

5%
16V

2

NP0-C0G
01005

21

C2604

1UF

20%

6.3V
X5R
0201

1

C2601

1UF

20%

6.3V

2

X5R
0201

1

2

C2605

1000PF

10%

6.3V
X5R-CERM
01005

1

C2600

56PF

5%
16V

2

NP0-C0G
01005

1

2

PP2V9_AVDD_CAM_FRONT_FILT

1

C2602

1000PF

10%

6.3V

2

X5R-CERM
01005

VOLTAGE=2.9V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

GND_AVDD_CAM_FRONT

VOLTAGE=0V
MIN_LINE_WIDTH=0.15 MM
MIN_NECK_WIDTH=0.15 MM
NET_SPACING_TYPE=GND

PP1V8_CAM_FRONT_FILT

20

MIPI1C_CAM_FRONT_CLK_FILT_P

20

20

20 53

MIPI1C_CAM_FRONT_CLK_FILT_N

20 53

MIPI1C_CAM_FRONT_DATA_FILT_P<0>

20 53

MIPI1C_CAM_FRONT_DATA_FILT_N<0>

20 53

150OHM-25%-200MA-0.7DCR

ISP1_CAM_FRONT_CLK_F_R

20 20

L2610

1

TCM0605-1

90-OHM-50MA

L2611

1

90-OHM-50MA

L2660

SYM_VER-2

SYM_VER-2

TCM0605-1

01005

32

4

32

4

21

ISP1_CAM_FRONT_CLK_F

MIPI1C_CAM_FRONT_CLK_P

MIPI1C_CAM_FRONT_CLK_N

MIPI1C_CAM_FRONT_DATA_P<0>

MIPI1C_CAM_FRONT_DATA_N<0>

7

53

OUT

7

53

OUT

7

53

OUT

7

53

OUT

C

L2602

7

52

BI

7

52

IN

5

22

BI

7

52

IN

240-OHM-0.2A-0.8-OHM

ISP1_CAM_FRONT_SDA
ISP1_CAM_FRONT_SCL

I2C3_SDA_1V8

ISP1_CAM_FRONT_CLK

0201-2

21

1

C2606

56PF

5%
16V

2

NP0-C0G
01005

1

C2607

1UF

20%

6.3V

2

X5R
0201

U2600

400MHZ-0.1A-27PF

IN1
IN2
IN3
IN4

1208

GND

1

C2608

1000PF

10%

6.3V

2

X5R-CERM
01005

OUT1
OUT2
OUT3
OUT4

PP3V0_ALS_FILT

ISP1_CAM_FRONT_SDA_F

ISP1_CAM_FRONT_SCL_F

I2C3_SDA_1V8_F

ISP1_CAM_FRONT_CLK_F

20

I2C3_SCL_1V8_F I2C3_SDA_1V8_F

20 20

GPIO_ALS_IRQ_L_F

20

PP3V0_ALS_FILT

20

MIPI1C_CAM_FRONT_DATA_FILT_P<0>

20 53

MIPI1C_CAM_FRONT_DATA_FILT_N<0>

20 53

MIPI1C_CAM_FRONT_CLK_FILT_P

20 53

MIPI1C_CAM_FRONT_CLK_FILT_N

20 53

20

20

20

20

=PP3V0_ALS

54

B

516S0869 PLUG FLEX

516S0876 RCPT MLB

CRITICAL

J2601

503548-1820

F-ST-SM

1920

12
3

4

5

6
8

7
9

10

11

12
14

13
15

16
18

17

21

22

ISP1_CAM_FRONT_CLK_F_R

ISP1_CAM_FRONT_SHUTDOWN_L_F

ISP1_CAM_FRONT_SDA_F
ISP1_CAM_FRONT_SCL_F

PP2V9_AVDD_CAM_FRONT_FILT

GND_AVDD_CAM_FRONT

PP1V8_CAM_FRONT_FILT

20

20

20

20

20

20

20

D

C

B

U2601

400MHZ-0.1A-27PF

1208

I2C3_SCL_1V8

5

22

IN

GPIO_ALS_IRQ_L

5

OUT

ISP1_CAM_FRONT_SHUTDOWN_L

7

52

IN

IN1
IN2
IN3
IN4

GND

OUT1
OUT2
OUT3
OUT4

A

NC_U2601_5NC_U2601_1

ISP1_CAM_FRONT_SHUTDOWN_L_F

1

R2601

100K

1%
1/32W
MF
01005

2

I2C3_SCL_1V8_F

w w w . c h i n a f i x . c o m

GPIO_ALS_IRQ_L_F

20

20

20

ISP1_CAM_FRONT_SHUTDOWN_L
LOW = SHUT DOWN CAMERA

HIGH = TURN ON CAMERA

6 3

SYNC_MASTER=J85 MLB_C

PAGE TITLE

CAMERA: FF-ALS CONN & FILTERS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/03/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

26 OF 121

SHEET

20 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

GYRO

1

R2750

0.00

0%
1/32W
MF
01005

2

L2702

01005

21

PP3V0_GYRO

1

C2721

0.1UF

20%

6.3V

2

X5R-CERM
01005

SPI_OSCAR2GYRO_CS_L

19

IN

GYRO2OSCAR_INT2

19

OUT

GYRO_DEN

GYRO2OSCAR_INT1

19

OUT

1

C2723

10UF

20%

6.3V

2

CERM-X5R
0402-2

CKPLUS_WAIVE=PWRTERM2GND

GYRO_RES_VDD

5
6
8

7

16

15

RES/VDD

U2720

AP3GDL20HAB18TR

CS
DRDY/

SDA/SDI/SDO

INT2

DEN

INT1

VDD

1

VDD_IO

CRITICAL

LGA

SCL/SPC

SDO/SA0

GND

GND

13

12

=PP1V8_S2R_GYRO

C2725

0.1UF

X5R-CERM

OMIT

2
3
4

SPI_OSCAR_MISO_GYRO

9

RES0

10

RES1

11

RES2

14

GYRO_PUMP

CAP

11V CHARGE PUMP

1

20%

6.3V
2

01005

SPI_OSCAR_SCLK
SPI_OSCAR_MOSI

1

2

OMIT

C2726

0.1UF

10%
16V
X5R-CERM
0201

54

D

19 21

IN
IN

19 21

R2727

0.00

1 2

0%

1/32W

MF

01005

SPI_OSCAR_MISO

19 21

C

=PP3V0_S2R_GYRO

54

ACCELEROMETER

120-OHM-25%-250MA-0.5DCR

D

=PP3V0_S2R_ACCEL

54

120-OHM-25%-250MA-0.5DCR

C

L2700

01005

SPI_OSCAR2ACCEL_CS_L

19

IN

ACCEL2OSCAR_INT1

19

OUT

ACCEL2OSCAR_INT2

19

OUT

C2700

10UF

6.3V

CERM-X5R

0402-2

20%

C2701

0.1UF

6.3V

X5R-CERM

01005

PP3V0_ACCEL

1

20%

2

4

CS

14

RES

13

RES

12

RES

6

INT1

5

INT2

8

7

VDD

VDD_IO

CRITICAL

U2700

AP2DHAB26TR

LGA

SCL/SPC

SDA/SDI/SDO

SDO/SA0

GND

9

=PP1V8_S2R_ACCEL

OMIT

1
2
3

10

RES

11

RES

1

C2750

0.1UF

20%

6.3V
2

X5R-CERM

01005

SPI_OSCAR_SCLK
SPI_OSCAR_MOSI
SPI_OSCAR_MISO_ACCEL

54

19 21

IN
IN

19 21

R2757

0.00

1 2

0%

1/32W

MF

01005

SPI_OSCAR_MISO

19 21

21

1

2

B

COMPASS

B

APN 338S1014

=PP3V0_S2R_COMP

54

A

120-OHM-25%-250MA-0.5DCR

L2701

21

01005

NC_COMPASS_TST1

w w w . c h i n a f i x . c o m

NC_COMPASS_RSV

NC_COMPASS_TRG

PP3V0_COMP

C2710

1.0UF

6.3V

0201-1

GND_COMP

21

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

PP1V8_COMP

21

TO VID WHEN NOT USED

20%
X5R

1

2

D1
D2

C2

B3 B4

C3

D4

GND_COMP

21

B1

VDD

CRITICAL

U2710

AK8963C

CSP

CAD0
CAD1

TST1

RSV SO

TRG

RST*

VSS

C1

C4

VID

SCL/SK
SDA/SI

CSB*

DRDY

A3
A4

A2

A1

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

21

1

C2711

0.1UF

20%

6.3V

2

X5R-CERM
01005

GND_COMP

SPI_OSCAR_SCLK
SPI_OSCAR_MOSI

SPI_OSCAR2COMPASS_CS_L

SPI_OSCAR_MISO_COMP1

COMPASS2OSCAR_INT

XW2700

21

XW2701

120-OHM-25%-250MA-0.5DCR

PP1V8_COMP

21

6 3

L2741

21

01005

19 21

IN

19 21

IN

19

IN

19

OUT

TIE CSB* TO VID FOR I2C MODE

=PP1V8_S2R_COMP

R2747

15.0

1 2

5%

1/32W

MF

01005

SPI_OSCAR_MISO

54

19 21

OUT

SIZE

A

D

SYNC_MASTER=N/A

PAGE TITLE

SENSOR: ACCEL, COMPASS, GYRO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=N/A

051-0886

A.0.0

27 OF 121

21 OF 54

124578

8 7 6 5 4 3

PROX SENSOR

12

D

=PP1V8_PROX

22 54

PROX

=PP3V0_PROX

54

240-OHM-0.2A-0.8-OHM

C

I2C3_SDA_1V8

5

20

BI

I2C3_SCL_1V8

5

20

IN

GPIO_PROX_IRQ_L

5

OUT

INT* IS OPEN DRAIN PU RAIL MATCH VDRIVE

INT IS 1.8V LEVEL.

PROX GPIO WILL NOT BE USED.

THEREFORE,PROX GPIO IS NOT

CONNECTED TO MLB INTERCONNECT.

L2800

2 1

=PP1V8_PROX

22 54

0201-2

PROX

C2802

0.01UF

X5R-CERM

0201

10%
10V

PROX

C2800

2.2UF

6.3V

1

2

10%
X5R

402

PROX

R2800

2.0K

1/32W
01005

1%
MF

C2807

NP0-C0G

PROX

1

C2804

0.1UF

20%

6.3V
2

X5R-CERM

01005

PP3V0_SENSOR_PROX_FILT

PROX

1

2

1

2

PROX

27PF

1%

25V
201

C2801

0.1UF

X5R-CERM

1

2

6.3V

01005

1

20%

2

PROX

R2801

100K

1/32W
01005

C2805

68PF

NP0-C0G

C2806

68PF

NP0-C0G

PROX_BIAS

PROX_GPIO PROX_CIN9

1

1%
MF

2

VDRIVE FOR: I2C AND GPIO

PROX

1

5%

6.3V
2

01005

PROX

1

5%

6.3V
2

01005

1.8 MA MAX

I2C ADDRESS: 0101100+R/W

READ: 0X59, WRITE: 0X58

C2

D2

PROX

VDRIVE

VCC

U2800

AD7149

BIAS

SDA

SCLK

ADD0

ADD1

INT*

GPIO

TP

WLCSP

353S2964

CRITICAL

VDRIVE RAIL

ACSHIELD

E4

GND

D3

CIN0

NC

A3
B3
A4
C3
A5
B4
B5
C4
C5
D4
D5
E5

PROX_CIN1

TP_PROX_CIN2

NC
NC
NC
NC

PROX_CIN7

NC

NC
NC
NC

PROX

C2803

0.5PF

+/-0.05PF

CERM

1

25V

2

201

JUST IN CASE

NEED EXTERNAL

REF CAP TO MEASURE

CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8

CIN9
CIN10
CIN11
CIN12

E2

E3

E1

C1

D1

B1

A1

A2

B2

NC

390NH-2%-170MA-4.0OHM

390NH-2%-170MA-4.0OHM

0.5 PF

PROX

CRITICAL

L2802

2 1

0603

PROX

CRITICAL

L2804

0603

PROX

CRITICAL

68NH-2%-320MA-1.0OHM

CIN9

68NH-2%-320MA-1.0OHM

CIN7

L2801

2 1

0402

PROX

CRITICAL

L2803

2 12 1

0402

CIN9 SENSOR ELECTRODE

CIN7 DUMMY

A PLANE UNDER PROX_CIN NETS

AND ALSO TIE TO CONNECTOR.

PROX_CIN9_CONN
PROX_CIN7_CONN
PROX_ACSHIELD_CONN

PCB: ACSHIELD NEEDS TO BE

516S0872

PROX

CRITICAL

J2800

503548-0620

F-ST-SM

7

3 4
5 6

9

8

21

NC_J2800_2
NC_J2800_4
NC_J2800_6

10

D

C

B

ACSHIELD_SB

PROX

CRITICAL

390NH-2%-170MA-4.0OHM

L2808

0603

68NH-2%-320MA-1.0OHM

ACSH_SB

2 12 1

PROX

CRITICAL

L2807

0402

CHOSE CIN NUMBERS FOR LAYOUT EASE

B

PCB: ENSURE ACSHIELD PLANE UNDER

U3200, NO GND PLANE NEAR PROX_CIN NETS..

w w w . c h i n a f i x . c o m

A

6 3

SYNC_MASTER=J85 MLB_C

PAGE TITLE

SENSOR: PROX

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/05/12

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

28 OF 121

SHEET

22 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

REAR CAMERA CONNECTOR

12

D

=PP1V8_CAM_REAR

54

1

C2972

56PF

5%
16V

2

NP0-C0G
01005

=PP1V3_CAM_REAR

54

1

C2973

56PF

5%
16V

2

NP0-C0G
01005

=PP2V9_CAM_REAR

C

54

=PP2V6_CAM_REAR_AF

54

1

C2970

56PF

5%
16V

2

NP0-C0G
01005

1

C2971

56PF

5%
16V

2

NP0-C0G
01005

L2902

240OHM-350MA

0201

L2903

240OHM-350MA

0201

L2900

240OHM-350MA

0201

XW2950

SM

1 2

L2901

240OHM-350MA

0201

XW2951

SM

1 2

21

1

C2906

56PF

16V

2

NP0-C0G
01005

21

1

C2909

56PF

5%
16V

2

NP0-C0G
01005

21

1

C2900

56PF

5%
16V

2

NP0-C0G
01005

21

1

C2903

56PF

5%
16V

2

NP0-C0G
01005

1

2

1

C2910

2

1

1UF

10%
10V

2

X5R
402

1

1UF

10%
10V

2

X5R
402

C2907

1UF

10%5%
10V
X5R
402

1UF

10%
10V
X5R
402

1

2

1

C2911

1000PF

2

1

C2902C2901

1000PF

10%

6.3V

2

X5R-CERM
01005

1

C2905C2904

1000PF

10%

6.3V

2

X5R-CERM
01005

C2908

1000PF

10%

6.3V
X5R-CERM
01005

10%

6.3V
X5R-CERM
01005

PP1V8_CAM_REAR_FILT

PP1V3_CAM_REAR_FILT

PP2V9_AVDD_CAM_REAR_FILT

VOLTAGE=2.9V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=GND

MAX_NECK_LENGTH=5 MM

PP2V6_CAM_REAR_AF_FILT

VOLTAGE=2.6V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR

MAX_NECK_LENGTH=3 MM

VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=GND

MAX_NECK_LENGTH=5 MM

ISP0_CAM_REAR_SCL

7

52

IN

ISP0_CAM_REAR_SDA

7

52

BI

ISP0_CAM_REAR_SHUTDOWN_L

7

52

IN

1

R2950

100K

1%
1/32W
MF
01005

2

CAM_REAR_VSYNC

GND_CAM_AVDD

GND_AF_AVDD

APN: 516S0973

PLUG: 516S0974

AA07-S022VA1

1

C2980

1000PF

10%

6.3V

2

X5R-CERM
01005

CRITICAL

J2950

F-ST-SM

24
23

1
3
5
7

9
11
13
15
17
19
21

25
26

ISP0_CAM_REAR_CLK_F

150OHM-25%-200MA-0.7DCR

2
4
6
8
10
12
14
16
18
20
22

MIPI0C_CAM_REAR_DATA_FILT_P<0>

53

MIPI0C_CAM_REAR_DATA_FILT_N<0>

53

MIPI0C_CAM_REAR_CLK_FILT_P

53

MIPI0C_CAM_REAR_CLK_FILT_N

53

MIPI0C_CAM_REAR_DATA_FILT_P<1>

53

MIPI0C_CAM_REAR_DATA_FILT_N<1>

53

L2950

01005

L2911

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

L2910

2

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

L2912

1

SYM_VER-2

TCM0605-1

90-OHM-50MA

21

32

MIPI0C_CAM_REAR_DATA_P<0>

4

MIPI0C_CAM_REAR_DATA_N<0>

3

4

32

MIPI0C_CAM_REAR_DATA_P<1>

4

MIPI0C_CAM_REAR_DATA_N<1>

ISP0_CAM_REAR_CLK

MIPI0C_CAM_REAR_CLK_P

MIPI0C_CAM_REAR_CLK_N

7

52

IN

7

53

OUT

7

53

OUT

7

53

OUT

7

53

OUT

7

53

OUT

7

53

OUT

D

C

B

B

w w w . c h i n a f i x . c o m

A

6 3

SYNC_MASTER=N/A

PAGE TITLE

CAMERA: REAR CONN & FILTERS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=N/A

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

29 OF 121

SHEET

23 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

AP INTERFACE & DEBUG CONNECTORS

D

PROBE POINTS

PP3000

P4MM

SM

BB_ERROR_FLAG

1

PP

PP3001

P4MM

SM

SLEEP_CLK_32K

1

PP

PP3002

P4MM

SM

PMIC_SSBI

1

PP

PP3003

P4MM

SM

19P2M_MDM

1

PP

PP3008

P4MM

SM

WTR_SSBI_TX_GPS

1

PP

C

PP3009

P4MM

SM

WTR_SSBI_PRX_DRX

1

PP

PP3010

P4MM

SM

WTR_RX_ON

1

PP

PP3011

P4MM

SM

WTR_RF_ON

1

PP

PP3012

P4MM

SM

UART_WLAN2BB_LTE_COEX

1

PP

PP3013

P4MM

SM

UART_BB2WLAN_LTE_COEX

1

PP

28

26 27

26 27

26 27

28 29

28 29

28 29

28 29

28 44

28 44

11 52 53

BI

27

27

11 52 53

BI

USB_BB_N

USB_BB_DEBUG_N

BI

USB_BB_DEBUG_P

BI

USB_BB_P

XW3002

SHORT-10L-0.25MM-SM

21

NOSTUFF

XW3003

SHORT-10L-0.25MM-SM

21

NOSTUFF

LAT_SW1_CTL

14 24 28 52

ANT_SEL_1

24 28 33 39 40

26 52

26 52

26 48 52

26 27

27 52

27 52

27 52

27 52

27 52

27 52

27 52

14 24 28 52

28 39 40

28 48 52

24 28 33 39 40

28

PP_SMPS3_MSME_1V8

NOSTUFF

NOSTUFF

1

1

R3002

R3003

10K

10K

5%

5%

1/32W

1/32W

MF

MF

01005

01005

2

2

GPIO48/BOOT_CONFIG_6
GPIO53/BOOT_CONFIG_1

PS_HOLD_PMIC

OUT

GPIO_SOC2BB_RADIO_ON_L

5

OUT

PMU_GPIO_PMU2BBPMU_RST_L

OUT

PMIC_RESOUT_L

IN

DEBUG_RST_L

OUT

BB_JTAG_TMS

5

OUT

BB_JTAG_TRST_L

5

OUT

BB_JTAG_TCK

5

OUT

BB_JTAG_TDO

5

IN

BB_JTAG_TDI

5

OUT

BB_JTAG_RTCLK

OUT

LAT_SW1_CTL

OUT

ANT_SEL_2

OUT

PMU_GPIO_BB2PMU_HOST_WAKE

IN

ANT_SEL_1

OUT

GPIO_51

OUT

24 25 27 28 30 52

GPIO48/BOOT_CONFIG_6

GPIO54/BOOT_CONFIG_0

GPIO53/BOOT_CONFIG_1
GPIO51/BOOT_CONFIG_3

DEBUG CONNECTOR

NOSTUFF

J3003

AXE654124

M-ST-SM

55

56

1

2
4

3

6

5

8

7
9

10

11

12

13

14

15

16
18

17
19

20
22

21

24

23
25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50
52

51

54

53

58 57

BOOT_CONFIG

BOOT OPTIONS

BOOT_DEFAULT_OPTION

BOOT_NAND_OPTION

BOOT_HSIC_OPTION

BOOT_USB_OPTION 0X03

ENABLE SAHARA PROTOCOL

SW REGISTER

VALUE

0X00

0X01

0X02

0X08

=PPBATT_VCC_BB

GPIO_SOC2BB_RST_L

PP_SMPS3_MSME_1V8

RESET_SOC_L

UART3_BB2SOC_TX
GPIO_DEBUG_LED

UART3_SOC2BB_TX
UART3_BB2SOC_RTS_L
UART3_SOC2BB_RTS_L

PMU_GPIO_BB_VBUS_DET

HSIC2_BB2SOC_DEVICE_RDY

GPIO_BB2SOC_RESET_DET_L

HSIC2_SOC2BB_HOST_RDY

GPIO/BOOT_CONFIG CONFIGURATION

6

5

48

47

49

51

52253054

X

0

0340500

1

X

X

1

0

X

1

0

X

1

0 0 1 0 X X X

000

0

000

0

0

25 33 34 35 36 37 38 54

IN

1 0

55

0

X

100

X

0

10

X

1

1

X

5

26 52

OUT

24 25 27 28 30 52

IN

11 48 52
4 8

OUT

CKPLUS_WAIVE=SINGLE_NODENET

10

5

11 28 52

IN

28

IN

5

11 28 52

OUT

5

28

IN

5

28

OUT

27 48 52

OUT

5

28

IN

5

28

IN

5

28

IN

D

C

J3002

MM4829-2702

F-ST-SM

B

PP_LDO6_RUIM_1V8

CELL

1

C3000

12V-33PF

01005-1

2

10 25 27 52

SIMCRD_IO_CONN

10 28 52

SIMCRD_RST_CONN

10 28 52

w w w . c h i n a f i x . c o m

SIM CARD ESD PROTECTION

CELL

U3000

ESD0P2RF-02LS

21

TSSLP-2-1

CELL

U3001

ESD0P2RF-02LS

21

TSSLP-2-1

U3002

ESD0P2RF-02LS

2 1

TSSLP-2-1

U3003

ESD0P2RF-02LS

2 1

TSSLP-2-1

CELL

CELL

SIM_TRAY_DETECT

SIMCRD_CLK_CONN

10 28 52

10 28 52

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

NOSTUFF

423

J3001

MM4829-2702

F-ST-SM

NOSTUFF

423

1

1

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

HSIC2_BB_DATA

HSIC2_BB_STB

CELL:AP INTERFACE & DEBUG CONNECTORS

Apple Inc.

R

4

27 53

4

27 53

DRAWING NUMBER

051-0886

REVISION

BRANCH

PAGE

SHEET

124578

A.0.0

30 OF 121

24 OF 54

SIZE

B

A

D

8 7 6 5 4 3

PMU (1 OF 2)

12

PP_LVS1

27

OUT

PP_VREG

INTERNAL USE ONLY

1

D

2.2UH-20%-1.2A-0.15OHM

REF_BYP

1

C3209

0.1UF

20%

6.3V

XW3200

SHORT-10L-0.1MM-SM

C

B

=PPBATT_VCC_BB

24 33 34 35 36 37 38 54

IN

1

C3200

10UF

20%

6.3V

2

CERM-X5R
0402-2

1

C3201

10UF

20%

6.3V

2

CERM-X5R
0402-2

1

C3202

10UF

20%

6.3V

2

CERM-X5R
0402-2

1

C3203

56PF

5%
16V

2

NP0-C0G
01005

1

C3204

4.7UF

20%
10V

2

X5R-CERM

S1_GND S2_GND S3_GND S4_GND S5_GND

25
26

0402

25
26

1

C3205

4.7UF

20%
10V

2

X5R-CERM
0402

25
26

25 30 52

IN

24 25 27 28 30 52

IN

25 52

IN

1

C3206

4.7UF

20%
10V

2

X5R-CERM
0402

25
26

PP_SMPS4_RF2_2V05
PP_SMPS3_MSME_1V8

1

C3207

4.7UF

20%
10V

2

X5R-CERM
0402

25
26

PP_SMPS5_DSP_1V05

2

X5R-CERM

28

21

01005

REF_GND

1

C3208

4.7UF

20%
10V

2

X5R-CERM
0402

REF_BYP

34

REF_GND

104

VDD_S1

95

VDD_S2

6
18
24

98

VDD_S4

89

101

8

VDD_XO

44

VDD_L2_L3

78

VDD_L4

5

VDD_L5_L6_L13_L14

75

VDD_L7

58

VDD_L8

70

VDD_L9

59

VDD_L10_L11

64

VDD_L12

VDD_S3

VDD_S5

U3300

PM8018-0

BGA

VREG

(SYM 5 OF 5)

CRITICAL

VOUT_LVS1

VREG_RFCLK

VSW_S1

VREG_S1

VSW_S2

VREG_S2

VSW_S3

VSW_S5_2

VREG_S3

VSW_S4

VREG_S4

VSW_S5

VREG_S5

VREG_XO
VREG_L2
VREG_L3
VREG_L4
VREG_L5

VREG_L6
VREG_L13
VREG_L14

VREG_L7

VREG_L8

VREG_L9
VREG_L10
VREG_L11
VREG_L12

53

13

92
97
79
90
102
83
42
48
100
12
81
87
105
82
88
76

20
31
32
84
11
17
23
29
63
54
77
65
55
43

PP_VSW_S1

PP_VSW_S2

PP_VSW_S3

PP_VSW_S4

PP_VSW_S5

1

2

1

C3210

1.0UF

20%

6.3V

2

X5R
0201-1

C3211

1.0UF

20%

6.3V
X5R
0201-1

1

C3212

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3213

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3214

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3215

1.0UF

20%

6.3V

2

X5R

0201-1

2.2UH-20%-1.2A-0.15OHM

2.2UH-20%-1.2A-0.15OHM

1

C3216

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3217

1.0UF

20%

6.3V

2

X5R
0201-1

L3200

21

0806

CRITICAL

2.2UH-20%-1.2A-0.15OHM

L3201

0806

CRITICAL

21

L3202

21

0806

CRITICAL

L3203

21

0806

CRITICAL

2.2UH-20%-2.34A-0.113OHM

1 2

1

C3218

10UF

20%

6.3V

2

CERM-X5R
0402-2

1

C3219

1.0UF

20%

6.3V

2

X5R
0201-1

L3204

2520-SM

CRITICAL

1

C3221

10UF

20%

6.3V

2

CERM-X5R
0402-2

1

C3220

10UF

20%

6.3V

2

CERM-X5R
0402-2

2

1

2

1

2

1

2

1

2

1

2

1

C3223

10UF

20%

6.3V

2

CERM-X5R
0402-2

C3230

1.0UF

20%

6.3V
X5R
0201-1

C3229

22UF

20%

6.3V
X5R-CERM-1
603

C3228

22UF

20%

6.3V
X5R-CERM-1
603

C3226

22UF

20%

6.3V
X5R-CERM-1
603

C3225

22UF

20%

6.3V
X5R-CERM-1
603

C3224

22UF

20%

6.3V
X5R-CERM-1
603

1

C3222

10UF

20%

6.3V

2

CERM-X5R
0402-2

PP_SMPS1_MSMC_1V05

S1_GND

25 26

PP_SMPS2_RF1_1V3

S2_GND

25 26

PP_SMPS3_MSME_1V8

1

2

S3_GND

25 26

PP_SMPS4_RF2_2V05

S4_GND

25 26

PP_SMPS5_DSP_1V05

S5_GND

25 26

PP_LDO1
PP_LDO2_XO_HS_1V8
PP_LDO3_AMUX_1V8
PP_LDO4_VDDA_3V3
PP_LDO5_GPS_LNA_2V5
PP_LDO6_RUIM_1V8
PP_LDO13_VDDPX_2V95
PP_LDO14_2V65
PP_LDO7_DAC_1V8
PP_LDO8_VDDPX_1V2
PP_LDO9_PLL_1V05
PP_LDO10_ADSP_1V05
PP_LDO11_MDSP_FW_1V05
PP_LDO12_MDSP_SW_1V05

1

C3231

1.0UF

20%

6.3V

2

X5R
0201-1

C3227

0.1UF

20%
4V
X5R
01005

NOSTUFF

INTERNAL USE ONLY

27 52

OUT

27 30

OUT

24 25 27 28 30 52

OUT

25 30 52

OUT

25 52

OUT

52

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

27

26 27

27

41

10 24 27 52

27

14 32 33 39 40

27

27

27

27

27

27

D

C

B

w w w . c h i n a f i x . c o m

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: BASEBAND PMU (1 0F 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-0886

A.0.0

32 OF 121

25 OF 54

SIZE

A

D

8 7 6 5 4 3

12

PMU (2 OF 2)

D

5

24 52

IN

C

GPIO_SOC2BB_RST_L

PS_HOLD

28

IN

R3300

1.00K

1 2

5%

1/32W

MF

01005

R3301

20.0K

1 2

5%

1/32W

MF

01005

GPIO_SOC2BB_RADIO_ON_L

5

24 52

IN

PMU_GPIO_PMU2BBPMU_RST_L

24 48 52

IN

PS_HOLD_PMIC

24 52

PA_ID

0.1V

85
67
66
72
73
80

0.3V

0.5V

1.1V

1.3V

1.5V

MPP_01
MPP_02
MPP_03
MPP_04
MPP_05
MPP_06

PP_LDO3_AMUX_1V8

25 26 27

IN

1

BOARD_ID

0.7V

0.9V

1.1V

1.3V

1.5V

1.7V

BB GPIO_29

1 (1.8V)
0 (NC, PD)

U3300

PM8018-0

BGA

CONTROL

PS_HOLD

KPD_PWR*
PM_RESIN_N

OPT_1
OPT_2

(SYM 1 OF 5)

LED_DRV_N

PON_RESET*

PM_USR_INT_N
PM_MDM_INT_N

47

69
16

62

NC

74

NC

86

NC

4

PMIC_RESOUT_L

21

PM_USR_IRQ_L

14

PM_MDM_IRQ_L

24 27

OUT

28

OUT

28

OUT

REVISION
PROTO1

PROTO2
EVT1
EVT2
DVT
PVT

PRODUCT_ID
JXX

NXX

PROTO2

R3304

100K

1%
1/32W
MF
01005

2

BOARD_ID PA_ID

1

R3305

100K

1%
1/32W
MF
01005

2

27

OUT

28

IN

VDDPX_BIAS

VREF_DAC_BIAS

1

R3306

100K

1%
1/32W
MF
01005

2

1.5V

1

R3307

499K

1%
1/32W
MF
01005

2

NC
NC

AP SECTION NEEDS ITS OWN THERMISTOR PLACED NEAR THE PA’S.

MAV VER

U3300

PM8018-0

BGA

MPP MISC

(SYM 4 OF 5)

CRITICAL

8.7

8.6

8.5

7.7

7.6

7.5

GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06

D

33

NC

38

NC

50

NC

60

NC

71

NC

49

NC

C

41

PON_TRIG

PMIC_SSBI

24 27

BI

68

SSBI

B

U3300

PM8018-0

BGA

INPUT PWR

(SYM 3 OF 5)

57

VCOIN

NC

GND_S1

GND_S2

GND_S3

GND_S4

GND_S5

GND

91
103
96
30
36
93
99
94

39
51
61
56
46
52
40

25

25

25

25

25

35

BAT_ID

GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL
TO MINIMIZE THERMAL DRIFT

Y3300

19.200MHZ

2.0X1.6-SM
1

CRITICAL

PP_LDO3_AMUX_1V8

25 26 27

IN

1

R3303

100K

1%
1/32W
MF
01005

2

S1_GND

S2_GND

S3_GND

S4_GND

S5_GND

XW3300

SM

1 2

XW3301

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

XW3302

SM

1 2

XW3303

XW3304

SM

1 2

21

21

w w w . c h i n a f i x . c o m

3

24

19P2M_XTAL_IN

19P2M_XTAL_OUT

XO_THERM_Y1

1

C3300

1000PF

10%

6.3V

2

X5R-CERM
01005

XO_GND

NC

2

XW3305

SHORT-10L-0.1MM-SM

1

1

XTAL_19M_IN

2

XTAL_19M_OUT

3

XTAL_32K_IN

15

XTAL_32K_OUT

45

GND1

27

GND0

10

XO_THERM

22

XOADC_GND

U3300

PM8018-0

BGA

CLOCKS

(SYM 2 OF 5)

XO_OUT_D0_EN

XO_OUT_A0
XO_OUT_D0

XO_OUT_A1

SLEEP_CLK

RSVD

19P2M_WTR

19

19P2M_MDM

25

37

NC

19P2M_CLK_EN

9

SLEEP_CLK_32K

26

7

29

OUT

24 27

OUT

27

IN

24 27

OUT

B

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: BASEBAND PMU (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

33 OF 121

SHEET

26 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

BASEBAND (1 OF 2)

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

D

25 27 52

C

25 27 52

B

A

PP_SMPS1_MSMC_1V05

25 27 52

IN

PP_LDO9_PLL_1V05

25 27

IN

PP_SMPS3_MSME_1V8 PP_SMPS3_MSME_1V8

24 25 27 28 30 52

IN

1

2

PP_SMPS1_MSMC_1V05

IN

PP_SMPS1_MSMC_1V05

IN

PP_LDO9_PLL_1V05

25 27

IN

PP_SMPS3_MSME_1V8

24 25 27 28 30 52

IN

PP_LDO13_VDDPX_2V95

25

IN

C3409

1.0UF

20%

6.3V
X5R
0201-1

1

C3421

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3400

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3405

1.0UF

20%

6.3V

2

X5R
0201-1

1

2

C3410

1.0UF

20%

6.3V
X5R
0201-1

1

C3401

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3406

1.0UF

20%

6.3V

2

X5R
0201-1

24 25 27

IN IN

28 30 52

F8

F9
F12
F13
F14

G9
G12

H9
H12

J8

J9
J12
J13

K8

K9
K12
K13

L8

L9
L12
L13

M8

M9
M12
M13

N8

N9
N12
N13

P9
P12

R9
R12

T8

T9

C17
C18
E17
F17

G7

G8
G13
G14

H7

H8
H13
H14

P7

P8
P13
P14

R7

R8
R13
R14

A14
A19
F21

M1
M21

K21

VDD_P2

1

C3402

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3407

1.0UF

20%

6.3V

2

X5R
0201-1

1

2

VDD_CORE

VDD_MEM

VDD_P1

1

C3403

1.0UF

2

1

C3408

1.0UF

2

C3411

1.0UF

20%

6.3V
X5R
0201-1

U3400

MDM9615M

BGA

(5 OF 6)

PWR

VDD_MDSP_FW

VDD_MDSP_SW

VDD_QFUSE_PRG

VDD_HVPAD_BIAS

20%

6.3V
X5R
0201-1

20%

6.3V
X5R
0201-1

1

C3412

1.0UF

20%

6.3V

2

X5R
0201-1

VDD_DDR

VDD_ADSP

VDD_USB_1P8
VDD_USB_3P3

VDD_PLL1

VDD_PLL2

VDD_A2
VDD_A2

VDD_A1
VDD_A1

VDD_P3

VDD_P4
VDD_P5
VDD_P6
VDD_P7

1

C3404

1.0UF

20%

6.3V

2

X5R
0201-1

GND
GND

GND

PP_LDO8_VDDPX_1V2

25 27

IN

PP_LDO10_ADSP_1V05

25 27

IN IN

25 27

AA20
B19
F20
M20

C5
C6
E6
E7
F5

T15
T16
T17
U14
U15
U16
U17
U19
T19

N15
N16
N17
N19
P15
P16
P17
P19

B13

E12
E10

E16

PP_LDO9_PLL_1V05

K17
L17
W12

U6
U7
AA11
AA18

W9
AA7
AA15

A15
G1
G21
L1
U1
W19

A2
A3
A7
A11

1

C3413

1.0UF

20%

6.3V

2

X5R
0201-1

PP_LDO12_MDSP_SW_1V05

1

C3415

1.0UF

20%

6.3V

2

X5R
0201-1

PP_SMPS3_MSME_1V8

PP_LDO10_ADSP_1V05

PP_LDO11_MDSP_FW_1V05

PP_LDO12_MDSP_SW_1V05

PP_LDO4_VDDA_3V3

PP_LDO3_AMUX_1V8

PP_LDO7_DAC_1V8

PP_SMPS3_MSME_1V8

PP_LDO6_RUIM_1V8
PP_SMPS3_MSME_1V8
PP_LDO8_VDDPX_1V2

PP_SMPS3_MSME_1V8

1

C3426

1.0UF

20%

6.3V

2

X5R
0201-1

1

2

1

2

PP_LVS1

IN

IN

IN

PP_LDO4_VDDA_3V3

25 27

IN

1

2

C3414

1.0UF

20%

6.3V
X5R
0201-1

C3416

1.0UF

20%

6.3V
X5R
0201-1

IN

25 27

IN

VDDPX_BIAS

25 27

25 26

25

24 25 27 28 30 52

IN

10 24 25 52

IN

24 25 27 28 30 52

IN

25 27

IN

24 25 27 28 30 52

IN

1

C3419

1.0UF

20%

6.3V

2

X5R
0201-1

IN

25 30

1

C3433

1.0UF

20%

6.3V

2

X5R
0201-1

1

2

25

C3431

1.0UF

20%

6.3V
X5R
0201-1

25 27

1

C3432

0.22UF

20%

6.3V

2

X5R
01005

PP_LDO11_MDSP_FW_1V05

1

C3417

1.0UF

20%

6.3V

2

X5R
0201-1

24 25 27 28 30 52

IN

25 27

IN

25 27

IN

25 27

1

R3400

470K

5%
1/32W
MF
01005

2

PP_LDO2_XO_HS_1V8

26

IN

1

C3423

0.1UF

20%
4V

2

X5R
01005

NOSTUFF

PP_SMPS2_RF1_1V3

1

C3424

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3418

1.0UF

20%

6.3V

2

X5R
0201-1

IN

25

1

C3425

1.0UF

20%

6.3V

2

X5R
0201-1

1

C3422

1.0UF

20%

6.3V

2

X5R
0201-1

IN

w w w . c h i n a f i x . c o m

C3420

1.0UF

20%

6.3V
X5R
0201-1

1

2

24 26

IN

24 52

IN

24 26

IN

5

24 52

IN

5

24 52

IN

5

24 52

IN

5

24 52

IN

24 26

IN

26

OUT

24 26

BI

24

BI

24

BI

C3434

0.22UF

20%

6.3V
X5R
0201

PMIC_RESOUT_L
DEBUG_RST_L
SLEEP_CLK_32K

BB_JTAG_TCK
BB_JTAG_TDI
BB_JTAG_TMS
BB_JTAG_TRST_L

TP_BB_TEST_MODE_0

52

TP_BB_TEST_MODE_1

52

19P2M_MDM

19P2M_CLK_EN
PMIC_SSBI

USB_BB_DEBUG_P
USB_BB_DEBUG_N

RREFEXT

52
24
48

1

R3401

200

1%
1/32W
MF
01005

2

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PMU_GPIO_BB_VBUS_DET

IN

NC

AA19

A21
AA1

AA21

B11
B14
B15
C19

F10
F15
F16
F19

G10
G11
G15
G16
G17
G20

H10
H11
H15
H16

J10
J11
J14
J15

K10
K11
K14
K15
K20

L10
L11
L14
L15

M10
M11

Y20

Y4

Y3

AA2

W4

AA4

W20
Y19

V20
U21
Y21

C11
E11
A12
C12
B12
C10

B2
B7

F6
F7

G2
G6

H6

J6
J7

K6
K7

L2
L6
L7

M6
M7

MDM9615M

GND

MDM9615M

RESIN*
SRST*
SLEEP_CLK

TCK
TDI
TMS
TRST*

MODE_0
MODE_1

CXO
CXO_EN
SSBI_PMIC

USB_HS_DP
USB_HS_DM
USB_HS_REXT
USB_HS_ID
USB_HS_SYSCLK
USB_HS_VBUS

U3400

BGA

(6 OF 6)

GND

CRITICAL

U3400

BGA

(1 OF 6)

DIGITAL

GND_ANA

RESOUT*

RTCK

HSIC_CAL

HSIC_DATA

HSIC_STB

DNC

DNC

SDC1_CMD
SDC1_CLK

SDC1_DATA0
SDC1_DATA1
SDC1_DATA2
SDC1_DATA3

GND

TDO

M14
M15
M16
M17
M19
N6
N7
N10
N11
N14
P6
P10
P11
R6
R10
R11
R15
R16
R17
R19
T10
T12
T13
T14
U2
V19

F11
J16
K16
L16
T6
T7
T11
U9
U12
W7
W14
Y7
Y11
Y15
Y18
U13
W13

U20

NC

BB_JTAG_TDO

AA3

BB_JTAG_RTCLK

Y2

50_HSIC_CAL

A8

HSIC2_BB_DATA

C7

HSIC2_BB_STB

B8

E8
C8
B9
A9

E9
C9
B10
A10

K19
L21

L19
L20
N20
N21

12

D

U3400

MDM9615M

BGA

NC
NC
NC
NC

NC
NC

D21

EBI2_NAND_CS*

E19

EBI2_OE*

D20

EBI2_WE*

D19

EBI2_BUSY*

C20

EBI2_CLE*

E20

EBI2_ALE*

(2 OF 6)

EBI1_EBI2

EBI1_CAL

EBI2_AD_0
EBI2_AD_1
EBI2_AD_2
EBI2_AD_3
EBI2_AD_4
EBI2_AD_5
EBI2_AD_6
EBI2_AD_7

C21

J20
J19
G19
H20
J21
H19
H21
E21

EBI1_CAL

NC
NC
NC
NC
NC
NC
NC
NC

R3403

240

1 2

1%

1/32W

MF

01005

C

B

5

24 52

OUT

24 52

OUT

4

24 53

BI

4

24 53

BI

NC
NC
NC
NC

NC
NC
NC
NC

NC
NC

NC
NC
NC
NC

R3402

240

1 2

1%

1/32W

MF

01005

PAGE TITLE

CELL: BASEBAND (1 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

051-0886

A.0.0

34 OF 121

27 OF 54

SIZE

A

D

124578

8 7 6 5 4 3

BASEBAND (2 OF 2)

12

19 44 52

SIZE

D

C

B

A

D

D

U3400

MDM9615M

BGA

(4 OF 6)

ANALOG

DAC0_VREF

29

IN

29

IN

29

IN

29

IN

29

IN

29

IN

29

IN

29

IN

PRX_BB_I_P
PRX_BB_I_N
PRX_BB_Q_P
PRX_BB_Q_N

DRX_BB_I_P
DRX_BB_I_N
DRX_BB_Q_P
DRX_BB_Q_N

C

29

IN

29

IN

29

IN

29

IN

GPS_BB_I_P
GPS_BB_I_N
GPS_BB_Q_P
GPS_BB_Q_N

U8

BBRX_IP_CH0

W8

BBRX_IM_CH0

Y8

BBRX_QP_CH0

AA8

BBRX_QM_CH0

Y10

BBRX_IP_CH1

AA10

BBRX_IM_CH1

Y9

BBRX_QP_CH1

AA9

BBRX_QM_CH1

W17

BBRX_IP_CH2

NC

W18

BBRX_IM_CH2

NC

W15

BBRX_QP_CH2

NC

W16

BBRX_QM_CH2

NC

W10

GNSS_BB_IP

U10

GNSS_BB_IM

W11

GNSS_BB_QP

U11

GNSS_BB_QM

CRITICAL

TX_DAC1_QP
TX_DAC1_QM

TX_DAC0_IP
TX_DAC0_IM
TX_DAC0_QP
TX_DAC0_QM

TX_DAC0_IREF

TX_DAC1_IP
TX_DAC1_IM

B

L3520

PP_SMPS3_MSME_1V8

24 25 27 28 30 52

IN

70-OHM-300MA

SPI_DATA_MOSI

28

SPI_CLK

28

01005-1

PP_SMPS3_MSME_1V8_FILT

21

D3

E2

D2
C2

A

W5

Y13

NC

AA13

NC

Y6
AA6
Y5
AA5
W6

Y14

NC

AA14

NC

H17

NC

J17

NC

V21

NC

W21

NC

Y12

DNC

SERIAL-SPI-2MX8-1.8V

WP*/SIO2

SI/SIO0

SCLK

NC/SIO3

NC

Y16

NC

Y17

NC

AA12

NC

AA16

NC

NC

AA17

1

C3520

0.1UF

20%
4V

2

X5R
01005

VCC

U3520

WLCSP

MX25U1635EBAI-10G

CRITICAL

GND

VREF_DAC_BIAS

1

C3500

0.1UF

20%
4V

2

X5R
01005

WTR_BB_TX_DAC_IREF

E3 B2

26

OUT

PP_SMPS3_MSME_1V8

24 25 27 28 30 52

1

R3502

10K

5%
1/32W

TX_BB_I_P
TX_BB_I_N

TX_BB_Q_P
TX_BB_Q_N

SO/SIO1

29

BI

29

OUT

29

OUT

29

OUT

29

OUT

R3531

0.00

OSCAR2RADIO_CONTEXT_A

19 44 52

IN

GPIO_29

1 (1.8V)
0 (NC, PD)

B3

SPI_CS_L

CS*

w w w . c h i n a f i x . c o m

C3

SPI_DATA_MISO

A4

NC

F1

NC

NC

F4

NC

28

28

PRODUCT_ID
JXX

NXX

1 2

0%

1/32W

MF

01005

10 24 52

10 24 52

10 24 52

10 24 52

24

5

24

11 24 52

5

11 24 52

5

52

24

24 25 27 28 30 52

RESERVED FOR FUTURE PRODUCT ID USE

37

37

35

33

34

36

32 33

33 34 35 36

24 29

24 29

MF
01005

2

IN
OUT
OUT
BI

28

28

28

28

5

OUT

IN

5

OUT

IN

OSCAR_CONTEXT_A_MDM

IN
OUT

IN

OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT

SIM_TRAY_DETECT
SIMCRD_RST_CONN
SIMCRD_CLK_CONN
SIMCRD_IO_CONN

SPI_CLK
SPI_CS_L
SPI_DATA_MISO
SPI_DATA_MOSI
UART3_BB2SOC_RTS_L
UART3_SOC2BB_RTS_L
UART3_SOC2BB_TX
UART3_BB2SOC_TX

GPIO_SOC2BB_WAKE_MODEM
GPIO_DEBUG_LED

PP_SMPS3_MSME_1V8

GSM_PA_LB_EN
GSM_PA_HB_EN
PA_ON_B7_B20

PA_MB_CTL1
PA_ON_B2_B3
PA_ON_B5_B8
PA_MB_CTL0

PA_BS
WTR_RX_ON
WTR_RF_ON

B6
A6
A5
B5
C4

NC

B3

NC

B4

NC

A4

NC

A16
A13
E14
E13
C14
C13
E15
A18
C15

NC

B16
B18
C16
A17

NC

B21

NC

B20

NC

A20

NC

B17

NC

P21

NC

R21

NC

P20

NC

R20

NC

T20
T21

NC

U5
V2
V1
U3

NC

T3
T1
T5
R5
R3

NC

T2
R2
P5
P1

NC

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

WLAN_TX_BLANK NEEDS TO CONNECT TO AP

CRITICAL

U3400

MDM9615M

BGA

(3 OF 6)

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_42
GPIO_43

GRFC_0
GRFC_1
GRFC_2
GRFC_3
GRFC_4
GRFC_5
GRFC_6
GRFC_7
GRFC_8
GRFC_9
GRFC_10
GRFC_11
GRFC_13

GPIO

GRFC_14
GRFC_15
GRFC_18
GRFC_19
GRFC_20
GRFC_21
GRFC_22
GRFC_23
GRFC_24
GRFC_25
GRFC_26
GRFC_27
GRFC_28
GRFC_29
GRFC_30
GRFC_31
GRFC_32
GRFC_33
GRFC_34
GRFC_35
GRFC_36
GRFC_37
GRFC_38
GRFC_39

GPIO_44
GPIO_45
GPIO_46
GPIO_47
GPIO_48
GPIO_49
GPIO_50
GPIO_51
GPIO_52
GPIO_53
GPIO_54
GPIO_55
GPIO_56
GPIO_57
GPIO_58
GPIO_59
GPIO_60
GPIO_61
GPIO_62
GPIO_63
GPIO_64
GPIO_65
GPIO_66
GPIO_67
GPIO_68
GPIO_69
GPIO_70
GPIO_71
GPIO_72
GPIO_73
GPIO_74
GPIO_75
GPIO_76
GPIO_77
GPIO_78
GPIO_79
GPIO_80
GPIO_81
GPIO_82
GPIO_83
GPIO_84
GPIO_85
GPIO_86
GPIO_87

P3

PA_R1

R1

B40_FILT_SELECT

N5

NC

LAT_SW3_CTL

N3

NC

P2

LAT_SW1_CTL

M2

GPIO_BB2SOC_GSM_TXBURST

N1

NC

N2

GPIO_51
ANT_SEL_0

M3
L3

ANT_SEL_1

M5

ANT_SEL_2

L5

ANT_SEL_3

K1

ANT_SEL_4

K5

3P4T_SEL_0

K3

3P4T_SEL_1

K2

LAT_SW2_CTL

J2

DCDC_EN

J5

DCDC_MODE

J1

NC

J3

NC

BB_PDM

H3

UART_WLAN2BB_LTE_COEX

H5

UART_BB2WLAN_LTE_COEX

G5
H1

NC

HSIC2_BB2SOC_REMOTE_WAKE

H2

BB_IPC_GPIO

F3

WTR_SSBI_PRX_DRX

F1

WTR_SSBI_TX_GPS

G3
V3

NC

BB_ERROR_FLAG

W3

WTR_GP_DATA0

W2

WTR_GP_DATA1

W1
Y1

NC

WLAN_TX_BLANK

F2

OSCAR_CONTEXT_B_MDM

E2
E3

HSIC2_BB2SOC_DEVICE_RDY

D1

HSIC2_SOC2BB_HOST_RDY

E1

PM_MDM_IRQ_L

D2

GPIO_BB2SOC_RESET_DET_L

D3

PS_HOLD

C1

NC

B1

GPIO_BB2SOC_GPS_SYNC

C2

PMU_GPIO_BB2PMU_HOST_WAKE

C3

PM_USR_IRQ_L

BOOT_CONFIG_6

BOOT_CONFIG_4
BOOT_CONFIG_3
BOOT_CONFIG_2
BOOT_CONFIG_1
BOOT_CONFIG_0

GPH
GPH

PAGE TITLE

CELL: BASEBAND (2 OF 2)

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

33 34 35 36 37

OUT

39

OUT

14 24 52

OUT

BOOT_CONFIG_5

24

IN

33 39 40

OUT

24 33 39 40

OUT

24 39 40

OUT

39 40

BI

39

OUT

33

OUT

33

OUT

14 52

OUT

38

OUT

38

OUT

38

OUT

24 44

IN

24 44

OUT

5

OUT

5

OUT

24 29

BI

24 29

BI

24

OUT

29

OUT

29

OUT

IN

1 2

5

24

OUT

5

24

IN

26

OUT

5

24

OUT

26

OUT

5

OUT

24 48 52

OUT

26

OUT

Apple Inc.

R

R3530

0.00

0%

1/32W

MF

01005

OUT

44 52

OSCAR2RADIO_CONTEXT_B

5

DRAWING NUMBER

051-0886

REVISION

BRANCH

PAGE

35 OF 121

SHEET

124578

IN

A.0.0

28 OF 54

8 7 6 5 4 3

RF TRANSCEIVER (1 OF 2)

12

PRX TRANSCEIVER RF AND IQ PORTS

D

100_XCVR_B20_PRX_P

31

IN

100_XCVR_B20_PRX_N

IN

100_XCVR_B8_PRX_N

31

IN

100_XCVR_B8_PRX_P

31

IN

100_XCVR_B5_B18_PRX_P

31

IN

100_XCVR_B5_B18_PRX_N

31

IN

100_XCVR_B2_PRX_P

31

IN

100_XCVR_B2_PRX_N

31

IN

100_XCVR_B3_PRX_P

31

IN

100_XCVR_B3_PRX_N

31

IN

100_XCVR_B1_B34_B39_DCS_PRX_N

31

IN

100_XCVR_B1_B34_B39_DCS_PRX_P

31

IN

100_XCVR_B7_B38_B40_PRX_P

31

IN

100_XCVR_B7_B38_B40_PRX_N

31

IN

78

PRX_LB1_INP

69

PRX_LB1_INM

61

PRX_LB2_INP

54

PRX_LB2_INM

48

PRX_LB3_INP

43

PRX_LB3_INM

36

PRX_MB1_INP

30

PRX_MB1_INM

23

PRX_MB2_INP

17

PRX_MB2_INM

8

PRX_MB3_INP

16

PRX_MB3_INM

7

PRX_HB_INP

15

PRX_HB_INM

DRX TRANSCEIVER RF AND IQ PORTS

C

100_XCVR_B5_B18_DRX_P

40

IN

100_XCVR_B5_B18_DRX_N

40

IN

100_XCVR_B8_B20_DRX_P

40

IN

100_XCVR_B8_B20_DRX_N

40

IN

100_XCVR_B1_B2_B3_B34_B39_DRX_P

40

IN

100_XCVR_B1_B2_B3_B34_B39_DRX_N

40

IN

100_XCVR_B7_B38_B40_DRX_P

40

IN

100_XCVR_B7_B38_B40_DRX_N

40

IN

100_XCVR_GPS_RX_P

40

IN

100_XCVR_GPS_RX_N

40

IN

5

DRX_LB1_INP

14

DRX_LB1_INM

4

DRX_LB2_INP

13

DRX_LB2_INM

3

DRX_MB_INP

12

DRX_MB_INM

2

DRX_HB_INP

11

DRX_HB_INM

10

GNSS_INP

18

GNSS_INM

U3600

WTR1605

SM

SYM 3 OF 5

PRX

CRITICAL

U3600

WTR1605

SM

SYM 1 OF 5

DRX_GPS

CRITICAL

PRX_BB_IP
PRX_BB_IM

PRX_BB_QP
PRX_BB_QM

DRX_BB_IP
DRX_BB_IM

DRX_BB_QP
DRX_BB_QM

GNSS_BB_IP
GNSS_BB_IM

GNSS_BB_QP
GNSS_BB_QM

DNC

GND

84
92

91
82

86

63
72

50
57

56
62

70
71

1

PRX_BB_I_P

PRX_BB_I_N
PRX_BB_Q_P

PRX_BB_Q_N

NC

DRX_BB_I_P
DRX_BB_I_N

DRX_BB_Q_P
DRX_BB_Q_N

GPS_BB_I_P
GPS_BB_I_N

GPS_BB_Q_P
GPS_BB_Q_N

28

OUT

28

OUT

28

OUT

28

OUT

R3600

4.75K

1 2

1%

1/32W

MF

01005

C3600

19P2M_WTR

26

IN

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

28

OUT

100PF

1 2

5%

16V

NP0-C0G

01005

19P2M_WTR_FILT_IN

TX_BB_I_P

28

IN

TX_BB_I_N

28

IN

TX_BB_Q_P

28

IN

TX_BB_Q_N

28

IN

WTR_BB_TX_DAC_IREF

28

IN

28

IN

WTR_GP_DATA1

28

IN

WTR_RBIAS

WTR_RX_ON

24 28

IN

WTR_RF_ON

24 28

IN

WTR_SSBI_TX_GPS

24 28

BI

WTR_SSBI_PRX_DRX

24 28

BI

R3604

0.00

1 2

0%

1/32W

MF

01005

TRANSCEIVER PHASE CONTROL, TX RF & IQ PORTS

WTR1605

SYM 2 OF 5

CRITICAL

19P2M_WTR_IN

GPHWTR_GP_DATA0
GPH

NC
NC
NC

NC

NC

1

2

130
138

131
139

109

105
121

88

114

96

90

60

79

45

100

89
80

134

120

C3601

10PF

5%
16V
CERM
01005

NOSTUFF

TX_BB_IP
TX_BB_IM

TX_BB_QP
TX_BB_QM

DAC_REF

GP_DATA0
GP_DATA1
GP_DATA2
DNC
DNC

DNC

RBIAS

VTUNE_PRX

RX_ON
RF_ON
SSBI_TX_GNSS
SSBI_PRX_DRX

GND

XO_IN

U3600

SM

TX

TX_LB1
TX_LB2
TX_LB3
TX_LB4

TX_MB1
TX_MB2
TX_MB3
TX_MB4

TX_HB

PDET_IN

DNC

140

50_XCVR_B20_TX

132

50_XCVR_2G_LB_TX

141

50_XCVR_B8_TX

133

50_XCVR_B5_B18_TX

126

50_XCVR_B2_TX

119

50_XCVR_B1_B3_TX

112

50_XCVR_B34_B39_TX

95

50_XCVR_2G_HB_TX

103

50_XCVR_B7_B38_B40_TX

93

NC

101

50_PDET_IN

C3602

56PF

1 2

5%

16V

NP0-C0G

01005

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT

50_PDET_PAD_OUT

32 31

37

32

32

32

32

32

37

32

R3602

61.9

1 2

1%

1/32W

MF

01005

1

R3601

105

1%
1/32W
MF
01005

2

9.0 DB ATTENUATOR

50_PDET_PAD_IN

1

R3603

105

1%
1/32W
MF
01005

2

D

35

IN

C

TRANSCEIVER GROUND CONNECTIONS

B

46

GND

77

GND

47

GND

68

GND

29

GND

22

GND

27

GND

21

GND

20

GND

33

GND

6

GND

75

GND

38

GND

41

GND

58

GND

74

GND

59

GND

52

GND

39

GND

73

GND

34

GND

64

A

GND

81

GND

35

GND

142

GND

U3600

WTR1605

SM

SYM 5 OF 5

GND

CRITICAL

125

GND

124

GND

123

GND

110

GND

102

GND

99

GND

129

GND

94

GND

115

GND

137

GND

122

GND

107

GND

106

GND

135

GND

128

GND

w w w . c h i n a f i x . c o m

104

GND

113

GND

19

GND

32

GND

49

GND

9

GND

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: RF TRANSCEIVER (1 0F 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-0886

REVISION

BRANCH

PAGE

36 OF 121

SHEET

124578

A.0.0

29 OF 54

SIZE

B

A

D

8 7 6 5 4 3

RF TRANSCEIVER (2 OF 2)

12

25
27

D

C

B

A

PP_SMPS2_RF1_1V3

22-OHM-25%-1800MA

R3700

0201

RF1_1V3

30

PP_SMPS2_RF1_1V3_FILT

21

1

2

C3701

10UF

20%
10V
X5R-CERM
0402-1

STAR ROUTING

STAR ROUTING

STAR ROUTING

STAR ROUTING

PP_RF1_1V3_PRX_PLL

ALIAS

1

C3702

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.66

PP_RF1_1V3_SHDR_PLL

ALIAS

1

C3703

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.65

PP_RF1_1V3_PRX_VCO

ALIAS

1

C3704

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.76

PP_RF1_1V3_SHDR_VCO

ALIAS

1

C3705

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.40

PP_RF1_1V3_TX_DA

ALIAS

1

C3706

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.118

NOSTUFF

PP_RF1_1V3_TX_SYNTH

ALIAS

1

C3707

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.98

PP_RF1_1V3_TX_LO

ALIAS

1

C3708

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.116

PP_RF1_1V3_TX_UPCONVERTER

ALIAS

1

C3709

100PF

5%
16V

2

NP0-C0G
01005

PLACE NEAR U3.117

1

C3710

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.53 AND U3.26

ALIAS

ALIAS

1

2

1

2

PP_RF1_1V3_PRX_FELO2

C3711

0.1UF

20%

6.3V
X5R-CERM
01005

PLACE NEAR U3.42

C3712

0.1UF

20%

6.3V
X5R-CERM
01005

PLACE NEAR U3.25 AND U3.28

PP_RF1_1V3_JAM_DET

6 3

RF1_1V3

30

30

30

PP_SMPS2_RF1_1V3_FILT

30

STAR ROUTING

STAR ROUTING

1

C3713

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.24 AND U3.31

STAR ROUTING

1

C3714

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.37 AND U3.55

PP_RF1_1V3_GPS_LNA

ALIAS

PP_RF1_1V3_GPS_DIG

ALIAS

PP_RF1_1V3_GPS_VCO

ALIAS

PP_RF1_1V3_GPS_PLL

ALIAS

30

PP_SMPS4_RF2_2V05

25 52

30

30

30

RF2_2V05

R3702

0

1 2

PP_SMPS4_RF2_2V05_FILT

5%

1/20W

MF

201

1

C3715

10UF

20%
10V

2

X5R-CERM
0402-1

STAR ROUTING

RF1_1V8

PP_SMPS3_MSME_1V8

24 25 27 28 52

30

30

1

C3721

56PF

5%
16V

2

NP0-C0G
01005

30

30

30

STAR ROUTING

30

STAR ROUTING

w w w . c h i n a f i x . c o m

PP_RF1_1V3_PRX_FELO1

ALIAS

ALIAS

30

PP_RF1_1V3_DRX_FE

PP_RF1_1V3_DRX_LBLO

ALIAS

PP_RF1_1V3_DRX_MBLO

ALIAS

ALIAS

30

30

30

30

1

C3700

1.0UF

20%
10V

2

X5R-CERM
0201-1

PLACE NEAR U3.87

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

PP_RF1_1V8_DIG

PP_RF1_1V3_PRX_FELO1

30

PP_RF1_1V3_PRX_FELO2

30

PP_RF1_1V3_DRX_LBLO

30

PP_RF1_1V3_DRX_FE

30

PP_RF1_1V3_DRX_MBLO

30

PP_RF1_1V3_JAM_DET

30

PP_RF2_2V05_PRX_BB

30

PP_RF2_2V05_DRX_BB

30

PP_RF2_2V05_PRX_VCO

30

PP_RF1_1V3_PRX_VCO

30

PP_RF1_1V3_PRX_PLL

30

PP_RF2_2V05_SHDR_VCO

30

PP_RF1_1V3_SHDR_VCO

30

PP_RF1_1V3_SHDR_PLL

30

30

TRANSCEIVER POWER CONNECTIONS

U3600

WTR1605

SM

SRM 4 OF 5

53

VDD_RF1_P_FELO

42

VDD_RF1_P_FELO

28

VDD_RF1_D_LBLO

26

VDD_RF1_D_FE

25

VDD_RF1_D_MBLO

85

VDD_RF1_JDET

83

VDD_RF2_P_BB

44

VDD_RF2_D_BB

67

VDD_RF2_P_VCO

76

VDD_RF1_P_VCO

66

VDD_RF1_P_PLL

51

VDD_RF2_S_VCO

40

VDD_RF1_S_VCO

65

VDD_RF1_S_PLL

PWR

CRITICAL

VDD_RF2_T_DA
VDD_RF1_T_DA

VDD_RF1_T_UPC

VDD_RF1_T_LO
VDD_RF2_T_BB

VDD_RF2_T_VCO

VDD_RF2_XO
VDD_RF1_T_SYN
VDD_RF2_T_PLL

VDD_RF1_G_LNA
VDD_RF1_G_VCO
VDD_RF1_G_PLL

VDD_RF1_G_BB

VDD_DIO

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

ALIAS

ALIAS

STAR ROUTING

STAR ROUTING

111

PP_RF2_2V05_TX_DA

118

PP_RF1_1V3_TX_DA

117

PP_RF1_1V3_TX_UPCONVERTER

116

PP_RF1_1V3_TX_LO

108

PP_RF2_2V05_TX_BB

136

PP_RF2_2V05_TX_VCO

127

PP_RF2_2V05_XO_FILT

98

PP_RF1_1V3_TX_SYNTH

97

PP_RF2_2V05_TX_PLL

24

PP_RF1_1V3_GPS_LNA

37

PP_RF1_1V3_GPS_VCO

55

PP_RF1_1V3_GPS_PLL

31

PP_RF1_1V3_GPS_DIG

87

PP_RF1_1V8_DIG

ALIAS

ALIAS

ALIAS

ALIAS

ALIAS

ALIAS

ALIAS

CELL: RF TRANSCEIVER (2 OF 2)

Apple Inc.

R

PP_RF2_2V05_DRX_BB

PP_RF2_2V05_TX_DA

1

C3716

100PF
5%
16V

2

NP0-C0G
01005

PLACE NEAR U3.111

NOSTUFF

PP_RF2_2V05_PRX_BB

PP_RF2_2V05_TX_BB

PP_RF2_2V05_PRX_VCO

1

C3717

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.67

PP_RF2_2V05_SHDR_VCO

1

C3718

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.51

PP_RF2_2V05_TX_VCO

1

C3719

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.136

PP_RF2_2V05_TX_PLL

PP_RF2_2V05_XO_FILT

1

C3720

0.1UF

20%

6.3V

2

X5R-CERM
01005

PLACE NEAR U3.127

30

30

30

30

30

30

30

30

30

30

30

30

30

30

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

37 OF 121

SHEET

30 OF 54

124578

30

30

30

30

30

30

D

C

30

30

30

B

A

SIZE

D

8 7 6 5 4 3

RX MATCHING

12

L3805

D

100_RX_MODULE_OUT_P

33

IN

100_RX_MODULE_OUT_N

33

IN

50_B2_DUPLX_RX

34

IN

C

50_B3_DUPLX_RX

34

IN

B

100_B20_DUPLX_RX_N

35

IN

100_B20_DUPLX_RX_P

35

IN

0.7NH-0.8A

1

2

1

2

50_B2_RX_BALUN

1

2

1

2

50_B3_RX_BALUN

1

2

CRITICAL

L3804

5.6NH-3%-0.35A

0201

CRITICAL

0.7NH-0.8A

CRITICAL

L3800

13NH-5%-0.28A

0201DS

CRITICAL

C3802

0.9PF

+/-0.05PF
16V
CERM
01005

L3802

8.7NH-5%-0.29A

0201DS

CRITICAL

C3805

1.2PF

+/-0.05PF
16V
NP0-C0G-CERM
01005

18NH-3%-140MA

1

L3823

22NH-5%-0.1A

01005

NOSTUFF

2

18NH-3%-140MA

21

0201

100_XCVR_B1_B34_B39_DCS_PRX_P

L3806

21

0201

+/-0.05PF

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

+/-0.05PF

NP0-C0G-CERM

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

100_XCVR_B1_B34_B39_DCS_PRX_N

C3800

0.6PF

1 2

16V

CERM

01005

C3801

27PF

1 2

5%

16V

NP0-C0G

01005

C3803

1.2PF

1 2

16V

01005

C3804

27PF

1 2

5%

16V

NP0-C0G

01005

L3822

21

01005

L3824

21

01005

100_B8_DUPLX_RX_N

29

OUT

29

OUT

36

IN

100_B8_DUPLX_RX_P

36

IN

1

L3811

18NH-3%-140MA

01005

2

8.2NH+/-3%-0.25A-0.7OHM

100_B5_DUPLX_RX_N

36

100_XCVR_B2_PRX_N

1

L3801

6.8NH-5%-0.5A

0201DS

CRITICAL

2

100_XCVR_B2_PRX_P

100_XCVR_B3_PRX_N

1

L3803

5.6NH-5%-0.33A

0201DS

CRITICAL

2

100_XCVR_B3_PRX_P

100_XCVR_B20_PRX_N

100_XCVR_B20_PRX_P

29

OUT

29

OUT

33

IN

50_3P4T_PRX_OUT

29

OUT

29

OUT

29

OUT

29

OUT

L3840

2.0NH+/-0.1NH-0.6A

33

BI

21

0201

CRITICAL

33

BI

33

BI

50_FULL_B40_FILTER

50_B7_B38_B40_PRX_BALUN_IN

50_B38_FILTER

50_B40_FILTER

w w w . c h i n a f i x . c o m

IN

36

IN

1

L3825

0.4PF

+/-0.1PF
25V

2

C0G-CERM
201

CRITICAL

U3803

2.3-2.69GHZ
LLP

UNBAL_PORT

BAL_PORT1
BAL_PORT2

CRITICAL

GND

1

1

2

1

C3809

6.8NH-3%-0.3A

0201

CRITICAL

2

2.7NH+/-0.1NH-200MA

1

C3811

56PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

1

2

100_B5_DUPLX_RX_P

100_B7_B38_B40_PRX_BALUN_OUT_N

2

3
4

100_B7_B38_B40_PRX_BALUN_OUT_P

C3808

9.1NH-3%-220MA

0201

CRITICAL

L3817

0

1 2

5%

1/20W

MF

201

L3819

01005

CRITICAL

L3807

22NH-5%-0.1A

01005

8.2NH+/-3%-0.25A-0.7OHM

50_B40_FILTER_MATCH

21

50_FULL_B40_FILTER_MATCH

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

L3810

10NH-3%-140MA

01005

L3812

10NH-3%-140MA

01005

L3808

0201

L3809

0201

21

21

21

21

100_XCVR_B8_PRX_N

100_XCVR_B8_PRX_P

100_XCVR_B5_B18_PRX_N

100_XCVR_B5_B18_PRX_P

C3806

27PF

1 2

100_B7_B38_B40_PRX_MATCH_N

5%

16V

NP0-C0G

01005

C3807

27PF

1 2

100_B7_B38_B40_PRX_MATCH_P

5%

16V

NP0-C0G

01005

FIL_DIPLEXER_B38_B40

1
3

SAFEA2G35MB0F57

4 1

UNB_PORT2 UNB_PORT1

U3801

ACFM-2043-AP1

LGA

B38

CRITICAL

GND

524

U3802

TX-BAND40-LTE

LGA

CRITICAL

GND

235

29

OUT

29

OUT

29

OUT

29

OUT

0.6NH+/-0.1NH-0.85A

1

L3814

3.6NH+/-0.1NH-400MA

0201

2

0.6NH+/-0.1NH-0.85A

6

ANTB40

987

50_FULL_B40_SPDT_MATCH

L3813

21

0201

L3815

21

0201

1

L3820

3.3NH+/-0.1NH-0.45A

0201

CRITICAL

2

100_XCVR_B7_B38_B40_PRX_N

100_XCVR_B7_B38_B40_PRX_P

L3821

0

1 2

5%

1/20W

MF

201

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

29

OUT

29

OUT

50_B38_B40_SPDT

1

C3810

5.6NH-3%-0.35A

0201

CRITICAL

2

50_FULL_B40_SPDT

CELL: RX MATCHING

Apple Inc.

R

39

BI

39

BI

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-0886

A.0.0

38 OF 121

31 OF 54

SIZE

D

C

B

A

D

8 7 6 5 4 3

TX INTERSTAGE FILTERS

12

2.0NH+/-0.1NH-0.2A-1.35OHM

IN

50_XCVR_B2_TX

29

D

50_XCVR_B5_B18_TX

29

IN

IN

50_XCVR_B8_TX

29

C

50_XCVR_B20_TX

IN

B

C3901

01005

CRITICAL

C3903

0.00

1 2

0%

1/32W

MF

01005

C3904

0.00

1 2

0%

1/32W

MF

01005

C3905

0.00

1 2

0%

1/32W

MF

01005

21

50_B2_TX_SAW_IN

50_B5_B18_TX_SAW_IN

50_B8_TX_SAW_IN

50_B20_TX_SAW_IN

50_XCVR_B7_B38_B40_TX

29

IN

1

C3902

56PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

1

L3901

10NH-5%-140MA

01005

CRITICAL

2

1

L3902

10NH-5%-140MA

01005

CRITICAL

2

1

L3903

10NH-5%-140MA

01005

2

C3906

3.3PF

1 2

+/-0.1PF

16V

NP0-C0G

01005

FL3901

SATGR832MBM0F57

1

INPUT BAND2

3

INPUT BAND5+18

5

INPUT BAND8

2

CRITICAL

GND

468

LGA

14 25 33 39 40

50_XCVR_B7_B38_B40_TX_MATCH

1

C3907

1.5NH+/-0.1NH-220MA

01005

2

28 33

IN

OUTPUT BAND2

OUTPUT BAND5+18

OUTPUT BAND8

THRM

PAD

13

10

12

PP_LDO14_2V65

IN

PA_MB_CTL0

1

2

1

C3909

0.01UF

10%

6.3V

2

X5R
01005

C3908

56PF

5%
16V
NP0-C0G
01005

11

9

7

50_B2_TX_SAW_OUT

50_B5_TX_SAW_OUT

50_B8_TX_SAW_OUT

4

VDD

U3901

BGS12SL6

TSLP6-2

5

RFIN

CRITICAL

6

CTRL

GND

2

D

C3913

0.00

29

34

OUT

36

OUT

36

OUT

29

35 29

OUT

3

RF1

1

RF2

50_B38_B40_TX_SPDT_OUT

50_XCVR_B34_B39_TX

IN

50_XCVR_B1_B3_TX

IN

50_B7_TX_SPDT_OUT

1

C3911

56PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

C3912

100PF

1 2

NP0-C0G

01005

1 2

0%

1/32W

MF

01005

C3914

0.00

1 2

0%

1/32W

MF

01005

C3910

0.00

1 2

0%

1/32W

MF

01005

50_B7_TX_FILT_IN

50_B38_B40_TX_SPDT_MATCH

5%

16V

1

L3904

1.2NH+/-0.1NH-220MA

01005

NOSTUFF

2

50_B34_B39_TX_FILT_IN

1

L3905

2.7NH+/-0.1NH-200MA

01005

CRITICAL

2

50_B1_B3_TX_SAW_IN

1

L3906

2.0NH+/-0.1NH-0.2A-1.35OHM

01005

2

35

OUT

33

OUT

SAW-BAND-TX-B1-B3-B34-B39

1

IN B34/B39

4

IN B1/B3

FL3902

AF48

LGA

CRITICAL

GND

532

10

OUT B34
OUT B39

OUT B1
OUT B3

9
8

7
6

50_B1_TX_SAW_MATCH

50_B3_TX_SAW_MATCH

1.5NH+/-0.1NH-220MA

1

L3907

10NH-3%-140MA

01005

NOSTUFF

2

1.5NH+/-0.1NH-220MA

1

L3908

5.1NH-3%-0.16A

01005

NOSTUFF

2

L3909

01005

50_B34_TX_SAW_OUT
50_B39_TX_SAW_OUT

R3901

21

01005

21

50_B3_TX_SAW_OUT

OUT
OUT

50_B1_TX_SAW_OUT

OUT

33

33

33

OUT

34

C

B

w w w . c h i n a f i x . c o m

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: RF TRANSCEIVER (3 OF 4)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

051-0886

A.0.0

39 OF 121

32 OF 54

SIZE

A

D

8 7 6 5 4 3

BAND 1/34/39/38/40 TX

=PPBATT_VCC_BB

24 25 34 35 36 37 38 54

IN

PP_PA

34 35 36 37 38

IN

D

PA_BS

28 34 35 36

IN

PA_MB_CTL1

28

IN

PA_MB_CTL0

28 32

IN

PA_R1

28 34 35 36 37

IN

1

C4041

56PF

5%
16V

2

NP0-C0G
01005

32

IN

32

IN

C

32

IN

50_B38_B40_TX_SPDT_MATCH

32

IN

50_B1_TX_SAW_OUT

50_B34_TX_SAW_OUT

50_B39_TX_SAW_OUT

L4020

100PF

1 2

5%

16V

NP0-C0G

01005

1

C4038

1.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

1

C4039

1.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

1

C4040

18NH-3%-140MA

01005

2

50_B38_B40_TX_MATCH

B

L4029

0.00

1 2

0%

1/32W

MF

01005

L4030

0.00

1 2

0%

1/32W

MF

01005

L4044

0.00

1 2

0%

1/32W

MF

01005

L4045

4.0PF

1 2

1

2

+/-0.1PF

NP0-C0G

C4037

7.5NH-3%-0.140A

01005

01005

50_B1_PA_IN

50_B34_PA_IN

50_B39_PA_IN

50_B38_B40_PA_IN

16V

1

C4001

0.1UF

20%

6.3V

2

X5R-CERM
01005

1

C4042

56PF

5%
16V

2

NP0-C0G
01005

1

C4043

100PF

5%
16V

2

NP0-C0G
01005

1

C4052

56PF

5%
16V

2

NP0-C0G
01005

50_B1_PA_OUT

BAND PA POWER MODE PA_BS PA_CTL1 PA_CTL0 PA_R1
=======================================================

OFF X X 0 0 0
B1 HPM X 1 0 0
B1 LPM X 1 0 1
B34 HPM 1 0 1 0
B34 LPM 1 0 1 1

A

B39 HPM 0 0 1 0
B39 LPM 0 0 1 1
B38 HPM 1 1 1 0
B38 LPM 1 1 1 1
B40 HPM 0 1 1 0
B40 LPM 0 1 1 1

6 3

1

2

1

2

2

RFIN_B1

21

RFOUT_B1

5

RFIN_B34

4

RFIN_B39

19

RFOUT_B34/B39

6

RFIN_B38/B40

17

RFOUT_B38

15

RFOUT_B40

9

1

3.0PF

+/-0.05PF

1

2

C0G-CERM

C4064

10NH-3%-250MA

0201

C4002

1.0UF

20%

6.3V
X5R
0201-1

C4053

56PF

5%
16V
NP0-C0G
01005

C4047

1 2

0201

ACPM-7900-AP1

GND

14131618202322

25V

1

C4054

100PF

5%
16V

2

NP0-C0G
01005

7

3

11

VBS_2

VBS_1

VBS_0

VMODE

U4025

LLP

CRITICAL

25272829303132

1

C4046

15NH+/-3%-0.25A-0.7OHM

0201

2

w w w . c h i n a f i x . c o m

VCC

26810

VBATT

R4064

0.00

THRM

PAD

CPL_IN

CPL_OUT

12

50_MBPA_CPL_IN

24

50_B2_B3_CPL_IN

36

IN

34

OUT

50_B1_PA_OUT_MATCH

100_RX_MODULE_OUT_P

31

OUT

100_RX_MODULE_OUT_N

31

OUT

PP_LDO14_2V65

14 25 32 33 39 40

IN

50_B38_PA_OUT

1

2

50_B40_PA_OUT

1

2

50_B34_B39_PA_OUT

1 2

0%

1/32W

MF

01005

3P4T_SEL_0

28 33

IN

3P4T_SEL_1

28 33

IN

ANT_SEL_1

24 28 39 40

IN

ANT_SEL_0

28 39 40

IN

C4058

0

1 2

5%

1/20W

MF

C4060

56PF

5%
25V
NP0-C0G
201

NOSTUFF

C4061

201

C4048

0

1 2

5%

1/20W

MF

201

12NH+/-3%-0.25A-0.7OHM

0201

C4049

0

50_B34_B39_PA_FILT_IN

5%

1/20W

MF

201

15

17

11
12

14 25 32 33 39 40

IN

1 2

PP_LDO14_2V65

PP_LDO14_3P4T

1

C4075

56PF

5%
16V

2

NP0-C0G
01005

50_B38_PA_MATCH

50_B40_PA_MATCH

1

2

R4065

0.00

1 2

0%

1/32W

MF

01005

BAND1_TX

BAND1ANT

BAND1_34_39_DCSRXOUT0
BAND1_34_39_DCSRXOUT1

PP_LDO14_RX_MOD

1

C4073

56PF

5%
16V

2

NP0-C0G
01005

LMSWFKJM

THRM

PAD

19

20

1

C4072

56PF

5%
16V

2

NP0-C0G
01005

1

C4076

56PF

5%
16V

2

NP0-C0G
01005

FL4012

1880-2025MHZ

DEA162025LT-5046B1SJ

C4071

8.2NH+/-3%-0.25A-0.7OHM

0201

CRITICAL

VDD

LGA

1

IN/OUT

CRITICAL

6

U4027

LGA

CRITICAL

BAND34_39_RXIN

GND

13910

14

16

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

2

GND

5

1

2

OUT/IN

4

1

2

4

C4008

56PF

5%
16V
NP0-C0G
01005

C4074

0.1UF

20%

6.3V
X5R-CERM
01005

DCSRXIN

3

1

C4012

56PF

5%
16V

2

NP0-C0G
01005

3

50_B34_B39_PA_FILT_OUT

8

VC1

7

VC2

1

18

2

50_B1_RX_MOD_ANT

A1

VDD

VC1

SKY13477

VC2
VC4
VC3

U4000

BGA

CRITICAL

DGND

GND1

B2C5B3

B4

B1
C1
C2
A2

50_RX_MOD_DCS_IN

50_RX_MOD_B34_B39_IN

1

C4056

5.6NH-3%-0.35A

0201

CRITICAL

2

100PF

NP0-CERM

CRITICAL

RF1

C4

RF2

C3
B5
A4
A5
A3

50_3P4T_PRX_OUT

50_B40_FILTER

50_FULL_B40_FILTER

50_B38_FILTER

GND2

RF3

RF4
RF5
RF6
RF7

50_B7_RX_SP3T_IN

1

C4023

56PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

2.9NH+/-0.1NH-0.5A-0.2OHM

1

C4063

0.6PF

+/-0.05PF
25V

2

CERM
0201

CRITICAL

0%
MF

CRITICAL

1

C4034

56PF

5%
16V

2

NP0-C0G
01005

L4071

4.0PF

1 2

+/-0.1PF

25V

COG-CERM

0201

CRITICAL

1

C4055

0.5PF

+/-0.05PF
16V

2

NP0-C0G
01005

NOSTUFF

50_B34_B39_RX_ASM

1

2

C4033

56PF

5%
16V
NP0-C0G
01005

1 2

L4070

0.00

1/32W
01005

L4072

1 2

5%

25V

0201

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

1

L4097

7.5NH-0.30A

0201

CRITICAL

2

CELL: PENTABAND PA

Apple Inc.

R

L4012

0.00

1 2

50_B7_DUPLX_RX

0%

1/32W

MF

01005

L4083

1 2

0201

CRITICAL

3P4T_SEL_0
3P4T_SEL_1

50_DCS_RX_ASM

50_B1_ANT

12

31

OUT

31

BI

31

BI

31

BI

50_B34_B39_TX_ASM

28 33

IN

28 33

IN

39

IN

39

IN

39

BI

DRAWING NUMBER

051-0886

REVISION

BRANCH

PAGE

40 OF 121

SHEET

33 OF 54

124578

35

IN

A.0.0

D

C

39

OUT

B

A

SIZE

D

8 7 6 5 4 3

BAND 2/3 PAD

12

D

29

BS

VEN_B2_B3

THRM_PAD

31

PA_ON_B2_B3

PA_BS

PA_R1

24

VMODE

IN

CPL_IN

CPL_OUT

ANT_B3
ANT_B2

28 33 35 36

4
20

16
8

50_B2_B3_CPL_IN

50_B7_B20_CPL_IN

50_B3_DPLX_ANT
50_B2_DPLX_ANT

33

IN

35

OUT

3.0NH+/-0.1NH-0.45A

1

C4154

2

1

C4155

2

CRITICAL

L4136

0201

CRITICAL

0.5PF

+/-0.05PF
25V
COG-CERM
0201

CRITICAL

3.0NH+/-0.1NH-0.45A

0.6PF

+/-0.05PF
25V
CERM
0201

L4138

0201

CRITICAL

1

C4102

100PF

5%

6.3V

2

CERM
01005

21

1

C4150

0.5PF

+/-0.05PF
25V

2

CERM
201

NOSTUFF

50_B2_DPLX_ANT_MATCH

21

1

C4151

0.5PF

+/-0.05PF
25V

2

CERM
201

NOSTUFF

1

2

PP_PA

33 35 36 37 38

IN

=PPBATT_VCC_BB

24 25 33 35 36 37 38 54

IN

C4146

0.00

50_B3_TX_SAW_OUT

32

IN

1

L4122

2

C

32

IN

50_B2_TX_SAW_OUT

1

C4104

0.5PF

+/-0.05PF
16V

2

C0G-CERM
01005

NOSTUFF

1 2

0%

1/32W

MF

01005

9.1NH-3%-140MA

01005

NOSTUFF

2.7NH+/-0.1NH-200MA

L4123

01005

1

L4182

2.2NH+/-0.1NH-200MA

01005

NOSTUFF

2

21

1

C4147

0.5PF

+/-0.05PF
16V

2

C0G-CERM
01005

1

C4100

0.22UF

20%

6.3V

2

X5R
01005

50_B3_TX_PAD_IN
50_B2_TX_PAD_IN

1

C4101

0.22UF

20%

6.3V

2

X5R
01005

50_B2_DUPLX_RX
50_B3_DUPLX_RX

26
28

13
14

11
10

1

C4148

0.1UF

20%

6.3V

2

X5R-CERM
01005

RFIN_B3
RFIN_B2

RX_B3
GND

RX_B2
GND

1

376

5129

1

2

GND

OUT

OUT

C4149

1.0UF

20%

6.3V
X5R
0201-1

1517181921

31

31

VBATT

2

VCC

U4123

LGA

CRITICAL

27

23

22

30

25

TQM6M6224

C4103

100PF

5%

6.3V
CERM
01005

28

IN

28 33 35 36 37

IN

R4139

0.00

1 2

1%

1/20W

MF

0201

50_B3_ANT

50_B2_ANT

39

BI

39

BI

D

C

B

BAND PA POWER MODE PA_BS PA_ON_B2_B3 PA_R1

w w w . c h i n a f i x . c o m

=====================================================
OFF X X 0 X

A

B3 HPM 0 1 0
B3 LPM 0 1 1

B2 HPM 1 1 0
B2 LPM 1 1 1

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: BAND 2/3 PAD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

41 OF 121

SHEET

34 OF 54

124578

SIZE

B

A

D

8 7 6 5 4 3

BAND 20/7 PAD

12

D

PA_ON_B7_B20
PA_BS

IN

CPL_IN

CPL_OUT

ANT_B20

ANT_B7

403941

1

C4233

100PF

5%

6.3V

2

CERM
01005

28 33 34 36 37

42

1

C4239

100PF

5%

6.3V

2

CERM
01005

PP_PA

33 34 36 37 38

IN

=PPBATT_VCC_BB

24 25 33 34 36 37 38 54

IN

C4231

22PF

50_B7_TX_FILT_IN

32

IN

C

2

50_B20_TX_SAW_IN

32

IN

1 2

01005

C4216

2.2NH+/-0.1NH-200MA

01005

NOSTUFF

1

C4219

56PF

5%
16V

2

NP0-C0G
01005

NOSTUFF

5%

16V

CERM

C4218

56PF

1 2

50_B20_TX_SAW_MATCH

5%

16V

NP0-C0G

01005

50_B7_TX_FILT_MATCH

FL4211

SAWFD847MGA0F57

4

INPUT_BAND7

1 9

INPUT_BAND20

LGA

CRITICAL

GND
532

7

OUTPUT_BAND7

OUTPUT_BAND20

8

10

50_B20_TX_SAW_OUT

6

50_B7_TX_FILT_OUT

2.7NH+/-0.1NH-200MA

1

C4227

1.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

L4254

3.3NH+/-0.1NH-180MA

CRITICAL

L4253

01005

CRITICAL

01005

21

211

CRITICAL

1

C4228

0.8PF

2

NOSTUFF

+/-0.1PF
16V
NP0-C0G
01005

1

C4235

0.22UF

20%

6.3V

2

X5R
01005

50_B20_TX_PAD_IN
50_B7_TX_PAD_IN

1

C4232

0.22UF

20%

6.3V

2

X5R
01005

100_B20_DUPLX_RX_N

100_B20_DUPLX_RX_P

1

C4229

0.1UF

20%

6.3V

2

X5R-CERM
01005

26

RFIN_B20

28

RFIN_B7

12

RX_P_B20

13

RX_N_B20

11

RX_B7

10

GND

567

3

1

50_B7_DUPLX_RX

1

C4230

1.0UF

20%

6.3V

2

X5R
0201-1

VBATT

30

2

VCC

25

U4215

AFEM-790720

LGA

CRITICAL

GND

22

23

27

211918

17

15914

33

OUT

31

OUT

31

OUT

29

24

BS

VEN_B7_B20

313233

PA_R1

VMODE

THRM_PAD

3738363435

1

C4234

100PF

5%

6.3V

2

CERM
01005

50_B7_B20_CPL_IN

50_PDET_PAD_IN

4
20

16
8

50_B7_DPLX_ANT

34

IN

29

OUT

50_B20_DPLX_ANT

1

L4257

10NH-3%-250MA

0201

NOSTUFF

2

IN

IN

28

28 33 34 36

1

2

CELL

C4207

1.0PF

1 2

+/-0.1PF

16V

NP0-C0G

01005

CRITICAL

CELL

L4200

6.2NH-0.30A

0201

CRITICAL

2.2NH+/-0.1NH-0.6A

L4229

0.5PF

+/-0.05PF
25V
COG-CERM
0201

CRITICAL

21

50_B20_ANT

CELL

1

C4208

3.9PF

+/-0.1PF
25V

2

C0G-CERM
0201

CRITICAL

39

BI

C4236

21

0201

50_B7_ANT

1

L4228

0.5PF

+/-0.05PF
25V

2

CERM
201

NOSTUFF

39

BI

B

D

C

B

w w w . c h i n a f i x . c o m

BAND PA POWER MODE PA_BS PA_ON_B20_B7 PA_R1
=====================================================

A

OFF X X 0 X
B20 HPM 0 1 0

B20 LPM 0 1 1
B7 HPM 1 1 0

B7 LPM 1 1 1

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: BAND 7/20 PAD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

42 OF 121

SHEET

35 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

BAND 5/8 PAD

12

D

25

BS

VEN_B5_B8

3332313534

PA_ON_B5_B8
PA_BS
PA_R1

30

VMODE

THRM_PAD

36383741394042

IN

CPL_IN

CPL_OUT

ANT_B5
ANT_B8

28 33 34 35 37

4
20

16
8

1

C4324

100PF

5%

6.3V

2

CERM
01005

50_PA_ISO

50_MBPA_CPL_IN

28

IN

28 33 34 35

IN

1

C4325

100PF

5%

6.3V

2

CERM
01005

OUT

50_B5_DPLX_ANT

50_B8_DPLX_ANT

2.7NH+/-0.1NH-0.50A

1

L4316

0.5PF

+/-0.05PF
25V

2

COG-CERM
0201

CRITICAL

1

L4317

22NH-100MA

2

33

0201

NOSTUFF

C4320

0201

CRITICAL

C4321

18PF

1 2

2%

25V

C0H-CERM

0201

1

R4300

49.9

1%
1/32W
MF
01005

2

21

50_B5_ANT

50_B8_ANT

39

BI

39

BI

PP_PA

33 34 35 37 38

IN

=PPBATT_VCC_BB

24 25 33 34 35 37 38 54

IN

50_B5_TX_SAW_OUT

32

IN

50_B8_TX_SAW_OUT

32

IN

C

2.2NH+/-0.1NH-200MA

1

C4316

1.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

2.2NH+/-0.1NH-200MA

1

C4317

2.2PF

+/-0.1PF
16V

2

NP0-C0G
01005-1

CRITICAL

L4314

01005

CRITICAL

L4315

01005

CRITICAL

21

1

C4327

1.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

21

1

C4326

1.2PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

1

C4322

0.22UF

20%

6.3V

2

X5R
01005

50_B5_TX_PAD_IN
50_B8_TX_PAD_IN

1

C4323

0.22UF

20%

6.3V

2

X5R
01005

1

C4318

0.1UF

20%

6.3V

2

X5R-CERM
01005

26

RFIN_B5

28

RFIN_B8

13

RX_P_B5

14

RX_N_B5

11

RX_P_B8

10

RX_N_B8

1

376

5129

100_B8_DUPLX_RX_N
100_B8_DUPLX_RX_P
100_B5_DUPLX_RX_N
100_B5_DUPLX_RX_P

GND

1

C4319

2

1.0UF

20%

6.3V
X5R
0201-1

29

VBATT

SKY77493

1517181921

31

OUT

31

OUT

31

OUT

31

OUT

2

VCC

U4358

LGA

CRITICAL

27

23

22

24

D

C

B

w w w . c h i n a f i x . c o m

BAND PA POWER MODE PA_BS PA_ON_B5_B8 PA_R1
=====================================================

A

OFF X X 0 X
B5 HPM 0 1 0

B5 LPM 0 1 1
B8 HPM 1 1 0

B8 LPM 1 1 1

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: BAND 5/8 PAD

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

43 OF 121

SHEET

36 OF 54

124578

SIZE

B

A

D

8 7 6 5 4 3

12

2G PA

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

D

PP_PA

33 34 35 36 38

IN

C

1

C4471

6.0PF

+/-0.1PF
16V

2

NP0-C0G
01005

NOSTUFF

C4472

12PF

1 21 2

5%

16V

CERM

01005

50_TX_G_HB_PAIN

C4484

33PF

50_TX_G_LB_PAIN

1 2

5%

16V

NP0-C0G

01005

C4467

50_XCVR_2G_HB_TX

29

IN

IN

50_XCVR_2G_LB_TX

29

2.7PF

+/-0.1PF

NP0-C0G
01005-1

16V

L4435

0.00

1 2

1/32W
01005

CRITICAL

50_TX_G_HB_MCH

1

L4436

2.7NH+/-0.1NH-200MA

01005

2

0%
MF

50_TX_G_LB_MCH

B

24 25 33 34 35 36 38 54

IN

28 33 34 35 36

IN

28

IN

28

IN

=PPBATT_VCC_BB

PA_R1
GSM_PA_LB_EN

GSM_PA_HB_EN

240OHM-350MA

1

C4489

56PF

5%
16V

2

NP0-C0G
01005

1

C4483

100PF

5%
16V

2

NP0-C0G
01005

L4440

0201

1

C4485

4.7UF

20%

6.3V

2

X5R-CERM1
402

1

C4486

2

21

100PF

5%
16V
NP0-C0G
01005

1

C4488

0.1UF

20%
4V

2

X5R
01005

PP_BATT_VCC_2G_PA

1

C4487

1.0UF

20%
10V

2

X5R-CERM
0201-1

U4410

HB_GSM_RF_IN

LB_GSM_RF_IN

VMODE0

PA_ON2
PA_ON3

GND

GND

GND

GND

9

2

SKY77355

CRITICAL

GND

15

131210

1

3

6
4

5

7

14

V2G

VBATT

LGA

THRM_PAD

THRM_PAD

THRM_PAD

HB_GSM_RF_OUT

LB_GSM_RF_OUT

THRM_PAD

THRM_PAD

THRM_PAD

THRM_PAD

THRM_PAD

22212019181716

THRM_PAD

23

11

50_TX_G_HB_PAOUT

8

50_TX_G_LB_PAOUT

2G PA GAIN MODES

BAND

=======================================================

LOW BAND
LOW BAND
LOW BAND
LOW BAND
HIGH BAND
HIGH BAND
HIGH BAND
LOW BAND
LOW BAND
LOW BAND
HIGH BAND
HIGH BAND

3.2NH+/-0.1NH-0.45A-025OHM

L4437

0201

CRITICAL

R4437

0.00

1 2

1/20W

0201

21

1%
MF

MODE

GSM
GSM
GSM
GSM
GSM
GSM
GSM
EDGE
EDGE
EDGE
EDGE
EDGE

1

L4438

3.6NH+/-0.1NH-400MA

0201

NOSTUFF

2

1

L4439

3.6NH+/-0.1NH-400MA

0201

NOSTUFF

2

GAIN MODE
ULTRA LOW

LOW

MEDIUM

HIGH

ULTRA LOW

LOW

HIGH

LOW

MEDIUM

HIGH

LOW

HIGH

50_TX_G_HB_ASM

50_TX_G_LB_ASM

PA_R1
HIGH

HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW

OUT

OUT

39

39

PCL RANGE

16 TO 19
14 TO 15
7 TO 13
5 TO 6
10 TO 15
7 TO 9
0 TO 6
15 TO 19
10 TO 14
8 TO 9
9 TO 15
2 TO 8

D

C

B

w w w . c h i n a f i x . c o m

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: 2G PA

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

44 OF 121

SHEET

37 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

PA DC/DC CONVERTER

12

D

=PPBATT_VCC_BB

24 25 33 34 35 36 37 54

IN

C

PLACE NEAR U1.H3

R4500

1.00K

BB_PDM

28

IN

1 2

1%

1/32W

MF

01005

BB_PDM_FILT

1

C4500

1000PF

10%

6.3V

2

X5R-CERM
01005

PLACE NEAR U11.D2

R4534

1.00K

1 2

1%

1/32W

MF

01005

1

C4545

1000PF

10%

6.3V

2

X5R-CERM
01005

1

C4502

56PF

5%
16V

2

NP0-C0G
01005

DCDC_ADJ

28

1

2

28

IN

C4503

0.01UF

10%

6.3V
X5R
01005

IN

DCDC_MODE

DCDC_EN

1

C4504

10UF

20%

6.3V

2

CERM
0402

D1

B3

A3

PVIN

VDD

U4500

LM3258

EN

BP

MODE

VCON

BGA

CRITICAL

PGND

B1

A1

SGND

C1

BGND

C4

C2

C3

D3

D2

ACB
ACB

DCDC_OUT

A2

SW

B2

SW

D4

FB

A4
B4

L4500

1.5UH-2.0A-0.137OHM

1 2

PIFE20161T-SM

CRITICAL

CRITICAL

1

C4507

10UF

20%

6.3V

2

CERM-X5R
0402

PP_PA

CRITICAL

1

C4508

3300PF

10%

6.3V

2

X5R
01005

OUT

33 34 35 36 37

D

C

B

B

w w w . c h i n a f i x . c o m

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: PA DCDC CONVERTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

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BRANCH

PAGE

SHEET

124578

051-0886

A.0.0

45 OF 121

38 OF 54

SIZE

A

D

8 7 6 5 4 3

PRIMARY ASM

12

D

PP_LDO14_2V65

14 25 32 33 39 40

IN

1

C4669

100PF

1 = PARTIAL B40
0 = FULL B40

C4640

1.8NH+/-0.1NH-600MA

C

IN

PP_LDO14_2V65

4
5
6
7

8
14
15
16
17
18

TRX1
TRX2
TRX3
TRX4
TRX5
TRX6
TRX7
TRX8
TRX9
TRX10

1

U4617

CRITICAL

GND

GND

9

26

LGA

GND

11

VDD

RF1495

GND

13

ANT1
ANT2

HBTX
LBTX

THRM

27

PAD

RF1
RF2

VC1
VC2
VC3
VC4
VC5

1

C4622

100PF

5%

6.3V

2

CERM
01005

2
20

50_ANT2_TERM

10

50_TX_G_HB_ASM

12

50_TX_G_LB_ASM

3

50_TXRX_B38_B40_ASM

19

50_RF2_TERM

21
22
23
24
25

50_ASM_ANT

1

C4641

0.1UF

20%
4V

2

X5R
01005

1

R4607

49.9

1%
1/20W
MF
201

2

1

R4608

49.9

1%
1/20W
MF
201

2

1

C4639

100PF

5%

6.3V

2

CERM
01005

R4605

0

1 2

5%

1/20W

MF

201

37

IN

37

IN

1

C4663

100PF

5%

6.3V

2

CERM
01005

1

C4664

100PF

5%

6.3V

2

CERM
01005

14 25 32 33 39 40

50_B3_ANT

34

BI

50_B2_ANT

34

BI

50_B34_B39_RX_ASM

33

BI

50_B20_ANT

35

BI

50_B7_ANT

35

BI

50_B5_ANT

36

BI

50_B8_ANT

36

BI

50_DCS_RX_ASM

33

BI

50_B1_ANT

33

B

BI

33

BI

50_B34_B39_TX_ASM

0201

21

1

L4613

56NH-100MA-3.9OHM

0201

2

1

C4665

100PF

5%

6.3V

2

CERM
01005

1

L4642

0.3PF

+/-0.1PF
25V

2

C0G-CERM
201

ANT_SEL_0
ANT_SEL_1
ANT_SEL_2
ANT_SEL_3
ANT_SEL_4

1

2

C4666

100PF

5%

6.3V
CERM
01005

50_TXRX_B38_B40_SPDT

B40_FILT_SELECT

28

IN

50_PRI_ANT_COAX

28 33 40

IN

24 28 33 40

IN

24 28 40

IN

28 40

IN

28

IN

42

BI

2

1

C4668

100PF

5%

6.3V

2

CERM
01005

5%

6.3V
CERM
01005

6

RF1

1

VC

5

VDD

SW4601

CXA4403GC

XFLGA

CRITICAL

GND

3

RF2

RF3

4

2

50_FULL_B40_SPDT

50_B38_B40_SPDT

31

BI

31

BI

D

C

B

w w w . c h i n a f i x . c o m

A

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PAGE TITLE

CELL: ASM AND HB LTE FRONT-END

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

DRAWING NUMBER

051-0886

REVISION

BRANCH

PAGE

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SHEET

39 OF 54

124578

A.0.0

SIZE

A

D

8 7 6 5 4 3

RX DIVERSITY

12

SIZE

D

C

B

A

D

D

CRITICAL

R4701

0

50_DRX_ANT

41

IN

28 33 39

IN

24 28 33 39

IN

24 28 39

IN

28 39

C

IN

100_XCVR_GPS_RX_N

29

OUT

100_XCVR_GPS_RX_P

29

OUT

41

IN

1

C4710

56PF

5%
16V

2

NP0-C0G
01005

50_GPS_LNA_OUT

1 2

5%

1/20W

MF

201

1

C4736

56PF

5%
16V

2

NP0-C0G
01005

B

R4711

5.6PF

1 2

50_B38_B40_DRX_AUX2_OUT

+/-0.1PF

1

NP0-C0G

C4708

2.3NH+/-0.1NH-0.50A-0.2OHM

0201

2

A

50_B38_B40_DRX_FILT_IN

25V

0201

1

w w w . c h i n a f i x . c o m

L4765

3.0NH+/-0.1NH-0.45A

0201

NOSTUFF

2

50_DRX_ASM_MCH

1

NOSTUFF

L4743

3.0NH+/-0.1NH-0.45A

0201

2

C4737

56PF

5%
16V
NP0-C0G
01005

21

21

U4722

885035

LGA

GND

1

2

1

2

C4755

5.6NH-3%-140MA

01005

C4756

5.6NH-3%-140MA

01005

BAW-DUAL-RX-B38-B40

8

B38_ANT

7

B40_ANT

C4738

56PF

5%
16V
NP0-C0G
01005

1

L4742

4.7NH-3%-160MA

01005

2

1

NOSTUFF

L4740

10NH-3%-140MA

01005

2

B38_RX

B40_RX

96532

10

C4794

27PF

1 2

5%

6.3V

NP0-C0G

0201

C4797

56PF

1 2

5%

16V

NP0-C0G

01005

1

50_B38_DRX_FILT_OUT

4

50_B40_DRX_FILT_OUT

1

C4799

6.8NH-3%-0.3A

0201

2

1

2

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST

6 3

PP_LDO14_2V65

14 25 32 33 39

IN

50_DIVERSITY_SWITCH_MATCH

100_XCVR_GPS_RX_MATCH_N
100_XCVR_GPS_RX_MATCH_P

50_GPS_DRX_MOD_IN

L4746

0

50_B38_DRX_MOD_IN

1 2

5%

1/20W

MF

201

CRITICAL

L4747

0

5%

1/20W

MF
201

50_B40_DRX_MOD_IN

1 2

L4701

5.6NH-3%-0.35A

0201

CRITICAL

ANT_SEL_0
ANT_SEL_1
ANT_SEL_2
ANT_SEL_3

1

C4798

0.01UF

10%

6.3V

2

X5R
01005

17
18
14

12
11

1

ANTENNA

6

VC1

5

VC2

4

VC3

3

VC4

GPS OUT
GPS OUT
GPS IN

BAND 38 IN
BAND 40 IN

GND

2

GND

GND

8

10

1

C4739

56PF

5%
16V

2

NP0-C0G
01005

HFQSWBUUA-239

CRITICAL

GND

GND

GND

GND

1315162728

7

VDD

U4714

LGA

BAND 5+18 OUT
BAND 5+18 OUT

BAND 8,20 OUT
BAND 8,20 OUT

BAND 7,38,40 OUT
BAND 7,38,40 OUT

BAND 1,2,3,34,39 OUT
BAND 1,2,3,34,39 OUT

GND

GND

GND

GND

GND

GND

343235

31

30

29

AUX1
AUX2

THRM

PAD

363738

25

100_XCVR_B5_B18_DRX_P
100_XCVR_B5_B18_DRX_N

26

100_XCVR_B8_B20_DRX_P

23

100_XCVR_B8_B20_DRX_N

24

19

100_XCVR_B7_B38_B40_DRX_P

20

100_XCVR_B7_B38_B40_DRX_N

21

100_XCVR_B1_B2_B3_B34_B39_DRX_P

22

100_XCVR_B1_B2_B3_B34_B39_DRX_N

33

50_DRX_MOD_TERM

9

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

29

OUT

1

R4739

49.9

1%
1/20W
MF
201

2

PAGE TITLE

CELL: RX DIVERSITY

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

47 OF 121

SHEET

40 OF 54

124578

8 7 6 5 4 3

GPS

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.

12

D

CELL

PP_GPS_LNA_2V5

150OHM-25%-200MA-0.7DCR

787MHZ TRAP

CELL

CELL

FL4801

SASLE1G58AB0F57

CELL

L4801

0

50_GPS_DIV_TRI_ANT

50_GPS_DIV_SW_CONN

41

C

1

L4802

27NH-3%-0.140A-2.3OHM

0201

NOSTUFF

2

1 2

5%

1/20W

MF

201

CRITICAL

1

L4803

10NH-3%-250MA

0201

NOSTUFF

2

ANT

LGA

GND

542

GPS/GNSS

8

7

HB/LB

9

8.2NH+/-3%-0.25A-0.7OHM

1

50_GPS_FILT1

36

L4804

0201

CRITICAL

CELL

C4803

5.0PF

1 2

+/-0.1PF

25V
C0G

0201

CRITICAL

21

50_GPS_FILT2 50_GPS_FILT4

50_GPS_FILT3

2400MHZ TRAP

CELL

L4806

4.7NH-3%-0.35A

0201

CRITICAL

CELL

C4805

0.9PF

1 2

+/-0.05PF

16V

CERM

1

L4805

15NH+/-3%-0.25A-0.7OHM

0201

CELL
CRITICAL

2

1

C4804

1.8PF

+/-0.1PF
16V

2

NP0-C0G
01005-1

CELL
CRITICAL

01005

CRITICAL

900MHZ TRAP

2

5

AI

VCC

CELL

U4801

BGA824N6

TSNP6

CRITICAL

GND

GND

1

3

A0

6

PON

4

21

CRITICAL
CELL

C4807

2.0NH+/-0.1NH-0.6A

0201

1

L4807

1.3PF

+/-0.1PF
25V

2

C0G-CERM
201

NOSTUFF

21

50_GPS_LNA_IN

FL4802

01005

CELL

1

C4809

0.1UF

20%

6.3V

2

X5R-CERM
01005

CRITICAL

50_GPS_LNA_OUT

CRITICAL

21

PP_LDO5_GPS_LNA_2V5

40

OUT

25

IN

D

C

50_DRX_ANT

B

GPS_DRX_ANT

CELL

J4800

MM5829-2700

F-ST-SM

1

423

50_GPS_ANT_COAX

1

C4801

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

NOSTUFF

TOP MOUNT

A

6 3

CELL

R4801

0

1 2

5%

1/20W

MF

201

CRITICAL

1

C4802

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

NOSTUFF

w w w . c h i n a f i x . c o m

40

OUT

B

CELL

J4802

MM8930-2600B

F-RT-SM

GND

5

623

4

1

CR

50_GPS_DIV_SW_CONN

41

50_GPS_ANT_TEST

TOP MOUNT

SIZE

A

D

SYNC_MASTER=RADIO_MLB_87

PAGE TITLE

CELL: GPS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/29/2013

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

48 OF 121

SHEET

41 OF 54

124578

8 7 6 5 4 3

ANTENNA FEEDS

12

D

C

D

C

PRI_ANT COAX

CELL

J4910

MM5829-2700

F-ST-SM

1

423

50_PRI_ANT_COAX

39

BI

B

B

w w w . c h i n a f i x . c o m

A

6 3

SYNC_MASTER=RADIO_MLB_87

PAGE TITLE

CELL: ANTENNA FEEDS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=10/29/2013

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

49 OF 121

SHEET

42 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

NOSTUFF

J5700

MLB-X200

SPKR_R_CONN_N

16 43 52

SPKR_R_CONN_P

D

16 43 52

CONN_DET_L

43

E75_DPAIR2_CONN_N

43 52

PPVBUS_E75_USB_CONN

43

E75_DPAIR1_CONN_N

43 52

SPKR_L_CONN_N

16 43 52

SPKR_L_CONN_P

16 43 52

NOTE: SPKR_L_CONN_N AND SPKR_L_CONN_P WERE SWAPPED ON 5/22/12 PER RADAR #11526818

HB-SM

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SPKR_R_CONN_N
SPKR_R_CONN_P

PPOUT_E75_ACC_ID2_CONN

E75_DPAIR2_CONN_P

PPVBUS_E75_USB_CONN

PPOUT_E75_ACC_ID1_CONN

E75_DPAIR1_CONN_P

SPKR_L_CONN_N
SPKR_L_CONN_P

16 43 52

16 43 52

43 52

43 52

43

43 52

43 52

16 43 52

16 43 52

PPVBUS_E75_USB_CONN

43

2

DZ5700

27V-100PF

0402

1

1

C5700

27PF

1%
25V

2

NP0-C0G
201

C

=PPVCC_MAIN_DOCK

CONN_DET_L

43

54

CRITICAL

C

DZ5702

14.2V-6PF

0201-1

A

1

C5704

6.8PF

+/-0.25PF
25V

2

CERM
201

NOSTUFF

1

R5705

100K

1%
1/32W
MF
01005

2

R5706

10K

1 2

1%

1/32W

MF

01005

CRITICAL

K

DZ5710

SM-201

DSF01S30SC

A

NOSTUFF

R5790

0.00

1 2

0%

1/32W

MF

01005

TS_CON_DET_L

1

R5791

0.00

0%
1/32W
MF
01005

2

B

L5701

0201

0.055 OHM DCR

21

PPOUT_E75_ACC_ID1

11

PPOUT_E75_ACC_ID1_CONN

43 52

CRITICAL

C

DZ5703

14.2V-6PF

0201-1

A

1

C5705

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

FERR-22-OHM-1A-0.055OHM

L5700

FERR-70-OHM-4A

1

C5701

0.01UF

10%
25V

2

X7R
402

PMU_E75_ACC_DET_L

11

OUT

0603

21

1

R5700

100K

1%
1/20W
MF
201

2

48

OUT

1

C5702

27PF

1%
25V

2

NP0-C0G
201

=PPVBUS_USB_EMI

1

C5703

6.8PF

+/-0.25PF
25V

2

CERM
201

54

L5703

90-OHM-50MA

TCM0605-1

E75_DPAIR1_CONN_P

43 52

E75_DPAIR1_CONN_N

43 52

E75_DPAIR2_CONN_P

43 52

E75_DPAIR2_CONN_N

43 52

2

1

2

1

CRITICAL

D5700

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D5701

ESD0P2RF-02LS

TSSLP-2-1

2

1

2

1

CRITICAL

D5702

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

D5703

ESD0P2RF-02LS

TSSLP-2-1

SYM_VER-1

1

L5704

90-OHM-50MA

TCM0605-1

SYM_VER-1

1

4

32

4

32

E75_DPAIR1_P

E75_DPAIR1_N

E75_DPAIR2_P

E75_DPAIR2_N

12

D

C

11

11

11

11

B

w w w . c h i n a f i x . c o m

PPOUT_E75_ACC_ID2_CONN

43 52

A

CRITICAL

C

DZ5704

14.2V-6PF

0201-1

A

1

C5707

8.2PF

+/-0.5PF
16V

2

NP0-C0G-CERM
01005

FERR-22-OHM-1A-0.055OHM

6 3

L5702

0201

0.055 OHM DCR

21

PPOUT_E75_ACC_ID2

11

SIZE

A

D

SYNC_MASTER=N/A

PAGE TITLE

IO: FILTERS & HOTBAR CONN

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=04/18/2011

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

57 OF 121

SHEET

43 OF 54

124578

D

C

B

48 52

IN

48 52

IN

48 52

IN

24 28

OUT

24 28

IN

5

53

OUT

5

53

IN

5

53

IN

CRITICAL

U5810

2.4-5.0GHZ

LOW(2.4GHZ)

HIGH(5.0GHZ)

ANT(COMMON)

GND

642

CRITICAL

J5810

MM4829-2702

F-ST-SM

423

8 7 6 5 4 3

WIFI/BT: MODULE

MODULE ISOLATION

XW5890

PMU_GPIO_WLAN_REG_ON

PMU_GPIO_BT_REG_ON

PMU_GPIO_CLK_32K_WLAN

UART_WLAN2BB_LTE_COEX

UART_BB2WLAN_LTE_COEX

UART2_WLAN2SOC_TX

UART2_SOC2WLAN_TX

HSIC1_SOC2WLAN_HOST_RDY

SM

1

RF_0_ANT

NOSTUFF

1

C5817

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

3

1

5

CRITICAL

R5810

0.00

1 2

1/20W

0201

RF_G_0_DIPLEXER

RF_0_ANT_MATCH_T

1%
MF

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

SHORT-10L-0.25MM-SM

NOSTUFF

1

C5816

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

XW5891

XW5892

XW5893

XW5894

XW5895

XW5896

XW5897

CRITICAL

R5830

1/20W

0.00

1 2

0201

21

PMU_GPIO_WLAN_REG_ON_R

21

PMU_GPIO_BT_REG_ON_R

21

PMU_GPIO_CLK_32K_WLAN_R

21

21

21

21

21

1%
MF

UART_WLAN2BB_LTE_COEX_R

UART_BB2WLAN_LTE_COEX_R

UART2_WLAN2SOC_TX_R

UART2_SOC2WLAN_TX_R

HSIC1_SOC2WLAN_HOST_RDY_R

1

CRITICAL

L5811

10NH-3%-250MA

0201

2

44

44

44

44

44

44

44

44

CRITICAL

U5811

BAW-2436MHZ

885061

LGA

GND

235

INOUT

=PP1V8_S2R_VDDIO_WLAN_BT

NOSTUFF

1

R5805

10K

5%
1/32W
MF
01005

2

JTAG_WLAN_SEL

52

1

R5800

10K

5%
1/32W
MF
01005

2

RF_G_0_BAW_MODRF_G_0_BAW_ANT

14

RF_A_0_DIPLEXER

=PPVCC_MAIN_WLAN

54

PMU_GPIO_CLK_32K_WLAN_R

44

PMU_GPIO_WLAN_REG_ON_R

44

PMU_GPIO_BT_REG_ON_R

44

HSIC1_WLAN_DATA

4

53

BI

HSIC1_WLAN_STB

4

53

BI

CRITICAL

C5811

2.0NH+/-0.1NH-0.6A

1

CRITICAL

L5810

8.2NH+/-3%-0.25A-0.7OHM

0201

2

CRITICAL

C5814

1.0NH+/-0.1NH-0.75A

NOSTUFF

1

C5815

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

0201

0201

21

21

44 54

RF_G_0_MATCH_MOD

CRITICAL

1

C5810

0.5PF

+/-0.05PF
25V

2

CERM
201

RF_A_0_MATCH

CRITICAL

1

C5813

0.2PF

+/-0.05PF
25V

2

COG-CERM
0201

1

C5880

10UF

20%

6.3V

2

CERM-X5R
0402-2

NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC

1

C5881

10UF

20%

6.3V

2

CERM-X5R
0402-2

33

CLK_32K

4

WL_REG_ON

3

BT_REG_ON

23

JTAG_SEL

13

HSIC_DATA

14

HSIC_STROBE

7

SDIO_CLK

6

SDIO_CMD

8

SDIO_DATA0

9

SDIO_DATA1

10

SDIO_DATA2

11

SDIO_DATA3

77

RF_SW_CTRL11

47

I2SWS

46

I2SDO

48

I2SDI

49

I2SCLK

67

RF_A_0

79

RF_A_1

62

RF_G_0

74

RF_G_1

1

C5882

10UF

20%

6.3V

2

CERM-X5R
0402-2

17

16

71

70

VBAT

VBAT

RF_VCC_FEM

RF_VCC_FEM

CRITICAL

U5800

WIFI-BT-DOPPELBOCK

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

5

121815213234404554585960616364656668697372757678808182838485868788

GND_SIGNAL

=PP3V3_S2R_WIFI_PA

1

C5800

4.7UF

20%

6.3V

2

X5R-CERM1
402

LGA

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

1

C5801

4.7UF

20%

6.3V

2

X5R-CERM1
402

BT_GPIO5/LTE_COEX_UART_TX
BT_GPIO4/LTE_COEX_UART_RX

BT_GPIO1/HOSTWAKE

GPIO0/WL_HOST_WAKE

GPIO9/AGG_CHANNEL

GPIO10/HSIC_DEVICE_READY

GPIO11/HSIC_RESUME
GPIO15/WLAN_UART_TX
GPIO14/WLAN_UART_RX

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

54

BT_GPIO0/BTWAKE

BT_UART_RXD

BT_UART_TXD
BT_UART_RTS*
BT_UART_CTS*

BT_PCM_CLK

BT_PCM_SYNC

BT_PCM_OUT

BT_PCM_IN

GPIO1/HOST_READY

GPIO2/WL_TCK
GPIO3/WL_TMS
GPIO4/WL_TDI
GPIO5/WL_TDO

GPIO12/WL_TRST*

GPIO6
GPIO7
GPIO8

DUMMY

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

GND_SIGNAL

51

UART_WLAN2BB_LTE_COEX_R

50

UART_BB2WLAN_LTE_COEX_R

55

PMU_GPIO_BT_HOST_WAKE
GPIO_BT_WAKE

56

UART1_SOC2BT_TX

37

UART1_BT2SOC_TX

38

UART1_BT2SOC_RTS_L

36

UART1_SOC2BT_RTS_L

39

I2S4_SOC2BT_BCLK

41
42

I2S4_SOC2BT_LRCK
I2S4_BT2SOC_DATA

43

I2S4_SOC2BT_DATA

44

22

PMU_GPIO_WLAN_HOST_WAKE
HSIC1_SOC2WLAN_HOST_RDY_R

20

TP_JTAG_WLAN_TCK

27
28

JTAG_WLAN_TMS_TX_BLANK

26

JTAG_WLAN_TDI_OSCAR_A

24

JTAG_WLAN_TDO_OSCAR_B

25

TP_JTAG_WLAN_TRST_L

19

NC

1

HSIC1_WLAN2SOC_DEVICE_RDY

2

HSIC1_WLAN2SOC_REMOTE_WAKE

52

UART2_WLAN2SOC_TX_R

53

UART2_SOC2WLAN_TX_R

30

NC

29

WLAN_GPIO7

31

NC

35

VIO

=PP1V8_S2R_VDDIO_WLAN_BT

57

NC

12

D

44

44

48 52

OUT

5

53

IN

5

53

IN

5

53

OUT

5

OUT

5

IN

10

IN

10

IN

10

OUT

10

IN

48 53

OUT

44

52

52

5

OUT

5

OUT

44

44

44 54

53

53

R5804

0.00

1 2

R5801

0.00

1 2

0%

1/32W

MF

01005

R5802

0.00

1 2

0%

1/32W

MF

01005

WLAN_TX_BLANK

0%

1/32W

MF

01005

OSCAR2RADIO_CONTEXT_A

OSCAR2RADIO_CONTEXT_B

=PP1V8_S2R_VDDIO_WLAN_BT

1

R5803

10K

5%
1/32W
MF
01005

2

IN

IN

IN

C

28 52

19 28 52

19 28 52

44 54

B

A

CRITICAL

J5820

MM4829-2702

F-ST-SM

423

1

RF_1_ANT

NOSTUFF

1

C5827

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

CRITICAL

R5820

0.00

1 2

1%

1/20W

MF

0201

RF_1_ANT_MATCH_T

NOSTUFF

1

C5826

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

CRITICAL

U5820

DPX205850DT-9038A1SJ

SM

GND

1

HI

3

LO

246

5

COM

CRITICAL

C5821

RF_G_1_DIPLEXER

w w w . c h i n a f i x . c o m

RF_A_1_DIPLEXER

NOSTUFF

1

C5822

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

CRITICAL

C5824

1.0NH+/-0.1NH-0.75A

NOSTUFF

1

C5825

0.2PF

+/-0.1PF
25V

2

COG-CERM
201

1.1NH+/-0.1NH

0201

0201

21

RF_G_1_MATCH_MOD

CRITICAL

1

C5820

0.5PF

+/-0.05PF
25V

2

CERM
201

21

RF_A_1_MATCH

CRITICAL

1

C5823

0.2PF

+/-0.05PF
25V

2

COG-CERM
0201

6 3

PAGE TITLE

WIFI/BT: MODULE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=05/20/2013SYNC_MASTER=WIFI_DEV

DRAWING NUMBER

051-0886

REVISION

BRANCH

PAGE

SHEET

124578

A.0.0

58 OF 121

44 OF 54

SIZE

A

D

8 7 6 5 4 3

12

D

XW7520

SM

BATT_SNS

46

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

=PPBATT_POS_CONN

45 54

240-OHM-0.2A-0.8-OHM

UART5_BATT_RTXD

5

48

45 48 52

BI

BI

BATT_NTC

NET_SPACING_TYPE=ANLG

C

1 2

FL7500

0201-2

21

C7522

33PF

NP0-C0G

01005

TP7500

A

TP-P55

NOSTUFF

1

5%

16V

2

1

C7523

33PF

NP0-C0G

01005

P/N 516S0906

CRITICAL

J7500

CPB2304-0101F

F-ST-SM

13

10

BATT_SWI_CONN

45

C7524

1000PF

X7R-CERM

0201

1

10%
16V

2

C7525

27PF

NP0-C0G

01005

1

5%

16V

2

C7526

4.7PF

+/-0.1PF

NP0-C0G

01005

1

16V

2

TP7501

1

A

TP-P55

NOSTUFF

1

5%

16V

2

9

2 1
4 3
6 5
8 7

11
14

=PPBATT_POS_CONN

BATT_SWI_CONN

BATT_NTC

12

45 54

45

45 48 52

D

C

PART NUMBER

155S0644

FL7500,L1702,L1800,L1920,L2602,L2700,L2701,L2702,L2800,L2960,L2961,L2962,L2963,L38014_RF

ALTERNATE FOR
PART NUMBER

155S0823

BOM OPTION

REF DES

COMMENTS:

RADAR:8391945

TABLE_ALT_HEAD

TABLE_ALT_ITEM

B

TP7503

1

A

TP-P55

NOSTUFF

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=N/A

PAGE TITLE

POWER: BATTERY CONNECTOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=N/A

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

75 OF 121

SHEET

45 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

PLACEMENT_NOTE=PLACE NEAR L8225.1

CRITICAL

C8190

100UF

20%

6.3V

TANT-POLY

B1G-1

VCC_MAIN BYPASS

PLACE TWO 10UF CAP
AT EACH VDD INPUT

D

PPVCC_MAIN

46 47 48 49 52 54

OVP_SW_EN_L

11 46

MOSFET
CHANNEL

C

RDS(ON)
IMAX
VGS MAX

FDMC6676BZ
P-TYPE
27 MOHM @-4.5V

6.9 A
+/- 25V

NOSTUFF

1

R8116

470K

1%

1/20W

MF

201

2

USB REVERSE VOLTAGE PROTECTION

B

=PPVCC_MAIN_CPU

46 54

=PPVCC_MAIN_GPU

46 54

=PPVCC_MAIN_SOC

46 54

A

PLACEMENT_NOTE=PLACE NEAR L8225.1

CRITICAL

1

C8140

100UF

20%

6.3V

2

TANT-POLY

B1G-1

NOSTUFF

R8170

4.7K

1 2

5%

1/20W

MF

201

CRITICAL

Q8123

FDMC6676BZ

MLP3.3X3.3

PPVBUS_USB_DCIN

52 54

CRITICAL

1

C8175

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8182

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8187

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8141

100UF

20%

6.3V

2

TANT-POLY

B1G-1

ESR MAX=70MOHMESR MAX=70MOHM

CRITICAL

1

C8160

10UF

20%

6.3V

2

CERM-X5R
0402

RDSON=0.0136@VGS=-2.5V
ID=12.0A

321

S

D

1

2

CRITICAL

1

2

G

5

CRITICAL

1

C8176

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8183

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8188

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

2

C8161

10UF

20%

6.3V
CERM-X5R
0402

PPBATT_VCC

46 52 54

ACT_DIO

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=ANLG

4

R8130

220K

1/20W

C8150

10UF

20%

6.3V
CERM-X5R
0402

CRITICAL

1

C8162

10UF

20%

6.3V

2

CERM-X5R
0402

4

G

USB_VBUS_DETECT

4

KA

NOTE: 10V ZENER

VBUS_PROT_G

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=ANLG

1

1%
MF

201

2

CRITICAL

1

C8177

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8184

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8151

10UF

20%

6.3V

2

CERM-X5R
0402

1

2

1 253

S

CRITICAL

Q8104

FDMC6683

MLP3.3X3.3

D

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6.0V

CRITICAL

DZ8120

BZT52C10LP

LLP

11 46

CRITICAL

1

10UF

2

1

2

CRITICAL CRITICAL

1

C8152

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

C8163

10UF

20%

6.3V
CERM-X5R
0402

2.2UH-20%-5.5A-0.054OHM

PPVBUS_PROT

11 52

OVP_SW_EN_L

LAYOUT NOTE:
R8146, C8146 CAN BE
ANYWHERE BET.TRISTAR
AND PMU

C8178

20%

6.3V
CERM-X5R
0402

CRITICAL

C8185

10UF

20%

6.3V
CERM-X5R
0402

1

C8153

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8164

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

L8112

PIME061D-SM

DCR=54MOHM MAX

PLACE_NEAR=U8100.R17:2MM

BATT_SNS

45

LAYOUT NOTE ­R8172- PLACE NEAR PMU

C8149- PLACE NEAR PMU
R8173- PLACE NEAR PMU

XW8114

SHORT-0201

12

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6.0V

R8146

4.7K

1 2

5%

1/20W

MF

201

CRITICAL

1

C8179

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8186

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8154 C8155

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8165

10UF

20%

6.3V

2

CERM-X5R
0402

21

CRITICAL

D8100

SOD-123W

PMEG4030ER

R8172

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U8100.F18:2MM

CRITICAL

1

C8148

4.7UF

10%
35V

2

X5R-CERM
0603

OVP_SW_EN_L_R

52

NOSTUFF

1

C8146

0.01UF

10%
25V

2

X5R-CERM
0201

CRITICAL

1

C8180

10UF

20%

6.3V

2

CERM-X5R
0402

C8142

82PF

5%
25V
CERM
0201

PPVCC_MAIN

1

C8143

18PF

5%
25V

2

C0G-CERM
0201

CRITICAL

1

C8166

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8167

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8156

10UF

20% 20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8168

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8157

10UF

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8169

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8158

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8170

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8159

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8171

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8144

1.0UF

20%

6.3V

2

X5R
0201-1

CRITICAL

1

C8172

10UF

20%

6.3V

2

CERM-X5R
0402

1

2

OMIT_TABLE

U8100

SW_CHGA

MIN_LINE_WIDTH=0.6 MM

K

MIN_NECK_WIDTH=0.20 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE
SWITCH_NODE=TRUE

A

PLACE_NEAR=U8100.R17:10MM

NOSTUFF

1

C8149

0.022UF

10%
25V

2

X7R
0402

PLACE_NEAR=U8100.L18:2MM

CRITICAL

1

C8147

4.7UF

10%
35V

2

X5R-CERM
0603

BATT_SNS_R

PLACE_NEAR=U8100.R17:10MM

1

R8173

499

1%
1/20W
MF
201

2

PMU_VCENTER

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6.0V

LAYOUT NOTE: PLACE
RIGHT AT THE PIN

PLACE_NEAR=U8100.F16:10MM

CRITICAL

C8145

2.2UF

X5R-CERM

LAYOUT NOTE: PLACE
RIGHT AT THE PIN

1

10%
25V

2

603

TP_HV_CHG_EN

=PPVCC_MAIN_CPU

46 54

=PPVCC_MAIN_GPU

46 54

=PPVCC_MAIN_SOC

46 54

PPVCC_MAIN

46 47 48 49 52 54

CRITICAL

1

C8181

10UF

20%

6.3V

2

CERM-X5R
0402

w w w . c h i n a f i x . c o m

G19
H19
J19
K19

R17
P17

M19
N19
P19
R19

N17

F18
F19
G18
H18
J18
K18
L18
L19

F16
F17
G16
G17
H16
H17
J17
K16
K17
L16

M18
N18

L17

C16

D17

T16

P18
R18

F1
F2
K1
K2

P1
P2
V1
V2
V3

U8
V8

A4
B4

A8
B8

U4
V4

B1
B2
B3

CHG_LX0
CHG_LX1
CHG_LX2
CHG_LX3

VBAT
IBAT_S

IBAT0
IBAT1
IBAT2
IBAT3

ACT_DIO

VCENTER

VBUS

VBUS_OVP_OFF

HV_CHG_DIS

VDD_BUCK0_01

VDD_BUCK0_23

VDD_BUCK1_01

VDD_BUCK1_2

VDD_BUCK2

VDD_BUCK3

VDD_BUCK4

VDD_BUCK5

VDD_BUCK6

VCC_MAIN_S

VCC_MAIN

D2089A0

FCBGA

SYM 1 OF 4

BUCK

USB/BAT

VCC-MAIN

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK1_LX0

BUCK1_LX1

BUCK1_LX2

BUCK2_LX0

BUCK3_LX0

BUCK4_LX0

BUCK5_LX0

BUCK6_LX0

BUCK6_BYP0
BUCK6_BYP1
BUCK6_BYP2

BUCK3_SW1

BUCK3_SW2
BUCK3_SW3

BUCK4_SW1

SWITCHED POWER

BUCK4_SW2

BUCK0_FB

BUCK1_FB

BUCK2_FB

BUCK3_FB

BUCK4_FB

BUCK5_FB

BUCK6_FB

VBUCK3

VBUCK4

VPUMP

E1
E2
G1
G2
J1
J2
L1
L2
H6

N1
N2
R1
R2
U1
U2
M6

U7
V7
P7

A5
B5
E6

A7
B7
E7

U5
V5
P6

C1
C2
F6
A1
A2
A3

B13
B14
C14
A12
B12
C12
C13
A13
A14

B10
B11
C11
A9
B9
C9
C10
A10

A11

NOTE: FOR NO BATTERY SITUATION

PPBATT_VCC

46 52 54

R8100

0.5

1/16W

CRITICAL

1

C8193

10UF

20%

6.3V

2

CERM-X5R
0402

1

1%
MF

402

2

CRITICAL

1

C8194

10UF

20%

6.3V

2

CERM-X5R
0402

PPBATT_POS_RC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.7V

PMU_VPUMP

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.6V

1

C8196

0.22UF

20%

6.3V

2

X5R
0201

46 47 48 49 52 54

BUCK0_LX0

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK0_LX1

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK0_LX2

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK0_LX3

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK0_FB

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

BUCK1_LX0

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK1_LX1

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK1_LX2

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK1_FB

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

BUCK2_LX0

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK2_FB

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

BUCK3_LX0

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK3_FB

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

BUCK4_LX0

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK4_FB

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

BUCK5_LX0

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK5_FB

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

BUCK6_LX0

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM

DIDT=TRUE

BUCK6_FB

MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM

1

C8135

1.0UF

20%

6.3V

2

X5R
0201-1

1

C8136

1UF

10%

6.3V

2

CERM
402

1

2

C8137

1.0UF

20%

6.3V
X5R
0201-1

1

2

C8137 0201 OKAY IF GRAPE HAS EXT FET

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

SWITCH_NODE=TRUE

C81A8

1.0UF

20%

6.3V
X5R
0201-1

CRITICAL

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

1

C8138

1.0UF

20%

6.3V

2

X5R
0201-1

L8100

1 2

PILE25201D

CRITICAL

L8101

1 2

PILE25201D

CRITICAL

L8102

1 2

PILE25201D

CRITICAL

L8103

1 2

PILE25201D

XW8101

1 2

SM

CRITICAL

L8104

1 2

PILE25201D

CRITICAL

L8105

1 2

PILE25201D

CRITICAL

L8106

1 2

PILE25201D

XW8102

1 2

SM

CRITICAL

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

1.0UH-3.51A-0.036OHM

2.2UH-2.35A-0.073OHM

L8107

1 2

PILE25201D

XW8103

1 2

CRITICAL

L8108

1 2

PILE25201D

XW8104

1 2

SM

CRITICAL

L8109

1 2

PILE25201D

XW8105

1 2

CRITICAL

L8110

1.0UH-3.33A-66MOHM

1 2

PILE20161D-SM

XW8106

1 2

SM

CRITICAL

L8111

PILE25201D

XW8107

1 2

PP1V8_S2R
PP1V8_SW1
PP1V8_SW2

PP1V8_S2R_SW3

PP1V2_S2R
PP1V2_SW1

PP1V2_S2R_SW2

1

C8139

1UF

10%

6.3V

2

CERM
402

1

2

1

2

1

2

1

2

1

2

1

SM

SM

21

SM

46 47 52 54

50 52 54

52 54

54

46 47 52 54

52 54

52 54

1

C81A9

1.0UF

20%

6.3V

2

X5R
0201-1

2

1

2

1

2

1

2

1

2

1

2

SYNC_MASTER=J72_MLB_C

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

C8100

15UF

20%
4V
X5R
0402

CRITICAL

C8105

15UF

20%
4V
X5R
0402

CRITICAL

C8110

15UF

20%
4V
X5R
0402

CRITICAL

C8112

15UF

20%
4V
X5R
0402

CRITICAL

C8117

15UF

20%
4V
X5R
0402

CRITICAL

C8121

15UF

20%
4V
X5R
0402

CRITICAL

C8124

15UF

20%
4V
X5R
0402

CRITICAL

C8127

15UF

20%
4V
X5R
0402

CRITICAL

C8130

15UF

20%
4V
X5R
0402

CRITICAL

C81A0

10UF

20%

6.3V
CERM-X5R
0402

CRITICAL

C81A4

10UF

20%

6.3V
CERM-X5R
0402

CRITICAL

1

C8101

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8106

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8111

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8113

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8118

15UF

20%

4V

2

X5R
0402

1

2

1

2

1

2

1

2

1

2

1

2

CRITICAL

1

C8102

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8107

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8114

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8119

2

ADDITIONAL DISTRIBUTED
27UF (NO DERATING)

CRITICAL

C8122

15UF

20%
4V
X5R
0402

ADDITIONAL DISTRIBUTED
64UF (NO DERATING)

CRITICAL

C8125

15UF

20%
4V
X5R
0402

ADDITIONAL DISTRIBUTED
27UF (NO DERATING)

CRITICAL

C8128

15UF

20%
4V
X5R
0402

ADDITIONAL DISTRIBUTED
64UF (NO DERATING)

CRITICAL

C8131

15UF

20%
4V
X5R
0402

ADDITIONAL DISTRIBUTED
32UF (NO DERATING)

CRITICAL

C81A1

10UF

20%

6.3V
CERM-X5R
0402

CRITICAL

C81A5

10UF

20%

6.3V
CERM-X5R
0402

15UF

20%
4V
X5R
0402

PPVDD_SOC

CRITICAL

1

C8123

15UF

20%
4V

2

X5R
0402

PP1V8_S2R

CRITICAL

1

C8126

15UF

20%
4V

2

X5R
0402

PP1V2_S2R

CRITICAL

1

C8129

15UF

20%
4V

2

X5R
0402

PPVDD_SRAM

CRITICAL

1

C8132

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C81A2

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C81A6

10UF

20%

6.3V

2

CERM-X5R
0402

PMU: ANYA PAGE 1

Apple Inc.

R

6 3

12

PPVDD_CPU

CRITICAL

1

C8103

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8108

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8115

15UF

20%
4V

2

X5R
0402

CRITICAL

1

C8120

15UF

2

20%
4V
X5R
0402

52 54

46 47 52 54

46 47 52 54

52 54

CRITICAL

1

C81A3

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C81A7

10UF

20%

6.3V

2

CERM-X5R
0402

CRITICAL

1

C8104

15UF

20%
4V

2

X5R

0402

CRITICAL

1

C8109

15UF

20%
4V

2

X5R
0402

PPVDD_GPU

CRITICAL

1

C8116

15UF

20%
4V

2

X5R
0402

PP3V3_S2R

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

81 OF 121

SHEET

46 OF 54

124578

52 54

52 54

52 54

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

OMIT_TABLE

LDO INPUTS

PP1V8_S2R

46 52 54

1 CAP PER PIN

D

PP1V2_S2R

46 52 54

CRITICAL

L8225

4.7UH-3.2A

PIME051E-SM

1

20%

2

CRITICAL

1

C8252

4.7UF

10%
35V

2

X5R-CERM
0603

CRITICAL

1

C8253

4.7UF

2

PPLED_OUT_A

52 54

CRITICAL

1

C8250

4.7UF

10%
35V

2

X5R-CERM
0603

54

=PPVCC_MAIN_LED

CRITICAL

C8226

10UF

6.3V

CERM-X5R

0402

CRITICAL

1

C8251

4.7UF

10%
35V

2

X5R-CERM
0603

C

21

10%
35V
X5R-CERM
0603

CRITICAL

D8228

PMEG4010BEA

A K

SOD-323

CRITICAL

1

C8254

4.7UF

10%
35V

2

X5R-CERM
0603

WLED_LX_A

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20 MM

1

C8259

56PF

2%
50V

2

NP0-C0G-CERM
0201

18

18

18

18

18

18

IN

IN

IN

IN

IN

IN

LED_IO_1_A

LED_IO_2_A

LED_IO_3_A

LED_IO_4_A

LED_IO_5_A

LED_IO_6_A

1

C8280

56PF

5%
25V

2

NP0-C0G-CERM
0201

R8231

1.00

1 2

1%

1/32W

MF

01005

R8235

1.00

1 2

1%

1/32W

MF

01005

R8240

1.00

1 2

1%

1/32W

MF

01005

1

C8281

56PF

5%
25V

2

NP0-C0G-CERM
0201

1

C8200

1UF

10%

6.3V

2

CERM
402

1

C8201

1UF

10%

6.3V

2

CERM
402

R8227

1.00

1 2

1%

1/32W

MF

01005

R8232

1.00

1 2

1%

1/32W

MF

01005

R8239

1.00

1 2

1%

1/32W

MF

01005

1

2

1

C8282

56PF

5%
25V

2

NP0-C0G-CERM
0201

C8203

1UF

10%

6.3V
CERM
402

(PPLED_OUT_A)

1

C8283

56PF

5%
25V

2

NP0-C0G-CERM
0201

PPVCC_MAIN

46 47 48 49 52 54

PPVCC_MAIN

46 47 48 49 52 54

PPVCC_MAIN

46 47 48 49 52 54

NET_SPACING_TYPE=PWR
DIDT=TRUE
SWITCH_NODE=TRUE

1

C8284

56PF

5%
25V

2

NP0-C0G-CERM
0201

52

LED_IO1_A_R

52

LED_IO2_A_R

52

LED_IO3_A_R

52

LED_IO4_A_R

52

LED_IO5_A_R

52

LED_IO6_A_R

NC_WLED_LXB0
NC_WLED_LXB1
NC_VOUT_WLED_B
NC_WLED1_B
NC_WLED2_B
NC_WLED3_B
NC_WLED4_B
NC_WLED5_B
NC_WLED6_B

1

2

C8285

56PF

5%
25V
NP0-C0G-CERM
0201

T18
B16

U10
U14
U15
B15
B17
U16
T17

C18
C19
D16
E14
F14
G14
H14
J14
J16

E18
E19
E16
K14
L14
M14
M16
N14
P14

U9

VDD_LDO1_3_4
VDD_LDO2
VDD_LDO5
VDD_LDO6
VDD_LDO7
VDD_LDO8
VDD_LDO9
VDD_LDO10
VDD_LDO11
VDD_LDO13

WLED_LXA0
WLED_LXA1
VOUT_WLED_A
WLED1_A
WLED2_A
WLED3_A
WLED4_A
WLED5_A
WLED6_A

WLED_LXB0
WLED_LXB1
VOUT_WLED_B
WLED1_B
WLED2_B
WLED3_B
WLED4_B
WLED5_B
WLED6_B

B

U8100

D2089A0

FCBGA

SYM 2 OF 4

LDO

LDO INPUT

VDD_LCM_SW

VDD_BOOST_LCM

BOOST_LCM_LX

LCM/GRAPE

LCD BACKLIGHT

XTAL

PP3V0_SPARE1

47 52 54

PP1V7_VA_VCP

16 47 52 54

PP3V0_S2R_TRISTAR

47 52 54

PP3V0_ALS

47 52 54

PP3V0_UVLO

47 52 54

PP3V3_ACC

47 52 54

PP3V0_S2R_SENSOR

47 52 54

CRITICAL

C8237

2.2UF

10%

6.3V
X5R
402

VLDO1
VLDO2
VLDO3
VLDO4
VLDO5
VLDO6
VLDO7
VLDO8

VLDO9
VLDO10
VLDO11
VLDO13
ON_BUF

LCM_FB

VDD_LCM

VLCM1

VLCM2

LCM2_EN

VLCM3

XTAL1

XTAL2

CRITICAL

1

2

U19

(50MA; 2.5-3.3V)

A16

(100MA; 1.65-1.805V; BUCK3)

U18

(50MA; 2.5-3.3V)

T19

(50MA; 2.5-3.3V)

V9

(1000MA; 2.5-3.6V)

V10

(150MA; 2.5-3.6V)

V14

(300MA; 1.7-3.0V)

V15

(300MA; 1.7-3.0V)

A15

(300MA; 1.2-3.0V)

A17

(150MA; 0.6-1.3V)

V16

(300MA; 1.7-3.0V)

U17

(300MA; 1.7-3.0V)

T10

(5MA; 1.8V; ON_BUFF)

C17

=PPVCC_MAIN_VDD_LCM

A18
B19
C15
U11
V11

(100MA; 5.0-6.0V)

V12

(100MA; 5.0-6.0V)
E8
U12

(5MA; 5.0-6.0V)

V18

PMU_XTAL

V17

PMU_EXTAL

32.768K-20PPM-12.5PF

1

C8215

18PF

5%

25V

2

C0G-CERM

0201

LDO BYPASS

LDO OUTPUTS

NO_TEST=TRUE

NO_TEST=TRUE

CRITICAL

Y8200

2 1

2012-1

CRITICAL

C8235

4.7UF

6.3V

CRITICAL

1

C8234

10UF

20%
X5R

402

6.3V

2

CERM-X5R

0402

PP3V0_SPARE1
PP1V7_VA_VCP
PP3V0_S2R_SENSOR
PP3V0_ALS

PP3V0_UVLO

PP3V3_ACC
PP3V0_S2R_TRISTAR
NC_LDO8
PP1V3_CAM
PP1V0_SOC
PP2V6_CAM_AF
PP2V9_CAM
PP1V8_ALWAYS

54

PP6V0_LCM_HI

LCM_LX

52

PP6V0_LCM_VBOOST
PP5V25_GRAPE

NC_VLCM2

NC_LCM2_EN

NC_VLCM3

CRITICAL

1

C8216

18PF

5%
25V

2

C0G-CERM
0201

CRITICAL

1

C8233

2.2UF

20%

2

6.3V

47 52 54

16 47 52 54

47 52 54

47 52 54

47 52 54

47 52 54

47 52 54

54

47 52 54

47 52 54
54

47
52

47 52 54

47 52 54

(NOTE: 2MHZ)

54

1

C8212

10UF

20%
25V

2

X5R-CERM
0603

2.2UH-1.05A-0.195OHM

MAKE_BASE=TRUE
VOLTAGE=6.0V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

1

C8210

2.2UF

20%
10V

2

X5R-CERM
402

CRITICAL

L8229

1 2

VLS201612E-SM

CRITICAL

1

C8211

4.7UF

20%
10V

2

X5R-CERM
0402

CRITICAL

1

C8290

4.7UF

20%
10V

2

X5R-CERM
0402

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE

CRITICAL

D8230

PMEG2005AEL

A K

SOD882

MAKE_BASE=TRUE
VOLTAGE=6.0V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM

D

C

TABLE_ALT_HEAD

TABLE_ALT_ITEM

B

10UF

6.3V
0402

20%

ALTERNATE FOR
PART NUMBER

CRITICAL

1

C8230

2.2UF

2

6.3V

BOM OPTION

1

10%

2

X5R
402

REF DES

Y8200

COMMENTS:

RDAR://PROBLEM/9936684

PART NUMBER

197S0399 197S0392

6.3V
0402

CRITICAL

1

C8231

20%

2

CERM-X5R

CRITICAL

1

C8232

10UF

10%

2

CERM-X5R

X5R
402

PP1V3_CAM

47 52 54

PP1V0_SOC

47 52 54

PP2V6_CAM_AF

47 52 54

PP2V9_CAM

47 52 54

PP1V8_ALWAYS

47 52 54

CRITICAL

1

C8242

0.22UF

20%

6.3V
X5R

w w w . c h i n a f i x . c o m

0201

C8241

10UF

2

CERM-X5R

6.3V
0402

CRITICAL

1

C8240

10UF

20%

2

CERM-X5R

A

6 3

6.3V
0402

CRITICAL

1

C8239

4.7UF

20%

2

X5R-CERM1

6.3V

CRITICAL

1

20%

2

402

C8238

4.7UF

X5R-CERM1

6.3V

1

20%

2

402

SIZE

A

D

SYNC_MASTER=J85 MLB_C

PAGE TITLE

PMU: ANYA PAGE 2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/03/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

82 OF 121

SHEET

47 OF 54

124578

8 7 6 5 4 3

ALTERNATE FOR
PART NUMBER

138S0706138S0739

R8330

1.00K

1 2

PMU_GPIO_PMU2BBPMU_RST_L

5%

1/32W

MF

01005

NOTE: NEW ON J85

BOM OPTION

PLACE_NEAR=U8100.M17:4MM

1

C8308

1.0UF

20%
10V

2

X5R-CERM
0201-1

NET_SPACING_TYPE=ANLG
MIN_LINE_WIDTH=0.1MM

MIN_NECK_WIDTH=0.1MM

OUT
OUT
OUT
OUT

IN
IN
IN
IN
IN
IN
IN
IN
IN

OUT

IN

OUT

PART NUMBER

1

R8303

200K

1%
1/20W
MF
201

2

PLACE_NEAR=U8100.T11:3MM

1

C8307

1UF

10%
10V

2

X5R
402-1

19 52

44 52

44 52

44 52

5

45

44

52

44 53

24 28 52

15 52

13

5

11

13

13

15

5

19

24

27 52

REVIEW: VERIFY NC ON TDEV2 IS OK

I2C ADDRESS: 0111100X (0X78)

OMIT_TABLE

U8100

D

1

C8300

0.01UF

10%

6.3V

2

X5R
01005

PMU_USB_BRICKID

11

IN

0201

0201

0201

0201

0201

1

2

1

2

1

2

1

2

1

2

CRITICAL

R8327

10KOHM-1%-0.31MA

PLACE_NEAR=U4000.1:10MM

PLACE_SIDE=TOP

(TEMP1 - NEAR BB)

CRITICAL

R8321

10KOHM-1%-0.31MA

C

(TEMP3 - TOP SIDE NEAR WIFI)

(TEMP4 - TOP SIDE NEAR SIM)

(TEMP5 - TOP SIDE NEAR NAND)

B

(TEMP6 TOP SIDE NEAR REAR CAM)

PLACE_NEAR=U5800.30:10MM

PLACE_SIDE=TOP

CRITICAL

R8322

10KOHM-1%-0.31MA

PLACE_NEAR=UJ000.8:10MM

PLACE_SIDE=TOP

CRITICAL

R8323

10KOHM-1%-0.31MA

PLACE_NEAR=U1600.A1:10MM

PLACE_SIDE=TOP

CRITICAL

R8324

10KOHM-1%-0.31MA

PLACE_NEAR=J2800.1:10MM

PLACE_SIDE=TOP

PLACE_NEAR=U8100.R9:10MM

1

C8327

100PF

5%
16V

2

NP0-C0G
01005

PLACE_NEAR=U8100.R13:10MM

1

C8321

100PF

5%
16V

2

NP0-C0G
01005

PLACE_NEAR=U8100.R14:10MM

1

C8322

100PF

5%
16V

2

NP0-C0G
01005

PLACE_NEAR=U8100.L4:10MM

1

C8323

100PF

5%
16V

2

NP0-C0G
01005

PLACE_NEAR=U8100.M4:10MM

1

C8324

100PF

5%
16V

2

NP0-C0G
01005

PA_NTC_P
PA_NTC_N

BOARD_TEMP3_P

52

BOARD_TEMP3_N

BOARD_TEMP4_P

52

BOARD_TEMP4_N

BOARD_TEMP5_P

52

BOARD_TEMP5_N

BOARD_TEMP6_P

52

BOARD_TEMP6_N

PLACE XW AND CAP

CLOSE TO PMU

PLACE_NEAR=U8100.R9:10MM

XW8327

1 2

SM

PLACE_NEAR=U8100.R13:10MM

XW8321

1 2

SM

PLACE_NEAR=U8100.R14:10MM

XW8322

2

1

SM

PLACE_NEAR=U8100.L4:10MM

XW8323

1 2

SM

PLACE_NEAR=U8100.M4:10MM

XW8324

1 2

SM

PLACE_NEAR=U8100.N4:10MM

XW8325

1 2

SM

PLACE_NEAR=U8100.P4:10MM

XW8326

1 2

SM

1

0.01UF

10%

6.3V

2

X5R
01005

10

11

5

IN
IN
IN

1

C8302C8301

0.01UF

10%

6.3V

2

X5R
01005

R8399

0.00

1 2

1%

1/20W

MF

0201

WDOG_SOC2PMU_RESET_IN
TS2PMU_RESET_IN
SOCHOT1_L

4 8

10 11 24 52

5

5

11 52

5

11 52

5

52

5

53

45 52

PMU_ACC_ID
PMU_USB_BRICKID_R

52

ADC_IN7

GPIO_SOC2PMU_KEEPACT

5

IN

PMU_SHDWN

IN

RESET_SOC_L

OUT

GPIO_PMU2SOC_IRQ_L

OUT

I2C0_SCL_1V8

IN

I2C0_SDA_1V8

BI

DWI_AP_CLK

IN

DWI_AP_DO

IN

NC_DWI_AP_DI

BATT_NTC

IN

C8340

100PF

5%

16V

NP0-C0G

01005

IN
IN
IN

IN

GPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
GPIO_BTN_SRL_L

NC_ANYA_BUTTON4

PMU_E75_ACC_DET_L

5

13

5

17

5

17

43

(INTERNAL PULL-DOWN)

(INTERNAL PULL-DOWN)

(PULLUP INSIDE SOC)

(INTERNAL PULL-DOWN)
(INTERNAL PULL-DOWN)

NO_TEST=TRUE

NET_SPACING_TYPE=BOARD_TEMP

NET_SPACING_TYPE=BOARD_TEMP

NET_SPACING_TYPE=BOARD_TEMP

NET_SPACING_TYPE=BOARD_TEMP

NET_SPACING_TYPE=BOARD_TEMP

NET_SPACING_TYPE=BOARD_TEMP

NET_SPACING_TYPE=BOARD_TEMP

NET_SPACING_TYPE=ANLG

NET_SPACING_TYPE=ANLG

PMU_TCAL

CRITICAL

2

1

2

1

R8340

3.92K

0.1%
0201
1/20W
MF

RESISTOR FOR TEMP CALIBRATION

D5

BUTTON1

D6

BUTTON2

D7

BUTTON3

D8

BUTTON4

T7

ACC_DET

R12

ACC_ID

P16

BRICK_ID

N16

ADC_IN7

R11

ADC_IN31

T8

KEEPACT

T9

SHDN

R5

RESET_IN1

R6

RESET_IN2

R7

RESET_IN3

R8

RESET*

T15

IRQ*

E12

SCL

E13

SDA

E11

DWI_CK

E10

DWI_DI

E9

DWI_DO

R9

TDEV1

R10

TDEV2

NC

R13

TDEV3

R14

TDEV4

L4

TDEV5

M4

TDEV6

N4

TDEV7

P4

TDEV8

R16

TBAT

R15

TCAL

D2089A0

FCBGA

SYM 3 OF 4

ANALOG

INPUT

REFRENCES

32K

INPUT

DIGITAL

WDOG

RESET

GPIO

I2C & DWI

TEMPERATURE

ANALOG MUX

CLK

IREF
VREF

VDD_REF

VDD_REF_A

VDD_RTC
ADC_REF

OUT_32K

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17

AMUX_A0
AMUX_A1
AMUX_A2
AMUX_A3
AMUX_AY
AMUX_B0
AMUX_B1
AMUX_B2
AMUX_B3
AMUX_BY

T12

PMU_IREF

NET_SPACING_TYPE=ANLG

V13

PMU_VREF

NET_SPACING_TYPE=ANLG

M17

PMU_VDD_REF

NET_SPACING_TYPE=ANLG

T11
U13

PMU_VDD_RTC

NET_SPACING_TYPE=ANLG

T13

PMU_ADC_REF

T14

NC_PMU_OUT_32K_CLK_GPS

T6

PMU_GPIO_CLK_32K_OSCAR

T5

PMU_GPIO_CLK_32K_WLAN

T4

PMU_GPIO_BT_REG_ON

R3

PMU_GPIO_WLAN_REG_ON

P3

PMU_GPIO_PMU2BBPMU_RST_R_L

N3

UART5_BATT_RTXD

M3

PMU_GPIO_BT_HOST_WAKE

L3

PMU_GPIO_WLAN_HOST_WAKE

K3

PMU_GPIO_BB2PMU_HOST_WAKE

J3

PMU_GPIO_CODEC_HS_INT_L

H3

PMU_GPIO_MB_HALL1_IRQ

G3

GPIO_TS2SOC2PMU_INT

F3

PMU_GPIO_MB_HALL2_IRQ

E3

PMU_GPIO_MB_HALL3_IRQ

D3

PMU_GPIO_CODEC_RST_L

C3

PMU_GPIO_OSCAR2PMU_HOST_WAKE

C4

PMU_GPIO_BB_VBUS_DET

E4

NC_PPVDD_CPU_SOC_SENSE

F4

NC_PPVDD_GPU_SOC_SENSE

G6

NC_PPVDD_SOC_SOC_SENSE

J6

NC_ADC_SMPS1_MSMC_1V05

G4

NC_AMUX_AY

K4

NC_PPVDD_CPU_RAIL_SENSE

J4

NC_PPVDD_GPU_RAIL_SENSE

K6

NC_PPVDD_SOC_RAIL_SENSE

L6

NC_ADC_SMPS3_MSME_1V8

H4

NC_AMUX_BY

1

C8305

0.1UF

10%

6.3V

2

CERM-X5R
0201

1

C8306

0.1UF

10%

6.3V

2

CERM-X5R
0201

REF DES

C8308

12

OUT

COMMENTS:

24 26 52

1

C8310

1000PF

10%

6.3V

2

X5R-CERM
01005

TABLE_ALT_HEAD

TABLE_ALT_ITEM

D

C

B

A

(TEMP7 - BOTTOM SIDE NEAR SOC)

(TEMP8 - BOTTOM SIDE NEAR PMU)

PART NUMBER

118S0764 118S0717

ALTERNATE FOR
PART NUMBER

107S0208107S0150

CRITICAL

R8325

10KOHM-1%-0.31MA

PLACE_NEAR=U0600.W19:10MM

PLACE_SIDE=BOTTOM

10KOHM-1%-0.31MA

PLACE_NEAR=U8100.K9:10MM

PLACE_SIDE=BOTTOM

BOM OPTION

0201

CRITICAL

R8326

0201

R8321,R8322,R8323,R8324,R8325,R8326

REF DES

R8340

1

2

1

2

COMMENTS:

RDAR://PROBLEM/8380367

RDAR://PROBLEM/8380367

PLACE_NEAR=U8100.N4:10MM

1

C8325

100PF

5%
16V

2

NP0-C0G
01005

PLACE_NEAR=U8100.P4:10MM

1

C8326

100PF

5%
16V

2

NP0-C0G
01005

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

BOARD_TEMP7_P

52

BOARD_TEMP7_N

BOARD_TEMP8_P

52

BOARD_TEMP8_N

BUCK6 POWER IS ON IN HIBERNATE DUE TO WIFI PAS
SWITCH NEEDED TO GATE POWER TO NAND AND SOC
REVIEW: CHECK FOR POWER SEQUENCING VOILATIONS BETWEEN PP1V8 AND PP3V3

=PP3V3_S2R_SWITCH

PPVCC_MAIN

w w w . c h i n a f i x . c o m

46 47 49 52 54

1

C8350

0.1UF

10%
16V

2

X5R-CERM
0201

VCC_MAIN_PP3V3SW_RAMP

=PP1V8_NAND

12 54

1

R8352

100K

5%
1/32W
MF
01005

2

CRITICAL

1

C8352

4700PF

10%
10V

2

X7R
201

54

U8350

SLG5AP1443V

TDFN

7

CAP

VDD

GND

8 1

CRITICAL

D

SON

3

52

1

C8355

1.0UF

20%

6.3V

2

X5R
0201-1

PP3V3_SW

CRITICAL

1

C8356

10UF

20%
10V

2

X5R-CERM
0402-2

52 54

6 3

SYNC_MASTER=J72_MLB_C

PAGE TITLE

PMU: ANYA PAGE 3

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

83 OF 121

SHEET

48 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

D

M1
M2

VSS_BUCK01

T1
T2

VSS_BUCK1_12

H1
H2

VSS_BUCK0_12

U6
V6

VSS_BUCK25

A6
B6

VSS_BUCK34

D1
D2

VSS_BUCK06

D18

VSS_WLED

D19

B18

VSS_LCM

A19

C

XW8410

PPVCC_MAIN

46 47 48 52 54

B

=PP3V0_UVLO

54

SHORT-10L-0.1MM-SM

NOSTUFF

R8420

150K

1 2

1%

1/32W

MF

01005

21

VCC_MAIN_UVLO_SENSE

R8451

4.7K

NOSTUFF

R8450

150K

1/32W
01005

NOSTUFF

1

C8460

100PF

5%

6.3V

2

CERM
01005

1/32W

1

01005

1%
MF

2

R8410

75K

1/32W
01005

R8411

50K

1/32W
01005

1

1%
MF

2

MAIN_UVLO_SENSE_R

1

1%
MF

2

UVLO_COMP_NEG

1

1%
MF

2

THROTTLER

=PP3V0_SPARE1

1

C8400

0.1UF

20%

6.3V

2

X5R-CERM
01005

U8400

A3

MAX9039BEBT+

UCSP

B2

VCC

B1

VEE

A1

APN 353S4103

A2

REF

B3

UVLO_COMP_REF

54

THROTTLER_OUT

49

1

R8435

100K

5%
1/32W
MF
01005

2

R8445

0.00

SOCHOT0_R_L

3

D

G

2

Q8440

DMN2990UFA

S

DFN0806-VML0806-COMBO-N78

1

1 2

0%

1/32W

MF

01005

SOCHOT0_L

5

52

OUT

D15
V19

D10
D11
D12
D13
D14
E17

F10
F11
F12
F13

G10
G11
G12
G13

D4
C5
C6
C7
C8
D9

F7
F8
F9

VSS

G7
G8
G9

H7
H8
H9

OMIT_TABLE

U8100

D2089A0

FCBGA

SYM 4 OF 4

VSS

H10
H11
H12
H13
J7
J8
J9
J10
J11
J12
J13
K7
K8
K9
K10
K11
K12
K13
L7
L8
L9
L10
L11
L12
L13
M7
M8
M9
M10
M11
M12
M13
N6
N7
N8
N9
N10
N11
N12
N13
P8
P9
P10
P11
P12
P13
R4
T3
U3

ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS

D

C

B

R8425

1.00K

UVLO_COMP_REF

49

1 2

1%

1/32W

MF

01005

UVLO_COMP_POS

A

6 3

R8430

w w w . c h i n a f i x . c o m

255K

1 2

1%

1/32W

MF

01005

SYNC_MASTER=J72_MLB_C

PAGE TITLE

PMU: ANYA PAGE 4

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

Apple Inc.

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

84 OF 121

SHEET

49 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

D

SWITCH TO GATE POWER TO SOC AND NAND. NEEDED FOR J72 ROUTING.

CRITICAL

U8550

TPS22924X

CSP

GND

A1

VOUT

B1

C1

PP1V8_EXT_SW

52 54 54

=PP1V8_S2R_EXT_SWITCH

1

2

C8550

10UF

20%
10V
X5R-CERM
0402-2

PP1V8_SW1

46 52 54

1

C8555

0.01UF

10%

6.3V

2

X5R
01005

A2

VIN

B2

C2

ON

C

D

C

B

B

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=J85 MLB_C

PAGE TITLE

POWER: PP1V8_SW

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

85 OF 121

SHEET

50 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

D

D

DEBUG

TP9002

=PP1V8_S2R_MISC

5

54

C

SEP EEPROM

1

TP-P55

A

C

UNPROGRAMMED P/N: 335S0894

=PP1V8_EEPROM

1

C9000

0.22UF

20%

CRITICAL

B

SEP_I2C0_SCL

5

B1 B2

VCC

U9000

CAT24C08C4A

WLCSP

SCL SDA

VSS

A2 A1

6.3V

2

X5R
0201

SEP_I2C0_SDA

54

B

5

w w w . c h i n a f i x . c o m

A

SYNC_MASTER=J72_MLB_C

PAGE TITLE

SEP: EEPROM & SOC DEBUG

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

90 OF 121

SHEET

51 OF 54

124578

SIZE

A

D

8 7 6 5 4 3

12

TP9300

1

GPIO_CODEC_IRQ_L

A

TP-P5

TP9304

1

PMU_GPIO_CODEC_HS_INT_L

A

TP-P5

TP9303

1

BATT_NTC

A

TP-P5

TP9305

1

PPLED_OUT_A

A

TP-P5

TP9396

1

PP3V0_UVLO

A

TP-P5

TP9397

1

PP3V0_SPARE1

A

TP-P5

D

C

B

A

TP9398

1

SOCHOT0_L

A

TP-P5

TP9312

1

BOARD_TEMP3_P

A

TP-P5

TP9313

1

BOARD_TEMP4_P

A

TP-P5

TP9314

1

BOARD_TEMP5_P

A

TP-P5

TP9315

1

BOARD_TEMP6_P

A

TP-P5

TP9316

1

BOARD_TEMP7_P

A

TP-P5

TP9317

1

BOARD_TEMP8_P

A

TP-P5

TP9318

1

CLK_32K_SOC2CUMULUS

A

TP-P5

TP9320

1

CODEC_HP_DET_R

A

TP-P5

TP9321

1

CODEC_HP_HS3

A

TP-P5

TP9322

1

CODEC_HP_HS3_REF

A

TP-P5

TP9323

1

CODEC_HP_HS4

A

TP-P5

TP9324

1

CODEC_HP_HS4_REF

A

TP-P5

TP9325

1

CODEC_HP_LEFT

A

TP-P5

TP9326

1

CODEC_HP_RIGHT

A

TP-P5

TP9328

1

DISPLAY_SYNC_R

A

TP-P5

TP9329

1

DWI_AP_CLK

A

TP-P5

TP9330

1

E75_DPAIR1_CONN_N

A

TP-P5

TP9331

1

E75_DPAIR1_CONN_P

A

TP-P5

TP9332

1

E75_DPAIR2_CONN_N

A

TP-P5

TP9333

1

E75_DPAIR2_CONN_P

A

TP-P5

TP9334

1

FMI0_CE0_L

A

TP-P5

TP9335

1

FMI1_CE0_L

A

TP-P5

TP9336

1

GND

A

TP-P5

TP9337

1

GND_AUDIO_CODEC

A

TP-P5

TP9338

1

GPIO_BTN_HOME_FILT_L

A

TP-P5

TP9339

1

GPIO_BTN_ONOFF_L_FILT

A

TP-P5

TP9340

1

GPIO_BTN_SRL_L_FILT

A

TP-P5

TP9341

1

GPIO_BTN_VOL_DOWN_L_FILT

A

TP-P5

TP9342

1

GPIO_BTN_VOL_UP_L_FILT

A

TP-P5

TP9343

1

GPIO_FORCE_DFU

A

TP-P5

TP9344

1

GPIO_GRAPE_IRQ_L

A

TP-P5

TP9345

1

GPIO_GRAPE_RST_L

A

TP-P5

TP9346

1

GPIO_SOC2BB_WAKE_MODEM

A

TP-P5

TP9347

1

GPIO_SPKAMP_KEEPALIVE

A

TP-P5

TP9348

1

I2C0_SCL_1V8

A

TP-P5

TP9349

1

I2C0_SDA_1V8

A

TP-P5

TP9350

1

I2C2_SCL_1V8

A

TP-P5

TP9351

1

I2C2_SDA_1V8

A

TP-P5

TP9352

1

ISP0_CAM_REAR_CLK

A

TP-P5

TP9353

1

ISP0_CAM_REAR_SCL

A

TP-P5

TP9354

1

ISP0_CAM_REAR_SDA

A

TP-P5

TP9355

1

ISP0_CAM_REAR_SHUTDOWN_L

A

TP-P5

TP9356

1

ISP1_CAM_FRONT_CLK

A

TP-P5

TP9357

1

ISP1_CAM_FRONT_SCL

A

TP-P5

TP9358

1

ISP1_CAM_FRONT_SDA

A

TP-P5

TP9359

1

ISP1_CAM_FRONT_SHUTDOWN_L

A

TP-P5

TP9360

1

JTAG_SOC_SEL

A

TP-P5

TP9361

1

JTAG_SOC_TCK

A

TP-P5

TP9362

1

JTAG_SOC_TDI

A

TP-P5

TP9363

1

JTAG_SOC_TMS

A

TP-P5

TP9364

1

JTAG_SOC_TRST_L

A

TP-P5

TP9365

1

JTAG_WLAN_SEL

A

TP-P5

TP9366

1

OSCAR2RADIO_CONTEXT_A

A

TP-P5

TP9367

1

OSCAR2RADIO_CONTEXT_B

A

TP-P5

TP9368

1

WLAN_TX_BLANK

A

TP-P5

TP9369

1

LAT_SW1_CTL

A

TP-P5

TP9370

1

LAT_SW2_CTL

A

TP-P5

TP9371

1

A

TP-P5

TP9372

1

LED_IO1_A_R

A

TP-P5

TP9373

1

LED_IO2_A_R

A

TP-P5

TP9374

1

LED_IO3_A_R

A

TP-P5

TP9375

1

LED_IO4_A_R

A

TP-P5

TP9376

1

LED_IO5_A_R

A

TP-P5

TP9377

1

LED_IO6_A_R

A

TP-P5

TP9378

1

MIKEY_TS_N

A

TP-P5

TP9379

1

MIKEY_TS_P

A

TP-P5

5

15

15 48

45 48 44 48

47 54

47 54

47 54

5

49

48

48

48

48

48

48

5

13

15

15

15

15

15

15

15

13

5

48

43

43

43

43

6

12

6

12

15

13

17

17

17

17

5

13

5

5

13

5

28

5

16

5

11 48

5

11 48

5

16

5

16

7

23

7

23

7

23

7

23

7

20

7

20

7

20

7

20

4

10

4

11

4

4

11

4

10

44

19 28 44

19 28 44

28 44

14 24 28

14 28

47

47

47

47

47

47

11 15

11 15

TP9380

1

OVP_SW_EN_L_R

A

TP-P5

TP9382

1

PMU_GPIO_BT_HOST_WAKE

A

TP-P5

TP9383

1

PMU_GPIO_BT_REG_ON

A

TP-P5

TP9384

1

PMU_GPIO_CLK_32K_OSCAR

A

TP-P5

TP9385

1

PMU_GPIO_CLK_32K_WLAN

A

TP-P5

TP9387

1

PMU_USB_BRICKID_R

A

TP-P5

TP9388

1

PP1V0_SOC

A

TP-P5

TP9389

1

PP1V2_S2R

A

TP-P5

TP9390

1

PP1V2_S2R_SW2

A

TP-P5

TP9391

1

PP1V2_SW1

A

TP-P5

TP9393

1

PP1V7_VA_VCP

A

TP-P5

TP9395

1

PP1V8_ALWAYS

A

TP-P5

TP93A0

1

PP1V8_EXT_SW

A

TP-P5

TP93A1

1

PP1V8_GRAPE_FILT

A

TP-P5

TP93A2

1

PP1V8_GRAPE_SW

A

TP-P5

TP93A3

1

PP1V8_PLL_SOC_F

A

TP-P5

TP93A4

1

PP1V8_S2R

A

TP-P5

TP93A6

1

PP1V8_S2R_SW3_COMP

A

TP-P5

TP93A7

1

PP1V8_SW1

A

TP-P5

TP93A8

1

PP1V8_SW2

A

TP-P5

TP93A9

1

PP1V8_XTAL

A

TP-P5

TP93B0

1

PP2V6_CAM_AF

A

TP-P5

TP93B8

1

PP3V0_S2R_HALL_FILT

A

TP-P5

TP93C0

1

PP3V0_S2R_SENSOR

A

TP-P5

TP93C1

1

PP3V0_S2R_TRISTAR

A

TP-P5

TP93C3

1

PP3V3_ACC

A

TP-P5

TP93C4

1

PP3V3_S2R

A

TP-P5

TP93C5

1

PP3V3_SW

A

TP-P5

TP93C6

1

PP5V25_GRAPE_FILT

A

TP-P5

TP93C8

1

PP6V0_LCM_VBOOST

A

TP-P5

TP93C9

1

PPBATT_VCC

A

TP-P5

TP93D0

1

PPLED_BACK_REG_A

A

TP-P5

TP93D1

1

PPOUT_E75_ACC_ID1_CONN

A

TP-P5

TP93D2

1

PPOUT_E75_ACC_ID2_CONN

A

TP-P5

TP93D3

1

PPVBUS_PROT

A

TP-P5

TP93D4

1

PPVBUS_USB_DCIN

A

TP-P5

TP93D5

1

PPVCC_MAIN

A

TP-P5

TP93D6

1

PPVCC_MAIN_LCD_SW_CONN

A

TP-P5

TP93D7

1

PPVDD_CPU

A

TP-P5

TP93D8

1

PPVDD_GPU

A

TP-P5

TP93D9

1

PPVDD_SOC

A

TP-P5

TP93E0

1

PPVDD_SRAM

A

TP-P5

46

44 48

19 48

44 48

48

47 54

46 47 54

46 54

46 54

16 47 54

47 54

50 54

13

13

4

46 47 54

54

46 50 54

46 54

8

47 54

13

47 54

47 54

47 54

46 54

48 54

13

47

46 54

18

43

43

11 46

46 54

46 47 48 49 54

18

46 54

46 54

46 54

46 54

TP93G4

1

A

TP93G9

A

TP93H1

A

TP93H2

A

TP93H3

A

TP93H4

A

TP93H5

A

TP93H6

A

TP93H7

A

TP93H8

A

TP93I1

A

TP93I2

A

TP93I3

A

TP93I4

A

TP93I5

A

TP93I6

A

TP93I7

A

TP93I8

A

TP93I9

A

TP93J0

A

TP93J1

A

TP93J9

A

TP93JA

A

TP93JB

A

TP93JC

A

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

1

TP-P5

PP_SMPS4_RF2_2V05

SOC_TESTMODE

SPI1_GRAPE_CS_L
SPI1_GRAPE_MISO
SPI1_GRAPE_MOSI
SPI1_GRAPE_SCLK_R
SPKR_L_CONN_N
SPKR_L_CONN_P
SPKR_R_CONN_N
SPKR_R_CONN_P

TP_JTAG_SOC_TDO
TP_JTAG_WLAN_TCK
TP_JTAG_WLAN_TRST_L
UART0_SOC_RXD
UART0_SOC_TXD
UART3_BB2SOC_TX
UART3_SOC2BB_TX
UART6_TS_ACC_RXD
UART6_TS_ACC_TXD
USB_SOC_N
USB_SOC_P

PP3V0_ALS
PP2V9_CAM
PP1V3_CAM
PMU_GPIO_WLAN_REG_ON

25 30

4

5

5

5

13

16 43

16 43

16 43

16 43

4

44

44

5

5

5

5

5

5

4

4

47 54

47 54

47 54

44 48

10

13

13

13

11

11

11 24 28

11 24 28

11

11

11

11

w w w . c h i n a f i x . c o m

TP93G1

1

A

TP-P5

TP9301

A

TP-P5

TP93G5

1

A

TP-P5

TP93E1

1

A

TP-P5

TP93H9

1

A

TP-P5

TP93I0

1

A

TP-P5

TP9302

SIMCRD_RST_CONN

A

TP-P5

TP93B9

SIMCRD_CLK_CONN

A

TP-P5

TP93E7

SIMCRD_IO_CONN

A

TP-P5

TP93E8

SIM_TRAY_DETECT

A

TP-P5

TP93F3

1

A

TP-P5

TP93J2

GPIO_SOC2BB_RADIO_ON_L

A

TP-P5

TP93J3

GPIO_SOC2BB_RST_L

A

TP-P5

TP93J4

PMU_GPIO_PMU2BBPMU_RST_L

A

TP-P5

TP9381

1

A

TP-P5

TP93J5

PS_HOLD_PMIC

A

TP-P5

TP9327

1

A

TP-P5

TP9306

1

A

TP-P5

TP9307

1

A

TP-P5

TP9308

1

A

TP-P5

TP9309

1

A

TP-P5

TP9310

1

A

TP-P5

TP9311

1

A

TP-P5

TP93J6

A

TP-P5

TP93J7

A

TP-P5

TP93G6

1

A

TP-P5

TP93J8

A

TP-P5

6 3

RF TEST POINTS

PP_SMPS1_MSMC_1V05

PP_SMPS3_MSME_1V8
PP_SMPS5_DSP_1V05
PP_LDO1
TP_BB_TEST_MODE_0
TP_BB_TEST_MODE_1

PP_LDO6_RUIM_1V8

PMU_GPIO_BB2PMU_HOST_WAKE

DEBUG_RST_L
BB_JTAG_RTCLK
BB_JTAG_TCK
BB_JTAG_TDI
BB_JTAG_TDO
BB_JTAG_TMS
BB_JTAG_TRST_L

USB_BB_N

USB_BB_P
RESET_SOC_L

PMU_GPIO_BB_VBUS_DET

25 27

24 25 27 28 30

25

25

27

27

10 24 28

10 24 28

10 24 28

10 24 28

10 24 25 27

5

24 26

5

24 26

24 26 48

24 28 48

24 26

24 27

24 27

5

24 27

5

24 27

5

24 27

5

24 27

5

24 27

11 24 53

11 24 53

4 8

10 11 24 48

24 27 48

STANDOFFS: P/N 860-1657

STDOFF-3.3X1.8R1.28H-SM

STDOFF-3.3X1.8R1.28H-SM

STD9300

1

STD9301

1

STANDOFF: P/N 860-1683

STDOFF-3.3X2.2R1.35H-SM-1

STD9302

1

PLATED THROUGH HOLES

DRILL SIZE: 1.1MM X 0.4MM

PLATING SIZE: 1.4MM X 0.7MM

SL9300

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9303

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9304

TH-NSP

1

SL-1.1X0.4-1.4X0.7

SL9305

TH-NSP

1

SL-1.1X0.4-1.4X0.7

MH9300

3P25R2P5

1

860-1688

MH9302

WASHER-BTN-MLB-X221

TH

1

NEAR BUTTON FLEX CONN

SYNC_MASTER=J85 MLB_C

PAGE TITLE

TEST: TP/HOLES/FIDUCIALS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=12/03/12

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

93 OF 121

SHEET

52 OF 54

124578

SIZE

D

C

B

A

D

8 7 6 5 4 3

12

FOR FRANK (SEG)

EE CHARACTERIZATION TP

PP9450

P4MM

NAND

PLACE_SIDE=BOTTOM

1

SM

SM

SM

SM

SM

SM

SM

PP

1

PP

1

PP

1

PP

1

PP

1

PP

1

PP

FMI0_DQS
FMI0_AD<3>

FMI0_DQS

TP_TCKC_U1400
TP_TMSC_U1400
TP_U1400_RB0
TP_U1400_RB1

PP9401

P4MM

PP9402

P4MM

PP9403

D

P4MM

PP9410

P4MM

PP9411

P4MM

PP9412

P4MM

PP9413

P4MM

PLACE_NEAR=U0652.D34:2MM

PLACE_SIDE=BOTTOM

PLACE_NEAR=U0652.C34:2MM

PLACE_NEAR=U0652.D34:2MM

6

12 53

6

12

6

12

53

12

12

12

12

PP9451

P4MM

1

PPVDD_SOC_SOC_SENSE

PP

SM

1

PPVDD_CPU_SOC_SENSE

PP

SM

DWI

PLACE_SIDE=BOTTOM

AUDIO

PLACE_NEAR=U8100:2MM

PLACE_NEAR=U1900:2MM

5

48

5

15

PP9405

P4MM

PP9406

P4MM

PP

SM

PP

SM

1

DWI_AP_DO

1

I2S0_CODEC_ASP_MCK

PLACE_NEAR=U0652.V31:1MM

PLACE_NEAR=U0652.AN30:1MM

9

9

D

WIFI

5

5

44 48

5

44

44

44

PP9480

P4MM

PP9481

P4MM

PP9482

P4MM

PP9483

P4MM

HSIC1_WLAN2SOC_DEVICE_RDY

PP

SM

HSIC1_WLAN2SOC_REMOTE_WAKE

PP

SM

PMU_GPIO_WLAN_HOST_WAKE

PP

SM

HSIC1_SOC2WLAN_HOST_RDY

PP

SM

GPIO_BT_WAKE

I76

1

PP9416

P4MM

PP9417

P4MM

C

PP9419

P4MM

PP9420

P4MM

PP9421

P4MM

PP9422

P4MM

PP9423

P4MM

PP9424

P4MM

PP9425

P4MM

PP9426

P4MM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

PP

SM

I2S2_CODEC_XSP_LRCK

1

I2S2_CODEC_XSP_DOUT

1

I2S1_SPKAMP_MCK

1

I2S1_SPKAMP_BCLK

1

I2S1_SPKAMP_LRCK

1

I2S1_SPKAMP_DOUT

1

I2S1_SPKAMP_DIN

1

SPI2_CODEC_SCLK

1

SPI2_CODEC_MOSI

1

SPI2_CODEC_MISO

PLACE_NEAR=U1900:2MM

PLACE_NEAR=U1900:2MM

PLACE_NEAR=U2040:2MM

PLACE_NEAR=U2040:2MM

PLACE_NEAR=U2040:2MM

PLACE_NEAR=U2040:2MM

PLACE_SIDE=BOTTOM

PLACE_NEAR=U0652:2MM

PLACE_NEAR=U1900:2MM

PLACE_NEAR=U1900:2MM

PLACE_SIDE=BOTTOM

PLACE_NEAR=U0652:2MM

1

PP

SM

1

PP

SM

1

PP

SM

1

PP

SM

1

PP

SM

1

PP

SM

1

PP

SM

HSIC1_WLAN_DATA

HSIC1_WLAN_DATA
HSIC1_WLAN_STB

UART1_BT2SOC_TX
UART1_SOC2BT_TX

UART2_WLAN2SOC_TX
UART2_SOC2WLAN_TX

5

15

5

15

5

16

5

16

5

16

5

16

5

16

5

15

5

15

5

15

PP9460

P4MM

PP9462

P4MM

PP9463

P4MM

PP9468

P4MM

PP9469

P4MM

PP9471

P4MM

PP9472

P4MM

FOR HSIC CHARACTERIZATION

FUNC_TEST=TRUE

PLACE_NEAR=U0652.AM33:3MM

PLACE_NEAR=U5800.13:3MM

PLACE_NEAR=U5800.14:3MM

PLACE_NEAR=U0652:3MM

PLACE_NEAR=U5800:3MM

PLACE_NEAR=U0652:3MM

PLACE_NEAR=U5800:3MM

5

44

4

44 53

4

44 53

4

44

5

44

5

44

5

44

5

44

C

GRAPE

BASEBAND

FOR HSIC CHARACTERIZATION

PP9428

P4MM

PP9429

P4MM

PP

SM

PP

SM

1

UART4_SOC2OSCAR_TXD

1

UART4_OSCAR2SOC_RXD

OSCAR

UART5

PLACE_SIDE=BOTTOM

PLACE_NEAR=U2400:2MM

PLACE_SIDE=BOTTOM

PLACE_NEAR=U0652:2MM

USB_BB_P

I192

USB_BB_N

PP9465

P4MM

PP9466

P4MM

SM

SM

I193

1

PP

1

PP

HSIC2_BB_STB
HSIC2_BB_DATA

5

19

5

19

B

FUNC_TEST=TRUE

FUNC_TEST=TRUE

PLACE_NEAR=U0652.B27:3MM

PLACE_NEAR=U3400.C7:3MM

11 24 52

11 24 52

4

24 27

4

24 27

B

PROX

HIGH SPEED, NO TEST

MIPI0C_CAM_REAR_CLK_P

I141

MIPI0C_CAM_REAR_CLK_N

I140

MIPI0C_CAM_REAR_DATA_P<0..3>

I139

MIPI0C_CAM_REAR_DATA_N<0..3>

I138

MIPI0C_CAM_REAR_CLK_FILT_P

I142

MIPI0C_CAM_REAR_CLK_FILT_N

I144

MIPI0C_CAM_REAR_DATA_FILT_P<0..3>

w w w . c h i n a f i x . c o m

PP9440

P4MM

A

PP9441

P4MM

PP9442

P4MM

PP9443

P4MM

PP9444

P4MM

PP9445

P4MM

PP9446

P4MM

PP9447

P4MM

MIPI1C_CAM_FRONT_CLK_P

PP

SM

1

MIPI1C_CAM_FRONT_CLK_N

PP

SM

1

MIPI1C_CAM_FRONT_DATA_P<0>

PP

SM

1

MIPI1C_CAM_FRONT_DATA_N<0>

PP

SM

1

MIPI0C_CAM_REAR_CLK_P

PP

SM

1

MIPI0C_CAM_REAR_CLK_N

PP

SM

1

MIPI0C_CAM_REAR_DATA_P<0>

PP

SM

1

MIPI0C_CAM_REAR_DATA_N<0>

PP

SM

1

CAMERA

PLACE_NEAR=U0652.AR33:3MM

PLACE_NEAR=U0652.AR34:3MM

PLACE_NEAR=U0652.AT33:3MM

PLACE_NEAR=U0652.AT34:3MM

PLACE_NEAR=U0652.AU25:3MM

PLACE_NEAR=U0652.AV25:3MM

PLACE_NEAR=U0652.AU27:3MM

PLACE_NEAR=U0652.AV27:3MM

7

20 53

7

20 53

7

20 53

7

20 53

7

23 53

7

23 53

7

23 53

7

23 53

I145

MIPI0C_CAM_REAR_DATA_FILT_N<0..3>

I143

MIPI1C_CAM_FRONT_CLK_P

I146

MIPI1C_CAM_FRONT_CLK_N

I149

MIPI1C_CAM_FRONT_DATA_P<0>

I150

MIPI1C_CAM_FRONT_DATA_N<0>

I148

MIPI1C_CAM_FRONT_CLK_FILT_P

I147

MIPI1C_CAM_FRONT_CLK_FILT_N

I152

MIPI1C_CAM_FRONT_DATA_FILT_P<0>

I151

MIPI1C_CAM_FRONT_DATA_FILT_N<0>

I153

EDP_DATA_P<0..3>

I187

EDP_DATA_N<0..3>

I185

EDP_DATA_EMI_P<0..3>

I186

EDP_DATA_EMI_N<0..3>

I188

EDP_DATA_EMI_CONN_P<0..3>

I190

EDP_DATA_EMI_CONN_N<0..3>

I189

6 3

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

7

23 53

7

23 53

7

23 53

7

23 53
23
23
23
23
7

20 53
7

20 53
7

20 53
7

20 53
20
20
20
20

7

18
7

18
18
18
18
18

SYNC_MASTER=J72_MLB_C

PAGE TITLE

TEST: EE TP/PP

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

94 OF 121

SHEET

53 OF 54

SIZE

A

D

124578

8 7 6 5 4 3

POWER CONNECTIONS

12

BUCK0

PPVDD_CPU

46 52

MAKE_BASE=TRUE

D

BUCK1

PPVDD_GPU

46 52

MAKE_BASE=TRUE

BUCK2

PPVDD_SOC

46 52

MAKE_BASE=TRUE

BUCK3

PP1V8_S2R

46 47 52

MAKE_BASE=TRUE

BUCK3_SW

C

B

PP1V8_SW1

46 50 52

MAKE_BASE=TRUE

PP1V8_EXT_SW

50 52

MAKE_BASE=TRUE

PP1V8_SW2

MAKE_BASE=TRUE

PP1V8_S2R_SW3

46

MAKE_BASE=TRUE

PP1V8_S2R_SW3_COMP

52 54

MAKE_BASE=TRUE

BUCK4

PP1V2_S2R

46 47 52

MAKE_BASE=TRUE

=PPVDD_CPU

=PPVDD_GPU

=PPVDD_SOC

=PP1V8_S2R_MISC
=PP1V8_S2R_VDDIO_WLAN_BT
=PP1V8_S2R_TRISTAR
=PP1V8_S2R_DDR
=PP1V8_S2R_GRAPE
=PP1V8_S2R_EXT_SWITCH
=PP1V8_S2R_REAR_CAMERA
=PP1V8_S2R_MESA
=PP1V8_S2R_VDD_CORE_GPS
=PP1V8_S2R_VDD_IO_GPS

=PP1V8_AUDIO
=PP1V8_DMIC
=PP1V8_CAM_FRONT
=PP1V8_CAM_REAR
=PP1V8_PROX

=PP1V8_VDDIO18_SOC
=PP1V8_SOC
=PP1V8_MIPI_SOC
=PP1V8_EDP_SOC
=PP1V8_NAND_SOC

=PP1V8_NAND
=PP1V8_PLL_SOC
=PP1V8_SPKRAMP
=PP1V8_EEPROM
=PP1V8_BEACON

=PP1V8_GRAPE

=PP1V8_S2R_GYRO
=PP1V8_S2R_ACCEL
=PP1V8_S2R_OSCAR

PP1V8_S2R_SW3_COMP

=PP1V8_S2R_COMP

PP1V8_S2R_SW3 SHOULD BE ON IN HIBERNATE
CURRENTLY POWERS OSCAR AND 1.8V RAIL ON SENSOR

=PP1V2_S2R_DDR
=PP1V2_S2R_DDR_SOC
=PP1V2_S2R_CAM_REAR

9

9

9

15

14

20

23

22

8 9

4 5 7

7

7

6

12 48

4

51

5

51

11

8

13

50

13 46 52

21

21

19

52 54

21

8

8

44

10 18

BUCK5

PPVDD_SRAM

46 52

MAKE_BASE=TRUE

BUCK6

PP3V3_S2R

46 52

MAKE_BASE=TRUE

PP3V3_SW

48 52

MAKE_BASE=TRUE

LDO1

PP3V0_SPARE1

47 52

MAKE_BASE=TRUE

LDO2

PP1V7_VA_VCP

16 47 52

MAKE_BASE=TRUE

LDO3

PP3V0_S2R_SENSOR

47 52

MAKE_BASE=TRUE

LDO4

PP3V0_ALS

47 52

MAKE_BASE=TRUE

LDO5

PP3V0_UVLO

47 52

MAKE_BASE=TRUE

=PPVDD_SRAM_CPU
=PPVDD_SRAM_SOC

=PP3V3_S2R_SWITCH
=PP3V3_S2R_WIFI_PA

=PP3V3_EDP_PU
=PP3V3_NAND
=PP3V3_USB_SOC

=PP3V0_SPARE1

=PP1V7_VA_VCP

LDO3 SHOULD BE ON IN HIBERNATE
COMPASS, ACCEL, GYRO, PROX ARE ON OSCAR
HALL EFFECT NEEDS TO BE ON IN HIBERNATE

=PP3V0_S2R_HALL

=PP3V0_S2R_GYRO
=PP3V0_S2R_ACCEL
=PP3V0_S2R_COMP

=PP3V0_ALS
=PP3V0_PROX

=PP3V0_HP_ALS
=PP3V0_IO_ALS

SHOULD IO ALS POWER HERE?

=PP3V0_UVLO

20

22

49

9

48

44

12

4

49

15 16

LDO7

PP3V0_S2R_TRISTAR

47 52

MAKE_BASE=TRUE

LDO7 SHOULD BE ON IN HIBERNATE

=PP3V0_S2R_TRISTAR

11

LDO8

NC_LDO8

47

MAKE_BASE=TRUE

LDO9

PP1V3_CAM

47 52

MAKE_BASE=TRUE

NO_TEST=TRUE

=NC_LDO8

BACKUP RAIL. CAN BE BOOSTED TO MEET

1.1V MIN ON CAMERA IF NEEDED.

=PP1V3_CAM_FRONT

=PP1V3_CAM_REAR

23

LDO10

PP1V0_SOC

47 52

MAKE_BASE=TRUE

=PP1V0_USB_SOC
=PP1V0_MIPI_SOC
=PP1V0_EDP_PAD_DVDD_SOC

4

7

7

LDO11

PP2V6_CAM_AF

47 52

MAKE_BASE=TRUE

13

21

21

21

=PP2V6_CAM_REAR_AF

23

LDO13

PP2V9_CAM

47 52

MAKE_BASE=TRUE

=PP2V9_CAM_FRONT
=PP2V9_CAM_REAR

20

23

CHARGER MAIN

PPVCC_MAIN

46 47 48 49 52

MAKE_BASE=TRUE

BATTERY

PPBATT_VCC

46 52

MAKE_BASE=TRUE

USB POWER INPUT

PPVBUS_USB_DCIN

46 52

MAKE_BASE=TRUE

ON_BUF

PP1V8_ALWAYS

47 52

MAKE_BASE=TRUE

BACKLIGHT BOOST

PPLED_OUT_A

MAKE_BASE=TRUE

=PPVCC_MAIN_AUDIO
=PPVCC_MAIN_LED
=PPVCC_MAIN_DOCK

=PPVCC_MAIN_DEV
=PPVCC_MAIN_CPU
=PPVCC_MAIN_GPU
=PPVCC_MAIN_SOC
=PPVCC_MAIN_GRAPE
=PPVCC_MAIN_LCD
=PPVCC_MAIN_NAVAJO
=PPVCC_MAIN_VDD_LCM

=PPVCC_MAIN_WLAN

=PPVCC_MAIN_GPS

=PPBATT_POS_CONN

=PPBATT_VCC_BB
=PPBATT_AUDIO

=PPVBUS_USB_EMI

=PP1V8_ALWAYS

=PPLED_REG_A

15 16

47

43

46

46

46

13

18

47

44

45

24 25 33 34 35 36 37 38

43

5

18 47 52

D

C

B

w w w . c h i n a f i x . c o m

BUCK4_SW

PP1V2_SW1

46 52

MAKE_BASE=TRUE

A

PP1V2_S2R_SW2

46 52

MAKE_BASE=TRUE

=PP1V2_VDDQ_DDR
=PP1V2_VDDIOD_SOC
=PP1V2_HSIC_SOC

=PP1V2_S2R_OSCAR

PP1V2_S2R_SW2 SHOULD BE ON IN HIBERNATE
PROVIDE 1.2V TO OSCAR

8

8

4

19

PP3V3_ACC

47 52

MAKE_BASE=TRUE

LDO6

=PP3V3_ACC

11

6 3

VLCM1

PP5V25_GRAPE

MAKE_BASE=TRUE

=PP5V25_GRAPE

13 47

SYNC_MASTER=J72_MLB_C

PAGE TITLE

POWER: ALIASES

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=11/26/2012

DRAWING NUMBER

051-0886

REVISION

A.0.0

BRANCH

PAGE

121 OF 121

SHEET

54 OF 54

SIZE

A

D

124578