Apple iPad Mini 2 Schematic PCB layout
8
7
6
5
4
3
2
1
D
D
MAIN LOGIC BOARD
C
SL9304
R4300
C4073
C4033 C4034
L4314L4315
C4326
C4327
C4322
C4323
C4317
C4318
C4316
C4074
C4319
C2971
L2901
XW2951
*
C2905
C2903
XW2950
C2901 C2904
U4358
C2902
C2900
L2900
C2908
C2970
C2906
C2980
L2911 L2910 L2912
L2902
J2950
C2972
C2907
C4485
L2950
L2807
L2808
J2800
*
C4488
C2911
C2909
C2973
L2903
*
L2800
C2800
R2800
C2802
C2807
C2806
C2801
*
U2800
L2802
L2804
L2801
L2803
L4803
FL4801
L4801
L4802
L4438L4437
C2910
R2801
C2804
U4410
C2805
C2803
*
C4472
C4487
C4484
C4486
C4483
L4436
L4440
C4471
C4467
C4489
L4435
R4605
L4613
L4807
C4805
*
C4807
L4806
*
L4805
*
U4801
*
C4804
C4803
L4804
*
C4809
FL4802
R4065
C4039
C4052
C4053
C4038
C4042
L4029
L4044
L4030
L4045
L4020
C4037
C4040
*
C4002
FL3901
L3909
R3901
L3908
*
C4049
C4071
C3811
L3819
L3817
C3809
C3808
R4064
C4230
U4215
C4231
FL4211
C4216
R4437
L3907
*
C4054
C3902
FL3902
C3905
C3904
C3903
L3903
L3902
C3901
L3901
*
L3906
C3914
L3904
C3913
L3905
C3912
C3908
C3706
*
C3721
C3716
C3907
C4064
C3906
C3909
U3901
L3824
C4047
L3823
L3822
*
C4046
C4023
L4012
U4000
*
C4012
C4076
C4075
C4072
C4232
*
C4234
C4239
L4254
C4228
C4227
L4253
C4229
*
C4218 C4219
U3600
C3911
C3910
L3810
*
L3809
L3811
L3812
*
R3600
L3808
L3807
C3801
C3800
L3800L3802
C3804
C3805 C3802
C3803
L3803 L3801
L3805
L3804
L3806
L3815
L3813
*
C4008
C3807
C3806
U3803
L3814
L3825
L3840
U4714
R4739
*
L4743
R4701
C4794
C4737
C4736
C4235
C4710
*
C4508
*
C4507
L4500
U4500
C4001
C4325 C4324
C4043
U4025
U4027
C4041
*
*
C4060
C4061
L4316
C4320
L4071
C4056
L4317
C4058
C4048
C4055
L4070
C4321
L4097
R4607
R4608
L4072
L4439
C4639
C4663
C4664
C4665
U4617
C4666
C4622
C4641
*
C4150
L4136
C4154
U4123
C4148
C4102
C4100
*
FL4012
*
C4063
L4083
L3821
*
U3802
L3820
C3810
C4668 C4669
*
SW4601
L4228
C4640
U3801
C4236
L4642
*
R4139
L4138
L4229
C4151
C4155
R8327
C4101
*
C4149
L4182
L4122
R3603
L4123
L4257
C4146
R3602
C4103
C4233
C4104
C4147
R3601
C4207
C4208
L4200
C3602
R3002
R3502
C3434
R3003
C3426
R3700
R3702
C3231
C3715
C3701
C3413
C3414
C3708
C3707
C3709
C3720
C3718
C3717
C3719
C3409
R3604
C3600
C3601
C4500
R4500
C3412
C3700
C3402
C3704
C3400
C3702
C3703
C3401
C3714
C3403
C3705
C3421
C3713
C3712
C3404
*
C3500
C3710
C3711
C3424
C3425
C4756
C4755
L4742
L4740
L4746
C4797
C4799
*
C3207
U4722
L4701
XW3303
L4747
C3225
R4711
L4765
C4708
C3206
C4798
C4739
C4738
XW3302
R4534
C4545
C3226
C3227
C4502
C4503
C4504
J2960
*
C3431
R3402
R3400
R3403
C3432
XW3002
XW3003
U3400
XW3301
XW3300
C3228
C3229
C3219
L3200
*
L3203
C3218
U3300
*
C3215
C3216
L3202
R3304
C3204
C3205
R3305 R3307
*
L3201
*
C3213
C3221
*
XW3200
L3204
XW3305
*
C3222
C3212
C3300
C3209
C3211
C3203
C3230
Y3300
C3210
R3303
C3214
C3217
DZ2963
DZ2960
MH9302
DZ2961
DZ2962
SL9303
L2962
C1400
C1411
U3520
R3401
L3520
C3423
C3520
C3422
C3407
C3433
C3406
C3410
C3411
R3530 R3531
C3416 C3408
C3415
C3417 C3405
C3420
C3419
C3418
R3306
R3300
R3301
C3223
C3220
C3208
XW3304
C1450
C3224
C1492
C3202
C1413
C3201
R8330
C3200
SL9300
PP9424
R1911
R2903
L2963
C2963
R1910
C2960
R1913
L2960
*
C1916
XW1902
R2900
R1912
XW1903
R2901
C1917
C2961
L2961
XW1900
C1910
R2902
PP9425
U1900
C1991 C1990
C2962
PP9406
C1901
C1903
R1460
C1460
C1461
C1913
R1953
R1952
R1461
C1930
R1930
C1404
C1480
C1931
C1932
C1407
R1931
C1491
U1400
C2701
L2700
R2747
U2700
R2757
R2405
C1920
*
U2400
C2401
C1412
C1494C0607
C1410
C1402
C1026
C1102
R1454
C1009
C1490 C1493
C1406
*
C1405
C2723
L2741
C2725
C2700
C2711
XW2700
U2710
C2750
*
*
C2710
R2406
U2720
L2701
XW2701
R2727
R0753
R0752
C2400
R2450
PP9403
R0870
R0871
R0720
R0646
R0831
R0655
R0640
C0613
Y0602
*
C1103
*
C1401
R8323
C1015
C1100
R0832
L2702
C2721
C1027
C2045
C2726
C2047
R2750
R1211
R1250
C0618
C1101
R0617
U0652
C1004
C2094
R2040
C2091
*
XW2041
XW2040
C2044 C2092
C2046
R0702
R0703
R0739
U2040
R0738
C2043
C2041 C2042
C2048
R0705
R0704
PP9423
PP9417
R1051
PP9419
R1052
PP9420
PP9416
C1070
R0721
R1000
C1052
C1007
R0750
R1209
R1208
R0770
R0765
R1207
U9000
R1213
R1260
C1148
C1915
C1902
R1940
C1909
C1951
C1904
*
R1951
C1914
C1905
R1950
C1906
C1950
R1920
C1907
C1908
C1912
R2400
R1901
C1911
C2055
L2040
*
C2093
C8352
C2095
*
XW2050
XW2051
C2090
C2057
C2054
C2056
U2050
PP9421
C2053
PP9422
R2051R2041
C2058
C8190
R8324
C1120
C1116
C8105
C1121
L8100
*
C1118
C1119
C8109
C8110
C1117
L8103
*
C1122
R1006
R1005
C1002
C1115 C8111
R1001
C1174
R1201
L8104
*
C1177
R0940
R0941
C8118
C1175
R0933
R0930
R0931
R0701
C1171
C1173
C8112
C8114C8116
C1176
C1170
C1172
R1205
R1206
C8120
R0751
C9000
*
C8356
C8550
C8350
U8550
U8350
*
R8352
C81A1
L2050
C81A7
C2052
C2051
C81A2
*
L8111
*
C8104
C8160
*
L8101
XW8101
C8102 C8103
C8101
C8107
*
L8102
C8100 C8106
C8171
C8108
C8117
L8105
C8113
C8172
C8119
XW8102
C8150
*
L8106
C8131
XW8106
C8132
C8115
C8130
C8127
C8126
C8128
C8555
C8355
C8129
C8125
XW8104
C8124
XW8105
L8108
L8109
*
*
C8152
C8151
C8166
C8162
C8170
C8167
C8165
C8139
C81A3 C81A0 C81A5 C81A6
XW8107
C81A4
*
C8178 C8175 C8157
U8100
C8183 C8181 C8179 C8177 C8176
*
C8161 C8158 C8184 C8182 C8180
L8110
C8235
C8188
C8186
C8168
C8185
C8187
C8156
C8159
C8242
C8307
C8154
C8234
C8164
R0735
*
*
C8153
C8212
L8107
C8122
R8425
U8400
C8123
C8121
R8420
C8460
XW8103
C8142
C8226
C8141
*
R0771
C8144
C8200
C8203
C8201
C8238
C8231
C8135
C8138
C8137
D8230
C8290
C8210
C8239
C81A9
C8196
C81A8
C8136
*
L8229
R0651
XW8114
C8145
C8148
C8147
C8308
R8172
R8173
C8149
C8233
C8230
C8237
C8241
C8216
C8215
C8305
R8303
C8240
C8232
Y8200
C8310
C8211
C8306
C8169
C8143
*
C8140
Q8104
C8400
R8430
C8163
R8445
R8411
R8410
*
Q8440
*
R8451
R8435
R8450
XW8410
D8100
L8225
*
*
C1752
C1750
U1700
R1751
C8254
C1751
C1753
C8250
C8253
C8252
D8228
C8259
C8251
L2200
Q8123
*
DZ8120
R8130
R8116
R3000
C3000
U3000
U3003
C3001
U3001
L8112
R2290
R2291
U2201
C2270
*
R8322
C2240
R2205
C8155
C8301
*
R8399
U1300
R1370
C1321
C1301
*
U2200
C2239
C1302
C1322
R8170
C2230
C2203
R8146
C8146
C1303
C2241
C2202
C1361
C1360
C1320
C1300
SL9305
MH9300
J3000
C3002
U3002
C5880
C5882
*
C5827
J5820
C5817
R5820
C5826
U5820
*
C5825
C5822
C5821
C5824
C5823
C5820
*
XW5891
XW5890
*
J5810
R5810
C5816
U5810
*
U5811
C5815
R5830
L5811
C5814
C5810
C5811
C5813
U5800
XW5897
R0736
C5881
PP9483 PP9482
XW5892
R5805
R5802
R5800
R5801
R5804
R5803
PP9469
PP9468
SP*
STD9302
L1702
R1752
R1753
C1761
C2233
C8280
R8227
C8281
*
R8231
C8282
R8232
R8235
*
C8283
L5810
R8239
C8284
R8240
C8285
L2201
C5800
C5801
*
STD9300
PP9472
XW5896
R2242
R2250
XW5895
PP9471
L2240
XW5893
XW5894
DZ5700
C5702
C5700
L5700
C5703
R5700
C7522
C5701
FL7500
C7523
C7525
C7526
C7524
C8193
C8194
R8100
C1708
C2221
R2241
C1707
C2250
C1706
C2251
R1790
R2243
C1760
C2242
L1760
C2243
L2212 L2242L2232L2202 L2222
L1701
*
C1704
C2245
C2244
C1705
C1703
J1700
* *
C2247
C1700
J2201
C2232
C2246
L1700
C1702
C2249
C2248
C2260
R8321
*
XW7520
*
J7500
C1701
D5701D5703
L5704
DZ5702
C5704
R5790
R5791
R5706 R5705
DZ5710
STD9301
L5701
C5705
DZ5703
L5702
C5707
DZ5704
D5702
L5703
D5700
C
*
J4910
*
L2602
C2606
C2608
L2660
C2607
B
L2600
C2601
C2600
L2611
C2602
J2601
XW2600
C2605
L2610
C2603
C2604
L2601
R2601
U2601
U2600
*
*
*
R1850
C1850
L1903
L1905
L1800
L1904
C1800
L1902
L1901
C1830
C1821 C1820
L1900
L1920
J1800
C1802
C1801
C1822
SP*
*
J4802
*
R4801
C4801
C4802
J4800
A
DRAWING
schemu
820-4124-A TOP
B
A
8 7 6 5 4 2 1
3
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCH AND BOARD PART NUMBERS
QTY
PART#
D
820-4124
C
B
DESCRIPTION
1
SCH,MLB-C1,X200
1
PCBF,MLB-C1,X200
PDF CSA
TABLE_TABLEOFCONTENTS_HEAD
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TABLE_TABLEOFCONTENTS_ITEM
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9
10
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12
13
14
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21
22
24
26
CONTENTS
TABLE OF CONTENTS
BLOCK DIAGRAM: SYSTEM
BOM TABLES
SOC: MAIN
SOC: I/OS
SOC: NAND
SOC: DP,MIPI
SOC: SRAM, IO PWRS
SOC: VDD, SRAM, CPU, GPU PWRS
SOC: MISC & ALIASES
IO: TRISTAR
NAND STORAGE
TOUCH: SUPPORT CKT & CONN
AUDIO: HP FLEX CONN
AUDIO: L81 CODEC
AUDIO: CS35L19A AMPS
BUTTON: CONN
VIDEO: EDP SUPPORT & CONN
SENSOR: OSCAR
CAMERA: FF-ALS CONN & FILTERS
7
REFERENCE DESIGNATOR(S)
SCH1051-0886
PCB1
BOM OPTION
3456
REV ECN
MLB-C1
X200
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
SYNC MASTER
N/A N/A
J85_MLB_B
J72_MLB_C
N/A
N/A
N/A
MLB
N/A
N/A
N/A
N/A N/A
MLB
N/A
N/A
KAVITHA
KAVITHA
N/A N/A
J85 MLB_C
J72_MLB_C
J85 MLB_C
DATE
04/02/2013
11/26/2012
04/18/2011
05/05/2011
04/18/2011
05/04/2012
04/18/2011
04/18/2011
04/11/2011
05/04/2012
06/21/2010
03/31/2011
01/18/2012
01/18/2012
12/05/2012
11/26/2012
12/03/2012
LAST_MODIFIED=Tue Oct 29 15:52:27 2013
TABLE_TABLEOFCONTENTS_HEAD
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
CSAPDF
CONTENTS
27
SENSOR: ACCEL, COMPASS, GYRO
28
SENSOR: PROX
29
CAMERA: REAR CONN & FILTERS
30
CELL:AP INTERFACE & DEBUG CONNECTORS
32
CELL: BASEBAND PMU (1 0F 2)
33
CELL: BASEBAND PMU (2 OF 2)
34
CELL: BASEBAND (1 OF 2)
35
CELL: BASEBAND (2 OF 2)
36
CELL: RF TRANSCEIVER (1 0F 2)
37
CELL: RF TRANSCEIVER (2 OF 2)
38
CELL: RX MATCHING
39
CELL: RF TRANSCEIVER (3 OF 4)
40
CELL: PENTABAND PA
41
CELL: BAND 2/3 PAD
42
CELL: BAND 7/20 PAD
43
CELL: BAND 5/8 PAD
44
CELL: 2G PA
45
CELL: PA DCDC CONVERTER
46
CELL: ASM AND HB LTE FRONT-END
47
CELL: RX DIVERSITY
48
CELL: GPS
49
CELL: ANTENNA FEEDS
57
IO: FILTERS & HOTBAR CONN
58
WIFI/BT: MODULE
75
POWER: BATTERY CONNECTOR
81
PMU: ANYA PAGE 1
82
PMU: ANYA PAGE 2
83
PMU: ANYA PAGE 3
84
PMU: ANYA PAGE 4
85
POWER: PP1V8_SW
90
SEP: EEPROM & SOC DEBUG
93
TEST: TP/HOLES/FIDUCIALS
94
TEST: EE TP/PP
121
POWER: ALIASES
SYNC MASTER
N/A N/A
J85 MLB_C
N/A N/A
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
RADIO_MLB_87
N/A
WIFI_DEV
N/A N/A
J72_MLB_C
J85 MLB_C
J72_MLB_C
J72_MLB_C
J85 MLB_C
J72_MLB_C
J85 MLB_C
J72_MLB_C
J72_MLB_C
DATE
12/05/12
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
10/29/2013
04/18/2011
05/20/2013
11/26/2012
12/03/2012
11/26/2012
11/26/2012
11/26/2012
11/26/2012
12/03/12
11/26/2012
11/26/2012
A
0002535199
DESCRIPTION OF REVISION
PRODUCTION RELEASED
12
CK
APPD
DATE
2014-01-13
D
C
B
w w w . c h i n a f i x . c o m
A
DRAWING
8 7 6 5 4 2 1
3
DRAWING TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SCH,MLB-C1,X200
Apple Inc.
R
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
1 OF 121
SHEET
1 OF 54
SIZE
A
D
8 7 6 5 4 3
12
ISP1_I2C
GRAPE
SPI1
MIPI1C
ISP0_I2C
CUMULUS
CUMULUS
D
MIPI0C
HSIC2
UART1
FRONT CAMERA
REAR CAMERA
D
MIMO
WIFI/BT ANT
WIFI/BT
UART2
I2S3
BT_I2S
CSA 58
WIFI/BT ANT
NOT ON
ALCATRAZ
DISPLAY/
TOUCH PANEL
EDP
C
BACKLIGHT
HSIC1
I2S4
UART3
CELLULAR/
HSIC1
JTAG
USART
USB
CSA 31-46
GPS
WIFI-ONLY CONFIG
PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT
GPS ANT
C
SIM CARD
UART5
BUTTON FLEX
HOME BUTTON
B
PMU
ANYA
CSA 81-84
HALL EFF
1-3
BATTERY
CSA 75
OSCAR
CSA 24
DWI
I2C0
UART4
I2C1
USB2.0
UART0
UART6
I2C0
I2C2
TRISTAR
CSA 13
B
I2S1
COMPASS
CSA 17
SPI BUS
ACCELEROMETER
GYRO
CSA 27CSA 27CSA 27
I2C3
FMI0
FMI1
SPI2
I2S0
I2S2
SPI
ASP
XSP
MBUS
AMP
CSA 20
AMP
CSA 20
w w w . c h i n a f i x . c o m
RIGHT
SPEAKER
LEFT
SPEAKER
L81
AUDIO
A
HP
PROX SENSOR
CSA 28
NAND FLASH
ALS
CSA 14
6 3
CODEC
CSA 19
MIC1 MIC2
SYNC_MASTER=J85_MLB_B
PAGE TITLE
BLOCK DIAGRAM: SYSTEM
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/02/2013
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
2 OF 121
SHEET
2 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
12
SOC
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
D
C
BOM OPTIONS
COMMON
ALTERNATE
16GB_PROD
32GB_PROD
64GB_PROD
128GB_PROD
DEVELOPMENT_JTAG_TAP
JTAG_DAP
MLB (WDOG TO PMU)
WIFI BOM OPTIONS
ANDGATE_TI
FERRITE_TY
FERRITE_TDK
BOM GROUP
BASIC
BOM OPTIONS
COMMON,ALTERNATE
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
PART#
339S0207
PART NUMBER
PMU
PART#
343S0656
FLASH CONFIGURATIONS
PART#
335S0922 32GB
335S0924
PART NUMBER
335S0931 335S0922
335S0932
DESCRIPTION
QTY
H6P + 1GB ELPIDA
1
ALTERNATE FOR
PART NUMBER
339S0207339S0208
DESCRIPTION
QTY
1
IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342
QTY
DESCRIPTION
1
TOS,19NM,PPN1.5,C,DDP,16GB
TOS,19NM,PPN1.5,C,QDP,32GB
1
1
TOS,19NM,PPN1.5,C,ODP,64GB
1
TOS,19NM,PPN1.5,C,12DP,64GB
1
TOS,19NM,PPN1.5,C,16DP,128GB
ALTERNATE FOR
PART NUMBER
335S0921335S0930
335S0923
BOM OPTION
BOM OPTION
16GB
32GB
64GB
REFERENCE DESIGNATOR(S)
U0652
REF DES
COMMENTS:
HYNIX DDR
U0652
REFERENCE DESIGNATOR(S)
U8100
REFERENCE DESIGNATOR(S)
U1400
U1400
U1400
U1400
U1400
REF DES
COMMENTS:
U1400
HYNIX 20NM PPN1.5 16GB
HYNIX 20NM PPN1.5 32GB
U1400
HYNIX 20NM PPN1.5 64GB
U1400
CRITICAL BOM OPTION
CRITICAL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CRITICAL BOM OPTION
CRITICAL
BOM OPTION
16GB335S0921
64GB335S0923
96GB335S0929
128GB
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
D
TABLE_5_HEAD
TABLE_5_ITEM
C
U2200
TABLE_5_HEAD
TABLE_5_ITEM
WIFI
PART NUMBER
ALTERNATE FOR
PART NUMBER
339S0213339S0223
BOM OPTION
REF DES
U5800
COMMENTS:
QTY
PART#
353S4272
NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES)
TABLE_ALT_HEAD
TABLE_ALT_ITEM
4.3UF CAP
PART NUMBER
DESCRIPTION
IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8
1
ALTERNATE FOR
PART NUMBER
138S0657138S0702
BOM OPTION
REFERENCE DESIGNATOR(S)
U2200
REF DES
COMMENTS:
RDAR #13988471
C1009,C1015,...
BOM OPTION
TABLE_ALT_HEAD
TABLE_ALT_ITEM
MECHANICAL PARTS
PART#
B
806-6207
806-7613
DESCRIPTION
QTY
1
FENCE,TALL,MLB,X221
FENCE,RADIO,MLB,C BRD,X221
1
REFERENCE DESIGNATOR(S)
PD_FENCE_MLB
PD_CAN_RADIO
CRITICAL BOM OPTION
CRITICAL
CRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
B
GYRO
PART#
338S1192
BARCODE LABEL/EEEE CODES
PART#
825-7639
825-7639
825-7639
825-7639
825-7639
825-7639
825-7639
A
825-7639
825-7639
825-7639
DESCRIPTION
QTY
EEEE FOR 639-5393 (X200C1 GOOD)
1
EEEE FOR 639-5394 (X200C1 BETTER)
1
EEEE FOR 639-5385 (X200C1 BEST)
1
EEEE FOR 639-5386 (X200C1 BEST+)
1
EEEE FOR 639-5387 (X200C1 ULTIMATE)
1
EEEE FOR 639-5388 (X200C1 GOOD IVS)
1
EEEE FOR 639-5389 (X200C1 BETTER IVS)
1
EEEE FOR 639-5390 (X200C1 BEST IVS)
1
EEEE FOR 639-5391 (X200C1 BEST+ IVS)
1
EEEE FOR 639-5392 (X200C1 ULTIMATE IVS)
1
REFERENCE DESIGNATOR(S)
FNJD
FNJ5
FNJ9
FNJH
FNJ6
FNJ8
FNJF
FNJC
FNJ7
FNJG
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
EEEE_X200C_GOOD
EEEE_X200C_BETTER
EEEE_X200C_BEST
EEEE_X200C_BEST+
EEEE_X200C_ULTIMATE
EEEE_X200C_GOOD_IVS
EEEE_X200C_BETTER_IVS
EEEE_X200C_BEST_IVS
EEEE_X200C_BEST+_IVS
EEEE_X200C_ULTIMATE_IVS
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
w w w . c h i n a f i x . c o m
132S0391 CRITICAL
132S0288
ACCEL
PART#
PART NUMBER
DESCRIPTION
QTY
1
GYRO, ST MICRO
1
GYRO, INVENSENSE
CAP 0.01UF 25V 0201
1
CAP 0.1UF 16V 0201
1
DESCRIPTION
QTY
1
IC,ACCEL,3-AXIS,DIG,BMA282,LGA14
ALTERNATE FOR
PART NUMBER
338S1233 ST MICRO - DISQUAL’ED
338S1114 OLD ACCEL - ST MICRO
338S1191 OLD ACCEL - ST MICRO
BOM OPTION
REFERENCE DESIGNATOR(S)
U2720
U2720
C2726
C2726
REFERENCE DESIGNATOR(S)
U2700
REF DES
COMMENTS:
CRITICAL BOM OPTION
CRITICAL
CRITICAL338S1218
CRITICAL
CRITICAL BOM OPTION
CRITICAL338S1163
TABLE_ALT_HEAD
GYRO_STMICRO
GYRO_INVENSENSE
GYRO_STMICRO
GYRO_INVENSENSE
6 3
TABLE_5_HEAD
TABLE_5_ITEM
338S1158 OLD GYRO - ST MICRO
TABLE_5_ITEM
OLDER INVENSENSE P/N 338S1135
OLD INVENSENSE P/N 338S1200 (3/22/13)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
SYNC_MASTER=J72_MLB_C
PAGE TITLE
BOM TABLES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=11/26/2012
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
4 OF 121
SHEET
3 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
H6P: JTAG, USB, PLL, HSIC, XTAL
12
D
NOTE: CANDIDATE FOR COST-SAVINGS
(REPLACE WITH XW LATER?)
=PP1V8_PLL_SOC
54
R0622
1 2
0.00
=PP1V2_HSIC_SOC
54
C0690
0.22UF
20%
6.3V
X5R
0201
01005
1
2
1
C0651
0.1UF
20%
6.3V
2
X5R-CERM
C0691
0.22UF
6.3V
0201
20%
X5R
C
=PP1V8_SOC
4 5 7
10 18 54
JTAG_SOC_TDI
4
52
JTAG_SOC_TMS
4
11 52
JTAG_SOC_TCK
4
11 52
B
1
R0647
100K
1%
1/32W
MF
01005
2
1
R0646
100K
1%
1/32W
MF
01005
2
10 11 24 48 52
10 18 54
8
1
2
4 5 7
IN
R0645
100K
1%
1/32W
MF
01005
=PP1V8_SOC
RESET_SOC_L
1
R0617
100K
1%
1/32W
MF
01005
2
1
C0618
1000PF
10%
6.3V
2
X5R-CERM
01005
HSIC2_BB_DATA
24 27 53
BI
HSIC2_BB_STB
24 27 53
BI
HSIC1_WLAN_DATA
44 53
BI
HSIC1_WLAN_STB
44 53
BI
1.8V TOLERANT
10 52
10 52
4
52
4
11 52
4
11 52
10
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
JTAG_SOC_SEL
IN
JTAG_SOC_TRST_L
IN
JTAG_SOC_TDI
IN
JTAG_SOC_TMS
IN
JTAG_SOC_TCK
IN
SOC_HOLD_RESET
IN
NC_HSIC0_DATA
NC_HSIC0_STB
HSIC1_BB_DATA
HSIC1_BB_STB
HSIC2_WLAN_DATA
HSIC2_WLAN_STB
NC_JTAG_SOC_TRTCK
TP_JTAG_SOC_TDO
52
1
2
PP1V8_PLL_SOC_F
52
1
C0648
0.01UF
10%
6.3V
2
X5R
0100501005
A26
HSIC0_DATA
B26
HSIC0_STB
A27
HSIC1_DATA
B27
HSIC1_STB
AM33
HSIC2_DATA
AM34
HSIC2_STB
D28
JTAG_SEL
D27
JTAG_TRTCK
E28
JTAG_TRST*
E27
JTAG_TDO
F27
JTAG_TDI
F28
JTAG_TMS
C28
JTAG_TCK
F29
RESET*
E29
CFSB
D29
HOLD_RESET
H16
FUSE1_FSRC
1
C0608
0.01UF
10%
6.3V
2
X5R
01005
G22
G23
AM31
(3X 13MA)
HSIC_VDD120
HSIC_VDD122
HSIC_VDD121
HSIC_VDD120
HSIC_VDD121
HSIC_VDD122
VDDIO18_GRP3
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 1 OF 13
VDDIO18_GRP1
U16
AE20
(1MA)
(6X 1MA)
VDD_ANA_PLL
VDD_ANA_PLL_CCC
VDDIO18_GRP4
ANALOGMUXOUT
USB_ANALOGTEST
TST_CLKOUT
FAST_SCAN_CLK
(25MA)
F23
F24
USB_DVDD
USB_VDD330
(5.4MA)
USB_DP
USB_DM
USB_VBUS
USB_ID
USB_REXT
TESTMODE
(25MA)
XI0
XO0
WDOG
F25
E25
E26
B29
A29
D26
D23
E24
E23
AD4
AC3
AD3
AB3
NC_USB_ANALOGTEST
=PP1V0_USB_SOC
1
C0627
0.01UF
10%
6.3V
2
X5R
01005
=PP3V3_USB_SOC
1
C0630
0.1UF
20%
6.3V
2
X5R-CERM
01005
XTAL_SOC_24M_I
XTAL_SOC_24M_O
NC_ANALOGMUXOUT
USB_VBUS_DETECT_R
NC_USB_ID
WDOG_SOC
SOC_TEST_CLKOUT
SOC_FAST_SCAN_CLK
SOC_TESTMODE
54
54
TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD
1
R0655
OUT
IN
IN
USB_SOC_P
USB_SOC_N
10
TP0600
TP
TP-P55
10
10 52
1.00M
1%
1/32W
MF
01005
11 52
BI
11 52
BI
R0651
68.1K
1%
1/32W
MF
01005
24.000MHZ-30PPM-9.5PF-60OHM
USB_REXT
R0640
1.33K
1 2
1%
1/32W
USB_VBUS_DETECT
1
R0642
2
2
200
1%
1/32W
MF
01005
01005
Y0602
1.60X1.20MM-SM
SOC_24M_O
MF
USBHS ON/OFF TOLERANCE 5V/1.98V
46
IN
NOTE: NEW USB_REXT
VALUE FOR H6 = 200 OHM
OLD (H5) VALUE: 44.2 OHM
42
1 3
C0607
12PF
1 2
5%
16V
CERM
01005
C0613
12PF
1 2
5%
16V
CERM
01005
D
C
B
HSIC_VSS120
HSIC_VSS121
HSIC_VSS122
H20
H21
AM32
USB_VSSA0
H23
w w w . c h i n a f i x . c o m
A
SYNC_MASTER=N/A
PAGE TITLE
SOC: MAIN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=04/18/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
6 OF 121
SHEET
4 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
SOC I/OS
12
R0720
33.2
1%
1/32W
MF
01005
I2S0_CODEC_ASP_MCK
15 53
OUT
D
I2S1_SPKAMP_MCK
16 53
OUT
1 2
R0721
33.2
1%
1/32W
MF
01005
1 2
I2S0_CODEC_ASP_MCK_R
I2S0_CODEC_ASP_BCLK
15
OUT
I2S0_CODEC_ASP_LRCK
15
OUT
I2S0_CODEC_ASP_DIN
15
IN
I2S0_CODEC_ASP_DOUT
15
OUT
I2S1_SPKAMP_MCK_R
I2S1_SPKAMP_BCLK
16 53
OUT
I2S1_SPKAMP_LRCK
16 53
OUT
I2S1_SPKAMP_DIN
16 53
IN
I2S1_SPKAMP_DOUT
16 53
OUT
NC_GPIO_GYRO_IRQ1
I2S2_CODEC_XSP_BCLK
15
OUT
I2S2_CODEC_XSP_LRCK
15 53
OUT
I2S2_CODEC_XSP_DIN
15
IN
I2S2_CODEC_XSP_DOUT
15 53
OUT
GPIO_SPKAMP_RIGHT_IRQ_L
16
IN
I2S3_SOC2BT_BCLK
10
OUT
I2S3_SOC2BT_LRCK
10
OUT
I2S3_BT2SOC_DATA
10
IN
I2S3_SOC2BT_DATA
10
OUT
BB_JTAG_TCK
24 27 52
OUT
BB_JTAG_TMS
24 27 52
OUT
BB_JTAG_TDI
24 27 52
OUT
BB_JTAG_TDO
24 27 52
IN
BB_JTAG_TRST_L
24 27 52
OUT
C30
AL32
AL31
AJ31
AK31
AL33
AL34
AK33
AJ32
AK34
E30
AJ33
AJ34
AH31
AH34
AG31
AG32
AH33
AF31
AG34
AE31
AF33
AE32
AD31
AE33
I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT
I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT
I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT
I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT
I2S4_MCK
I2S4_BCLK
I2S4_LRCK
I2S4_DIN
I2S4_DOUT
C
AV10
AN12
AT10
AP11
AN6
AP5
AT5
AV5
AU5
AV4
AU4
AR5
AU6
AR6
AP7
AN8
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
GPIO_BOARD_ID2
10
IN
GPIO_BOARD_ID1
10
IN
GPIO_BOARD_ID0
10
IN
SPI1_GRAPE_MISO
13 52
IN
SPI1_GRAPE_MOSI
13 52
OUT
SPI1_GRAPE_SCLK
13
OUT
SPI1_GRAPE_CS_L
13 52
OUT
SPI2_CODEC_MISO
15 53
IN
SPI2_CODEC_MOSI
15 53
OUT
SPI2_CODEC_SCLK
15 53
OUT
SPI2_CODEC_CS_L
15
OUT
NC_SPI0_SSIN
NC_SPI1_NAVAJO_MISO
NC_SPI1_NAVAJO_MOSI
NC_SPI1_NAVAJO_SCLK
NC_GPIO_NAVAJO2SOC_INT
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 3 OF 13
CRITICAL
VDDIO18_GRP2
VDDIO18_GRP2
VDDIO18_GRP1
VDDIO18_GRP1
VDDIO18_GRP1
SEP_7816UART0_RST
SEP_7816UART0_SCL
SEP_7816UART0_SDA
VDDIO18_GRP1
SEP_7816UART1_RST
SEP_7816UART1_SCL
SEP_7816UART1_SDA
SIO_7816UART0_RST
SIO_7816UART0_SCL
SIO_7816UART0_SDA
SIO_7816UART1_RST
SIO_7816UART1_SCL
VDDIO18_GRP2
SIO_7816UART1_SDA
DISP_VSYNC
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
I2C3_SCL
I2C3_SDA
DWI_CLK
DWI_DI
DWI_DO
SOCHOT0
SOCHOT1
AV6
AR7
AP8
AU7
AT11
AR11
W30
W32
AP19
AT18
AT19
AR1
AP3
AP2
AR4
AR2
AP4
AB33
AA31
AB31
AA33
AA32
AA34
AP18
AP17
AN17
I2C0_SCL_1V8
I2C0_SDA_1V8
I2C1_SOC2OSCAR_SWDCLK_1V8
I2C1_SOC2OSCAR_SWDIO_1V8
I2C2_SCL_1V8
I2C2_SDA_1V8
I2C3_SCL_1V8
I2C3_SDA_1V8
TP_SOC_TST_CPUSWITCH_OUT
NC_SEP_7816UART0_RST
SEP_I2C0_SCL
SEP_I2C0_SDA
NC_SEP_7816UART1_RST
NC_SEP_7816UART1_SCL
NC_SEP_7816UART1_SDA
HSIC1_WLAN2SOC_REMOTE_WAKE
HSIC1_WLAN2SOC_DEVICE_RDY
HSIC1_SOC2WLAN_HOST_RDY
HSIC2_BB2SOC_REMOTE_WAKE
HSIC2_BB2SOC_DEVICE_RDY
HSIC2_SOC2BB_HOST_RDY
DISPLAY_SYNC
DWI_AP_CLK
DWI_AP_DO
SOCHOT0_L
SOCHOT1_L
24 28
5
OUT
OUT
OUT
OUT
OUT
5
24 28
49 52
OUT
OUT
BI
BI
BI
IN
BI
28
44 53
44 53
5
5
5
48 52
48 53
5
44 53
5
13
11 48 52
5
11 48 52
16 52
5
16 52
20 22
5
20 22
51
5
51
48
TRISTAR
PMU
5
OUT
BI
SPK AMPS
ALS
PROX
19
5
19
GPIO_BTN_HOME_L
5
13 48
IN
GPIO_BTN_ONOFF_L
5
17 48
IN
GPIO_BTN_VOL_UP_L
17
IN
GPIO_BTN_VOL_DOWN_L
17
IN
GPIO_BTN_SRL_L
5
17 48
IN
GPIO_SOC2BEACON_EN
OUT
GPIO_SOC2AJ_HS4_SHUNT_EN
GPIO_SOC2AJ_HS3_SHUNT_EN
14
OUT
GPIO_BOARD_REV0
10
IN
GPIO_BOARD_REV1
10
IN
GPIO_BOARD_REV2
10
IN
15 52
IN
28 52
OUT
GPIO_GRAPE_IRQ_L
13 52
IN
28
IN
20
IN
GPIO_BOARD_ID3
10
IN
GPIO_BB2SOC_RESET_DET_L
24 28
IN
GPIO_BOOT_CONFIG0
10
IN
GPIO_PMU2SOC_IRQ_L
48
IN
GPIO_SOC2PMU_KEEPACT
5
48
OUT
GPIO_GRAPE_RST_L
13 52
OUT
GPIO_BB2SOC_GPS_SYNC
28
IN
GPIO_SOC2BB_RADIO_ON_L
24 26 52
IN
NC_GPIO_BB_HSIC_DEV_RDY
GPIO_BOOT_CONFIG1
10
IN
GPIO_FORCE_DFU
5
52
IN
TP_GPIO_DFU_STATUS
GPIO_BOOT_CONFIG2
10
IN
GPIO_BOOT_CONFIG3
10
IN
GPIO_SOC2OSCAR_DBGEN
19
OUT
GPIO_SOC2BB_RST_L
24 26 52
OUT
GPIO_PROX_IRQ_L
22
IN
GPIO_BB2SOC_GSM_TXBURST
28
IN
GPIO_SPKAMP_RST_L
5
16
OUT
GPIO_BT_WAKE
44 53
OUT
GPIO_TS2SOC2PMU_INT
11 48
IN
GPIO_SPKAMP_LEFT_IRQ_L
16
IN
GPIO_SOC2LCD_PWREN
18
OUT
GPIO_CODEC_IRQ_L
GPIO_SOC2BB_WAKE_MODEM
BB_IPC_GPIO
GPIO_ALS_IRQ_L
AC5
AB1
AB2
AD1
AD5
AE4
AF1
AE2
AE5
AF3
AF4
AF2
AG1
AG3
AG4
AH3
AH2
AH4
AG5
AJ5
AJ4
AK2
AP13
AP12
AR13
AN14
AT12
AT13
AV13
AP14
AU13
AP15
AR14
AT14
AT15
AP16
AR16
AT16
AT17
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
POP-1GB-DDR
SYM 2 OF 13
CRITICAL
VDDIO18_GRP1
OMIT
U0652
H6P
FCMSP
TMR32_PWM0
TMR32_PWM1
TMR32_PWM2
UART0_RXD
UART0_TXD
UART1_CTSN
UART1_RTSN
UART1_RXD
UART1_TXD
UART2_CTSN
UART2_RTSN
UART2_RXD
UART2_TXD
VDDIO18_GRP1
UART3_CTSN
UART3_RTSN
UART3_RXD
UART3_TXD
UART4_CTSN
UART4_RTSN
UART4_RXD
UART4_TXD
UART5_RTXD
UART6_RXD
UART6_TXD
VDDIO18_GRP2 VDDIO18_GRP2
AC31
AD34
AC32
AR19
AR18
AL2
AL4
AK4
AK3
AL5
AM3
AM2
AM1
AN3
AN4
AP1
AN1
AV3
AU3
AT3
AT2
AM5
W31
Y31
OSCAR_TIME_SYNC_HOST_INT
GPIO_SPKAMP_KEEPALIVE
CLK_32K_SOC2CUMULUS
UART0_SOC_RXD
UART0_SOC_TXD
UART1_BT2SOC_RTS_L
UART1_SOC2BT_RTS_L
UART1_BT2SOC_TX
UART1_SOC2BT_TX
NC_UART2_CTS
NC_UART2_RTS
UART2_WLAN2SOC_TX
UART2_SOC2WLAN_TX
UART3_BB2SOC_RTS_L
UART3_SOC2BB_RTS_L
UART3_BB2SOC_TX
UART3_SOC2BB_TX
PMU_GPIO_OSCAR2PMU_HOST_WAKE
GPIO_OSCAR_RESET_L
UART4_OSCAR2SOC_RXD
UART4_SOC2OSCAR_TXD
UART5_BATT_RTXD
UART6_TS_ACC_RXD
UART6_TS_ACC_TXD
IN
OUTOUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
BI
IN
OUT
19
5
16 52 14
13 52
11 52
11 52
44
44
44 53
44 53
44 53
53
44
24 28
24 28
11 24
28 52
11 24 28 52
19 48
19
19 53
19 53
45 48
11 52
11 52
D
C
=PP1V8_S2R_MISC
5
B
51 54
=PP1V8_ALWAYS
54
=PP1V8_S2R_MISC
5
51 54
R0771
220K
1
5%
1/32W
MF
01005
R0770
220K
1 2
5%
1/32W
MF
01005
R0765
220K
1 2
5%
1/32W
MF
01005
2
GPIO_BTN_HOME_L
GPIO_BTN_ONOFF_L
GPIO_BTN_SRL_L
(SCREEN ROTATION LOCK)
=PP1V8_SOC
4 5 7
5
13 48
5
17 48
5
17 48
10 18 54
I2C0_SDA_1V8
5
11 48 52
I2C0_SCL_1V8
5
11 48 52
I2C2_SDA_1V8
5
16 52
I2C2_SCL_1V8
5
16 52
I2C3_SDA_1V8
5
20 22
I2C3_SCL_1V8
5
20 22
SEP_I2C0_SDA
5
51
SEP_I2C0_SCL
5
51
I2C1_SOC2OSCAR_SWDIO_1V8
5
19
I2C1_SOC2OSCAR_SWDCLK_1V8
5
19
1
1
R0700
2.2K
5%
1/32W
MF
01005MF01005
2
2
R0701
2.2K
5%
1/32W
1
R0702
1.8K
5%
1/32W
MF
01005
2
1
R0703
1.8K
5%
1/32W
MF
01005
2
1
2.2K
5%
1/32W
MF
01005
2
1
R0705R0704
2.2K
5%
1/32W
MF
01005
2
1
R0750
2.2K
5%
1/32W
MF
01005
2
1
R0751
2.2K
5%
1/32W
MF
01005
2
NOSTUFF
1
R0752
2.2K
5%
1/32W
MF
01005
2
NOSTUFF
1
R0753
2.2K
5%
1/32W
MF
01005
2
1
R0739
100K
1%
1/32W
MF
01005
2
1
100K
1%
1/32W
MF
01005
2
1
R0736R0735
100K
1%
1/32W
MF
01005
2
1
R0737
100K
1%
1/32W
MF
01005
2
GPIO_SPKAMP_RST_L
GPIO_SOC2PMU_KEEPACT
HSIC1_SOC2WLAN_HOST_RDY
GPIO_FORCE_DFU
GPIO_SPKAMP_KEEPALIVE
1
R0738
100K
1%
1/32W
MF
01005
2
5
16
5
48
5
44 53
5
52
5
16 52
B
w w w . c h i n a f i x . c o m
=PP1V8_SOC
4 5 7
10 18 54
A
=PP1V8_S2R_MISC
5
51 54
R0754
100K
1 2
5%
1/32W
MF
01005
R0755
100K
1 2
5%
1/32W
MF
01005
SOCHOT0_L
SOCHOT1_L
5
49 52
SIZE
A
D
SYNC_MASTER=N/A
PAGE TITLE
5
48
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SOC: I/OS
Apple Inc.
R
6 3
SYNC_DATE=05/05/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
7 OF 121
SHEET
5 OF 54
124578
8 7 6 5 4 3
12
AN32
AN33
AN34
AP6
AP20
AP21
AP24
D
C
B
A
AP25
AP26
AP27
AP28
AP29
AP30
AP31
AP32
AR3
AR8
AR12
AR15
AR17
AR20
AR21
AR22
AR23
AR24
AR25
AR28
AR29
AR32
AT1
AT4
AT6
AT20
AT21
AT22
AT23
AT24
AT25
AT26
AT27
AT28
AT29
AT30
AT31
AT32
AU1
AU2
AU11
AU16
AU18
AU21
AU33
AU34
AV1
AV2
AV9
AV11
AV14
AV16
AV18
AV20
AV33
AV34
B10
B11
B12
B13
B15
B16
B17
B18
B19
B25
B28
B30
B33
B34
VSS
B1
B2
B4
B5
B6
B7
B8
B9
C1
C2
C3
C5
C6
C7
C9
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 12 OF 13
CRITICAL
VSS
C10
C11
C12
C13
C15
C16
C17
C18
C19
C22
C23
C24
C26
C27
C29
C31
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D15
D16
D17
D18
D19
D20
D21
D22
D32
E1
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E18
E19
E20
E21
E22
E31
E32
E34
F2
F3
F4
F5
F6
F7
F8
F9
F10
F12
F13
F14
F15
F26
F30
F31
G1
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G26
G28
AA10
AA12
AA14
AA16
AA18
AA22
AA24
AA26
AA28
AA30
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AB29
AB32
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AC30
AC34
AD11
AD13
AD15
AD17
AD19
AD21
AD23
AD25
AD29
AD32
AE10
AE12
AE14
AE16
AE18
AE22
AE24
AE26
AE28
AF11
AF13
AF15
AF17
AF19
A11
A13
A14
A16
A18
A25
A28
A30
A33
A34
AA1
AA2
AA3
AA4
AA8
AB5
AB7
AB9
AC4
AC8
AD2
AD7
AD9
AE3
AE8
AF5
AF7
AF9
A1
A2
A3
A4
A5
A7
A9
VSS
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 11 OF 13
CRITICAL
AF21
AF23
AF29
AF32
AG2
AG8
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG28
AG30
AH5
AH7
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25
AH27
AH29
AH32
AJ1
AJ3
AJ8
AJ10
AJ12
VSS
AJ14
AJ16
AJ18
AJ22
AJ24
AJ26
AJ28
AJ30
AK5
AK7
AK9
AK11
AK13
AK15
AK17
AK19
AK21
AK23
AK27
AK29
AK32
AL3
AL6
AL8
AL10
AL12
AL14
AL16
AL18
AL20
AL22
AL24
AL26
AL28
AL30
AM4
AM7
AM18
AM30
AN2
AN5
AN7
AB6
AM9
AM11
w w w . c h i n a f i x . c o m
AM13
AN16
AM15
AN19
AN20
AN21
AN22
AN23
AN24
AN31
=PP1V8_NAND_SOC
6
54
R0831
1
100K
1%
1/32W
MF
01005
2
FMI0_CE0_L
12 52
OUT
G32
H31
PPN0_CEN0
PPN0_CEN1
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 4 OF 13
PPN1_CEN0
PPN1_CEN1
R32
P32
NC_PPN1_CEN1NC_PPN0_CEN1
CRITICAL
FMI0_AD<0>
12
BI
FMI0_AD<1>
12
BI
FMI0_AD<2>
12
BI
FMI0_AD<3>
12 53
BI
FMI0_AD<4>
12
BI
FMI0_AD<5>
12
BI
FMI0_AD<6>
12
BI
FMI0_AD<7>
12
BI
FMI0_ALE
12
OUT
FMI0_CLE
12
OUT
FMI0_WE_L
12
OUT
12
OUT
FMI0_DQS
12 53 12
BI BI
R0870
240
1 2 1 2
1%
1/32W
MF
01005
FMI0_ZQ FMI1_ZQ
B32
C32
C33
C34
F32
F33
F34
G34
A31
B31
A32
D33
D34
E33
D31
PPN0_IO0
PPN0_IO1
PPN0_IO2
PPN0_IO3
PPN0_IO4
PPN0_IO5
PPN0_IO6
PPN0_IO7
PPN0_ALE
PPN0_CLE
PPN0_WEN
PPN0_REN
PPN0_DQS
PPN0_ZQ
PPN0_VREF
VDDIO18_GRP3
PPVREF_FMI_SOC
PPN1_IO0
PPN1_IO1
PPN1_IO2
PPN1_IO3
PPN1_IO4
PPN1_IO5
PPN1_IO6
PPN1_IO7
PPN1_ALE
PPN1_CLE
PPN1_WEN
PPN1_REN
PPN1_DQS
PPN1_VREF
PPN1_ZQ
M34
M33
L32
M32
K32
J32
H33
H34
N34
P31
N32
L31
L34
K33
N31
6 3
R0832
1
100K
1%
1/32W
MF
01005
2
FMI1_CE0_L
FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>
FMI1_ALE
FMI1_CLE
FMI1_WE_L
FMI1_RE_LFMI0_RE_L
FMI1_DQS
R0871
240
1%
1/32W
MF
01005
=PP1V8_NAND_SOC
1
R0860
50K
1%
1/32W
MF
01005
2
1
R0861
50K
1%
1/32W
MF
01005
2
SYNC_MASTER=N/A
PAGE TITLE
1
2
1
2
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
C0860
0.01UF
10%
6.3V
X5R
01005
C0861
0.01UF
10%
6.3V
X5R
01005
12 52
12
12
12
12
12
12
12
12
12
12
12
12
6
54
SOC: NAND
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=04/18/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
8 OF 121
SHEET
6 OF 54
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
=PP1V8_MIPI_SOC
D
=PP1V0_MIPI_SOC
54
NC_SENSOR0_ISTRB
NC_SENSOR0_XSHUTDOWN
NC_SENSOR1_ISTRB
NC_SENSOR1_XSHUTDOWN
MIPI0C_CAM_REAR_DATA_P<0>
23 53
IN
MIPI0C_CAM_REAR_DATA_N<0>
23 53
IN
MIPI0C_CAM_REAR_DATA_P<1>
23 53
IN
MIPI0C_CAM_REAR_DATA_N<1>
23 53
IN
DISPLAYPORT
C
=PP1V8_EDP_SOC
54
54
1
2
=PP1V0_EDP_PAD_DVDD_SOC
B
C0951
56PF
5%
16V
NP0-C0G
01005
R0901
0.00
1 2
0%
1/32W
MF
01005
1
C0952
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C0957
1.0UF
20%
6.3V
2
X5R
0201-1
1
C0953
56PF
5%
16V
2
NP0-C0G
01005
1
C0958
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C0954
0.22UF
20%
6.3V
2
X5R
0201
PP1V8_EDP_AVDD_AUX
1
C0955
1.0UF
20%
6.3V
2
X5R
0201-1
F20
G18
F17
F16
(14MA)
(14MA)
(10MA)
DP_PAD_DVDD
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
DP_PAD_AVDDX
DP_PAD_AVDDP0
(50MA)
DP_PAD_AVDD1
1
C0956
1.0UF
20%
6.3V
2
X5R
0201-1
F18
F19
DP_PAD_AVDD0
DP_PAD_AVDD_AUX
(50MA)
(1MA)
F21
F22
DP_PAD_AVDD2
DP_PAD_AVDD3
(50MA)
(50MA)
23 53
OUT
23 53
OUT
NC_MIPI0C_CAM_REAR_DATA_P2
NC_MIPI0C_CAM_REAR_DATA_N2
NC_MIPI0C_CAM_REAR_DATA_P3
NC_MIPI0C_CAM_REAR_DATA_N3
MIPI0C_CAM_REAR_CLK_P
MIPI0C_CAM_REAR_CLK_N
NC_MIPI0D_DPDATA0
NC_MIPI0D_DNDATA0
NC_MIPI0D_DPDATA1
NC_MIPI0D_DNDATA1
NC_MIPI0D_DPDATA2
NC_MIPI0D_DNDATA2
NC_MIPI0D_DPDATA3
NC_MIPI0D_DNDATA3
NC_MIPI0D_DPCLK
NC_MIPI0D_DNCLK
1
C0930
1UF
20%
4V
2
X6S
0204
AN10
SENSOR0_ISTRB
AR9
SENSOR0_XSHUTDOWN
AR10
SENSOR1_ISTRB
AP10
SENSOR1_XSHUTDOWN
AU27
MIPI0C_DPDATA0
AV27
MIPI0C_DNDATA0
AU26
MIPI0C_DPDATA1
AV26
MIPI0C_DNDATA1
AU24
MIPI0C_DPDATA2
AV24
MIPI0C_DNDATA2
AU23
MIPI0C_DPDATA3
AV23
MIPI0C_DNDATA3
AU25
MIPI0C_DPCLK
AV25
MIPI0C_DNCLK
AU32
MIPI0D_DPDATA0
AV32
MIPI0D_DNDATA0
AU31
MIPI0D_DPDATA1
AV31
MIPI0D_DNDATA1
AU29
MIPI0D_DPDATA2
AV29
MIPI0D_DNDATA2
AU28
MIPI0D_DPDATA3
AV28
MIPI0D_DNDATA3
AU30
MIPI0D_DPCLK
AV30
MIPI0D_DNCLK
AN25
AN26
AN27
MIPI_VDD10
(55MA)
AN28
AM25 AN29
VDDIO18_GRP1
U0652
POP-1GB-DDR
SYM 5 OF 13
CRITICAL
MIPI_VDD10
MIPI_VSS
AM29
AM28
AM27
AM26
OMIT
H6P
FCMSP
AL25
AR26
MIPI0D_VDD18
(2MA)
VDDIO18_GRP1
MIPI1C_DPDATA0
MIPI1C_DNDATA0
MIPI1C_DPDATA1
MIPI1C_DNDATA1
MIPI1C_DPCLK
MIPI1C_DNCLK
AR30
AR31
AR27
MIPI1D_VDD18
MIPI1D_VREG_0P4V
MIPI0D_VREG_0P4V
(2MA)
ISP0_SCL
ISP0_SDA
ISP1_SCL
ISP1_SDA
SENSOR0_CLK
SENSOR0_RST
SENSOR1_CLK
SENSOR1_RST
NC_MIPI0D_VREG
NC_MIPI1D_VREG
AT7
AV7
AU8
AP9
AV8
AT8
AU9
AT9
AT33
AT34
AP33
AP34
AR33
AR34
54
1
C0962
0.1UF
20%
6.3V
2
X5R-CERM
01005
ISP0_CAM_REAR_CLK_R
ISP1_CAM_FRONT_CLK_R
NC_MIPI1C_CAM_FRONT_DATA_P1
NC_MIPI1C_CAM_FRONT_DATA_N1
1
R0931
2.2K
5%
1/32W
MF
01005
2
1
R0930
2.2K
5%
1/32W
MF
01005
2
100
01005
1 2
49.9
01005
1 2
=PP1V8_SOC
1
1
R0932
R0933
2.2K
2.2K
5%
5%
1/32W
1/32W
MF
MF
01005
01005
2
2
ISP0_CAM_REAR_SCL
ISP0_CAM_REAR_SDA
ISP1_CAM_FRONT_SCL
ISP1_CAM_FRONT_SDA
R0941
R0940
MIPI1C_CAM_FRONT_DATA_P<0>
MIPI1C_CAM_FRONT_DATA_N<0>
ISP0_CAM_REAR_CLK
ISP0_CAM_REAR_SHUTDOWN_L
ISP1_CAM_FRONT_CLK
ISP1_CAM_FRONT_SHUTDOWN_L
MIPI1C_CAM_FRONT_CLK_P
MIPI1C_CAM_FRONT_CLK_N
4 5
10 18 54
D
23 52
BI
23 52
OUT
20 52
BI
20 52
OUT
23 52
OUT
23 52
OUT
20 52
OUT
20 52
OUT
20 53
IN
20 53
IN
20 53
OUT
20 53
OUT
C
B
TP_EDP_PAD_DC_TP
SOC_EDP_R_BIAS
NOSTUFF
1
C0950
0.01UF
10%
6.3V
2
X5R
01005
1
R0900
4.99K
1%
1/32W
MF
01005
2
A
E16
DP_PAD_DC_TP
E17
DP_PAD_R_BIAS
DP_PAD_DVSS
DP_PAD_AVSS2
DP_PAD_AVSS3
G20
G21
G16
SYM 6 OF 13
CRITICAL
DP_PAD_AVSSX
DP_PAD_AVSSP0
H18
H17
DP_PAD_AVSS0
DP_PAD_AVSS1
DP_PAD_AVSS_AUX
G17
H19
G19
D30
A20
B20
A21
B21
A22
B22
A23
B23
A24
B24
EDP_HPD
EDP_AUX_P
EDP_AUX_N
EDP_DATA_P<0>
EDP_DATA_N<0>
EDP_DATA_P<1>
EDP_DATA_N<1>
EDP_DATA_P<2>
EDP_DATA_N<2>
EDP_DATA_P<3>
EDP_DATA_N<3>
18
IN
18
BI
18
BI
18 53
OUT
18 53
OUT
18 53
OUT
18 53
OUT
18 53
OUT
18 53
OUT
18 53
OUT
18 53
OUT
VDDIO18_GRP3
EDP_HPD
DP_PAD_AUXP
DP_PAD_AUXN
DP_PAD_TX0P
DP_PAD_TX0N
w w w . c h i n a f i x . c o m
DP_PAD_TX1P
DP_PAD_TX1N
DP_PAD_TX2P
DP_PAD_TX2N
DP_PAD_TX3P
DP_PAD_TX3N
6 3
SYNC_MASTER=MLB
PAGE TITLE
SOC: DP,MIPI
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=05/04/2012
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
9 OF 121
SHEET
7 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
12
=PP1V2_VDDIOD_SOC
54
CAPS FOR VDDIOD ARE SHARED WITH VDDQ
D
AM20
AM21
AM22
AM23
AM24
R29
T29
U29
V29
AA6
H10
H11
H12
H13
H14
H15
H6
H7
H8
H9
M6
N6
P6
R6
T6
U6
V6
W6
Y6
VDDIOD_DDR0CA
VDDIOD_DDR1CA
VDDIOD_DDRDQ
(1000MA)
SYM 9 OF 13
C
CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX
=PP1V8_VDDIO18_SOC
9
54
1
C1070
4.7UF
20%
6.3V
2
X5R
402
1
C1072
1UF
20%
4V
2
X6S
B
0204
1
C1071
1UF
20%
4V
2
X6S
0204
1
C1073
0.47UF
20%
4V
2
X7S
0204
FL1000
1KOHM-25%-0.2A
0201
PP1V8_XTAL
52
1
C1042
1.0UF
20%
10V
2
X5R-CERM
0201-1
AD6
AH6
AM8
AM10
VDDIO18_GRP1
AM12
AM14
AM16
AM19
AD30
AH30
21
G25
G27
H30
K30
M30
P30
G29
G24
VDDIO18_GRP4
(65MA)
(GPIO,UART,SPI,I2C)
(SENSOR,SOCHOT,PMU)
VDDIO18_GRP2
(20MA)
VDDIO18_GRP3
(31MA)
(2MA)
A
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
CRITICAL
R33
T1
T2
VSS
T3
T5
T7
T9
T11
T13
T15
T17
T19
T21
T23
T25
T27
T30
T31
T32
T33
T34
U3
U5
U8
U10
U12
U14
U18
U20
U22
U24
U26
U28
U30
U34
V2
V3
V4
V5
V7
V9
V11
V13
V15
V17
V19
V21
V23
V25
V27
V30
V32
V34
W1
W2
W3
W4
W5
W8
W10
W12
W14
W16
W18
W20
W22
W24
W26
W28
W33
Y2
Y3
Y4
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y27
Y29
Y32
AM17
Y30
AC6
AE6
AG6
AJ6
AE30
=PP1V2_S2R_DDR
8
54
1
R1005
2.21K
1%
1/32W
MF
01005
2
PPVREF_DDR0_CA
NOSTUFF
1
0.01UF
10%
6.3V
2
X5R
01005
C1002
=PP1V2_VDDQ_DDR
8
54
1
R1006
2.21K
1%
1/32W
MF
01005
2
1
R1053
1.00K
1%
1/32W
MF
01005
2
PPVREF_DDR0_DQ
NOSTUFF
1
0.01UF
10%
6.3V
2
X5R
01005
C1054
=PP1V2_S2R_DDR
8
54
1
R1054
1.00K
1%
1/32W
MF
01005
2
1
R1051
2.21K
1%
1/32W
MF
01005
2
PPVREF_DDR1_CA
NOSTUFF
1
0.01UF
10%
6.3V
2
X5R
01005
C1052
=PP1V2_VDDQ_DDR
8
54
1
R1052
2.21K
1%
1/32W
MF
01005
2
1
R1055
1.00K
1%
1/32W
MF
01005
2
PPVREF_DDR1_DQ
1
R1056
1.00K
1%
1/32W
MF
01005
w w w . c h i n a f i x . c o m
2
NOSTUFF
1
2
01005
C1056
0.01UF
10%
6.3V
X5R
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8
=PP1V2_S2R_DDR_SOC
54
1
C1000
0.1UF
20%
6.3V
X5R-CERM
2
01005
1
2
R1001
240
1%
1/32W
MF
01005
6 3
1
R1000
240
1%
1/32W
MF
01005
2
NOTE: CKEIN CONFIRMED 1.8V TOLERANT
DDR0_CA_ZQ
DDR1_CA_ZQ
DDR0_DQ_ZQ
1
1
R1030
240
1%
1/32W
MF
01005
2
2
(DDR IMPEDANCE CONTROL)
=PP1V2_S2R_DDR
8
54
R1031
240
1%
1/32W
MF
01005
1
C1009
4.3UF
20%
4V
2
X5R-CERM
0610
=PP1V8_S2R_DDR
54
54
DDR1_DQ_ZQ
=PP1V2_VDDQ_DDR
8
RESET_SOC_L
4
10 11 24 48 52
ON 5/6/12, BY MANU G
PPVREF_DDR0_CA
8
PPVREF_DDR1_CA
8
PPVREF_DDR0_DQ
8
PPVREF_DDR1_DQ
8
C1006
1UF
20%
4V
X6S
0204
1
C1015
4.3UF
20%
4V
2
X5R-CERM
0610
C1028
1UF
20%
4V
X6S
0204
1
C1007
1UF
20%
4V
2
X6S
0204
1
C1004
20%
4V
2
X7S
0204
1
2
1
2
1
C1026
0.47UF
20%
4V
2
X7S
0204
1
2
1
2
1
C1031
0.47UF
20%
4V
2
X7S
0204
0.47UF
C1027
4.3UF
20%
4V
X5R-CERM
0610
C1029
1UF
20%
4V
X6S
0204
AP22
DDR0_CKEIN
U32
DDR1_CKEIN
AP23
DDR0_VDD_CKE
U31
DDR1_VDD_CKE
AU15
DDR0_RREF_CA
AC33
DDR1_RREF_CA
F11
DDR0_RREF_DQ
T4
DDR1_RREF_DQ
AU17
DDR0_VREF_CA
Y33
DDR1_VREF_CA
D14
DDR0_VREF_DQ
U4
DDR1_VREF_DQ
AB34
AF34
AV12
(CURRENT CONSUMPTION
SHARED WITH VDDIOD)
AV15
AV19
VDDCA
AV21
R34
W34
AC2
AD33
C20
G2
J33
L3
P33
U2
(500MA)
U33
Y34
VDD2
AG33
AJ2
AU10
AU14
AU20
AU22
AV17
C4
C8
C14
D24
AE34
AK1
B3
B14
D25
E2
(45MA)
J34
VDD1
P34
U1
V33
AU12
AU19
AV22
A6
A8
C21
C25
F1
J1
L1
(CURRENT CONSUMPTION
SHARED WITH VDDIOD)
N1
R1
V1
VDDQ
A10
A12
A15
A17
A19
AC1
AE1
AH1
AL1
Y1
SYNC_MASTER=N/A
PAGE TITLE
(<1MA)
(<1MA)
POP-1GB-DDR
CRITICAL
SYM 7 OF 13
OMIT
U0652
H6P
FCMSP
SOC: SRAM, IO PWRS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
G30
G31
G33
H1
H2
H3
H4
H5
H25
H27
H29
H32
J2
J3
J4
J5
J6
J8
J10
J12
J14
J16
J18
J20
J22
J24
J26
J28
J30
J31
VSS
K1
K2
K3
K4
K5
K7
K9
K11
K13
K15
K17
K19
K21
K23
K25
K27
K29
K31
K34
L2
SYNC_DATE=04/18/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
10 OF 121
SHEET
8 OF 54
124578
SIZE
D
C
B
A
D
8 7 6 5 4 3
=PPVDD_GPU
54
C1170
15UF
20%
4V
X5R
0402
C1116
15UF
20%
4V
X5R
0402
CRITICAL
C1122
4.3UF
20%
4V
X5R-CERM
0610
CRITICAL
C1128
1UF
20%
4V
X6S
0204
C1134
8.2PF
+/-0.5PF
16V
NP0-C0G-CERM
01005
CRITICAL
1
C1141
0.47UF
20%
4V
2
X7S
0204
1
C1171
15UF
20%
4V
2
X5R
0402
1
2
1
2
CRITICAL
C1140
0.47UF
20%
4V
X7S
0204
1
2
1
2
1
2
1
2
1
2
=PPVDD_SOC
54
1
C1100
4.3UF
20%
4V
2
X5R-CERM
0610
D
CRITICAL
1
C1104
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1110
0.47UF
20%
4V
2
X7S
0204
CRITICAL
1
C1105
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1111
0.47UF
20%
4V
2
X7S
0204
C
B
A
PPVDD_SOC_SOC_SENSE
53
CRITICAL
1
C1106
1UF
20%
4V
2
X6S
0204
1
2
AA7
AA17
AA19
L29
M28
N27
P26
R25
U15
V22
AB30
AH20
H26
J25
K20
K22
K24
K26
K28
L7
L9
L11
L13
L15
L17
L19
L21
L23
L25
L27
(VDD BALLS = VDD_SOC PWR DOMAIN)
M8
M10
M12
M14
M16
M18
M20
M22
M24
M26
N7
N9
N11
N13
N15
N17
N19
N21
N23
N25
N29
P8
P10
P12
P14
P16
P18
P20
P22
P24
P28
R7
R9
R11
R13
R15
R17
R19
R21
V31
VDD_SENSE
CRITICALCRITICAL
1
C1101
4.3UF
20%
4V
2
X5R-CERM
0610
CRITICAL
1
C1107
1UF
20%
4V
2
X6S
0204
C1112
0.22UF
20%
6.3V
X5R
0201
1
2
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 10 OF 13
CRITICAL
2,500MA FOR VDD_SOC
@125C
@1.0V
(THERMAL VIRUS)
C1113
0.22UF
20%
6.3V
X5R
0201
OMIT
CRITICAL
1
C1102
4.3UF
20%
4V
2
X5R-CERM
0610
CRITICAL
1
C1108
1UF
20%
4V
2
X6S
0204
1
C1114
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
CRITICAL
1
C1103
4.3UF
20%
4V
2
X5R-CERM
0610
CRITICAL
1
C1109
1UF
20%
4V
2
X6S
0204
R23
R27
T14
T16
T18
T20
T22
T24
T26
T28
U7
U17
U19
U21
U23
U25
U27
V14
V16
V18
V20
V24
V26
V28
W7
W17
W19
Y16
Y18
Y20
AN11
AB14
VDDVDD
AB20
AN13
AD20
AN15
AE21
AF6
AF20
AF30
AN18
AK6
AK20
AK30
AL23
AN9
H24
H28
J7
J9
J11
J13
J15
J17
J19
J21
J23
J27
J29
K6
K8
K10
K12
K14
K16
K18
=PPVDD_SRAM_SOC
54
1
C1150
1UF
20%
4V
2
X6S
0204
1
C1152
0.47UF
20%
4V
2
X7S
0204
=PP1V8_VDDIO18_SOC
8
54
1
C1160
0.1UF
20%
6.3V
2
X5R-CERM
01005
AD24
1
C1148
4.3UF
20%
4V
2
X5R-CERM
0610
1
C1151
1UF
20%
4V
2
X6S
0204
1
C1153
0.47UF
20%
4V
2
X7S
0204
w w w . c h i n a f i x . c o m
AD26
AD28
AE23
AE25
AE27
VDD_SRAM_CPU
1,500MA FOR CYCLONE + M$ SRAM
AF24
@125C
AF26
@1.0V
AF28
AK25
Y25
AA9
AA11
AA13
AA15
(1500MA)
AB8
T8
T10
T12
U9
U11
U13
VDD_SRAM_SOC
V8
V10
V12
W9
W11
W13
W15
Y8
Y10
Y12
Y14
AJ20
VDD_ANA_TMPSADC0
AA20
VDD_ANA_TMPSADC1
AB4
VDD_ANA_TMPSADC2
H22
VDD_ANA_TMPSADC3
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 8 OF 13
CRITICAL
(2.5MA)
(2.5MA)
(2.5MA)
(2.5MA)
VSS
L4
L5
L6
L8
L10
L12
L14
L16
L18
L20
L22
L24
L26
L28
L30
L33
M1
M2
M3
M4
M5
M7
M9
M11
M13
M15
M17
M19
M21
M23
M25
M27
M29
M31
N2
N3
N4
N5
N8
N10
N12
N14
N16
N18
N20
N22
N24
N26
N28
N30
N33
P1
P2
P3
P4
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
P27
P29
R2
R3
R4
R5
R8
R10
R12
R14
R16
R18
R20
R22
R24
R26
R28
R30
R31
CRITICAL
1
C1139
0.47UF
20%
4V
2
X7S
0204
1
C1115
15UF
20%
4V
2
X5R
0402
CRITICAL
1
C1121
4.3UF
20%
4V
2
X5R-CERM
0610
CRITICAL
1
C1127
1UF
20%
4V
2
X6S
0204
1
C1133
0.22UF
20%
6.3V
2
X5R
0201
1
2
CRITICAL
C1117
4.3UF
20%
4V
X5R-CERM
0610
CRITICAL
C1123
1UF
20%
4V
X6S
0204
CRITICAL
1
C1129
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1135
0.47UF
20%
4V
2
X7S
0204
CRITICAL
1
C1142
0.47UF
20%
4V
2
X7S
0204
CRITICAL
1
C1172
4.3UF
20%
4V
2
X5R-CERM
0610
1
2
1
2
CRITICAL
C1118
4.3UF
20%
4V
X5R-CERM
0610
CRITICAL
C1124
1UF
20%
4V
X6S
0204
CRITICAL
1
C1130
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1136
0.47UF
20%
4V
2
X7S
0204
1
C1143
0.22UF
20%
6.3V
2
X5R
01005
CRITICAL
1
C1173
4.3UF
20%
4V
2
X5R-CERM
0610
1
2
CRITICAL
C1188
0.47UF
20%
4V
X7S
0204
54
1
2
1
2
CRITICAL
1
C1174
4.3UF
20%
4V
2
X5R-CERM
0610
CRITICAL
1
C1181
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1189
2
=PPVDD_CPU
CRITICAL
C1119
4.3UF
20%
4V
X5R-CERM
0610
CRITICAL
C1125
1UF
20%
4V
X6S
0204
CRITICAL
1
C1131
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1137
0.47UF
20%
4V
2
X7S
0204
1
C1144
0.22UF
20%
6.3V
2
X5R
01005
PPVDD_CPU_SOC_SENSE
53
CRITICAL
1
C1182
1UF
20%
4V
2
X6S
0204
0.47UF
20%
4V
X7S
0204
CRITICAL
1
C1120
4.3UF
20%
4V
2
X5R-CERM
0610
CRITICAL
1
C1126
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1132
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1138
0.47UF
20%
4V
2
X7S
0204
1
C1145
0.22UF
20%
6.3V
2
X5R
0201
CRITICAL
1
C1175
4.3UF
20%
4V
2
X5R-CERM
0610
1
2
CRITICAL
1
C1183
1UF
2
C1190
0.22UF
20%
6.3V
X5R
01005
20%
4V
X6S
0204
CRITICAL
1
C1176
4.3UF
20%
4V
2
X5R-CERM
0610
AA21
AA23
AA25
AA27
AA29
AB22
AB24
AB26
AB28
AC21
AC23
AC25
AC27
AC29
AD22
AD27
AE29
AF22
AF25
AF27
AG21
AG23
AG25
AG27
AG29
AH22
AH24
AH26
AH28
AJ21
AJ23
AJ25
AJ27
AJ29
AK22
AK24
AK26
AK28
AL21
AL27
W21
W23
W25
W27
W29
Y22
Y24
Y26
Y28
AL29
AN30
CRITICAL
1
C1177
4.3UF
20%
4V
2
X5R-CERM
0610
CRITICAL
1
C1184
0.47UF
20%
4V
2
X7S
0204
1
C1191
0.22UF
20%
6.3V
2
X5R
01005
10,800MA FOR CPU0+1
@125C
@1.1V/1.2GHZ
VDD_SENSE_CPU
SYNC_MASTER=N/A
PAGE TITLE
SOC: VDD, SRAM, CPU, GPU PWRS
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CRITICAL
1
C1178
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1185
0.47UF
20%
4V
2
X7S
0204
1
0.22UF
20%
6.3V
2
X5R
01005
OMIT
U0652
H6P
POP-1GB-DDR
FCMSP
SYM 13 OF 13
CRITICAL
7,500MA FOR G3 GPU
R
CRITICAL
1
C1179
1UF
20%
4V
2
X6S
0204
CRITICAL
1
C1186
0.47UF
20%
4V
2
X7S
0204
1
C1193C1192
0.22UF
20%
6.3V
2
X5R
01005
@125C
@1.1V
VDD_GPUVDD_CPU
VDD_GPU_SENSE
Apple Inc.
1
2
1
2
1
C1194
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
6 3
12
CRITICAL
C1180
1UF
20%
4V
X6S
0204
CRITICAL
C1187
0.47UF
20%
4V
X7S
0204
AB10
AB12
AB16
AB18
AC11
AC13
AC15
AC17
AC19
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE7
AE9
AF10
AF12
AF14
AF16
AF18
AF8
AG11
AG13
AG15
AG17
AG19
AG7
AG9
AH10
AH12
AH14
AH16
AH18
AH8
AJ11
AJ13
AJ15
AJ17
AJ19
AJ7
AJ9
AK10
AK12
AK14
AK16
AK18
AK8
AL11
AL13
AL15
AL17
AL19
AL7
AL9
AM6
PPVDD_GPU_SOC_SENSE
AA5
SYNC_DATE=04/18/2011
DRAWING NUMBER
051-0886
REVISION
BRANCH
PAGE
11 OF 121
SHEET
9 OF 54
124578
A.0.0
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
D
BOARD ID
C
BOOT CONFIG ID
BOOT_CONFIG[3] (GPIO29)
BOOT_CONFIG[2] (GPIO28)
BOOT_CONFIG[1] (GPIO25)
BOOT_CONFIG[0] (GPIO18)
BOARD_ID[3]
BOARD_ID[2]
BOARD_ID[1]
BOARD_ID[0]
10 18 54
MLB
MLB_B
MLB_C
=PP1V8_SOC
4 5 7
GPIO_BOARD_ID3
5
GPIO_BOARD_ID2
5
GPIO_BOARD_ID1
5
GPIO_BOARD_ID0
5
ID[3-0] SYSTEM
1010 J85 AP
1011 J85 DEV
1100 J86 AP
1101 J86 DEV
1110 J87 AP
1111 J87 DEV
=PP1V8_SOC
4 5 7
10 18 54
GPIO_BOOT_CONFIG3
5
GPIO_BOOT_CONFIG2
5
GPIO_BOOT_CONFIG1
5
GPIO_BOOT_CONFIG0
5
BOOT_CONFIG[3-0]
0000
SPI0
SPI0 TEST MODE
0001
0010
NAND <-- SELECTED
0011
NAND TEST MODE
1
R1213
2.2K
5%
1/32W
MF
01005
2
S/W READ FLOW
1. SET GPIO AS INPUT
2. DISABLE PU AND ENABLE PD
3. READ
NOSTUFFNOSTUFF
1
R1200
2.2K
5%
1/32W
MF
01005 01005
2
ID_J86_J87
1
R1204
2.2K
5%
1/32W
MF
01005
2
1
R1201
2.2K
5%
1/32W
MF
01005
2
ID_J85_J87
1
R1205
2.2K
5%
1/32W
MF
01005
2
1
R1202
2.2K
5%
1/32W
MF
01005
2
S/W READ FLOW
1. SET GPIO AS INPUT
2. DISABLE PU AND ENABLE PD
3. READ
ID_DEV
1
R1206
2.2K
5%
1/32W
MF
01005
2
NOSTUFF
1
R1203
2.2K
5%
1/32W
MF
2
JTAG
JTAG_SOC_TRST_L
4
52
1
R1211
100
5%
1/32W
MF
01005
2
JTAG_SOC_SEL
1
R1210
100
5%
1/32W
MF
01005
2
1 2
R1260
100
5%
1/32W
MF
01005
NOSTUFF
R1250
0.00
1 2
0%
1/32W
MF
01005
4
52
OUT
SOC_TESTMODE
SOC_FAST_SCAN_CLK
SOC_HOLD_RESET
RESET_SOC_L
4
52
4
4
4 8
11 24 48 52
I2S3_SOC2BT_BCLK
5
I2S3_SOC2BT_LRCK
5
I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA
5
I2S3_SOC2BT_DATA
5
WDOG_SOC
4
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
I2S4_SOC2BT_BCLK
I2S4_SOC2BT_LRCK
I2S4_SOC2BT_DATA
WDOG_SOC2PMU_RESET_IN
D
44
44
44
44
48
C
BOARD REVISION
B
A
GPIO_BOARD_REV2
5
GPIO_BOARD_REV1
5
GPIO_BOARD_REV0
5
BRD_REV[2-0]
EVT101
NOSTUFF
1
R1207
2.2K
5%
1/32W
MF
01005
2
1. SET GPIO AS INPUT
2. ENABLE PU AND DISABLE PD
3. READ
CKPLUS RULE EXCEPTIONS
SCHEMATIC DEFINED CONSTRAINTS (YES/NO)
1
R1208
2.2K
5%
1/32W
MF
01005
2
S/W READ FLOW
REQUIRED
SIM CARD
NOSTUFF
1
R1209
2.2K
5%
1/32W
MF
01005
2
24 28 52
IN
PP_LDO6_RUIM_1V8
24 25 27 52
SIMCRD_RST_CONN
SIMCRD_CLK_CONN
CELL
1
C3001
1.0UF
10%
16V
2
X5R
0402
1
VCC VPP
CELL
J3000
SIM-CARD-X113-X223
RESET
CLK
F-ST-SM
GND
DETGND
9
8
2
3
GND
GND
111012
NC_J3000_5
5
I/O
DETECT
GND
GND
4
B
CELL
1
R3000
15.00K
1%
1/32W
MF
01005
2
6
7
SIMCRD_IO_CONN
SIM_TRAY_DETECT
CELL
1
C3002
100PF
5%
6.3V
2
CERM
01005
24 28 52 24 28 52
BIIN
24 28 52
OUT
w w w . c h i n a f i x . c o m
SIZE
A
D
SYNC_MASTER=N/A
PAGE TITLE
SOC: MISC & ALIASES
Apple Inc.
R
TABLE_DASHBOARD_INFO
NO
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=04/11/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
12 OF 121
SHEET
10 OF 54
124578
8 7 6 5 4 3
343S0658 = TRISTAR 2, A1
998-5855 = TRISTAR 2, TC
343S0639 = TRISTAR 2, A0
343S0614 = TRISTAR 1
12
D
D
TRISTAR
=PP3V0_S2R_TRISTAR
54
C
TO USB BB MUX
AP USB
ACCESSORY UART
AP DEBUG UART
BB DEBUG UART
(T’S OFF TO H4A UART4)
1
C1320
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
54 54
MIKEY_TS_P
15 52
MIKEY_TS_N
15 52
USB_BB_P
24 52 53
USB_BB_N
24 52 53
PMU_USB_BRICKID
48
USB_SOC_P
4
52
USB_SOC_N
4
52
UART6_TS_ACC_TXD
5
52
UART6_TS_ACC_RXD
5
52
UART0_SOC_TXD
5
52
UART0_SOC_RXD
5
52
UART3_BB2SOC_TX
5
24 28 52
UART3_SOC2BB_TX
5
24 28 52
JTAG_SOC_TCK
4
52
JTAG_SOC_TMS
4
52
1
C1300
0.1UF
20%
6.3V
2
X5R-CERM
01005
=PP1V8_S2R_TRISTAR
1
C1321
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
2
1
2
C1301
C1360
1.0UF
20%
10V
X5R-CERM
0201-1
0.1UF
20%
6.3V
X5R-CERM
01005
CBTL1610A1UK
C3
DIG_DP
C4
DIG_DN
A1
USB1_DP
B1
USB1_DN
C2
BRICK_ID
A3
USB0_DP
B3
USB0_DN
E2
UART0_TX
E1
UART0_RX
F2
UART1_TX
F1
UART1_RX
D2
UART2_TX
D1
UART2_RX
A5
JTAG_CLK
B5
JTAG_DIO
F4
F3
VDD_3V0
VDD_1V8
U1300
WLCSP
CON_DET_L
POW_GATE_EN*
SWITCH_EN
HOST_RESET
DVSS
DVSS
F5C1A6
CRITICAL
D5
ACC_PWR
BYPASS
DVSS
P_IN
ACC1
ACC2
DP1
DN1
DP2
DN2
SDA
SCL
INT
1
C1302
0.1UF
10%
6.3V
2
CERM-X5R
0201
F6
C5
PPOUT_E75_ACC_ID1
E5
PPOUT_E75_ACC_ID2
A2
E75_DPAIR1_P
B2
E75_DPAIR1_N
A4
E75_DPAIR2_P
B4
E75_DPAIR2_N
E3
TS_CON_DET_L
D6
OVP_SW_EN_L
E4
RESET_SOC_L
B6
TS2PMU_RESET_IN
D3
I2C0_SDA_1V8
D4
I2C0_SCL_1V8
C6
GPIO_TS2SOC2PMU_INT
E6
TRISTAR_BYPASS
CRITICAL
1
C1303
1.0UF
20%
10V
2
X5R-CERM
0201-1
1
C1322
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
43
43
43
43
43
43
43
OUT
IN
OUT
5
48 52
5
48 52
OUT
VOLTAGE=3V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5MM
TRISTAR BYPASS FOR 3V LDO
46
4 8
10 24 48 52
48
5
48
=PP3V3_ACC
PPVBUS_PROT
CRITICAL
1
C1361
1UF
10%
25V
2
X5R
402
46 52
C
B
L81_MBUS_REF
15
OUT
R1370
0.00
1 2
0%
1/32W
MF
01005
B
w w w . c h i n a f i x . c o m
A
SYNC_MASTER=N/A
PAGE TITLE
IO: TRISTAR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=N/A
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
13 OF 121
SHEET
11 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
12
D
=PP3V3_NAND
54
OA0
OB0
1
2
C1404
G3
H2
J3
K2
L5
K6
J5
H6
G1
J1
L1
N3
N5
L7
J7
G7
0.47UF
20%
4V
X7S
0204
VDDI
IO0-0
IO1-0
IO2-0
IO3-0
IO4-0
IO5-0
IO6-0
IO7-0
IO0-1
IO1-1
IO2-1
IO3-1
IO4-1
IO5-1
IO6-1
IO7-1
TCKC
TMSC
OB8
F2M6B6
VCC
VSS
N1
OC8
N7
CRITICAL
OMIT
U1400
LGA-12X17
XXNM-XGBX8-MLC-PPN1.5-ODP
VSSQ
A7M2L3F6B2
OC0
OD8
VCCQ
OD0
OE8
OF8G0OE0
OF0
G8
OA8
CE0*
CLE0
ALE0
WE0*
RE0*
DQS0
DQS0*
R/B0*
CE1*
CLE1
ALE1
WE1*
RE1*
DQS1
DQS1*
R/B1*
VREF
RE0
RE1
A5
A3
C1
E3
B4
C7
H4
F4
E5
C5
C3
D2
E1
D4
D6
M4
K4
E7
G5
A1
ZQ
FMI0_CE0_L
FMI0_CLE
FMI0_ALE
FMI0_WE_L
NC_U1400_RE0
FMI0_RE_L
FMI0_DQS
NC_U1400_DQS0
TP_U1400_RB0
FMI1_CE0_L
FMI1_CLE
FMI1_ALE
FMI1_WE_L
NC_U1400_RE1
FMI1_RE_L
FMI1_DQS
NC_U1400_DQS1
TP_U1400_RB1
FMI_ZQ_U1400
1
2
C1410
15UF
20%
4V
X5R
0402
53
53
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
R1454
243
1%
1/32W
MF
01005
2
1
C1411
15UF
20%
4V
2
X5R
0402
6
52
6
6
6
6
6
53
6
52
6
6
6
6
6
PPVREF_FMI_NAND
1
2
C1412
15UF
20%
4V
X5R
0402
1
2
C1413
2.2UF
20%
4V
X5R-CERM
0201
1
2
C1493
27PF
5%
16V
NP0-C0G
01005
=PP1V8_NAND
1
C1494
27PF
5%
16V
2
NP0-C0G
01005
1
R1460
50K
1%
1/32W
MF
01005
2
1
R1461
50K
1%
1/32W
MF
01005
2
12 48 54
=PP1V8_NAND
1
C1460
0.01UF
10%
6.3V
2
X5R
01005
1
C1461
0.01UF
10%
6.3V
2
X5R
01005
12 48 54
C1401
10UF
20%
6.3V
CERM-X5R
0402-2
1
2
C1402
10UF
20%
6.3V
CERM-X5R
0402-2
1
C1480
10UF
20%
6.3V
2
CERM-X5R
0402-2
1
2
1
2
53
C1405
1UF
20%
4V
X6S
C1492
27PF
5%
16V
NP0-C0G
01005
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
1
C1406
1UF
20%
6.3V
2
X5R
0201
PPVDDI_NAND
1
C1450
2.2UF
20%
4V
2
X5R-CERM
0201
FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>
FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>
1
2
C1407
1UF
20%
6.3V
X5R
02010204
1
2
C1490
27PF
5%
16V
NP0-C0G
01005
1
2
C1491
27PF
5%
16V
NP0-C0G
01005
1
2
1
C1400
10UF
20%
6.3V
2
CERM-X5R
0402-2
LAYOUT NOTE FOR U1400 VDDI:
ENSURE TRACE INDUCTANCE < 2NH
C
B
TP_TCKC_U1400
53
TP_TMSC_U1400
53
D
C
B
w w w . c h i n a f i x . c o m
A
SYNC_MASTER=MLB
PAGE TITLE
NAND STORAGE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=05/04/2012
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
14 OF 121
SHEET
12 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
TOUCH SUBSYSTEM
12
L1700
1
R1751
100K
1%
1/32W
MF
01005
2
240OHM-350MA
0201
CRITICAL
1
C1750
0.1UF
10%
16V
2
X5R-CERM
0201
VCC_MAIN_GRAPE_RAMP
CRITICAL
1
C1751
4700PF
10%
10V
2
X7R
201
21
18
VDD
U1700
TDFN
GND
1
C1702
1000PF
10%
16V
2
X7R-CERM
0201
CRITICAL
D
3
1
C1700
27PF
5%
16V
2
NP0-C0G
01005
1
C1701
1UF
10%
10V
2
X5R
402
=PP1V8_S2R_GRAPE
54
SLG5AP302
7
CAP
2 5
ON S
PP5V25_GRAPE_FILT
CRITICAL
1
C1752
1UF
20%
6.3V
2
X5R
0201
PP1V8_GRAPE_SW
CRITICAL
1
C1753
10UF
20%
10V
2
X5R-CERM
0402-2
52
SPI1_GRAPE_SCLK
5
DISPLAY_SYNC
5
1 2
R1753
0.00
0%
1/32W
MF
01005
R1752
0.00
1/32W
01005
1 2
NOSTUFF
1
C1761
27PF
5%
16V
2
NP0-C0G
01005
0%
MF
PP3V0_S2R_HALL_FILT
13 52
52
SPI1_GRAPE_SCLK_R
SPI1_GRAPE_MISO
5
52
SPI1_GRAPE_MOSI
5
52
SPI1_GRAPE_CS_L
5
52
CLK_32K_SOC2CUMULUS
5
52
GPIO_GRAPE_IRQ_L
5
52
GPIO_GRAPE_RST_L
5
52
PP1V8_GRAPE_FILT
13 52
=PP5V25_GRAPE
D
54 13 52
=PPVCC_MAIN_GRAPE
54
=PP1V8_GRAPE
54
C
L1760
LAYOUT NOTE:
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION
0.38 DCR
L1701
240OHM-350MA
0201
21
1
C1703
27PF
5%
16V
2
NP0-C0G
01005
1
C1704
1UF
20%
6.3V
2
X5R
0201
1
2
PP1V8_GRAPE_FILT
C1705
1000PF
10%
16V
X7R-CERM
0201
13 52
GPIO_BTN_HOME_L
5
48 13 52
150OHM-25%-200MA-0.7DCR
01005
21
RCPT - MLB 998-4526 -> 516S1054
(PLUG - FLEX 998-4527)
503304-2010
DISPLAY_SYNC_R
52
GPIO_BTN_HOME_R_L
1
C1760
27PF
5%
16V
2
NP0-C0G
01005
CRITICAL
J1700
F-ST-SM-1
2
4
6
8
10
12
14
16
18
20
22
21
1
3
5
7
9
11
13
15
17
19
23
24
R1790
1.00K
1 2
1%
1/32W
MF
01005
GPIO_BTN_HOME_FILT_L
NC_PMU_GPIO_HALL_IRQ_4
PMU_GPIO_MB_HALL3_IRQ
PMU_GPIO_MB_HALL2_IRQ
PMU_GPIO_MB_HALL1_IRQ
PP5V25_GRAPE_FILT
GPIO_BTN_HOME_FILT_L
13 52
48
48
48
D
13 52
C
B
=PP3V0_S2R_HALL
54 13 52
L1702
240-OHM-0.2A-0.8-OHM
0201-2
21
1
C1706
27PF
5%
16V
2
NP0-C0G
01005
1
C1707
1UF
20%
6.3V
2
X5R
0201
1
C1708
1000PF
10%
16V
2
X7R-CERM
0201
PP3V0_S2R_HALL_FILT
B
w w w . c h i n a f i x . c o m
A
6 3
SYNC_MASTER=N/A
PAGE TITLE
TOUCH: SUPPORT CKT & CONN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=06/21/2010
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
17 OF 121
SHEET
13 OF 54
124578
SIZE
A
D
8 7 6 5 4 3
12
D
R1850
0.00
1 2
0%
1/32W
MF
01005
DMIC1_FF_SD
15
GPIO_SOC2AJ_HS4_SHUNT_EN
5
GPIO_SOC2AJ_HS3_SHUNT_EN
5
LAT_SW2_CTL
28 52
PP_LDO14_2V65
25 32 33 39 40
LAT_SW1_CTL
24 28 52
=PP1V8_DMIC
54
L1800
0201-2
240-OHM-0.2A-0.8-OHM
DMIC1_FF_SCLK
15
C1800
27PF
5%
16V
NP0-C0G
01005
PP1V8_DMIC_FILT
21
1
2
C
DMIC1_FF_SCLK_FILT
NOSTUFF
1
C1850
27PF
5%
16V
2
NP0-C0G
01005
VOLTAGE=2.65V
1
C1820
56PF
5%
16V
2
NP0-C0G
01005 01005
1
C1830
56PF
16V
2
NP0-C0G
01005
1
C1821
56PF
5%
16V
2
NP0-C0G
01005
1
C1822
56PF
5%5%
16V
2
NP0-C0G
MIN_NECK_WIDTH=0.06 MM
1
C1801
0.1UF
10%
6.3V
2
CERM-X5R
0201
P/N 510S0760 - MLB
(P/N 510S0761 - FLEX)
CRITICAL
J1800
AA07A-S016VA1
F-ST-SM-COMBO
2
4
6
8
10
12
14
16
1
C1802
27PF
5%
16V
2
NP0-C0G
01005
18
17
1
3
5
7
9
11
13
15
19
20
CONN_HP_HS4_FILT
CONN_HP_HS4_REF_FILT
CONN_HP_HS3_REF_FILT
CONN_HP_HS3_FILT
CONN_HP_RIGHT_FILT
CONN_HP_LEFT_FILT
CONN_HP_HEADSET_DET_FILT
15
15
15
15
15
15
15
AUDIO_JACK_FLEX RET2
AUDIO_JACK_FLEX MIC1
AUDIO_JACK_FLEX MIC2
AUDIO_JACK_FLEX RET1
PER DAVE BREECE
D
C
B
B
w w w . c h i n a f i x . c o m
A
SYNC_MASTER=N/A
PAGE TITLE
AUDIO: HP FLEX CONN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=03/31/2011
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
14 OF 54
PAGE
18 OF 121
SHEET
124578
SIZE
A
D
8 7 6 5 4 3
=PPVCC_MAIN_AUDIO
16 54
=PP1V8_AUDIO
15 54
R1950
D
=PP1V7_VA_VCP
16 54
CRITICAL
1
C1901
4.7UF
20%
6.3V
2
X5R
GND_AUDIO_CODEC
15 52
R1901
2.21K
1 2
MF
1%
1/20W
C
C1911
1.0UF
6.3V
0201-1
1
20%
2
X5R
L81_MIC2_BIAS_FILT_IN
XW1902
SHORT-8L-0.25MM-SM
CODEC_HP_HS4
15 52
CODEC_HP_HS3
15 52
2 1
NOSTUFF
XW1903
SHORT-8L-0.25MM-SM
2 1
NOSTUFF
402
L81_MIC2_BIAS_IN
201
L81_MIC2_BIAS
C1912
4.7UF
1 2
20%
6.3V
X5R
402
HP_MIC_POS
HP_MIC_NEG
CRITICAL
1
C1903
0.1UF
10%
10V
2
X5R-CERM
0201
L81_MIC2_BIAS_FILT
C1916
0.1UF
1 2
10%
6.3V
0201 CERM-X5R
C1917
0.1UF
1 2
10%
6.3V
0201 CERM-X5R
15
15
15
15
15
15
15
15
15
1.00
1 2
MF-LF
1%
1/20W
GND_AUDIO_CODEC
15 52
C1905
4.7UF
12
6.3V
20%
402
X5R
C1906
4.7UF
12
20%
6.3V
402 X5R
NC_MIC1_BIAS
AIN1P
AIN1N
MIC1_BIAS_FILT
NC_MIC3_BIAS
AIN3P
AIN3N
MIC3_BIAS_FILT
NC_MIC4_BIAS
AIN4P
AIN4N
MIC4_BIAS_FILT
0201
L81_FLYP
0.3MM
0.15MM
L81_FLYC
0.3MM
0.15MM
L81_FLYN
0.3MM
0.15MM
L81_AIN2_POS
L81_AIN2_NEG
PP1V7_VCP
CRITICAL
1
C1950
4.7UF
20%
6.3V
2
X5R
402
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
1
2
VOLTAGE=1.7V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
NC_SPEAKER_VQ
C1902
0.1UF
20%
6.3V
X5R-CERM
01005
CRITICAL
1
C1951
1.0UF
20%
6.3V
2
X5R
0201-1
H10
FLYP
J10
FLYC
K10
FLYN
H2
MIC1_BIAS
E3
AIN1+
E4
AIN1-
H3
MIC1_BIAS_FILT
J3
MIC2_BIAS_IN
G4
MIC2_BIAS
K3
MIC2_BIAS_FILT_IN
F3
MIC2_BIAS_FILT
C1
AIN2+
D1
AIN2M
H4
MIC3_BIAS
C3
AIN3+
C2
AIN3-
G3
MIC3_BIAS_FILT
F4
MIC4_BIAS
D2
AIN4+
E2
AIN4-
F2
MIC4_BIAS_FILT
C10
SPEAKER_VQ
1
C1915
0.1UF
20%
6.3V
2
X5R-CERM
01005
G1
G9
A9E8A8
G8
VA
VCP0
VCP1
VD
CRITICAL
CS42L81-CWZR-A1
WLCSP
SYM 1 OF 2
GNDP
B
E10
VP0VLVP1
U1900
GNDA
GNDD
GNDHS
GNDHS
G2
K2
J2
A10
SHORT-8L-0.25MM-SM
0.1UF
10%
10V
X5R-CERM
0201
E9
LINEOUT_REF
NOSTUFF
XW1900
G10
VPROG_CP
+VCP_FILT
-VCP_FILT
HPDETECT
LINEOUTA
LINEOUTB
21
CRITICAL
1
1
C1909C1904
4.7UF
20%
10V
2
2
X5R-CERM
0402
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PPVCC_VPROG_CP
1
C1914
0.1UF
10%
10V
2
X5R-CERM
0201
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PPVCC_VPROG_MB_F
1
2
H1
VPROG_MB
H9
J9
GNDCP
K9
F10
AOUT1+
AOUT1_M
AOUT2+
AOUT2-
HPOUTA
HPOUTB
HS3_REF
HS4_REF
FILT+
FILT-
HS3
HS4
NO_TEST=TRUE
F9
NO_TEST=TRUE
D10
NO_TEST=TRUE
D9
NO_TEST=TRUE
J4
DP
K4
DN
J8
K8
J1
K1
K7
J7
H8
K6
NO_TEST=TRUE
J6
NO_TEST=TRUE
H6
L81_FILT
E1
F1
R1951
1.00
1 2
1/20W
0201
MF-LF
R1952
255K
1 2
1/20W
C1913
0.1UF
10%
10V
X5R-CERM
0201
L81_PVCP
L81_NVCP
NC_LEFT_CH_OUT_P
NC_LEFT_CH_OUT_N
NC_RIGHT_CH_OUT_P
NC_RIGHT_CH_OUT_N
L81_MBUS_P
L81_MBUS_N
CODEC_HP_LEFT
52
CODEC_HP_RIGHT
52
CODEC_HP_HS3
15 52
CODEC_HP_HS4
15 52
CODEC_HP_DET
NC_CODEC_LINE_OUT_L
NC_CODEC_LINE_OUT_R
CRITICAL
1
C1910
10UF
20%
6.3V
2
CERM-X5R
0402
VOLTAGE=0V
GND_AUDIO_CODEC
NOTE:
U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846
1%
1
R1953
0
5%
1/20W
MF
201
2
1%
201
MF
PPVCC_VPROG_MB
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
CRITICAL
C1907
4.7UF
1 2
0.30MM
0.15MM
0.15MM
MIN_LINE_WIDTH=0.20MM
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
0.15MM
0.20MM
15 52
0.30MM
15
15
20%
X5R
CRITICAL
C1908
4.7UF
1 2
15
6.3V
402
GND_AUDIO_CODEC
6.3V
20%
X5R
402
MIN_NECK_WIDTH=0.15MM
15 52
CODEC_HP_DET
15
CODEC_HP_HS3_REF
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
CODEC_HP_HS4_REF
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
MIKEY BUS FILTER
SIGNAL_MODEL=EMPTY
1
C1930
100PF
5%
PLACE R1930 & R1931 CLOSE TO U3600
R1930
12
1 2
5%
0201
0201
1/20W
MF
201
R1931
12
1 2
5%
1/20W
MF
201
L1920
21
0201-2
21
CONN_HP_LEFT_FILT
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
21
CONN_HP_RIGHT_FILT
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
21
CONN_HP_HS3_FILT
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
21
CONN_HP_HS4_FILT
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
21
CONN_HP_HS3_REF_FILT
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
21
CONN_HP_HS4_REF_FILT
MIN_LINE_WIDTH=0.15MM
MIN_NECK_WIDTH=0.1MM
L81_MBUS_P MIKEY_TS_P
15
L81_MBUS_N
15
R1920
3.3K
1 2
1/32W
01005
52
52
5%
MF
CODEC_HP_DET_R
52
NOSTUFF
1
C1920
4700PF
10%
10V
2
X7R
201
240-OHM-0.2A-0.8-OHM
PLACE L1900 TO 1905 CLOSE
TO THE HP CONNECTOR
FERR-33-OHM-0.8A-0.09-OHM
FERR-33-OHM-0.8A-0.09-OHM
FERR-33-OHM-0.8A-0.09-OHM
FERR-33-OHM-0.8A-0.09-OHM
L1900
L1901
L1902
0201
L1903
0201
L1904
120-OHM-210MA
01005
L1905
120-OHM-210MA
01005
25V
2
NP0-CERM
0201
NOSTUFF
1
C1931
100PF
5%
25V
2
NP0-CERM
0201
SIGNAL_MODEL=EMPTY
1
C1932
100PF
5%
25V
2
NP0-CERM
0201
CONN_HP_HEADSET_DET_FILT
IN
OUT
OUT
IN
IN
IN
IN
MIKEY_TS_N
14
14
14
14
14
14
14
12
11 52
BI
11 52
BI
TO HEADPHONE JACK
D
C
B
MIC1_BIAS_FILT
CODEC_MIC_BIAS_FILT
MAKE_BASE=TRUE
1
C1990
100PF
5%
16V
2
NP0-C0G
01005
MIC3_BIAS_FILT
MIC4_BIAS_FILT
AIN1P
CODEC_AIN
MAKE_BASE=TRUE
1
C1991
100PF
5%
16V
2
NP0-C0G
A
01005
AIN1N
AIN3P
AIN3N
AIN4P
AIN4N
15
15
15
5
53
15
15
15
15
15
15
=PP1V8_AUDIO
15 54
48
IN
w w w . c h i n a f i x . c o m
NOSTUFF
1
R1940
1.00K
5%
1/32W
MF
01005
2
IN
5
IN
5
IN
5
IN
5
IN
5
IN
53
5
IN
5
53
IN
5
IN
11
IN
5
OUT
5
53
OUT
5
53
IN
5
53
OUT
5
52
OUT
48 52
OUT
DIGITAL MIC
DMIC1_FF_SD
14
IN
DMIC1_FF_SCLK
14
IN
I2S0_CODEC_ASP_MCK
I2S0_CODEC_ASP_BCLK
I2S0_CODEC_ASP_LRCK
I2S0_CODEC_ASP_DOUT
I2S0_CODEC_ASP_DIN
I2S2_CODEC_XSP_BCLK
I2S2_CODEC_XSP_LRCK
I2S2_CODEC_XSP_DOUT
I2S2_CODEC_XSP_DIN
L81_MBUS_REF
SPI2_CODEC_CS_L
SPI2_CODEC_SCLK
SPI2_CODEC_MOSI
SPI2_CODEC_MISO
GPIO_CODEC_IRQ_L
PMU_GPIO_CODEC_HS_INT_L
PMU_GPIO_CODEC_RST_L
R1910
1/32W
R1911
1/32W
R1912
1/32W
R1913
1/32W
5%
1 2
5%
1 2
5%
1 2
1 2
22
01005
MF
22
MF
01005
NC_DMIC2_SCLK
I2S0_CODEC_ASP_SDOUT
22
01005
MF5%
I2S2_CODEC_XSP_SDOUT
22
MF
01005
L81_DMIC1_FF_SD
L81_DMIC1_FF_SCLK
NO_TEST=TRUE
B1
DMIC1_SD
B2
DMIC1_SCLK
B7
DMIC2_SD
B6
DMIC2_SCLK
C8
MCLK
A3
ASP_SCLK
B3
ASP_LRCK
A2
ASP_SDIN
A1
ASP_SDOUT
B4
XSP_SCLK
B5
XSP_LRCK_FSYNC
A5
XSP_SDIN_DAC2_MUTE
A4
XSP_SDOUT
K5
MBUS_REF
C5
CS*
A6
CCLK
B8
CDIN
A7
CDOUT
B9
INT*
B10
WAKE*
C9
RESET*
U1900
CS42L81-CWZR-A1
WLCSP
SYM 2 OF 2
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
TSTI0
TSTI1
TSTI2
C6
D3
D5
D6
D7
D8
E5
E6
E7
F5
F6
F7
F8
G5
G6
G7
H5
H7
J5
C4
C7
D4
PART NUMBER
155S0773 155S0453
338S1213 338S1116
ALTERNATE FOR
PART NUMBER
BOM OPTION
SYNC_MASTER=KAVITHA
PAGE TITLE
REF DES
L1904,L1905
U1900
COMMENTS:
RADAR:11100717
RADAR:13373870 SSMC FAB
AUDIO: L81 CODEC
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
SYNC_DATE=01/18/2012
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
15 OF 54
PAGE
19 OF 121
SHEET
124578
SIZE
A
D
8 7 6 5 4 3
12
RIGHT SPEAKER AMP
=PPVCC_MAIN_AUDIO
15 16 54 15 16 54
CRITICAL
1
2
D
47 52 54
1
C2041
4.7UF
20%
10V
2
X5R-CERM
0402
PP1V7_VA_VCP
CRITICAL
C2042
4.7UF
20%
10V
X5R-CERM
0402
CRITICAL
C2043
4.7UF
20%
10V
X5R-CERM
0402
1
2
C2044
0.1UF
10%
10V
X5R-CERM
0201
1
2
2.2UH-20%-3.3A-0.115OHM
TFA302610A-SM
I2C2_SDA_1V8
5
16 52
I2C2_SCL_1V8
5
16 52
GPIO_SPKAMP_RIGHT_IRQ_L
5
GPIO_SPKAMP_RST_L
5
16
GPIO_SPKAMP_KEEPALIVE
5
16 52
I2S1_SPKAMP_MCK
5
16 53
I2S1_SPKAMP_BCLK
5
16 53
I2S1_SPKAMP_LRCK
5
16 53
I2S1_SPKAMP_DOUT
5
16 53
I2S1_SPKAMP_DIN
5
16 53
CRITICAL
L2040
1
2
0.1UF
10%
10V
X5R-CERM
0201
L19_R_VBOOST
CRITICAL
1
C2045
10UF
20%
10V
2
X5R
603
21
L19_R_SWITCH
CRITICAL
1
2
C
LEFT SPEAKER AMP
=PPVCC_MAIN_AUDIO
15 16 54
CRITICAL
1
2
B
C2051
4.7UF
20%
10V
X5R-CERM
0402
CRITICAL
1
C2052
4.7UF
20%
10V
2
X5R-CERM
0402
CRITICAL
1
C2053
1
C2054
4.7UF
0.1UF
20%
10%
10V
X5R-CERM
0402
2
10V
X5R-CERM
0201
2
2.2UH-20%-3.3A-0.115OHM
I2C2_SDA_1V8
5
16 52
I2C2_SCL_1V8
5
16 52
GPIO_SPKAMP_LEFT_IRQ_L
5
GPIO_SPKAMP_RST_L
5
16
GPIO_SPKAMP_KEEPALIVE
5
16 52
I2S1_SPKAMP_MCK
5
16 53
I2S1_SPKAMP_BCLK
5
16 53
I2S1_SPKAMP_LRCK
5
16 53
I2S1_SPKAMP_DOUT
5
16 53
I2S1_SPKAMP_DIN
5
16 53
TFA302610A-SM
1
C2093
0.1UF
10%
10V
2
X5R-CERM
0201
L2050
L19_L_VBOOST
CRITICAL
1
C2055
10UF
20%
10V
2
X5R
603
21
L19_L_SWITCH
CRITICAL
1
C2090
10UF
20%
10V
2
X5R-CERM
0402-1
I2C ADDRESS: 1000001X
NET_SPACING_TYPE=PWR
CRITICAL
1
C2094C2092
C2091
10UF
10UF
20%
20%
10V
10V
2
X5R-CERM
X5R-CERM
0402-1
0402-1
A2
B2
D5
A7
A6
D7
C7
E7
E6
F6
F7
E5
A1
SW
SDA
SCL
INT*
RESET*
ALIVE
ADO
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
B3
A3
B1
D1D6A4
C1
VBST
U2040
CS35L19B-CWZR/C0
WLCSP
GNDP
B4
C4
C3
D3
I2C ADDRESS: 1000000X
NET_SPACING_TYPE=PWR
CRITICAL
1
C2095
10UF
20%
10V
2
X5R-CERM
0402-1
A2
B2
D5
A7
A6
D7
C7
E7
E6
F6
F7
E5
A1
SW
SDA
SCL
INT*
RESET*
ALIVE
ADO
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
A3
B3
B1
D1D6A4
C1
VBST
U2050
CS35L19B-CWZR/C0
WLCSP
GNDP
B4
D3
C4
C3
VER1
D4
VER1
D4
=PP1V7_VA_VCP
1
C2046
0.1UF
10%
6.3V
2
F5
A5
VA
VP
F2
FILT+
C5
LDO_FILT
E3
VSENSE-
E2
VSENSE+
F1
ISENSE-
E1
ISENSE+
D2
OUT+
C2
OUT-
B7
IREF+
GNDA
B5
B6
F4
F3
C6
E4
CERM-X5R
0201
L19_R_FILT
L19_R_LDO_FILT
SPKR_R_SES_N
SPKR_R_SES_P
SPKR_R_P
L19_R_IREF
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
1
R2041
44.2K
1%
1/20W
MF
201
2
=PP1V7_VA_VCP
1
C2056
0.1UF
10%
6.3V
2
F5
A5
VA
VP
F2
FILT+
C5
LDO_FILT
E3
VSENSE-
E2
VSENSE+
F1
ISENSE-
E1
ISENSE+
D2
OUT+
C2
OUT-
B7
IREF+
GNDA
w w w . c h i n a f i x . c o m
B5
B6
F4
F3
C6
E4
CERM-X5R
0201
L19_L_FILT
L19_L_LDO_FILT
SPKR_L_SES_N
SPKR_L_SES_P
SPKR_L_P
L19_L_IREF
MIN_LINE_WIDTH=0.5 MM
1
MIN_NECK_WIDTH=0.2 MM
R2051
44.2K
1%
1/20W
MF
201
2
CRITICAL
C2047
4.7UF
1 2
20%
6.3V
CRITICAL
C2048
4.7UF
1 2
20%
6.3V
SM
XW2040
R2040
SIGNAL_MODEL=EMPTY
SPKR_R_CONN_N
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
CRITICAL
C2057
4.7UF
1 2
20%
6.3V
CRITICAL
C2058
4.7UF
1 2
20%
6.3V
SM
XW2050
R2050
SIGNAL_MODEL=EMPTY
1 2
X5R-CERM1
402
X5R-CERM1
402
CRITICAL
0.100
1 2
1%
1/4W
MF
0402
15 16 54
X5R-CERM1
402
X5R-CERM1
402
CRITICAL
0.100
1%
1/4W
MF
0402
SM
XW2041
SIGNAL_MODEL=EMPTY
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SM
XW2051
SIGNAL_MODEL=EMPTY
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM
SPKR_R_VSENSE_N
16
SPKR_R_VSENSE_P
16
SPKR_R_CONN_P
SPKR_L_VSENSE_N
16
SPKR_L_VSENSE_P
16
SPKR_L_CONN_P
SPKR_R_CONN_P
SPKR_R_VSENSE_P
16
SPKR_R_CONN_N
SPKR_R_VSENSE_N
16
SPKR_L_CONN_P
SPKR_L_VSENSE_P
16
SPKR_L_CONN_N
SPKR_L_VSENSE_N
16
SPEAKER CONNECTOR
XW2074
SM
SIGNAL_MODEL=EMPTY
1 2
XW2075
SM
SIGNAL_MODEL=EMPTY
1 2
XW2076
SM
SIGNAL_MODEL=EMPTY
1 2
XW2077
SM
SIGNAL_MODEL=EMPTY
1 2
PLACE XWS CLOSE TO CONNECTOR
UPDATED: DEC 13
1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN
REMOVED BASED ON PERFORMANCE ON J65
2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0
BY MARCH 2013. C0 FIXES PROCESS ISSUES.
16 43 52 16 43
52
16 43
16 43 52
52
16 43 52 16 43
52
16 43 52 16 43
52
D
C
B
A
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SPKR_L_CONN_N
6 3
SYNC_MASTER=KAVITHA
PAGE TITLE
AUDIO: CS35L19A AMPS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=01/18/2012
DRAWING NUMBER
051-0886
REVISION
A.0.0
BRANCH
PAGE
20 OF 121
SHEET
4 OF 4
16 OF 54
124578
SIZE
A
D
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