Apple iPad 4 Schematic
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6 5 4 3
2 1
REV ECN
A
0001554595
DESCRIPTION OF REVISION
PRODUCTION RELEASED
CK
APPD
DATE
2012-07-26
iPad 4th Gen
LAST_MODIFIED=Thu Jul 26 10:29:36 2012
SIZE
D
C
B
A
D
D
C
B
TABLE_TABLEOFCONTENTS_HEAD
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CSAPDF
CONTENTS
Table of Contents
1
BLOCK DIAGRAM: SYSTEM
2
BOM TABLES
4
AP: MAIN
6
AP: I/Os
7
AP: NAND
8
AP: TV,DP,MIPI
9
10
AP: DDR
AP: POWER
11
12
AP: MISC & ALIASES
13
DDR 0 AND 1
DDR 2 AND 3
14
NAND
16
ALIASES
21
VIDEO: EDP CONNECTOR
22
GRAPE: GROUNDHOG,CONN,BOOST
30
GRAPE: Z1, Z2
31
AUDIO: L81 CODEC
36
AUDIO: SPEAKER AMP
37
SENSOR FLEX CONN
54
SENSOR CONN FILTERS 1
55
SENSOR CONN FILTERS 2
56
E75 DOCK SUPPORT
57
IO FLEX CONN
58
TRISTAR
59
CONNECTOR: CELLULAR
60
61
WIFI/BT
75
POWER: BATTERY CONNECTOR
PMU: ADRIANA PAGE 1
81
82
PMU: ADRIANA PAGE 2
SYNC MASTER
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MADHAVI
MADHAVI
MADHAVI
DATE
N/A
N/A
N/AN/A
N/A
N/A
N/A
N/AN/A
N/A
N/A
N/AN/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12/06/2011
12/06/2011
12/06/2011
A
DRAWING
MLB
DRAWING
(SYSTEM DRI)
(AMANDA)
(AMANDA)
(AMANDA)
(TERRY)
(AMANDA)
(TERRY)
(TERRY)
(TERRY)
(TERRY)
(TERRY)
(TERRY)
(TERRY)
(AMANDA)
(AMANDA)
(JOE)
(AMANDA)
(AMANDA)
(TERRY)
(TERRY)
(MARK)
(MARK)
(MARK)
(JOE)
(JOE)
(JOE)
(AMANDA)
(MATT)
(MADHAVI)
(MADHAVI)
(MADHAVI)
PDF
TABLE_TABLEOFCONTENTS_HEAD
31
TABLE_TABLEOFCONTENTS_ITEM
32
TABLE_TABLEOFCONTENTS_ITEM
33
TABLE_TABLEOFCONTENTS_ITEM
34
TABLE_TABLEOFCONTENTS_ITEM
35
TABLE_TABLEOFCONTENTS_ITEM
36
TABLE_TABLEOFCONTENTS_ITEM
37
TABLE_TABLEOFCONTENTS_ITEM
38
TABLE_TABLEOFCONTENTS_ITEM
39
TABLE_TABLEOFCONTENTS_ITEM
CSA
83
90
93
121
150
151
152
153
154
CONTENTS
PMU: ADRIANA PAGE 3
DEBUG/MISC.
TEST/HOLES/FIDUCUALS
POWER ALIASES
CONSTRAINTS: MLB RULES
CONSTRAINTS: LOW SPEED BUS
CONSTRAINTS: DISPLAY/AUDIO
CONSTRAINTS: DDR/FMI
CONSTRAINTS: POWER / GND
3
SYNC MASTER
MADHAVI 12/06/2011
MLB
N/A N/A
N/A N/A
MIKE
MIKE
MIKE
MIKE
MIKE
DATE
11/09/2011
11/30/2011
11/30/2011
11/30/2011
11/30/2011
11/30/2011
DRAWING TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
(SYSTEM DRI)
(MADHAVI)
(AMANDA)
(AMANDA)
(MADHAVI)
(AMANDA)
(AMANDA)
(AMANDA)
(AMANDA)
(AMANDA)
X140 MLB
Apple Inc.
R
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
1 OF 154
SHEET
1 OF 39
1245678
8 7 6 5 4 3
12
ISP_I2C1
Z2
CSA 31
SPI3
MIPI1C
ISP_I2C0
MIPI0C
D
GROUNDHOG
Z1
HSIC1_1
UART3
FF CAMERA
VGA FLEX
REAR CAMERA
VA5 FLEX
D
WIFI/BT ANT
WIFI/BT
CSA 30
CSA 31
LPDDR2
CSA 13-14
DISPLAY/
TOUCH PANEL
C
BACKLIGHT
EDP
BALI
UART4
I2S2
HSIC3
UART1
BT_I2S
CSA 61
CELLULAR/
HSIC1
IPC
USART
USART
CSA 60
GPS
NOT ON
WIFI-ONLY CONFIG
PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT
GPS ANT
SIM CARD
C
UART5
HALL EFF 1
BUTTON FLEX
HALL EFF 2
HOME BUTTON
B
PMU
ADRIANA
CSA 81,82
BATTERY
CSA 75
DWI
I2C0
I2C1
USB11
USB2.0
UART2
UART6
I2S1
AUDIO CODEC
TRISTAR
CSA 59
B
L81
PROX SENSOR
SENSOR BOARD
COMPASS
SENSOR BOARD
SPI1
I2S0
SPI
ASP
MBUS
AMP
I2S3
I2C2
GYRO
A
SENSOR BOARD
ACCELEROMETER
SENSOR BOARD
ALS
VGA FLEX
FMI0 FMI1
I2S4
NC
NAND FLASH
CSA 16
XSP
CSA 36
AMP
HP
SYNC_MASTER=N/A
PAGE TITLE
MIC2MIC1
BLOCK DIAGRAM: SYSTEM
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
SPEAKER
DRAWING NUMBER
051-9385
REVISION
BRANCH
PAGE
2 OF 154
SHEET
2 OF 39
124578
SYNC_DATE=N/A
A.0.0
SIZE
A
D
8 7 6 5 4 3
12
SCH AND BOARD P/N
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
D
BOM OPTIONS
COMMON
ALTERNATE
16GB_PROD: 16GB CONFIG
32GB_PROD: 32GB CONFIG
64GB_PROD: 64 GB CONFIG
DEV: DEV BOARD ONLY
MLB: MLB BOARD ONLY
MLB_A: WIFI ONLY CONFIG
MLB_B: CELLULAR CONFIG
MLB_C: CELLULAR CONFIG
MLB_D: LEGACY CELLULAR CONFIG
MLB_E: LEGACY CELLULAR CONFIG
PART#
SOC
PART#
343S0598 CRITICAL
PMU
PART#
343S0622
DESCRIPTION
QTY
1
SCH,MLB,X140
1
PCBF,MLB,X140
DESCRIPTION
QTY
IC,SOC,H5G,FCBGA1089,0.5MM
1
DESCRIPTION
QTY
1
IC,PMU,ADRIANA,D2018A1,FCBGA
REFERENCE DESIGNATOR(S)
SCH1051-9385
PCB1
REFERENCE DESIGNATOR(S)
U0600
REFERENCE DESIGNATOR(S)
U8100
CRITICAL BOM OPTION
CRITICAL
CRITICAL820-3249
CRITICAL BOM OPTION
CRITICAL BOM OPTION
CRITICAL
SDRAM
PART#
333S0636
BOM GROUP
BASIC
BOM OPTIONS
COMMON,ALTERNATE
C
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
PART NUMBER
333S0637
333S0638 333S0636
DESCRIPTION
QTY
2
LPDDR2,533MHZ,512MB,SAMSUNG,35NM
ALTERNATE FOR
PART NUMBER
333S0636
BOM OPTION
REFERENCE DESIGNATOR(S)
U1300,U1400
REF DES
COMMENTS:
U1300,U1400
U1400,U1400
LPDDR2,533MHZ,HYNIX,38NM
LPDDR2,533MHZ,ELPIDA,38NM
CRITICAL BOM OPTION
CRITICAL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
D
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
C
NAND
16GB FLASH CONFIGURATIONS
PART#
335S0878
DESCRIPTION
QTY
TOSHIBA PPN1.5 16GB
1
REFERENCE DESIGNATOR(S)
U1600
CRITICAL BOM OPTION
CRITICAL
16GB_PROD
32GB FLASH CONFIGURATIONS
MECHANICAL PARTS
PART#
B
NAND
SOC/PMU
806-4195
806-3493
AUDIO
GRAPE
MEMORY
806-4196 CRITICAL
806-3492
DESCRIPTION
QTY
FENCE,NAND,TOP,MLB,X140
1
FENCE,LARGE,TOP,MLB,X140
1
FENCE,AMP,MLB,X140
1
FENCE,1,BTM,MLB,X140
1
FENCE,2,BTM,MLB,X140
1
REFERENCE DESIGNATOR(S)
PD_FENCE_NAND
PD_FENCE_LARGE
PD_FENCE_AMP
PD_FENCE_BTM1
PD_FENCE_BTM2
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL806-3956
CRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART#
335S0879
DESCRIPTION
QTY
TOSHIBA PPN1.5 32GB
1
REFERENCE DESIGNATOR(S)
U1600
CRITICAL BOM OPTION
CRITICAL
32GB_PROD
64GB FLASH CONFIGURATIONS
BARCODE LABEL/EEEE CODES
PART#
825-7838
825-7838
825-7838
825-7838
825-7838
825-7838
825-7838
A
825-7838
825-7838
825-7838
825-7838
DESCRIPTION
QTY
EEEE FOR 639-3736 (MLB A 16G)
1
EEEE FOR 639-3737 (MLB A 32G)
1
1
EEEE FOR 639-3738 (MLB A 64G)
1
EEEE FOR 639-4176 (MLB A 128G)
1
EEEE FOR 639-3263 (MLB B 16G)
1
EEEE FOR 639-3739 (MLB B 32G)
EEEE FOR 639-3740 (MLB B 64G)
1
1
EEEE FOR 639-4177 (MLB B 128G) EEEE_MLB_B_128G
1
EEEE FOR 639-3741 (MLB C 16G)
1
EEEE FOR 639-3742 (MLB C 32G)
1
EEEE FOR 639-3743 (MLB C 64G)
1
EEEE FOR 639-4178 (MLB C 128G) EEEE_MLB_C_128G
REFERENCE DESIGNATOR(S)
EEEE_F1WD
EEEE_F1WH
EEEE_F1W8
EEEE_F80Q
EEEE_DWKG
EEEE_F1W7
EEEE_F1WC
EEEE_F80P
EEEE_F1WG
EEEE_F1WF
EEEE_F1W9
EEEE_F80R
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL825-7838
EEEE_MLB_A_16G
EEEE_MLB_A_32G
EEEE_MLB_A_64G
EEEE_MLB_A_128G
EEEE_MLB_B_16G
EEEE_MLB_B_32G
EEEE_MLB_B_64G
EEEE_MLB_C_16G
EEEE_MLB_C_32G
EEEE_MLB_C_64G
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART#
335S0880
128GB FLASH CONFIGURATIONS
PART#
DESCRIPTION
QTY
1
TOSHIBA PPN1.5 64GB
DESCRIPTION
QTY
1
TOSHIBA PPN1.5 128GB
REFERENCE DESIGNATOR(S)
U1600
REFERENCE DESIGNATOR(S)
U1600
CRITICAL BOM OPTION
CRITICAL
CRITICAL BOM OPTION
CRITICAL
64GB_PROD
128GB_PROD335S0912
6 3
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
B
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
SIZE
A
D
SYNC_MASTER=N/A
PAGE TITLE
BOM TABLES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
4 OF 154
SHEET
3 OF 39
124578
8 7 6 5 4 3
12
C0605
0.1UF
20%
4V
X5R
01005
PP0600
SM
1
C0640
1000PF
10%
16V
2
X7R-CERM
0201
P4MM
R0604
1 2
1
C0633
0.1UF
20%
6.3V
2
X5R-CERM
01005
PP
0.00
0%
1/32W
MF
01005
1
14 36
14 36
26 36
26 36
10 36 39
10
10
10
10
BCM4330
WLAN
BI
BI
MDM9615
BB
BI
BI
10
IN
36
36
25 36
25 36
IN
OUT
OUT
IN
R0642
100K
1/32W
01005
R0643
221K
1/32W
01005
1
C0606
0.1UF
20%
4V
2
X5R
01005
1
C0630
0.01UF
10%
6.3V
2
X5R
01005
1
C0634
0.1UF
20%
6.3V
2
X5R-CERM
01005
HSIC1_WLAN_DATA
HSIC1_WLAN_STB
NC_HSIC2_DATA
NC_HSIC2_STB
HSIC3_BB_DATA
HSIC3_BB_STB
JTAG_AP_SEL
JTAG_AP_TRST_L
TP_JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TMS
JTAG_AP_TCK
NC_JTAG_AP_TRTCK
AP_TESTMODE
AP_TST_STPCLK
TP_AP_TST_CLKOUT
AP_FAST_SCAN_CLK
AP_HOLD_RESET
1
1%
MF
2
AP_DDR1_CKEIN_1V2
1
1%
MF
2
1
C0607
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C0631
0.01UF
10%
6.3V
2
X5R
01005
1
C0635
0.01UF
10%
6.3V
2
X5R
01005
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
1
C0637
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C0636
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
R33
HSIC1_DATA
T33
HSIC1_STB
R31
HSIC2_DATA
T31
HSIC2_STB
AN17
HSIC3_DATA
AM17
HSIC3_STB
H17
JTAG_SEL
J16
JTAG_TRTCK
K16
JTAG_TRST*
H16
JTAG_TDO
F16
JTAG_TDI
F17
JTAG_TMS
J17
JTAG_TCK
D18
TESTMODE
L31
FUSE1_FSRC
A19
TST_STPCLK
C19
TST_CLKOUT
N27
FAST_SCAN_CLK
G16
HOLD_RESET
G17
RESET*
A18
CFSB
L6
DDR0_CKEIN
F9
DDR1_CKEIN
AG10
DDR2_CKEIN
AD5
DDR3_CKEIN
39
PP1V8_PL0_F
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
R26
AF19
HSIC_VDD122
HSIC_VDD123
2.7MA
PER PIN
T28
R28
R27
HSIC_VDD121
11.9MA
PER PIN
AF18
U18
VDD_ANA_PLL
8MA
HSIC2_DVDD102
HSIC3_DVDD103
U0600
BALI-H5G
BGA
SYM 1 OF 12
OMIT_TABLE
USB 1.1 BASEBAND/TRISTAR
NEEDED IF WE GO TO 9600
CPU_VDD CONTROL
HSIC_VSS121
HSIC_VSS122
HSIC_VSS123
HSIC2_DVSS
HSIC3_DVSS
T29
T25
AG18
AG19
TRISTAR
NEW TO BALI
USB_BRICKID_DM_MON
USB_VSSA0
P32
R29
R30
P26
USB_DVDD
USB_VDD330
5.4MA
30MA
USB11_DP
USB11_DM
USB_DP
USB_DM
USB_ANALOGTEST
USB_VBUS
USB_ID
USB_BRICKID
USB_REXT
CPU0_SWITCH
CPU1_SWITCH
USB_ASW_VSS18
N26
USB_ASW_VDD18
<1MA
C18
WDOG
J33
XI0
K33
XO0
E32
D32
M33
N33
R25
P28
P27
P31
T30
N32
N24
P29
1
C0621
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C0623
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
AP_WDOG
36
XTAL_AP_24M_I
XTAL_AP_24M_O
36
USB11_AP_BBMUX_P
USB11_AP_BBMUX_N
USB_AP_P
USB_AP_N
NC_USB_ANALOGTEST
NO_TEST=TRUE
USB_AP_VBUS0
NC_USB_ID
NO_TEST=TRUE
NC_USB_BRICKID
NO_TEST=TRUE
USB_REXT0
CPU0_SWITCH
CPU1_SWITCH
NC_USB_BRICKID_DM_MON
NO_TEST=TRUE
1
C0608
0.01UF
10%
6.3V
2
X5R
01005
1
C0612
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C0613
0.1UF
20%
4V
2
X5R
01005
MLB
R0652
0.00
1 2
0%
1/32W
MF
01005
25 36
BI
25 36
BI
25 36
BI
25 36
BI
30
OUT
30
OUT
1
C0609
0.01UF
10%
6.3V
2
X5R
01005
1
C0614
1UF
10%
6.3V
2
CERM
402
=PP1V8_VDDIO18_H5
MLB OPTION USED FOR FF
AP_WDOG_RESET_IN
1
R0650
1.00M
1%
1/32W
MF
01005
2
1
R0613
43.2
1%
1/20W
MF
201
2
1 2
=PP1V0_USB_H5
=PP3V3_USB_H5
OUT
R0651
22
36
5%
1/32W
MF
01005
SYNC_MASTER=N/A
PAGE TITLE
34
34
CHANGE TO USB 3.3V TO AVOID
ISSUE FOUND IN H5P:
FAILURE IN CHARGE DETECT CIRCUIT AT 3.0V-5%
6 7 9
34
25
CRITICAL
Y0602
24.000MHZ-16PF-60PPM
AP_24M_O
CRITICAL
1
C0650
22PF
5%
16V
2
CERM
01005
SM-2
1 3
PPVBUS_USB
1
R0610
68.1K
1%
1/20W
MF
201
2
2 4
29
AP: MAIN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
CRITICAL
1
C0651
22PF
5%
16V
2
CERM
01005
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
6 OF 154
SHEET
4 OF 39
124578
SIZE
D
C
B
A
D
A1
A2
C33
F1
A11
A14
A17
A32
A33
B12
B15
B32
B33
C10
C13
C16
D11
D14
D17
U19
E10
E22
E24
E25
F22
F24
F25
F30
A31
G18
G21
G22
G26
V18
H10
H11
H12
H13
H14
H21
H22
H28
H33
J11
J13
J15
J21
T18
K10
K12
K14
K22
K26
K30
L11
L13
L15
L17
L19
L21
L33
M10
M12
M14
M16
M18
M20
M22
B1
B2
B4
B9
C7
A3
D3
D5
D8
F2
F5
G3
H4
H9
J2
J9
K3
K8
L1
L4
L9
M2
M3
M8
D
C
B
A
U0600
BALI-H5G
BGA
SYM 11 OF 12
OMIT_TABLE
M28
N3
N9
N11
N13
N15
N17
N19
N21
N23
P1
P8
P10
P12
P14
P16
P18
P20
P22
P30
P33
R2
R6
R9
R11
R13
R15
R17
R19
R21
R23
R32
T5
T6
T8
T10
T12
T14
T16
T22
T24
T32
U1
U2
U4
U9
U11
VSSVSS
U13
U15
U17
U21
U23
U33
V8
V10
V12
V14
V16
V19
V21
V23
V30
W3
W9
W11
W13
W15
W17
W20
W22
W24
Y1
Y10
Y12
Y14
Y16
Y18
Y19
Y21
Y23
Y25
Y28
Y32
AA2
AA9
AA11
AA13
AA15
AA17
AA20
AA22
AA24
25 26 30 39
IN
10 34
10 34
10 34
=PP1V8_H5
4 5 7
=PP1V8_H5
4 5 7
=PP1V8_H5
4 5 7
RST_AP_L
=PP1V8_PLL_H5
34
=PP1V0_HSIC_H5
34
=PP1V2_HSIC_H5
34
1
R0640
7.5K
5%
1/32W
MF
01005
2
1
C0632
0.1UF
20%
6.3V
2
X5R-CERM
01005
NOSTUFF
R0608
100K
1 2
5% MF
R0620
100K
1 2
5%
R0621
100K
1 2
5%
1/32W 01005
R0622
100K
1 2
5%
1
2
010051/32W
010051/32W
010051/32W
6 3
D
C
USED FOR DEBUG
AND SW UPDATE
OS CURRENTLY SUPPORTS
USB1.1 FOR DEBUG.
B
I2S0_CODEC_ASP_MCK_R
18 36
OUT
L81 CODEC ASP
1.8V
I2S1_SPKAMP_MCK_R
19
OUT
L19 AMPLIFIERS
1.8V
TO BB
1.8V IO
8 7 6 5 4 3
R0700
33.2
1%
1/32W
MF
BT
1.8V
L81 CODEC XSP
1.8V
NOT USED
26 36
OUT
R0720
1 2
100K
1/20W
201
01005
1 2
R0730
33.2
1%
1/32W
MF
01005
1
5%
MF
2
I2S0_CODEC_ASP_MCK
36
I2S0_CODEC_ASP_BCLK
18 36
OUT
I2S0_CODEC_ASP_LRCK
18 36
OUT
I2S0_CODEC_ASP_DIN
18 36
IN
I2S0_CODEC_ASP_DOUT
18 36
OUT
I2S1_SPKAMP_MCK
I2S1_SPKAMP_BCLK
19
OUT
I2S1_SPKAMP_LRCK
19
OUT
I2S1_SPKAMP_DIN
19
IN
I2S1_SPKAMP_DOUT
19
OUT
NC_I2S2_MCK
I2S2_BT_BCLK
14 36
OUT
I2S2_BT_LRCK
14 36
OUT
I2S2_BT_DIN
14 36
IN
I2S2_BT_DOUT
14 36
OUT
NC_I2S3_MCK
I2S3_CODEC_XSP_BCLK
18 36
OUT
I2S3_CODEC_XSP_LRCK
18 36
OUT
I2S3_CODEC_XSP_DIN
18 36
IN
I2S3_CODEC_XSP_DOUT
18 36
OUT
NC_I2S4_MCK
NC_I2S4_BCLK
NC_I2S4_LRCK
NC_I2S4_DIN
NC_I2S4_DOUT
NC_AP_GPIO216
GPIO_BOARD_ID_2
10
IN
GPIO_BOARD_ID_1
10
IN
GPIO_BOARD_ID_0
10
IN
TP_SPI0_SSIN
SPI1_CODEC_MISO
18 36
IN
SPI1_CODEC_MOSI
18 36
OUT
SPI1_CODEC_SCLK
18 36
OUT
SPI1_CODEC_CS_L
18 36
OUT
BB_JTAG_TRST_RF_L
26
IN
BB_JTAG_TDI_RF
26
OUT
BB_JTAG_TDO_RF
26
IN
GPIO_BB_HSIC_HOST_RDY
SPI3_GRAPE_MISO
16 36
IN
SPI3_GRAPE_MOSI
16 36
OUT
SPI3_GRAPE_SCLK
16 36
OUT
SPI3_GRAPE_CS_L
16 36
OUT
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
M27
M29
N31
M32
M26
H30
L24
L23
M24
N30
J29
L29
L28
L26
L25
L32
E29
K32
J25
M30
F31
H25
K28
K31
J32
K29
Y31
V28
V32
V29
AB29
Y29
AA28
AA32
AB28
AB33
AC29
W33
D19
G20
E19
F19
I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT
I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT
I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT
I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT
I2S4_MCK
I2S4_BCLK
I2S4_LRCK
I2S4_DIN
I2S4_DOUT
SPDIF
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN
SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN
U0600
BALI-H5G
SYM 3 OF 12
OMIT_TABLE
GRAPE
3.0V
4 5 7
10 34
GPIO_GRAPE_IRQ_L
5
16
BGA
=PP1V8_H5
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
I2C2_SCL
I2C2_SDA
SWI_DATA
DWI_CLK
DWI_DI
DWI_DO
NOSTUFF
1
R0760
100K
5%
1/20W
MF
201
2
Y33
U29
W27
W29
H20
B19
AB27
T26
W32
W28
I2C0_SCL_1V8
I2C0_SDA_1V8
I2C1_SCL_1V8
I2C1_SDA_1V8
I2C2_SCL_3V0
I2C2_SDA_3V0
NC_SWI_AP
NO_TEST=TRUE
DWI_AP_CLK
DWI_AP_DI
DWI_AP_DO
5
19 25 30 36
BI
5
19 25 30 36
OUT
22 36
5
BI
5
22 36
OUT
5
22 36
BI
5
22 36
OUT
30 36
OUT
30 36
IN
30 36
OUT
TO:
TRISTAR 0011010X
ADRIANA PMU 0111100X
L19 LEFT 1000000X
L19 RIGHT 1000001X
TO SENSOR BOARD:
AD7149 PROX 0101100X
AKM8975B COMPASS 0001110X
TO SENSOR BOARD:
CT809 ALS 0111001X
LIS331DLH ACCEL 0011001X
AP3GDL8 GYRO 1101000X
GPIO_BTN_HOME_L
5
23 30
IN
20 30
26
14 36
30
32
20 30
16
19
19
GPIO_BTN_ONOFF_L
5
IN
GPIO_BB_HSIC_DEV_RDY
26 36
IN
GPIO_BTN_VOL_UP_L
20
IN
GPIO_ALS_IRQ_L
22
IN
GPIO_BT_WAKE
14
OUT
GPIO_AP_MODEM_WAKE
26
IN
BB_JTAG_TMS_RF
26
OUT
GPIO_BB_RST_L
26 39
OUT
GPIO_BB_RADIO_ON_L
5
OUT
GPIO_BB_RESET_DET_L
26
IN
GPIO_ACCEL_IRQ2_L
22
IN
GPIO_BB_HSIC_RESUME
26 36
IN
GPIO_WLAN_HSIC_HOST_RDY
5
OUT
GPIO_BTN_VOL_DOWN_L
20
IN
GPIO_BB_GSM_TXBURST
26
IN
GPIO_BOARD_ID_3
10
IN
PMU_GPIO_TS_INT
25 30
IN
GPIO_BOOT_CONFIG_0
10
IN
GPIO_BB_GPS_SYNC
26
OUT
GPIO_PROX_IRQ_L
22
IN
GPIO_GYRO_IRQ1
22
IN
GPIO_PMU_KEEPACT
5
OUT
GPIO_PMU_IRQ_L
30
IN
GPIO_WLAN_HSIC_DEV_RDY
14 36
IN
GPIO_BOOT_CONFIG_1
10
IN
GPIO_FORCE_DFU
5
IN
GPIO_DFU_STATUS
5
OUT
GPIO_BOOT_CONFIG_2
10
IN
GPIO_BOOT_CONFIG_3
10
IN
GPIO_BTN_SRL_L
5
IN
GPIO_GRAPE_IRQ_L
5
IN
GPIO_WL_HSIC_RESUME
14
IN
GPIO_SPKAMP_RST_L
5
OUT
GPIO_SPKAMP_KEEPALIVE
5
OUT
GPIO_SPKAMP_RIGHT_IRQ_L
19
IN
PM_LCDVDD_PWREN
15
OUT
GPIO_SPKAMP_LEFT_IRQ_L
19
IN
SPK_ID
19
IN
GPIO_CODEC_IRQ_L
18
IN
GPIO_GRAPE_FW_DNLD_EN_L
16
OUT
GPIO_GRAPE_RST_L
16
OUT
AK20
AJ19
AK22
AK19
AK21
AK24
AJ21
AK18
AL26
AH25
AJ18
AJ23
AK23
AJ20
AJ22
AJ24
AL25
AM26
AK25
AN26
F26
E26
J31
F29
E30
H31
J30
H32
G27
E27
F32
J28
G31
G32
G28
G33
J26
G30
G29
F27
H19
J19
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO_3V0
GPIO_3V1
OMIT_TABLE
U0600
BALI-H5G
BGA
SYM 2 OF 12
EHCI_PORT_PWR0
EHCI_PORT_PWR1
EHCI_PORT_PWR2
EHCI_PORT_PWR3
TMR32_PWM0
TMR32_PWM1
TMR32_PWM2
UART0_RXD
UART0_TXD
UART1_CTSN
UART1_RTSN
UART1_RXD
UART1_TXD
UART2_CTSN
UART2_RTSN
UART2_RXD
UART2_TXD
UART3_CTSN
UART3_RTSN
UART3_RXD
UART3_TXD
UART4_CTSN
UART4_RTSN
UART4_RXD
UART4_TXD
UART5_RXD
UART5_TXD
UART6_CTSN
UART6_RTSN
UART6_RXD
UART6_TXD
GPIO_SVSEL18_FMI
GPIO_SVSEL25_FMI
GPIO_VSEL25_I2C2
GPIO_VSEL25_SPI3
VSEL18_FMI AND VSEL25_FMI LOW => FMI CHANNEL AT 1.8V
VSEL25_I2C2 HIGH => I2C2 3.0V
VSEL25_SPI3 HIGH => SPI3 3.0V
AK28
GPIO_BRD_REV0
AJ25
GPIO_BRD_REV1
AK26
GPIO_BRD_REV2
AK27
NC_EHCI_PORT_PWR3_AP
NO_TEST=TRUE
V33
GPIO_GYRO_IRQ2
W31
GPIO_ACCEL_IRQ1_L
V27
NC_TMR32_PWM2_AP
NO_TEST=TRUE
K18
NC_UART0_RXD
NO_TEST=TRUE
K19
NC_UART0_TXD
NO_TEST=TRUE
AM27
UART1_BB_CTS_L
AM28
UART1_BB_RTS_L
AN27
UART1_BB_RXD
AN28
UART1_BB_TXD
Y30
BB_JTAG_TCK_RF
AC27
NC_UART2_RTSN
NO_TEST=TRUE
AC33
UART2_TS_ACC_RXD
AD33
UART2_TS_ACC_TXD
AB32
UART3_BT_CTS_L
AC30
UART3_BT_RTS_L
AC32
UART3_BT_RXD
AD32
UART3_BT_TXD
NO_TEST=TRUE
Y27
NC_UART4_CTS_L
NO_TEST=TRUE
AA29
NC_UART4_RTC_L
AB31
UART4_WLAN_RXD
AC31
UART4_WLAN_TXD
J18
UART5_BATTERY_TRXD
K17
NC_UART5_TXD
NO_TEST=TRUE
AC28
NC_UART6_CTSN
NO_TEST=TRUE
W30
NC_UART6_RTSN
NO_TEST=TRUE
AA30
UART6_AP_RXD
AA31
UART6_AP_TXD
H27
G25
E31
H29
35
GPIO_VSEL25_I2C2
GPIO_VSEL25_SPI3
12
10
IN
10
IN
10
IN
22
IN
22
IN
26 36
IN
26 36
OUT
25 26 36
IN
25 26 36
OUT
26
OUT
25 36
IN
25 36
OUT
14 36
IN
14 36
OUT
14 36
IN
14 36
OUT
14 36
IN
14 36
OUT
25 36
IN
25 36
OUT
28 30
OUT
=PP1V8_H5
1
R0716
100K
5%
1/20W
MF
201
2
TO BB UART
MDM9600
TO TRISTAR
1.8V
TO BT UART
BCM4330
WIFI DEBUG
TO TRISTAR
1.8V
4 5 7
1
R0717
100K
5%
1/20W
MF
201
2
10 34
D
C
B
BUTTON PULLUPS
R0708
220K
=PP1V8_S2R_MISC
5
32 34
GPIO_BTN_HOME_L
5
23 30
=PP1V8_ALWAYS
34
GPIO_BTN_ONOFF_L
5
A
20 30
=PP1V8_S2R_MISC
32 34
5
GPIO_BTN_SRL_L
5
20 30
1 2
5%
1/20W
MF
201
R0709
220K
1 2
5%
1/20W
MF
201
R0710
220K
1 2
5%
1/20W
MF
201
1
R0711
100K
5%
1/20W
MF
201
2
1
R0713
5%
1/20W
MF
201
2
NOSTUFF
1
R0714
100K100K
5%
1/20W
MF
201
2
NOSTUFF
1
R0715
100K
5%
1/20W
MF
201
2
1
R0718
100K
5%
1/20W
MF
201
2
GPIO_PMU_KEEPACT
GPIO_FORCE_DFU
GPIO_DFU_STATUS
GPIO_BB_RADIO_ON_L
GPIO_WLAN_HSIC_HOST_RDY
GPIO_SPKAMP_RST_L
GPIO_SPKAMP_KEEPALIVE
1
R0719
100K
5%
1/20W 1/20W
MF
201
2
1
2
R0721
100K
5%
MF
201
5
30
5
32
5
5
26
5
14 36
5
19
5
19
10 34
I2C0_SDA_1V8
5
19 25 30 36
I2C0_SCL_1V8
19 25 30 36
5
I2C1_SDA_1V8
5
22 36
I2C1_SCL_1V8
5
22 36
I2C2_SDA_3V0
5
22 36
I2C2_SCL_3V0
5
22 36
=PP1V8_H5
4 5 7
6 3
I2C PULL-UPS
NEED TO CHARACTERIZE RISE TIME
AND SIZE THESE RESISTORS
R0701
2.2K
5%
1/32W
MF
01005
1
2
1
2
R0702
2.2K
5%
1/32W
MF
01005
PP3V0_SENSOR_FLT
20 21
1
R0703
1.00K
5%
1/32W
MF
01005
2
1
R0704
1.00K
5%
1/32W
MF
01005
2
1
R0705
5%
1/32W
MF
01005
2
1
R0706
1.00K1.00K
5%
1/32W
MF
01005
2
SYNC_MASTER=N/A
PAGE TITLE
AP: I/Os
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
7 OF 154
SHEET
5 OF 39
124578
SIZE
A
D
8 7 6 5 4 3
12
D
=PP1V8_NAND_H5
34
AB8
AB10
AB12
AB14
AB16
AB18
AB19
AB21
AB23
AB25
AB30
AC1
AC3
AC9
AC11
AC13
AC15
AC17
C
B
AC20
AC22
AC24
AD8
AD10
AD12
AD14
AD16
AD18
AD19
AD21
AD23
AD25
AE4
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE17
AE22
AE30
AE32
AF3
AF16
AG2
AG16
AG17
AG25
VSS
A6
U0600
BALI-H5G
BGA
SYM 12 OF 12
OMIT_TABLE
VSS
AH5
AH10
AH15
AH16
AH17
AH30
AH32
P24
AJ17
AJ27
AK2
AK8
AK14
AK17
AH1
AL3
AL7
AL10
AL13
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL1
AL29
AM1
AM2
AM6
AM9
AM12
AM15
AM32
AM33
AN1
AN2
AL33
T20
AN11
AN14
AN32
AN33
AN3
AN31
AN6
C1
6 9
1
R0832
100K
5%
1/32W
MF
01005
FMI1_CE0_L
6
13 38
FMI0_CE0_L
6
13 38
FMI0_CE0_L
6
13 38
OUT
NC_FMI0_CE1_L
NC_FMI0_CE2_L
NC_FMI0_CE3_L
NC_FMI0_CE4_L
NC_FMI0_CE5_L
NC_FMI0_CE6_L
NC_FMI0_CE7_L
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
34
6 9
6
FMI0_AD<0>
FMI0_AD<1>
FMI0_AD<2>
FMI0_AD<3>
FMI0_AD<4>
FMI0_AD<5>
FMI0_AD<6>
FMI0_AD<7>
NC_FMI0_RE
FMI0_ALE
FMI0_CLE
FMI0_WE_L
FMI0_RE_L
FMI0_DQS
NC_FMI0_DQSN
=PP1V8_NAND_H5
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
13 38
2
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
AN29
AM30
AL28
AL27
AJ32
AJ31
AM31
AL30
AM29
AK33
AJ30
AK31
AH28
AJ29
AN30
AH27
AK29
AJ28
AH29
AK32
AK30
AL31
AL32
AG27
AF26
AB26
AG28
1
R0831
100K
5%
1/32W
MF
01005
2
FMI0_CEN0
FMI0_CEN1
FMI0_CEN2
FMI0_CEN3
FMI0_CEN4
FMI0_CEN5
FMI0_CEN6
FMI0_CEN7
FMI0_IO0
FMI0_IO1
FMI0_IO2
FMI0_IO3
FMI0_IO4
FMI0_IO5
FMI0_IO6
FMI0_IO7
FMI0_WENN
FMI0_ALE
FMI0_CLE
FMI0_WEN
FMI0_REN
FMI0_DQS
FMI0_DQSN
FMI0_DQVREF
PVDDP_GRP1
PVDDP_GRP2
U0600
BALI-H5G
BGA
SYM 4 OF 12
OMIT_TABLE
FMI1_CEN0
FMI1_CEN1
FMI1_CEN2
FMI1_CEN3
FMI1_CEN4
FMI1_CEN5
FMI1_CEN6
FMI1_CEN7
FMI1_IO0
FMI1_IO1
FMI1_IO2
FMI1_IO3
FMI1_IO4
FMI1_IO5
FMI1_IO6
FMI1_IO7
FMI1_WENN
FMI1_ALE
FMI1_CLE
FMI1_WEN
FMI1_REN
FMI1_DQS
FMI1_DQSN
FMI1_DQVREF
PVDDP_GRP3
PVDDP_GRP4
PVDDP_GRP5
FMI1_VREFFMI0_VREF
AF29
AF30
AE29
AD30
AF27
AE27
AF28
AE28
AE33
AH33
AG33
AG30
AD31
AE31
AG29
AD29
CKPLUS_WAIVE=PDIFPR_BADTERMCKPLUS_WAIVE=PDIFPR_BADTERM
AG31
AJ33
AH31
AG32
AF31
AF32
AF33
AD27
P25
G19
K24
AD28
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
FMI1_CE0_L
NC_FMI1_CE1_L
NC_FMI1_CE2_L
NC_FMI1_CE3_L
NC_FMI1_CE4_L
NC_FMI1_CE5_L
NC_FMI1_CE6_L
NC_FMI1_CE7_L
FMI1_AD<0>
FMI1_AD<1>
FMI1_AD<2>
FMI1_AD<3>
FMI1_AD<4>
FMI1_AD<5>
FMI1_AD<6>
FMI1_AD<7>
NC_FMI1_RE
FMI1_ALE
FMI1_CLE
FMI1_WE_L
FMI1_RE_L
FMI1_DQS
NC_FMI1_DQSN
=PP1V8_VDDIO18_H5
FMI_DQVREF_H5FMI_DQVREF_H5
6
6
13 38
OUT
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
BI
13 38
OUT
13 38
OUT
13 38
OUT
13 38
OUT
13 38
OUT
1
R0842
51.1K
34
4 6 7 9
1
R0843
51.1K
1%
1/32W
MF
01005
2
2
1%
1/32W
MF
01005
=PP1V8_NAND_H5
1
C0842
0.1UF
20%
4V
2
X5R
01005
1
C0843
0.1UF
20%
4V
2
X5R
01005
6 9
34
D
C
B
=PP1V8_NAND_H5
34
6 9
1
C0820
0.1UF
A
2
20%
4V
X5R
01005
1
C0821
0.1UF
20%
4V
2
X5R
01005
6 3
4 6 7 9
34
=PP1V8_VDDIO18_H5
1
C0810
0.1UF
20%
4V
2
X5R
01005
1
C0811
0.1UF
20%
4V
2
X5R
01005
1
C0812
0.1UF
20%
4V
2
X5R
01005
SYNC_MASTER=N/A
PAGE TITLE
AP: NAND
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
8 OF 154
SHEET
6 OF 39
124578
SIZE
A
D
8 7 6 5 4 3
=PP1V0_DP_PAD_DVDD_H5
34
R0911
0
C0931
56PF
5%
6.3V
NP0-C0G
01005
1
R0932
2
0.00
1 2
0%
0.00
1 2
1 2
5%
1/20W
MF
201
240-OHM-0.2A-0.8-OHM
1.00K
5%
1/32W
MF
01005
NO_TEST=TRUE
R0900
MF
01005
ISP0_CAM_RF_SHUTDOWN
R0940
MF0%
ISP1_CAM_FF_SHUTDOWN_L
1
C0928
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
NOSTUFF
FL0911
1 2
0201
NOSTUFF
C0955
1
0.1UF
10%
6.3V
2
X5R
201
=PP1V8_H5
1
R0933
1.00K
5%
1/32W
MF
01005
2
ISP0_CAM_RF_RST_L
NC_ISP0_CAM_RF_FLASH
ISP0_CAM_RF_I2C_SCL
ISP0_CAM_RF_I2C_SDA
REAR FACING CAM
FRONT FACING CAM
ISP1_CAM_FF_I2C_SCL
ISP1_CAM_FF_I2C_SDA
NOSTUFF
1
R0950
6.34K
1%
1/20W
MF
201
2
4 5 7
ISP0_CAM_RF_CLK
ISP1_CAM_FF_CLK
21 37
IN
21 37
IN
21 37
IN
21 37
IN
1
C0929
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
=PP1V0_EDP_PAD_DVDD_H5
34
DAC_AP_COMP_FTR
DAC_AP_VREF
39
DAC_AP_IREF
15 37
IN
15 37
OUT
15 37
OUT
15 37
OUT
15 37
OUT
15 37
OUT
15 37
OUT
15 37
OUT
15 37
OUT
15 37
OUT
15 37
OUT
NOTE: 0.6V ANALOG REF
AP_EDP_R_BIAS
NOSTUFF
1
C0957
0.01UF
10%
6.3V
2
X5R
10 34
01005
TP_EDP_AP_ANALOG_TEST
22
OUT
22 36
OUT
22 36
BI
22 36
OUT
22 36
BI
22 36
OUT
22
OUT
SHUTDOWN IS ACTIVE HIGH
22 36
OUT
22
OUT
SHUTDOWN IS ACTIVE LOW
1
C0930
56PF
5%
6.3V
2
NP0-C0G
01005
NOSTUFF
1
C0956
0.1UF
10%
6.3V
2
X5R
201
DAC_AP_COMP
EDP_HPD
EDP_AUX_P
EDP_AUX_N
EDP_DATA_P<0>
EDP_DATA_N<0>
EDP_DATA_P<1>
EDP_DATA_N<1>
EDP_DATA_P<2>
EDP_DATA_N<2>
EDP_DATA_P<3>
EDP_DATA_N<3>
1
R0921
4.99K
1%
1/32W
MF
01005
2
1
C0932
0.22UF
20%
6.3V
2
X5R
402
1
C0909
0.1UF
10%
6.3V
2
X5R
201
J24
K23
E18
C30
C29
A30
A29
D28
D27
B28
B27
C26
C25
E28
F28
SOCHOT1_L PULL-UP ON CSA 90
32
=PP1V8_EDP_H5
34
D
=PP1V8_VDDIO18_H5
4 6 7 9
34
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
?
REF DES
FL0910155S0725 155S0359
COMMENTS:
RDAR://PROBLEM/11104943
C
FL0910
80-OHM-0.2A-0.4-OHM
=PP1V0_MIPI_PLL_H5
34
=PP1V0_MIPI_H5
34
1
C0935
1UF
10%
6.3V
2
CERM
402
1 2
0201-1
1
C0908
0.1UF
10%
6.3V
2
X5R
201
1
C0903
0.1UF
10%
6.3V
2
X5R
201
1
C0980
1UF
10%
6.3V
2
CERM
402
1
C0904
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
PP1V0_MIPI_PLL_F
39
1
C0981
0.01UF
10%
6.3V
2
X5R
01005
B
NC_MIPI_VSYNC_H5
MIPI0C_CAM_RF_DATA_P<0>
21 37
IN
MIPI0C_CAM_RF_DATA_N<0>
21 37
IN
MIPI0C_CAM_RF_DATA_P<1>
21 37
IN
MIPI0C_CAM_RF_DATA_N<1>
21 37
IN
NC_MIPI0C_CAM_RF_DATA_P<2>
NC_MIPI0C_CAM_RF_DATA_N<2>
NC_MIPI0C_CAM_RF_DATA_P<3>
NC_MIPI0C_CAM_RF_DATA_N<3>
MIPI0C_CAM_RF_CLK_P
21 37
IN
MIPI0C_CAM_RF_CLK_N
21 37
IN
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
U27
AM22
AN22
AM21
AN21
AM19
AN19
AM18
AN18
AM20
AN20
MIPI_VSYNC
MIPI0C_DPDATA0
MIPI0C_DNDATA0
MIPI0C_DPDATA1
MIPI0C_DNDATA1
MIPI0C_DPDATA2
MIPI0C_DNDATA2
MIPI0C_DPDATA3
MIPI0C_DNDATA3
MIPI0C_DPCLK
MIPI0C_DNCLK
A
TABLE_ALT_HEAD
TABLE_ALT_ITEM
VOLTAGE=1.0V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
1
C0982
56PF
5%
6.3V
2
NP0-C0G
01005
AF20
AF21
AF22
AF23
AF24
MIPI_VDD10
40MA
3.3MA
BALI-H5G
SYM 5 OF 12
OMIT_TABLE
AG20
AH22
AH24
AH21
AH19
MIPI0D_VDD18
MIPI1D_VDD18
2MA
PER PIN
MIPI0D_VDD10_PLL
MIPI1D_VDD10_PLL
3.3MA
U0600
BGA
MIPI_VSS
AG21
AG22
AG23
AG24
=PP1V8_MIPI_H5
1
C0907
0.1UF
10%
6.3V
2
X5R
201
AH23
AH20
MIPI1D_VREG_0P4V
MIPI0D_VREG_0P4V
ISP0_FLASH
ISP0_PRE_FLASH
ISP0_SCL
ISP0_SDA
ISP1_FLASH
ISP1_PRE_FLASH
ISP1_SCL
ISP1_SDA
SENSOR0_CLK
SENSOR0_RST
SENSOR1_CLK
SENSOR1_RST
MIPI1C_DPDATA0
MIPI1C_DNDATA0
MIPI1C_DPDATA1
MIPI1C_DNDATA1
MIPI1C_DPCLK
MIPI1C_DNCLK
PP0V4_MIPI0D
PP0V4_MIPI1D
1
R0930
1.00K
5%
1/32W
MF
01005
2
M25
M31
AA27
U28
N25
SOCHOT1_L
L30
SOCHOT0_L
AA33
U30
V31
ISP0_CAM_RF_CLK_R
36
U32
U31
ISP1_CAM_FF_CLK_R
36
T27
AM23
AN23
NO_TEST=TRUE
AM25
NO_TEST=TRUE
AN25
AM24
AN24
34
VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
1
2
1
2
1
2
C0960
2.2NF
10%
10V
X5R-CERM
0201
VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
C0961
2.2NF
10%
10V
X5R-CERM
0201
1
R0931
1.00K
5%
1/32W
MF
01005
2
7
32
7
1/32W
1/32W 01005
MIPI1C_CAM_FF_DATA_P<0>
MIPI1C_CAM_FF_DATA_N<0>
NC_MIPI1C_CAM_FF_DATA_P<1>
NC_MIPI1C_CAM_FF_DATA_N<1>
MIPI1C_CAM_FF_CLK_P
MIPI1C_CAM_FF_CLK_N
1
C0910
8.2PF
+/-0.1PF%
25V
2
CER
0201
1
PP1V8_EDP_AVDD_AUX
39
1
C0933
0.22UF
20%
6.3V
2
X5R
402
C31
EDP_PAD_DVDD
15MA
DAC_VREF DAC_OUT3
DAC_IREF
DAC_COMP
EDP_HPD
EDP_PAD_AUXP
EDP_PAD_AUXN
EDP_PAD_TX0P
EDP_PAD_TX0N
EDP_PAD_TX1P
EDP_PAD_TX1N
EDP_PAD_TX2P
EDP_PAD_TX2N
EDP_PAD_TX3P
EDP_PAD_TX3N
EDP_PAD_R_BIAS
EDP_PAD_DC_TP
EDP_PAD_AVSS3
EDP_PAD_AVSS2
B26
B25
1
C0934
0.22UF
20%
6.3V
2
X5R
402
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
D26
D25
D29
B31
EDP_PAD_AVDDX
EDP_PAD_AVDD3
EDP_PAD_AVDD2
EDP_PAD_AVDDP0
65MA
PER PIN
22MA
10MA
EDP_PAD_AVSS0
EDP_PAD_DVSS
D31
A28
C32
EDP_PAD_AVSSX
EDP_PAD_AVSS1
A27
C28
C27
D30
EDP_PAD_AVDD1
EDP_PAD_AVDD0
EDP_PAD_AVDD_AUX
16MA
BALI-H5G
SYM 6 OF 12
OMIT_TABLE
EDP_PAD_AVSSP0
EDP_PAD_AVSS_AUX
B30
B29
C23
C24
DP_PAD_DVDD
15MA
U0600
BGA
DP_PAD_DVSS
A24
DP_PAD_AVDDX
22MA
=PP1V8_H5
NOSTUFF
7
7
SOCHOT1_L
SOCHOT0_L
1
R0942
100K
5%
1/32W
MF
01005
2
1
R0941
100K
5%
1/32W
MF
01005
2
2
A20
D21
DP_PAD_AVDD3
DP_PAD_AVDDP0
65MA
PER PIN
10MA
DP_PAD_AVSSP0
DP_PAD_AVSSX
B21
A23
C0927
0.1UF
20%
4V
X5R
01005
E20
B20
DP_PAD_AVDD2
DP_PAD_AVDD1
DP_PAD_AVSS3
DP_PAD_AVSS1
F20
C20
4 5 7
E21
D22
DP_PAD_AVDD0
DP_PAD_AVDD_AUX
16MA
DP_PAD_AUXP
DP_PAD_AUXN
DP_PAD_TX0P
DP_PAD_TX0N
DP_PAD_TX1P
DP_PAD_TX1N
DP_PAD_TX2P
DP_PAD_TX2N
DP_PAD_TX3P
DP_PAD_TX3N
DP_PAD_R_BIAS
DP_PAD_DC_TP
DP_PAD_AVSS2
DP_PAD_AVSS0
DP_PAD_AVSS_AUX
F21
D20
B22
10 34
=PP1V8_DP_H5
1
C0924
56PF
5%
6.3V
2
NP0-C0G
01005
H24
H23
DAC_AVDD18D
DAC_AVDD18A
15MA
15MA
DAC_OUT2
DAC_OUT1
DP_HPD
DAC_AVSS18D
G23
34
1
C0951
0.1UF
20%
4V
2
X5R
01005
NO_TEST=TRUE
D33J23
NO_TEST=TRUE
E33
NO_TEST=TRUE
F33
NO_TEST=TRUE
B18
NO_TEST=TRUE
A26
NO_TEST=TRUE
A25
NO_TEST=TRUE
D24
NO_TEST=TRUE
D23
NO_TEST=TRUE
B24
NO_TEST=TRUE
B23
NO_TEST=TRUE
C22
NO_TEST=TRUE
C21
NO_TEST=TRUE
A22
NO_TEST=TRUE
A21
E23
F23
TP_DP_AP_ANALOG_TEST
DAC_AVSS18A
G24
SYNC_MASTER=N/A
PAGE TITLE
NC_DAC_AP_OUT3
NC_DAC_AP_OUT2
NC_DAC_AP_OUT1
NC_DP_HPD
NC_DP_AUX_P
NC_DP_AUX_N
NC_DP_DATA_P<0>
NC_DP_DATA_N<0>
NC_DP_DATA_P<1>
NC_DP_DATA_N<1>
NC_DP_DATA_P<2>
NC_DP_DATA_N<2>
NC_DP_DATA_P<3>
NC_DP_DATA_N<3>
DP_R_BIAS
NOTE: 0.6V ANALOG REF
AP: TV,DP,MIPI
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
=PP1V8_VDDIO18_H5
1
C0953
0.01UF
10%
6.3V
2
X5R
01005
=PP1V8_VDDIO18_H5
1
C0952
0.01UF
10%
6.3V
2
X5R
01005
1
R0920
4.99K
1%
1/32W
MF
01005
2
6 3
12
NOSTUFF
1
C0950
0.01UF
10%
6.3V
2
X5R
01005
DRAWING NUMBER
051-9385
REVISION
BRANCH
PAGE
9 OF 154
SHEET
7 OF 39
124578
4 6 7 9
34
4 6 7 9
34
SYNC_DATE=N/A
A.0.0
SIZE
D
C
B
A
D
8 7 6 5 4 3
12
NO_TEST=TRUE
NO_TEST=TRUE
1
2
C1022
0.22UF
20%
6.3V
X5R
0201
AH11
AG11
AG12
AH12
AG13
AH14
AH13
AN10
AB2
AB3
AC2
AC4
AD2
AD3
AE2
AE3
AF2
AF4
AG5
AH2
AJ2
AG3
AH3
AJ3
AA3
AA4
AA5
AK3
AL2
AM3
AM4
AL4
AL5
AK5
AJ5
AH6
AG6
AH7
AG7
AH8
AD4
AG4
AB6
AK4
AA1
AB1
AG1
AF1
AK1
AJ1
AN9
AH9
AG9
AG8
AB4
W2
W4
Y2
Y3
Y4
V1
W1
Y8
DDR2_DQ0
DDR2_DQ1
DDR2_DQ2
DDR2_DQ3
DDR2_DQ4
DDR2_DQ5
DDR2_DQ6
DDR2_DQ7
DDR2_DQ8
DDR2_DQ9
DDR2_DQ10
DDR2_DQ11
DDR2_DQ12
DDR2_DQ13
DDR2_DQ14
DDR2_DQ15
DDR2_DQ16
DDR2_DQ17
DDR2_DQ18
DDR2_DQ19
DDR2_DQ20
DDR2_DQ21
DDR2_DQ22
DDR2_DQ23
DDR2_DQ24
DDR2_DQ25
DDR2_DQ26
DDR2_DQ27
DDR2_DQ28
DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_CA0
DDR2_CA1
DDR2_CA2
DDR2_CA3
DDR2_CA4
DDR2_CA5
DDR2_CA6
DDR2_CA7
DDR2_CA8
DDR2_CA9
DDR2_DM0
DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR2_NDQS0
DDR2_PDQS1
DDR2_NDQS1
DDR2_PDQS2
DDR2_NDQS2
DDR2_PDQS3
DDR2_NDQS3
DDR2_CK
DDR2_CKB
DDR2_CKE0
DDR2_CKE1
DDR2_RREF
DDR2_CSN0
DDR2_CSN1
DDR2_VREF_DQ
DDR2_VDD_CKE
U0600
BALI-H5G
BGA
SYM 8 OF 12
OMIT_TABLE
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_PDQS0DDR2_PDQS0
DDR3_NDQS0
DDR3_PDQS1
DDR3_NDQS1
DDR3_PDQS2
DDR3_NDQS2
DDR3_PDQS3
DDR3_NDQS3
DDR3_CKE0
DDR3_CKE1
DDR3_RREF
DDR3_CSN0
DDR3_CSN1
DDR3_VREF_DQ
DDR3_VDD_CKE
1
2
NO_TEST=TRUE
NO_TEST=TRUE
C1020
0.22UF
20%
6.3V
X5R
0201
B14
B13
D13
C12
D12
B11
C11
B10
B17
C17
B16
E17
D16
E16
C15
D15
E12
C14
A13
A12
A16
A15
D10
H15
C9
D9
B8
C8
B7
B6
C6
D7
E6
B5
C5
E5
C4
D4
B3
C3
G5
G6
H5
H6
J5
M5
M6
N6
P5
P6
E9
D6
A7
A8
A4
A5
P4
N4
J1
K1
M4
K6
J6
DDR0_DQ0
DDR0_DQ1
DDR0_DQ2
DDR0_DQ3
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6
DDR0_DQ7
DDR0_DQ8
DDR0_DQ9
DDR0_DQ10
DDR0_DQ11
DDR0_DQ12
DDR0_DQ13
DDR0_DQ14
DDR0_DQ15
DDR0_DQ16
DDR0_DQ17
DDR0_DQ18
DDR0_DQ19
DDR0_DQ20
DDR0_DQ21
DDR0_DQ22
DDR0_DQ23
DDR0_DQ24
DDR0_DQ25
DDR0_DQ26
DDR0_DQ27
DDR0_DQ28
DDR0_DQ29
DDR0_DQ30
DDR0_DQ31
DDR0_CA0
DDR0_CA1
DDR0_CA2
DDR0_CA3
DDR0_CA4
DDR0_CA5
DDR0_CA6
DDR0_CA7
DDR0_CA8
DDR0_CA9
DDR0_DM0
DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_PDQS0
DDR0_NDQS0
DDR0_PDQS1
DDR0_NDQS1
DDR0_PDQS2
DDR0_NDQS2
DDR0_PDQS3
DDR0_NDQS3
DDR0_CK
DDR0_CKB
DDR0_CKE0
DDR0_CKE1
DDR0_RREF
DDR0_CSN0
DDR0_CSN1
DDR0_VREF_DQ
DDR0_VDD_CKE
U0600
BALI-H5G
BGA
SYM 7 OF 12
OMIT_TABLE
DDR1_DQ10
DDR1_DQ11
DDR1_DQ12
DDR1_DQ13
DDR1_DQ14
DDR1_DQ15
DDR1_DQ16
DDR1_DQ17
DDR1_DQ18
DDR1_DQ19
DDR1_DQ20
DDR1_DQ21
DDR1_DQ22
DDR1_DQ23
DDR1_DQ24
DDR1_DQ25
DDR1_DQ26
DDR1_DQ27
DDR1_DQ28
DDR1_DQ29
DDR1_DQ30
DDR1_DQ31
DDR1_PDQS0
DDR1_NDQS0
DDR1_PDQS1
DDR1_NDQS1
DDR1_PDQS2
DDR1_NDQS2
DDR1_PDQS3
DDR1_NDQS3
DDR1_CKE0
DDR1_CKE1
DDR1_RREF
DDR1_CSN0
DDR1_CSN1
DDR1_VREF_DQ
DDR1_VDD_CKE
DDR0_DQ<0>
11 38
BI
DDR0_DQ<1>
11 38
BI
DDR0_DQ<2>
11 38
BI
DDR0_DQ<3>
11 38
BI
DDR0_DQ<4>
11 38
BI
DDR0_DQ<5>
11 38
BI
DDR0_DQ<6>
11 38
D
C
B
1
R1020
240
1%
1/20W
MF
201
2
BI
DDR0_DQ<7>
11 38
BI
DDR0_DQ<8>
11 38
BI
DDR0_DQ<9>
11 38
BI
DDR0_DQ<10>
11 38
BI
DDR0_DQ<11>
11 38
BI
DDR0_DQ<12>
11 38
BI
DDR0_DQ<13>
11 38
BI
DDR0_DQ<14>
11 38
BI
DDR0_DQ<15>
11 38
BI
DDR0_DQ<16>
11 38
BI
DDR0_DQ<17>
11 38
BI
DDR0_DQ<18>
11 38
BI
DDR0_DQ<19>
11 38
BI
DDR0_DQ<20>
11 38
BI
DDR0_DQ<21>
11 38
BI
DDR0_DQ<22>
11 38
BI
DDR0_DQ<23>
11 38
BI
DDR0_DQ<24>
11 38
BI
DDR0_DQ<25>
11 38
BI
DDR0_DQ<26>
11 38
BI
DDR0_DQ<27>
11 38
BI
DDR0_DQ<28>
11 38
BI
DDR0_DQ<29>
11 38
BI
DDR0_DQ<30>
11 38
BI
DDR0_DQ<31>
11 38
BI
DDR0_CA<0>
11 38
OUT
DDR0_CA<1>
11 38
OUT
DDR0_CA<2>
11 38
OUT
DDR0_CA<3>
11 38
OUT
DDR0_CA<4>
11 38
OUT
DDR0_CA<5>
11 38
OUT
DDR0_CA<6>
11 38
OUT
DDR0_CA<7>
11 38
OUT
DDR0_CA<8>
11 38
OUT
DDR0_CA<9>
11 38
OUT
DDR0_DM<0>
11 38
OUT
DDR0_DM<1>
11 38
OUT
DDR0_DM<2>
11 38
OUT
DDR0_DM<3>
11 38
OUT
DDR0_DQS_P<0>
11 38
BI
DDR0_DQS_N<0>
11 38
BI
DDR0_DQS_P<1>
11 38
BI
DDR0_DQS_N<1>
11 38
BI
DDR0_DQS_P<2>
11 38
BI
DDR0_DQS_N<2>
11 38
BI
DDR0_DQS_P<3>
11 38
BI
DDR0_DQS_N<3>
11 38
BI
DDR0_CK_P
11 38
OUT
DDR0_CK_N
11 38
OUT
DDR0_CKE<0>
11 38
OUT
NC_DDR0_CKE<1>
H5G_DDR0_ZQ H5G_DDR2_ZQ
DDR0_CSN<0>
11 38
OUT
NC_DDR0_CSN<1>
PPVREF_DDR0_DQ_H5
8 8
=PP1V2_S2R_H5 =PP1V2_S2R_H5
34
8
DDR1_DQ0
DDR1_DQ1
DDR1_DQ2
DDR1_DQ3
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6
DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_CA0
DDR1_CA1
DDR1_CA2
DDR1_CA3
DDR1_CA4
DDR1_CA5
DDR1_CA6
DDR1_CA7
DDR1_CA8
DDR1_CA9
DDR1_DM0
DDR1_DM1
DDR1_DM2
DDR1_DM3
DDR1_CK
DDR1_CKB
H2
H3
J3
J4
K2
L2
K4
K5
N2
P2
P3
R3
T2
R4
T3
T4
C2
D2
E2
E4
E3
F3
F4
G2
U3
V2
V3
U5
V4
V5
U6
V6
E15
F15
F14
E14
F13
E8
F8
F7
E7
F6
L5
N5
G4
R5
G1
H1
N1
M1
D1
E1
T1
R1
F11
F12
A10
NO_TEST=TRUE
A9
E11
F10
NO_TEST=TRUE
E13
L3
PPVREF_DDR1_DQ_H5
H8
DDR1_DQ<0>
DDR1_DQ<1>
DDR1_DQ<2>
DDR1_DQ<3>
DDR1_DQ<4>
DDR1_DQ<5>
DDR1_DQ<6>
DDR1_DQ<7>
DDR1_DQ<8>
DDR1_DQ<9>
DDR1_DQ<10>
DDR1_DQ<11>
DDR1_DQ<12>
DDR1_DQ<13>
DDR1_DQ<14>
DDR1_DQ<15>
DDR1_DQ<16>
DDR1_DQ<17>
DDR1_DQ<18>
DDR1_DQ<19>
DDR1_DQ<20>
DDR1_DQ<21>
DDR1_DQ<22>
DDR1_DQ<23>
DDR1_DQ<24>
DDR1_DQ<25>
DDR1_DQ<26>
DDR1_DQ<27>
DDR1_DQ<28>
DDR1_DQ<29>
DDR1_DQ<30>
DDR1_DQ<31>
DDR1_CA<0>
DDR1_CA<1>
DDR1_CA<2>
DDR1_CA<3>
DDR1_CA<4>
DDR1_CA<5>
DDR1_CA<6>
DDR1_CA<7>
DDR1_CA<8>
DDR1_CA<9>
DDR1_DM<0>
DDR1_DM<1>
DDR1_DM<2>
DDR1_DM<3>
DDR1_DQS_P<0>
DDR1_DQS_N<0>
DDR1_DQS_P<1>
DDR1_DQS_N<1>
DDR1_DQS_P<2>
DDR1_DQS_N<2>
DDR1_DQS_P<3>
DDR1_DQS_N<3>
DDR1_CK_P
DDR1_CK_N
DDR1_CKE<0>
NC_DDR1_CKE<1>
H5G_DDR1_ZQ
DDR1_CSN<0>
NC_DDR1_CSN<1>
=PP1V2_S2R_H5
1
C1021
0.22UF
20%
6.3V
2
X5R
0201
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
BI
11 38
OUT
11 38
OUT
11 38
OUT
11 38
OUT
8
8
34
1
R1021
240
1%
1/20W
MF
201
2
1
R1022
240
1%
1/20W
MF
201
2
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
8
34
DDR2_DQ<0>
DDR2_DQ<1>
DDR2_DQ<2>
DDR2_DQ<3>
DDR2_DQ<4>
DDR2_DQ<5>
DDR2_DQ<6>
DDR2_DQ<7>
DDR2_DQ<8>
DDR2_DQ<9>
DDR2_DQ<10>
DDR2_DQ<11>
DDR2_DQ<12>
DDR2_DQ<13>
DDR2_DQ<14>
DDR2_DQ<15>
DDR2_DQ<16>
DDR2_DQ<17>
DDR2_DQ<18>
DDR2_DQ<19>
DDR2_DQ<20>
DDR2_DQ<21>
DDR2_DQ<22>
DDR2_DQ<23>
DDR2_DQ<24>
DDR2_DQ<25>
DDR2_DQ<26>
DDR2_DQ<27>
DDR2_DQ<28>
DDR2_DQ<29>
DDR2_DQ<30>
DDR2_DQ<31>
DDR2_CA<0>
DDR2_CA<1>
DDR2_CA<2>
DDR2_CA<3>
DDR2_CA<4>
DDR2_CA<5>
DDR2_CA<6>
DDR2_CA<7>
DDR2_CA<8>
DDR2_CA<9>
DDR2_DM<0>
DDR2_DM<1>
DDR2_DM<2>
DDR2_DM<3>
DDR2_DQS_P<0>
DDR2_DQS_N<0>
DDR2_DQS_P<1>
DDR2_DQS_N<1>
DDR2_DQS_P<2>
DDR2_DQS_N<2>
DDR2_DQS_P<3>
DDR2_DQS_N<3>
DDR2_CK_P
DDR2_CK_N
DDR2_CKE<0>
NC_DDR2_CKE<1>
DDR2_CSN<0>
NC_DDR2_CSN<1>
PPVREF_DDR2_DQ_H5
DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8
DDR3_DQ9
DDR3_CA0
DDR3_CA1
DDR3_CA2
DDR3_CA3
DDR3_CA4
DDR3_CA5
DDR3_CA6
DDR3_CA7
DDR3_CA8
DDR3_CA9
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_CK
DDR3_CKB
AL8
AL9
AK9
AJ9
AM10
AJ10
AK10
AL11
AM11
AL12
AK12
AJ12
AM13
AK13
AJ13
AJ14
AM5
AL6
AK6
AJ6
AM7
AK7
AJ7
AM8
AM14
AL14
AJ15
AK15
AL15
AJ16
AK16
AM16
W5
W6
Y5
Y6
AA6
AD6
AE5
AE6
AF6
AF5
AK11
AG14
AJ8
AG15
AN7
AN8
AN13
AN12
AN4
AN5
AN16
AN15
AH4
AJ4
AD1
NO_TEST=TRUE
AE1
AB5
AC6
NO_TEST=TRUE
AC5
AJ11
PPVREF_DDR3_DQ_H5
AE8
DDR3_DQ<0>
DDR3_DQ<1>
DDR3_DQ<2>
DDR3_DQ<3>
DDR3_DQ<4>
DDR3_DQ<5>
DDR3_DQ<6>
DDR3_DQ<7>
DDR3_DQ<8>
DDR3_DQ<9>
DDR3_DQ<10>
DDR3_DQ<11>
DDR3_DQ<12>
DDR3_DQ<13>
DDR3_DQ<14>
DDR3_DQ<15>
DDR3_DQ<16>
DDR3_DQ<17>
DDR3_DQ<18>
DDR3_DQ<19>
DDR3_DQ<20>
DDR3_DQ<21>
DDR3_DQ<22>
DDR3_DQ<23>
DDR3_DQ<24>
DDR3_DQ<25>
DDR3_DQ<26>
DDR3_DQ<27>
DDR3_DQ<28>
DDR3_DQ<29>
DDR3_DQ<30>
DDR3_DQ<31>
DDR3_CA<0>
DDR3_CA<1>
DDR3_CA<2>
DDR3_CA<3>
DDR3_CA<4>
DDR3_CA<5>
DDR3_CA<6>
DDR3_CA<7>
DDR3_CA<8>
DDR3_CA<9>
DDR3_DM<0>
DDR3_DM<1>
DDR3_DM<2>
DDR3_DM<3>
DDR3_DQS_P<0>
DDR3_DQS_N<0>
DDR3_DQS_P<1>
DDR3_DQS_N<1>
DDR3_DQS_P<2>
DDR3_DQS_N<2>
DDR3_DQS_P<3>
DDR3_DQS_N<3>
DDR3_CK_P
DDR3_CK_N
DDR3_CKE<0>
NC_DDR3_CKE<1>
H5G_DDR3_ZQ
DDR3_CSN<0>
NC_DDR3_CSN<1>
=PP1V2_S2R_H5
1
C1023
0.22UF
20%
6.3V
2
X5R
0201
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
BI
12 38
OUT
12 38
OUT
12 38
OUT
12 38
OUT
8
34
8
1
R10234
240
1%
1/20W
MF
201
2
D
C
B
=PP1V2_VDDIOD_H5
34
=PP1V2_VDDIOD_H5
8 9
=PP1V2_VDDIOD_H5
34
8 9
A
1
R1053
4.7K
1%
1/32W
MF
01005
2
1
R1054
4.7K
1%
1/32W
MF
01005
2
1
C1057
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR0_DQ_H5
1
C1054
0.01UF
10%
6.3V
2
X5R
01005
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8
34
1
R1055
4.7K
1%
1/32W
MF
01005
2
1
R1056
4.7K
1%
1/32W
MF
01005
2
1
C1058
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR1_DQ_H5
1
C1056
0.01UF
10%
6.3V
2
X5R
01005
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8
8 9
1
R1083
4.7K
1%
1/32W
MF
01005
2
1
R1084
4.7K
1%
1/32W
MF
01005
2
1
C1085
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR2_DQ_H5
1
C1084
0.01UF
10%
6.3V
2
X5R
01005
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
6 3
=PP1V2_VDDIOD_H5
34
8 9
1
R1095
4.7K
1%
1/32W
MF
01005
2
1
R1096
4.7K
1%
1/32W
MF
01005
2
1
C1095
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR3_DQ_H5
1
C1096
0.01UF
10%
6.3V
2
X5R
01005
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8 8
SYNC_MASTER=N/A
PAGE TITLE
AP: DDR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
10 OF 154
SHEET
8 OF 39
124578
SIZE
A
D
8 7 6 5 4 3
=PPVDD_CPUB_H5
34
1
C1147
4.3UF
20%
4V
2
X5R-CERM
0610
=PPVDD_SOC_H5
34
9
D
VDD
C1103
10UF
6.3V
20%
X5R
603
1
2
U10
U12
U14
U16
U22
U24
V9
V11
V13
V15
V17
V25
W8
W10
W12
W14
W16
T19
W26
Y9
Y11
Y13
Y15
Y17
Y26
AA8
AA10
AA12
AA14
AA16
AA18
AA26
AB9
AB11
AB13
AB15
AB17
AC8
AC10
AC12
AC14
AC16
AC18
AD9
AD11
AD13
AD15
AD17
AE16
AE18
AF17
U20
R18
R24
C1104
10UF
6.3V
J8
J10
J12
J14
J22
K9
K11
K13
K15
K21
L8
L10
L12
L14
L16
L18
L20
L22
M9
M11
M13
M15
M17
C
B
=PPVDD_SOC_H5
9
34
M19
M21
M23
9500MA MAX
N8
VDD
N10
N12
N14
N16
N18
N20
N22
P9
P11
P15
P17
P19
P21
P23
R8
R10
R12
R14
R16
R20
R22
T9
T11
T13
T15
T17
T21
T23
U8
1
C1100
10UF 10UF
20%
6.3V
X5R
603
C1101
2
20%
6.3V
X5R
603
U0600
BALI-H5G
SYM 10 OF 12
OMIT_TABLE
1
2
BGA
C1102
10UF
6.3V
20%
X5R
603
1
2
1
C1148
4.3UF
20%
4V
2
X5R-CERM
0610
=PPVDD_CPU0_H5
34
=PPVDD_CPU1_H5
34
=PPVDD_SRAM_H5
34
1
C1179
10UF
20%
6.3V
2
X5R
603
34
1
C1105
20%
2
X5R
603
C1149
1UF
20%
6.3V
X5R
0201
1
C1161
1UF
20%
6.3V
2
X5R
0201
C1173
1UF
20%
6.3V
X5R
0201
C1180
4.3UF
20%
4V
X5R-CERM
0610
=PP3V0_VDDIO30_H5
9
34
=PP3V0_VDDIO30_H5
9
34
=PP1V8_NAND_H5
6
34
=PP1V8_VDDIO18_H5
4 6 7 9
1
10UF
20%
6.3V
2
X5R
603
1
2
C1162
1
2
1
2
1
C1150
1UF
20%
6.3V
2
X5R
CERM-X5R-1
0201
1
1UF
20%
6.3V
2
X5R
0201
1
C1174
1UF
20%
6.3V
2
X5R
0201
1
C1181
4.3UF
20%
4V
2
X5R-CERM
0610
1
CA193
10UF
20%
6.3V 6.3V
2
CERM-X5R
0402-1
1
C1151
0.47UF 0.47UF
C1155
4.3UF
X5R-CERM
0610
C1163
1UF
20%
6.3V
X5R
0201
C1167
4.3UF
X5R-CERM
0610
C1175
1UF
6.3V
0201
C1182
1UF
6.3V
0201
CA185
10UF
6.3V
1
CA194
4.3UF
20%
4V
2
X5R-CERM
0610
20%
201
20%
X5R
20%
X5R
20%
X5R
603
4V
20%
20%
4V
1
2
4V
2
CERM-X5R-1
1
2
1
2
1
2
1
2
1
2
1
CA189
2
1
CA150
2
C1152
C1156
4.3UF
X5R-CERM
C1164
1UF
6.3V
0201
C1168
4.3UF
X5R-CERM
C1176
C1183
CA186
0.22UF
0.22UF
20%
6.3V
X5R
0201
1
2
0.22UF
20%
6.3V
X5R
0201
1UF
6.3V
0201
1UF
6.3V
0201
20%
4V
201
20%
4V
0610
20%
X5R
20%
4V
0610
20%
X5R
20%
X5R
20%
6.3V
X5R
0201
CA195
1UF
10%
6.3V
CERM
402
1
2
1
2
1
2
1
2
1
2
1
2
CERM-X5R-1
1
2
1
2
1
2
C1153
0.1UF
X5R-CERM
C1157
C1165
0.1UF
X5R-CERM
C1169
C1177
0.1UF
X5R-CERM
C1184
0.47UF
CA187
0.22UF
CA190
0.22UF
20%
6.3V
X5R
0201
CA151
0.22UF
20%
6.3V
X5R
0201
20%
6.3V
01005
1UF
20%
6.3V
X5R
0201
20%
6.3V
01005
1UF
20%
6.3V
X5R
0201
20%
6.3V
01005
20%
201
20%
6.3V
X5R
0201
1
CA196
10UF
20%
6.3V
2
CERM-X5R
0402-1
4V
1
2
1
2
1
2
1
2
1
2
1
2
CERM-X5R-1
1
2
1
CA191
0.22UF
20%
6.3V
2
X5R
0201
1
CA152
0.22UF
20%
6.3V
2
X5R
0201
C1154
X5R-CERM
C1158
C1166
X5R-CERM
C1170
C1178
X5R-CERM
C1185
0.47UF
0.22UF
1
0.1UF
20%
6.3V
2
NP0-C0G-CERM
01005
1
1UF
20%
6.3V 6.3V
2
X5R
0201
1
0.1UF
20%
6.3V
2
NP0-C0G-CERM
01005
1
1UF
20%
6.3V
2
X5R
0201
1
0.1UF
20%
6.3V
2
NP0-C0G-CERM
01005
1
20%
4V
2
NP0-C0G-CERM
201
CA188
1
20%
6.3V
2
X5R
0201
1
CA192
0.22UF
20%
6.3V
2
X5R
0201
1
CA197
10UF
20%
2
CERM-X5R
0402-1
1
CA153
0.22UF
20%
6.3V
2
X5R
0201
1
C11B0
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C1159
1UF 1UF
20%
2
X5R
0201
1
C11C0
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C1171
1UF
20%
6.3V
2
X5R
0201
1
C11D0
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
C11E0
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
1
CA198
1UF
10%
6.3V
2
CERM
402
C11B1
8.2PF
+/-0.5PF
01005
C1160
6.3V
0201
C11C1
8.2PF
+/-0.5PF
01005
C1172
1UF
6.3V
0201
C11D1
8.2PF
+/-0.5PF
01005
C11E1
8.2PF
+/-0.5PF
01005
CRITICAL
1
CA199
0.47UF
20%
4V
2
X7S
0204
16V
20%
X5R
16V
20%
X5R
16V
16V
1
2
1
2
1
2
1
2
1
2
1
2
1
C11F0
8.2PF
+/-0.5PF
16V
2
NP0-C0G-CERM
01005
V20
V22
V24
Y20
Y22
Y24
AA21
AB20
AB22
AC19
AC21
AD20
AE19
AE21
AA23
AB24
AC23
AC25
AD22
AD24
AE23
AE25
AA19
AA25
W19
W21
W23
W25
N28
VDDIO30_GRP1
F18
VDDIO30_GRP2
K25
VDDIO30_GRP3
J20
VDDIOD0
K20
VDDIOD1
AG26
AH26
AJ26
AC26
AD26
AE26
AE20
VDD_ANA0
AE24
VDD_ANA1
W18
VDD_ANA_TMPSADC0
P13
VDD_ANA_TMPSADC1
VDD_CPUB
1.1A@1.1V
VDD_CPU0
2.5A@1.1V
2.5A@1.1V
VDD_CPU1
550MA@1.1V
VDD_SRAM
52MA
2MA
2MA
VDDIOD2
45MA
VDDIOD3
45MA
5MA
5MA
U0600
BALI-H5G
BGA
SYM 9 OF 12
OMIT_TABLE
FAST SCAN CLK
GPIO_3V0
USB11
SPI3
I2C2
FMI0-3 (1.8V)
FMI1-3 (1.8V)
TEMP SENSOR
ANALOG
VDDIOD
1000MA@1.2V
12MA
VDDIO18_GRP1
45MA
VDDIO18_GRP2
18MA
VDDIO18_GRP3
35MA
VDDIO18_GRP4
10MA
VDDIO18_GRP5
12MA
VDDIO18_GRP6
G7
G8
G9
G10
G11
G12
G13
G14
G15
H7
J7
K7
L7
M7
N7
P7
R7
T7
U7
V7
W7
Y7
AA7
AB7
AC7
AD7
AE7
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
H18
H26
J27
K27
L27
N29
U25
U26
V26
AF25
AH18
C1193
1UF
20%
6.3V
X5R
0201
C1194
1UF
20%
6.3V
X5R
0201
C1143
0.22UF
6.3V
0201
1
C1198
0.22UF
20%
6.3V
2
X5R
0201
20%
X5R
1
2
1
2
1
2
C1190
4.3UF
20%
X5R-CERM
0610
C1195
0.47UF
CERM-X5R-1
C1144
0.22UF
6.3V
0201
1
2
1
C1191
4.3UF
20%
X5R-CERM
0610
C1196
0.47UF
CERM-X5R-1
4V
20%
201
20%
201
20%
X5R
4V
2
1
4V
2
1
2
=PP1V8_VDDIO18_H5
C1199
0.22UF
20%
6.3V
X5R
0201
4V
1
2
1
2
1
2
C1145
56PF
5%
6.3V
NP0-C0G
01005
12
=PP1V2_VDDIOD_H5
1
C1192
10UF
20%
6.3V
2
X5R
603
C1197
0.22UF
20%
6.3V
X5R
0201
4 6 7 9
34
8
34
D
C1142
0.22UF
6.3V
0201
20%
X5R
1
2
1
2
C
B
C1107
4.3UF
X5R-CERM
0610
C1120
0.47UF0.47UF
C1130
20%
6.3V
X5R
0201
20%
20%
4V
4V
1
2
1
2
1
2
CERM-X5R-1
0.22UF
1
C1106
4.3UF
20%
4V
2
X5R-CERM
0610
1
C1119
A
C1128
0.22UF
20%
6.3V
X5R
0201
CERM-X5R-1
1
2
20%
201
C1129
0.22UF
20%
6.3V
X5R
0201
4V
2
CERM-X5R-1
1
0.22UF
2
C1108
4.3UF
X5R-CERM
0610
C1121
0.47UF
C1131
20%
6.3V
X5R
0201
20%
20%
201201
1
4V
2
1
4V
2
1
2
C1109
4.3UF
20%
4V
X5R-CERM
0610
C1122
0.47UF
CERM-X5R-1
C1132
0.22UF
20%
6.3V
X5R
0201
20%
201
1
2
1
4V
2
CERM-X5R-1
1
0.22UF
2
C1110
4.3UF
X5R-CERM
0610
C1123
0.47UF
C1133
20%
6.3V
X5R
0201
20%
1
4V
2
1
20%
4V
2
201
1
0.22UF
2
C1111
4.3UF
20%
4V
X5R-CERM
0610
C1124
0.47UF
CERM-X5R-1
C1134
20%
6.3V
X5R
0201
1
2
1
20%
4V
2
201
1
2
0.47UF
CERM-X5R-1
C1135
0.22UF
6.3V
0201
1
2
C1125
1
20%
2
X5R
C1113
1UF
10%
6.3V
CERM
402
20%
4V
201
1
2
1
2
C1126
0.47UF
CERM-X5R-1
C1114
1UF
10%
6.3V
CERM
402
20%
4V
201
1
2
C1136
0.1UF
6.3V
X5R-CERM
01005
20%
1
C1115
1UF
10%
6.3V
2
CERM
402
1
2
C1137
0.1UF
6.3V
X5R-CERM
01005
1
C1116
1UF
10%
6.3V
2
CERM
402
20%
1
C1117
1UF
10%
6.3V
2
CERM
402
1
C1138
0.1UF
20%
2
6.3V
X5R-CERM
01005
1
C1118
1UF
10%
6.3V
2
CERM
402
1
2
C1139
0.1UF
6.3V
X5R-CERM
01005
20%
1
2
C1140
0.1UF
6.3V
X5R-CERM
01005
20%
1
2
C1141
0.1UF
6.3V
X5R-CERM
01005
20%
1
2
NP0-C0G-CERM
C11A0
8.2PF
+/-0.5PF
01005
16V
1
2
C11A1
8.2PF
+/-0.5PF
NP0-C0G-CERM
01005
16V
PART NUMBER
138S0702 138S0657
1
2
ALTERNATE FOR
PART NUMBER
C1106,C1107,C1108,C1109,C1110,C1111,C1147,C1148,C1155,C1156,C1167,C1168,C1180,C1181,C1190,C1191,C1315,C1321,C1415,C1421,CA194
BOM OPTION
SYNC_MASTER=N/A
PAGE TITLE
REF DES
COMMENTS:
QTY 21 RDAR://PROBLEM/8837828
AP: POWER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 3
TABLE_ALT_HEAD
TABLE_ALT_ITEM
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
11 OF 154
SHEET
9 OF 39
124578
SIZE
A
D
8 7 6 5 4 3
12
BOOT CONFIG ID
BOOT_CONFIG[3]
BOOT_CONFIG[2]
D
BOOT_CONFIG[1]
BOOT_CONFIG[0]
CURRENT SETTING --->
=PP1V8_H5
10 34
4 5 7
GPIO_BOOT_CONFIG_3
5
OUT
GPIO_BOOT_CONFIG_2
5
OUT
GPIO_BOOT_CONFIG_1
5
OUT
GPIO_BOOT_CONFIG_0
5
OUT
BOOT_CONFIG[3-0]
FMI0/1 2/2 CS
1100
1101
FMI0/1 4/4 CS
1110
FMI0/1 4/4 CS WITH TEST
STUFF FOR FORM FACTOR BOARD
1
R1200
10K
5%
1/32W
MF
01005
2
1
R1201
10K
5%
1/32W
MF
01005
2
S/W READ FLOW
1. SET GPIO AS INPUT
2. DISABLE PU AND ENABLE PD
3. READ
NOSTUFF
1
R1202
10K
5%
1/32W
MF
01005
2
NOSTUFF
1
R1203
10K
5%
1/32W
MF
01005
2
JTAG
R1210
100
1 2
5%
1/32W
MF
01005
R1211
100
1 2
5%
1/32W
MF
01005
JTAG_AP_SEL
JTAG_AP_TRST_L
4
OUT
D
36 39
4
OUT
FOR REFERENCE
BOOT_CONFIG[3:0]
0000 SPI0
0001 SPI1
0010 SPI0 W/TEST
0011 SPI1 W/TEST
0100 FMI0 2CS
0101 FMI0 4CS
0110 FMI0 4CS W/TEST
0111 RESERVED
1000 FMI1 2 CS
1001 FMI1 4 CS
1010 FMI1 4CS W/TEST
1100 FMI0/1 2/2 CS
1101 FMI0/1 4/4 CS
1110 FMI0/1 4/4 CS W/TEST
C
1111 RESERVED
R1260
100K
1 2
5%
1/32W
MF
BOARD ID
BOARD_ID[3]
BOARD_ID[2]
BOARD_ID[1]
BOARD_ID[0]
BOARD_ID[3-0]
B
0000
0001
0010
0011
0100
0101
1010
1011
1110
1111
=PP1V8_H5
10 34
4 5 7
GPIO_BOARD_ID_3
5
OUT
GPIO_BOARD_ID_2
5
OUT
GPIO_BOARD_ID_1
5
OUT
GPIO_BOARD_ID_0
5
OUT
X140 AP WLAN (MLB A)
X140 DEV WLAN
X140 AP BB_41 (MLB B)
X140 DEV BB_41
X140 AP BB_42 (MLB C)
X140 DEV BB_42
X140 AP BB_26A (MLB D)
X140 DEV BB_26A
X140 AP BB_26 (MLB E)
X140 DEV BB_26
MLB_D&MLB_E
1
R1220
10K
5%
1/32W
MF
01005
2
1. SET GPIO AS INPUT
2. DISABLE PU AND ENABLE PD
3. READ
MLB_C&MLB_E
1
2
S/W READ FLOW
R1204
10K
5%
1/32W
MF
01005
MLB_B&MLB_D
1
R1205
10K
5%
1/32W
MF
01005
2
DEV
1
R1206
10K
5%
1/32W
MF
01005
2
IN
USB_BRICKID
01005
NOSTUFF
XW1200
SHORT-01005
NOSTUFF
XW1201
SHORT-01005
NOSTUFF
XW1202
SHORT-01005
12
12
12
AP_TESTMODE
AP_TST_STPCLK
AP_FAST_SCAN_CLK
AP_HOLD_RESET
MAKE_BASE=TRUE
4
OUT
4
OUT
4
OUT
4
OUT
PMU_USB_BRICKID
30 25
OUT
C
B
BOARD REVISION
GPIO_BRD_REV2
5
OUT
GPIO_BRD_REV1
5
OUT
GPIO_BRD_REV0
5
OUT
A
BRD_REV[2-0]
000
PROTO
PROTO 2
001
EVT010
CURRENT SETTING --->
011 DVT
NOSTUFF
1
R1207
10K
5%
1/32W
MF
01005
2
1. SET GPIO AS INPUT
2. ENABLE PU AND DISABLE PD
3. READ
NOSTUFF
1
R1208
10K
5%
1/32W
MF
01005
2
S/W READ FLOW
1
R1209
10K
5%
1/32W
MF
01005
2
6 3
SYNC_MASTER=N/A
PAGE TITLE
AP: MISC & ALIASES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
12 OF 154
SHEET
10 OF 39
124578
SIZE
A
D
8 7 6 5 4 3
12
DDR1_CA<0>
38
8
DDR1_CA<1>
8
38
DDR1_CA<2>
8
38
DDR1_CA<3>
8
38
DDR1_CA<4>
8
38
DDR1_CA<5>
8
=PP1V2_S2R_DDR
D
C
11 12 34
1
R1305
10K
1%
1/32W
MF
01005
2
1
R1306
10K
1%
1/32W
MF
01005
2
=PP1V2_S2R_DDR
11 12 34
1
R1351
10K
1%
1/32W
MF
01005
2
1
R1352
10K
1%
1/32W
MF
01005
2
=PP1V2_VDDQ_DDR
11 12 34
1
R1353
4.7K
1%
1/32W
MF
01005
2
1
R1354
4.7K
1%
1/32W
MF
01005
2
1
C1360
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR0_CA
1
C1350
0.01UF
10%
6.3V
2
X5R
01005
1
C1361
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR1_CA
1
C1352
0.01UF
10%
6.3V
2
X5R
01005
1
C1362
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR0_DQ
1
C1354
0.01UF
10%
6.3V
2
X5R
01005
11 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
11 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
11 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
B
=PP1V2_VDDQ_DDR
11 12 34
1
R1355
4.7K
1%
1/32W
MF
01005
2
1
R1356
4.7K
1%
1/32W
MF
01005
2
1
C1363
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR1_DQ
1
C1356
0.01UF
10%
6.3V
2
X5R
01005
11 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
38
DDR1_CA<6>
8
38
DDR1_CA<7>
8
38
DDR1_CA<8>
38
8
DDR1_CA<9>
8
38
DDR1_CK_P
38
8
DDR1_CK_N
8
38
DDR1_CKE<0>
38
8
DDR1_CSN<0>
8
38
DDR1_DM<1>
38
8
DDR1_DM<0>
8
38
DDR1_DM<3>
38
8
DDR1_DM<2>
8
38
DDR1_DQ<8>
38
8
DDR1_DQ<9>
8
38
DDR1_DQ<10>
8
38
DDR1_DQ<11>
8
38
DDR1_DQ<12>
8
38
DDR1_DQ<13>
38
8
DDR1_DQ<14>
8
38
DDR1_DQ<15>
8
38
DDR1_DQ<0>
8
38
DDR1_DQ<1>
8
38
DDR1_DQ<2>
8
38
DDR1_DQ<3>
8
38
DDR1_DQ<4>
8
38
DDR1_DQ<5>
8
38
DDR1_DQ<6>
8
38
DDR1_DQ<7>
8
38
DDR1_DQ<24>
8
38
DDR1_DQ<25>
38
8
DDR1_DQ<26>
38
8
DDR1_DQ<27>
8
38
DDR1_DQ<28>
8
38
DDR1_DQ<29>
8
38
DDR1_DQ<30>
8
38
DDR1_DQ<31>
8
38
DDR1_DQ<16>
8
38
DDR1_DQ<17>
8
38
DDR1_DQ<18>
8
38
DDR1_DQ<19>
8
38
DDR1_DQ<20>
8
38
DDR1_DQ<21>
8
38
DDR1_DQ<22>
8
38
DDR1_DQ<23>
8
38
8
38
8
38
DDR1_DQS_P<0>
8
38
38
8
DDR1_DQS_P<3>
8
38
DDR1_DQS_N<3>
8
38
DDR1_DQS_P<2>
8
38
DDR1_DQS_N<2>
8
38
PPVREF_DDR1_CA
11 38 39
PPVREF_DDR1_DQ
11 38 39
DDR1_ZQ DDR0_ZQ
38 38
T15 G16
CA0_1
U15 G17
CA1_1
U14 H17
CA2_1
V14 H18
CA3_1
T13 J16
CA4_1
T9 N16
CA5_1
U9 N17
CA6_1
U8 P17
CA7_1
V8 P18
CA8_1
T7 R16
CA9_1
U12 K17
CK_1
U11 L17
CKB_1
V13 J18
CKE_1
U13 J17
CSB_1
C12 K3
DM0_1
B10 M2
DM1_1
B16 G4
DM2_1
D7 T2
DM3_1
C15 G3
DQ0_1
D15 G2
DQ1_1
B14 H5
DQ2_1
C14 H4
DQ3_1
D14 H3
DQ4_1
E14 H2
DQ5_1
B13 J3
DQ6_1
C13 J2
DQ7_1
C9 N4
DQ8_1
D9 N3
DQ9_1
B8 P5
DQ10_1
C8 P4
DQ11_1
D8 P3
DQ12_1
E8 P2
DQ13_1
B7 R4
DQ14_1
C7 R3
DQ15_1
B18 B2
DQ16_1
C18 C2
DQ17_1
D18 D3
DQ18_1
E18 D2
DQ19_1
B17 E4
DQ20_1
D17 E3
DQ21_1
E17 E2
DQ22_1
E16 F2
DQ23_1
B6 T5
DQ24_1
B5 U5
DQ25_1
C5 U4
DQ26_1
D5 U2
DQ27_1
B4 V5
DQ28_1
C4 V4
DQ29_1
B3 V3
DQ30_1
C3 V2
DQ31_1
D13 J4
D12 K4
D10 M4
DQS1_1
C10 M3
C16 F4
DQS2_1
D16 F3
DQSB2_1
D6 T3
DQS3_1
C6 T4
DQSB3_1
U10 M17
VREFCA_1 VREFCA_2
D11 L4
VREFDQ_1 VREFDQ_2
U1300
H4G-DRAM
XXXMB
BGA
SYM 1 OF 2
OMIT_TABLE
DDR_1
U7 R17
DDR_2
DQSB0_2DQSB0_1
DQSB1_2DQSB1_1
DQSB2_2
DQSB3_2
CA0_2
CA1_2
CA2_2
CA3_2
CA4_2
CA5_2
CA6_2
CA7_2
CA8_2
CA9_2
CK_2
CKB_2
CKE_2
CSB_2
DM0_2
DM1_2
DM2_2
DM3_2
DQ0_2
DQ1_2
DQ2_2
DQ3_2
DQ4_2
DQ5_2
DQ6_2
DQ7_2
DQ8_2
DQ9_2
DQ10_2
DQ11_2
DQ12_2
DQ13_2
DQ14_2
DQ15_2
DQ16_2
DQ17_2
DQ18_2
DQ19_2
DQ20_2
DQ21_2
DQ22_2
DQ23_2
DQ24_2
DQ25_2
DQ26_2
DQ27_2
DQ28_2
DQ29_2
DQ30_2
DQ31_2
DQS0_2DQS0_1
DQS1_2
DQS2_2
DQS3_2
2_QZ1_QZ
DDR0_CA<0>
DDR0_CA<1>
DDR0_CA<2>
DDR0_CA<3>
DDR0_CA<4>
DDR0_CA<5>
DDR0_CA<6>
DDR0_CA<7>
DDR0_CA<8>
DDR0_CA<9>
DDR0_CK_P
DDR0_CK_N
DDR0_CKE<0>
DDR0_CSN<0>
DDR0_DM<1>
DDR0_DM<0>
DDR0_DM<3>
DDR0_DM<2>
DDR0_DQ<8>
DDR0_DQ<9>
DDR0_DQ<10>
DDR0_DQ<11>
DDR0_DQ<12>
DDR0_DQ<13>
DDR0_DQ<14>
DDR0_DQ<15>
DDR0_DQ<0>
DDR0_DQ<1>
DDR0_DQ<2>
DDR0_DQ<3>
DDR0_DQ<4>
DDR0_DQ<5>
DDR0_DQ<6>
DDR0_DQ<7>
DDR0_DQ<24>
DDR0_DQ<25>
DDR0_DQ<26>
DDR0_DQ<27>
DDR0_DQ<28>
DDR0_DQ<29>
DDR0_DQ<30>
DDR0_DQ<31>
DDR0_DQ<16>
DDR0_DQ<17>
DDR0_DQ<18>
DDR0_DQ<19>
DDR0_DQ<20>
DDR0_DQ<21>
DDR0_DQ<22>
DDR0_DQ<23>
DDR0_DQS_P<1>DDR1_DQS_P<1>
DDR0_DQS_N<1>DDR1_DQS_N<1>
DDR0_DQS_P<0>
DDR0_DQS_N<0>DDR1_DQS_N<0>
DDR0_DQS_P<3>
DDR0_DQS_N<3>
DDR0_DQS_P<2>
DDR0_DQS_N<2>
PPVREF_DDR0_CA
PPVREF_DDR0_DQ
38
8
8
38
8
38
8
38
8
38
8
38
8
38
8
38
38
8
8
38
38
8
8
38
38
8
8
38
38
8
8
38
38
8
8
38
38
8
8
38
8
38
8
38
8
38
38
8
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
38
8
38
8
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
38
8
8
38
8
38
8
38
8
38
11 38 39
11 38 39
=PP1V8_S2R_DDR
12 34
=PP1V2_VDDQ_DDR
11 12 34
1
C1323
56PF
5%
6.3V
2
NP0-C0G
01005
=PP1V2_S2R_DDR
11 12 34
C1314
10UF
C1320
10UF
6.3V
6.3V
20%
X5R
603
20%
X5R
603
1
C1301
10UF
20%
6.3V
2
X5R
603
=PP1V2_S2R_DDR
11 12 34
C1315
1
4.3UF
X5R-CERM
2
1
2
1
C1327
10UF
20%
6.3V
2
X5R
603
C1302
C1306
0.22UF
20%
4V
0610
C1321
4.3UF
X5R-CERM
0610
C1328
C1332
0.22UF
1UF
10%
6.3V
CERM
402
20%
6.3V
X5R
0201
0.22UF
1
2
20%
4V
1UF
10%
6.3V
CERM
402
20%
6.3V
X5R
0201
1
2
1
2
C1310
6.3V
0201
C1316
1
2
1
2
1
2
1
20%
2
X5R
1UF
10%
6.3V
CERM
402
C1324
0.22UF
C1303
1UF
6.3V
CERM
C1307
0.22UF
6.3V
0201
C1311
0.22UF
1
2
20%
6.3V
X5R
0201
C1329
1UF
6.3V
CERM
C1333
0.22UF
6.3V
0201
1
10%
2
402
1
20%
2
X5R
20%
6.3V
X5R
0201
C1317
1UF
10%
6.3V
CERM
402
1
0.22UF
2
1
10%
2
402
1
20%
2
X5R
1
2
1
2
C1325
6.3V
0201
C1304
0.01UF
C1308
0.22UF
C1312
0.22UF
C1318
0.01UF
X5R-CERM
20%
X5R
C1330
0.01UF
C1334
0.22UF
01005
1
2
01005
6.3V
6.3V
0201
6.3V
6.3V
0201
10%
X5R
20%
X5R
10%
X5R
20%
X5R
6.3V
0201
1
2
1
2
20%
X5R
10%
10V
0201
C1326
0.22UF
1
2
1
2
1
2
1
2
0.01UF
0.22UF
20%
6.3V
X5R
0201
0.01UF
C1305
6.3V
01005
C1309
56PF
6.3V
NP0-C0G
01005
C1313
6.3V
0201
C1319
56PF
NP0-C0G
01005
1
2
C1331
6.3V
01005
C1335
56PF
6.3V
NP0-C0G
01005
10%
X5R
5%
20%
X5R
5%
6.3V
C1322
0.01UF
10%
X5R
5%
1
2
1
2
1
2
1
2
1
2
1
2
01005
6.3V
D
A2
VDD1_0
B1
VDD1_1
B11
VDD1_2
F17
VDD1_3
L2
VDD1_4
M16
VDD1_5
T10
VDD1_6
U18
VDD1_7
V17
VDD1_8
V6
VDD1_9
W17
VDD1_10
U19
VDD1_11
E11
VDD2_1
E19
VDD2_2
L5
VDD2_3
M18
VDD2_4
U17
VDD2_5
T18
VDD2_6
V10
VDD2_7
V16
VDD2_8
V18
VDD2_9
W5
VDD2_10
W16
VDD2_11
W19
VDD2_12
W18
VDD2_13
V19
VDD2_14
A3
VDD2_15
T19
VDD2_16
H1
VDDQ27
M1
B12
A14
C17
C19
A10
A17
A13
E10
E15
F18
H16
K16
L16
P16
T11
T12
T14
W3
E1
U1
D4
U3
J5
K2
A8
N2
R5
P1
V7
T8
VDDQ32
VDDQ31
VDDQ
VDDQ1
VDDQ3
VDDQ6
VDDQ30
VDDQ23
VDDQ25
VDDQ26
VDDQ22
VDDQ34
VDDQ16
VDDQ17
VDDQ21
VDDQ19
VDDQ20
VDDQ24
VDDQ28
VDDQ29
VDDQ33
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDDCA9
VDDCA10
1
10%
2
X5R
U1300
H4G-DRAM
XXXMB
BGA
SYM 2 OF 2
OMIT_TABLE
VDD1
VDD2VDDQ
VDDCA
VSS
VSS0
VSS55
VSS2
VSS3
VSS4
VSS49
VSS6
VSS7
VSS9
VSS10
VSS1
VSS12
VSS13
VSS51
VSS52
VSS50
VSS18
VSS48
VSS20
VSS53
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS47
VSS32
VSS33
VSS34
VSS35
VSS36
VSS54
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
A16
A19
A4
A6
B15
C1
B9
C11
D1
D19
A1
E12
E13
G5
T16
E7
F16
B19
G18
V1
J1
K18
K5
L18
L3
M5
N18
N5
A18
R18
R2
T1
T17
U16
W2
U6
V11
V12
V15
T6
V9
W1
W4
C
B
1
R1320
240
1%
1/20W
MF
201
2
A
6 3
1
R1321
240
1%
1/20W
MF
201
2
SYNC_MASTER=N/A
PAGE TITLE
DDR 0 AND 1
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
13 OF 154
SHEET
11 OF 39
124578
SIZE
A
D
8 7 6 5 4 3
12
DDR3_CA<0>
8
38
DDR3_CA<1>
8
38
DDR3_CA<2>
38
=PP1V2_S2R_DDR
11 12 34
1
R1405
10K
1%
1/32W
MF
01005
D
C
B
2
1
R1406
10K
1%
1/32W
MF
01005
2
=PP1V2_S2R_DDR
11 12 34
1
R1451
10K
1%
1/32W
MF
01005
2
1
R1452
10K
1%
1/32W
MF
01005
2
=PP1V2_VDDQ_DDR
11 12 34
1
R1453
4.7K
1%
1/32W
MF
01005
2
1
R1454
4.7K
1%
1/32W
MF
01005
2
=PP1V2_VDDQ_DDR
11 12 34
1
R1455
4.7K
1%
1/32W
MF
01005
2
1
R1456
4.7K
1%
1/32W
MF
01005
2
1
C1460
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR2_CA
1
C1450
0.01UF
10%
6.3V
2
X5R
01005
1
C1461
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR3_CA
1
C1452
0.01UF
10%
6.3V
2
X5R
01005
1
C1462
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR2_DQ
1
C1454
0.01UF
10%
6.3V
2
X5R
01005
1
C1463
0.01UF
10%
6.3V
2
X5R
01005
PPVREF_DDR3_DQ
1
C1456
0.01UF
10%
6.3V
2
X5R
01005
12 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
12 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
12 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
12 38 39
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
8
DDR3_CA<3>
8
38
DDR3_CA<4>
8
38
DDR3_CA<5>
8
38
DDR3_CA<6>
8
38
DDR3_CA<7>
8
38
DDR3_CA<8>
8
38
DDR3_CA<9>
38
8
DDR3_CK_P
38
8
DDR3_CK_N
8
38
DDR3_CKE<0>
8
38
DDR3_CSN<0>
38
8
DDR3_DM<1>
38
8
DDR3_DM<0>
38
8
DDR3_DM<3>
8
38
DDR3_DM<2>
8
38
DDR3_DQ<8>
8
38
DDR3_DQ<9>
8
38
DDR3_DQ<10>
8
38
DDR3_DQ<11>
8
38
DDR3_DQ<12>
8
38
DDR3_DQ<13>
8
38
DDR3_DQ<14>
8
38
DDR3_DQ<15>
8
38
DDR3_DQ<0>
38
8
DDR3_DQ<1>
38
8
DDR3_DQ<2>
8
38
DDR3_DQ<3>
8
38
DDR3_DQ<4>
8
38
DDR3_DQ<5>
38
8
DDR3_DQ<6>
38
8
DDR3_DQ<7>
38
8
DDR3_DQ<24>
38
8
DDR3_DQ<25>
8
38
DDR3_DQ<26>
38
8
DDR3_DQ<27>
8
38
DDR3_DQ<28>
8
38
DDR3_DQ<29>
8
38
DDR3_DQ<30>
38
8
DDR3_DQ<31>
8
38
DDR3_DQ<16>
8
38
DDR3_DQ<17>
8
38
DDR3_DQ<18>
38
8
DDR3_DQ<19>
8
38
DDR3_DQ<20>
8
38
DDR3_DQ<21>
38
8
DDR3_DQ<22>
8
38
DDR3_DQ<23>
38
8
DDR3_DQS_P<1> DDR2_DQS_P<1>
8
38
DDR3_DQS_N<1> DDR2_DQS_N<1>
8
38
DDR3_DQS_P<0>
8
38
DDR3_DQS_N<0> DDR2_DQS_N<0>
8
38
DDR3_DQS_P<3>
8
38
DDR3_DQS_N<3>
8
38
DDR3_DQS_P<2>
8
38
DDR3_DQS_N<2>
8
38
DDR3_ZQ DDR2_ZQ
38 38
1
R1420
240
1%
1/20W
MF
201
2
T15 G16
CA0_1
U15 G17
CA1_1
U14 H17
CA2_1
V14 H18
CA3_1
T13 J16
CA4_1
T9 N16
CA5_1
U9 N17
CA6_1
U8 P17
CA7_1
V8 P18
CA8_1
T7 R16
CA9_1
U12 K17
CK_1
U11 L17
CKB_1
V13 J18
CKE_1
U13 J17
CSB_1
C12 K3
DM0_1
B10 M2
DM1_1
B16 G4
DM2_1
D7 T2
DM3_1
C15 G3
DQ0_1
D15 G2
DQ1_1
B14 H5
DQ2_1
C14 H4
DQ3_1
D14 H3
DQ4_1
E14 H2
DQ5_1
B13 J3
DQ6_1
C13 J2
DQ7_1
C9 N4
DQ8_1
D9 N3
DQ9_1
B8 P5
DQ10_1
C8 P4
DQ11_1
D8 P3
DQ12_1
E8 P2
DQ13_1
B7 R4
DQ14_1
C7 R3
DQ15_1
B18 B2
DQ16_1
C18 C2
DQ17_1
D18 D3
DQ18_1
E18 D2
DQ19_1
B17 E4
DQ20_1
D17 E3
DQ21_1
E17 E2
DQ22_1
E16 F2
DQ23_1
B6 T5
DQ24_1
B5 U5
DQ25_1
C5 U4
DQ26_1
D5 U2
DQ27_1
B4 V5
DQ28_1
C4 V4
DQ29_1
B3 V3
DQ30_1
C3 V2
DQ31_1
D13 J4
D12 K4
D10 M4
DQS1_1
C10 M3
C16 F4
DQS2_1
D16 F3
DQSB2_1
D6 T3
DQS3_1
C6 T4
DQSB3_1
U10 M17
VREFCA_1 VREFCA_2
D11 L4
VREFDQ_1 VREFDQ_2
U1400
H4G-DRAM
XXXMB
BGA
SYM 1 OF 2
OMIT_TABLE
DDR_1
U7 R17
DDR_2
DQSB0_2DQSB0_1
DQSB1_2DQSB1_1
DQSB2_2
DQSB3_2
CA0_2
CA1_2
CA2_2
CA3_2
CA4_2
CA5_2
CA6_2
CA7_2
CA8_2
CA9_2
CK_2
CKB_2
CKE_2
CSB_2
DM0_2
DM1_2
DM2_2
DM3_2
DQ0_2
DQ1_2
DQ2_2
DQ3_2
DQ4_2
DQ5_2
DQ6_2
DQ7_2
DQ8_2
DQ9_2
DQ10_2
DQ11_2
DQ12_2
DQ13_2
DQ14_2
DQ15_2
DQ16_2
DQ17_2
DQ18_2
DQ19_2
DQ20_2
DQ21_2
DQ22_2
DQ23_2
DQ24_2
DQ25_2
DQ26_2
DQ27_2
DQ28_2
DQ29_2
DQ30_2
DQ31_2
DQS0_2DQS0_1
DQS1_2
DQS2_2
DQS3_2
2_QZ1_QZ
DDR2_CA<0>
DDR2_CA<1>
DDR2_CA<2>
DDR2_CA<3>
DDR2_CA<4>
DDR2_CA<5>
DDR2_CA<6>
DDR2_CA<7>
DDR2_CA<8>
DDR2_CA<9>
DDR2_CK_P
DDR2_CK_N
DDR2_CKE<0>
DDR2_CSN<0>
DDR2_DM<1>
DDR2_DM<0>
DDR2_DM<3>
DDR2_DM<2>
DDR2_DQ<8>
DDR2_DQ<9>
DDR2_DQ<10>
DDR2_DQ<11>
DDR2_DQ<12>
DDR2_DQ<13>
DDR2_DQ<14>
DDR2_DQ<15>
DDR2_DQ<0>
DDR2_DQ<1>
DDR2_DQ<2>
DDR2_DQ<3>
DDR2_DQ<4>
DDR2_DQ<5>
DDR2_DQ<6>
DDR2_DQ<7>
DDR2_DQ<24>
DDR2_DQ<25>
DDR2_DQ<26>
DDR2_DQ<27>
DDR2_DQ<28>
DDR2_DQ<29>
DDR2_DQ<30>
DDR2_DQ<31>
DDR2_DQ<16>
DDR2_DQ<17>
DDR2_DQ<18>
DDR2_DQ<19>
DDR2_DQ<20>
DDR2_DQ<21>
DDR2_DQ<22>
DDR2_DQ<23>
DDR2_DQS_P<0>
DDR2_DQS_P<3>
DDR2_DQS_N<3>
DDR2_DQS_P<2>
DDR2_DQS_N<2>
PPVREF_DDR2_CAPPVREF_DDR3_CA
PPVREF_DDR2_DQPPVREF_DDR3_DQ
8
38
8
38
38
8
8
38
8
38
8
38
8
38
8
38
8
38
38
8
38
8
8
38
8
38
38
8
38
8
38
8
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
38
8
38
8
8
38
8
38
8
38
38
8
38
8
38
8
38
8
8
38
38
8
8
38
8
38
8
38
38
8
8
38
8
38
8
38
38
8
8
38
8
38
38
8
8
38
38
8
8
38
8
38
8
38
8
38
8
38
8
38
8
38
8
38
12 38 39 12 38 39
12 38 39 12 38 39
1
R1421
240
1%
1/20W
MF
201
2
=PP1V8_S2R_DDR
11 34
=PP1V2_VDDQ_DDR
11 12 34
1
C1423
56PF
5%
6.3V
2
NP0-C0G
01005
=PP1V2_S2R_DDR
11 12 34
C1401
10UF
6.3V
=PP1V2_S2R_DDR
11 12 34
1
C1414
10UF
20%
6.3V
2
X5R
603
1
C1420
10UF
20%
6.3V
2
X5R
603
C1427
10UF
20%
X5R
603
C1415
X5R-CERM
20%
6.3V
X5R
603
1
2
4.3UF
0610
1
2
C1402
C1406
0.22UF
1
20%
4V
2
C1421
4.3UF
X5R-CERM
0610
0.22UF
1UF
10%
6.3V
CERM
402
20%
6.3V
X5R
0201
C1410
0.22UF
1
20%
4V
2
C1428
1UF
6.3V
CERM
C1432
6.3V
0201
1
2
1
2
20%
6.3V
X5R
0201
C1416
1UF
6.3V
CERM
1
10%
2
402
1
20%
2
X5R
0.22UF
1
2
1
10%
2
402
C1424
0.22UF
C1403
1UF
6.3V
CERM
C1407
6.3V
0201
C1411
0.22UF
C1417
20%
6.3V
X5R
0201
C1429
C1433
0.22UF
10%
402
20%
X5R
1UF
1
2
1UF
6.3V
CERM
6.3V
0201
6.3V
0201
6.3V
CERM
10%
402
20%
X5R
1
2
1
2
20%
X5R
10%
402
1
2
1
2
C1425
0.22UF
6.3V
0201
1
2
1
2
C1404
0.01UF
6.3V
01005
C1408
0.22UF
6.3V
0201
C1412
0.22UF
C1418
0.01UF
X5R-CERM
1
20%
2
X5R
C1430
0.01UF
C1434
0.22UF
10%
X5R
20%
X5R
6.3V
0201
0201
01005
20%
X5R
10%
10V
0.22UF
10%
6.3V
X5R
20%
6.3V
X5R
0201
1
2
1
2
1
2
1
2
C1426
1
2
1
2
C1405
0.01UF
C1409
56PF
NP0-C0G
C1413
0.22UF
C1419
56PF
NP0-C0G
20%
6.3V
X5R
0201
0.01UF
10%
6.3V
X5R
01005
5%
6.3V
01005
20%
6.3V
X5R
0201
5%
6.3V
01005
1
2
C1431
6.3V
01005
C1435
56PF
6.3V
NP0-C0G
01005
1
2
1
2
1
2
1
2
C1422
0.01UF
10%
X5R
5%
1
2
1
2
6.3V
01005
A2
VDD1_0
B1
VDD1_1
B11
VDD1_2
F17
VDD1_3
L2
VDD1_4
M16
VDD1_5
T10
VDD1_6
U18
VDD1_7
V17
VDD1_8
V6
VDD1_9
W17
VDD1_10
U19
VDD1_11
E11
VDD2_1
E19
VDD2_2
L5
VDD2_3
M18
VDD2_4
U17
VDD2_5
T18
VDD2_6
V10
VDD2_7
V16
VDD2_8
V18
VDD2_9
W5
VDD2_10
W16
VDD2_11
W19
VDD2_12
W18
VDD2_13
V19
VDD2_14
A3
VDD2_15
T19
VDD2_16
H1
VDDQ27
M1
VDDQ32
W3
VDDQ31
E1
B12
A14
C17
C19
A10
A17
A13
E10
E15
F18
H16
K16
L16
P16
T11
T12
T14
U1
D4
U3
J5
K2
A8
N2
R5
P1
V7
T8
VDDQ
VDDQ1
VDDQ3
VDDQ6
VDDQ30
VDDQ23
VDDQ25
VDDQ26
VDDQ22
VDDQ34
VDDQ16
VDDQ17
VDDQ21
VDDQ19
VDDQ20
VDDQ24
VDDQ28
VDDQ29
VDDQ33
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDCA6
VDDCA7
VDDCA8
VDDCA9
VDDCA10
1
10%
2
X5R
U1400
H4G-DRAM
XXXMB
BGA
SYM 2 OF 2
OMIT_TABLE
VDD1
VDD2VDDQ
VDDCA
VSS
VSS0
VSS55
VSS2
VSS3
VSS4
VSS49
VSS6
VSS7
VSS9
VSS10
VSS1
VSS12
VSS13
VSS51
VSS52
VSS50
VSS18
VSS48
VSS20
VSS53
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS47
VSS32
VSS33
VSS34
VSS35
VSS36
VSS54
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
A16
A19
A4
A6
B15
C1
B9
C11
D1
D19
A1
E12
E13
G5
T16
E7
F16
B19
G18
V1
J1
K18
K5
L18
L3
M5
N18
N5
A18
R18
R2
T1
T17
U16
W2
U6
V11
V12
V15
T6
V9
W1
W4
D
C
B
A
6 3
SYNC_MASTER=N/A
PAGE TITLE
DDR 2 AND 3
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-9385
REVISION
A.0.0
BRANCH
PAGE
14 OF 154
SHEET
12 OF 39
124578
SIZE
A
D
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