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iPad 3
Schematic
51 pgs1.97 Mb0
Schematic
48 pgs1.57 Mb0
Schematic
2 pgs187.47 Kb0
Schematics
2 pgs115.04 Kb0
User Manual [cz]
183 pgs22.56 Mb0
User Manual [ru]
153 pgs17.91 Mb0

Apple ipad3 Schematic

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820-2996-11-BOT MLB
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L4306
L4304
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U5600
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C7525
C7523
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L2200
R4312
R4201
R4205
L5501
L5500
R5513
R5512
R5511
U5500
C2233
L2210
R4204
C2220
C4202
C4201
R4203
R4202
U4200
R5613
R5612
U5502 U5601
C2253
C2270
C4200
L5601
C2249
C2247
C2248
C2246
R2284
R2286
R2285
R2287
C2203
C2204
R2250
R2204
R2210
C2240
R2203
C2241
C5500
C2202
R5602
R5600
R4210
C4216
C4212
R4211
R5621
C5501
R5603
R5601
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U5501U5503
R2242
C2245
C2243
C2244
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L2212 L2222 L2232 L2202
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J6000
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DRAWING TITLE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
SHEET
1245678
A
D
8
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820-2996-11-TOP MLB
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C8234
C8233
C8232
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C1705
C1701
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U1410
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J5400 J5401 J3011J3010
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C3002
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C1720
C1762
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C1721
C1726
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C1731
C1733
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C1708 C1734
C1729 C1728
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R1095 C1095 R0709
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C1717
C1732
C1722
C1711
C1713
C1712
C1725
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R5796
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C1704
C0650
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C1608
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C1627
C1607
C1610
C1623
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C1605
C1601
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C1633
C1620
C1631
C1626 R1653 C1662
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C1606
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C1632
C1622
C1604 C1625 C1612 C1609 C1613
C1616 C1617
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R1054
R1053
C1057
R1021
C1101
C1123
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R1214
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L8107
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L1
C2
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C55
C70C58
C59
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R8280
C49
C57
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R1
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FL4
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J5900
LED9000
R9002
C3714
J3700
C3704
L3700
C3700
J2
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3
DRAWING TITLE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
SHEET
1245678
A
D
8
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
6543
21
CK
REV ECN
10
0001231154
DESCRIPTION OF REVISION
ENGINEERING RELEASED
APPD
DATE
2011-09-06
J2 MLB - DVT OK2FAB
LAST_MODIFIED=Tue Sep 6 17:35:11 2011
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B
A
DRAWING
DRAWING MLB
Schematic / PCB #’s
10
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12 NAND
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CONTENTS
1
Table of Contents
BLOCK DIAGRAM: SYSTEM
2
4
BOM TABLES
AP: MAIN
6
AP: I/Os
7
8
AP: NAND
AP: TV,DP,MIPI
9
10
AP: DDR
11
AP: POWER
12
AP: MISC & ALIASES
13
AP: VIDEO BUFFER,BB USB MUXES
14
16
DDR 0 AND 1
17
DDR 2 AND 3
21
MLB ALIASES/CONNECTIONS
22
VIDEO: EDP CONNECTOR
GRAPE: GROUNDHOG,CONN,BOOST
30
31
GRAPE: Z1, Z2
36
AUDIO: L63B CODEC
37
AUDIO: SPEAKER AMP
38
AUDIO: HEADPHONE OUT
42
AUDIO: DETECT/MIC BIAS
AUDIO: HP/MIC FILTERS
43
54
CONNECTOR: SENSOR
SENSOR PANEL FILTERS 1
55
56
SENSOR PANEL FILTERS 2
IO FLEX: DOCK COMPONENTS
57
58
DISPLAY PORT MISC
IO FLEX: B2B CONNECTOR
59
60
CONNECTOR: X26
WLAN BB & POWER
61
SYNC MASTER
MIKE
J2DEV
MIKE
MIKE
JOE N/A
MIKE
JOE
MIKE
MIKE
ALEX
CHOPIN
MIKE
MIKE
MIKE
ALEX
JOE
RAMSIN
RAMSIN
KAVITHA 02/03/2011
KAVITHA 02/03/2011
KAVITHA 02/03/2011
KAVITHA 02/03/2011
KAVITHA 02/03/2011
MARK
MARK
MARK
JOE
JOE
JOE
JOE
X26_WIFI_MIKE_BT 09/01/2011
DATE
NA
N/A
N/A
N/A
N/A
01/13/2011
N/A
N/A
N/A
12/10/2010
N/A
06/21/2010
06/21/2010
09/30/2010
01/19/2011
12/17/2010
12/17/2010
01/11/2011
01/11/2011
01/11/2011
01/19/2011
01/19/2011
01/19/2011
01/19/2011
PDF
TABLE_TABLEOFCONTENTS_HEAD
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CSA
62
63
75
80
81
82
83
90
93
150
151
152
153
154
155
156
157
CONTENTS
WLAN 2.4GHZ AND ANT
WLAN 5GHZ AND TEST POINTS
POWER: BATTERY CONNECTOR
POWER ALIASES
POWER: AMELIA PMU
POWER: AMELIA PMU
POWER: AMELIA VSS
DEBUG AND MISC
FCT/ICT TEST/BRACKETS
CONSTRAINTS: MLB RULES
CONSTRAINTS: LOW SPEED BUS
CONSTRAINTS: DISPLAY/AUDIO
CONSTRAINTS: DDR/FMI
CONSTRAINTS: POWER / GND
CONSTRAINTS: DEBUG
FUNC TEST POINTS
FUNC TEST POINTS
3
SYNC MASTER
X26_WIFI_MIKE_BT
X26_WIFI_MIKE_BT
MADHAVI
MADHAVI
MADHAVI
MLB
MADHAVI
ALEX
ALEX
MIKE
MIKE
MIKE
MIKE
MIKE
MIKE
MIKE
MIKE
DATE
09/01/2011
09/01/2011
01/13/2011
01/13/2011
01/13/2011
01/14/2011
01/13/2011
10/04/2010
10/04/2010
01/21/2011
01/21/2011
01/21/2011
01/21/2011
01/21/2011
01/21/2011
01/21/2011
01/21/2011
SYNC_MASTER=MIKE
DRAWING TITLE
SCH,J2,MLB
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
1 OF 157
SHEET
1 OF 48
1245678
SYNC_DATE=NA
87 6 5 4 3
12
ISP_I2C1
Z2
CSA 31
SPI1
H4G
MIPI1C
ISP_I2C0
MIPI0C
D
GROUNDHOG
Z1
CSA 31CSA 30
LPDDR2
1 GBYTE
4X32-BIT
400MHZ/800MB/S
DISPLAY/
TOUCH PANEL
EDP
DUAL-CORE ARM
CORTEX-A9 W/ SMP
950 MHZ
GPU
QUAD-CORE IMG
SGX543-MP2
AUDIO
AE2
ARM A5 CPU
HSIC1_1
UART3 UART6
HSIC0_1
UART1
FF CAMERA
VGA FLEX
REAR CAMERA
VA5/8 FLEX
MIMO
WIFI/BT
BT_I2S
CSA 61-64
X26
CELLULAR/GPS
HSIC1 USART
D
WIFI ANT 1
WIFI/BT ANT 2
PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT
RESOLUTION: 2048X1536
C
BACKLIGHT
IPCSPI2
CSA 60
GPS ANT
C
PMU
AMELIA
UART5
BATTERY
USB2.0
UART0
30-PIN
DOCK
DISPLAYPORT
CSA 75
VIDEO DAC
CSA 81,82
I2C 8’H78
DWI I2C0
B
AMP
B
AUDIO CODEC
L63B
LINEOUT
CSA 36
AMP
AMP
MIC
MUX US/CHINA
I2C 8’H76
CSA 57
SPEAKER
EXT MIC
HALL EFF
BUTTON FLEX
PROX SENSOR
I2C 8’H58
COMPASS
I2C 8’H1C
SENSOR PANELSENSOR PANEL
I2C1
I2C2
FMI0
FMI1
FMI2
FMI3
I2S2
I2S0
I2S3
VSP
ASP
XSP
I2C 8’H94
A
GYRO
SENSOR PANEL SENSOR PANEL
ACCELEROMETER
ALS
I2C 8’H72I2C 8’H32I2C 8’HD0
VGA FLEX
NAND FLASHNAND FLASH
PPN1.0 PPN1.0
CSA 14CSA 14
SYNC_MASTER=J2DEV
PAGE TITLE
BLOCK DIAGRAM: SYSTEM
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6 3
SYNC_DATE=N/A
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
2 OF 157
SHEET
2 OF 48
124578
A
D
87 6 5 4 3
12
SCH AND BOARD P/N
PART#
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
D
ALL AVAIL BOM OPTIONS
COMMON ALTERNATE
16GB_PROD 32GB_PROD 64GB_PROD 128GB_PROD
DEVELOPMENT_JTAG DEVELOPMENT_JTAG_TAP JTAG_DAP
SPEAKER INTERNAL_MIC
NAND_IO_1V8 NAND_IO-3V3
SNOTE DEV MLB J2
BOM GROUP
BASIC
AUDIO
BOM OPTIONS
COMMON,ALTERNATE
SPEAKER,INTERNAL_MIC
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C
BARCODE LABEL/EEEE CODES
PART#
825-7691
825-7691
825-7691
825-7691
825-7691
825-7691
825-7691
825-7691
825-7691
825-7691
DESCRIPTION
QTY
EEEE FOR 639-2352 (J1 16G)
1
1
EEEE FOR 639-2058 (J1 32G)
EEEE FOR 639-2059 (J1 64G)
1
EEEE FOR 639-2353 (J2 16G)
1
EEEE FOR 639-1572 (J2 32G)
1
EEEE FOR 639-1871 (J2 64G)
1
1
EEEE FOR 639-1870 (J2 128G)
EEEE FOR 639-2844 (J2A 16G)
1
1
EEEE FOR 639-2826 (J2A 32G)
1
EEEE FOR 639-2827 (J2A 64G)
REFERENCE DESIGNATOR(S)
EEEE_DNKT
EEEE_DM2N
EEEE_DM2P
EEEE_DNKV
EEEE_DHWV
EEEE_DKQL
EEEE_DKQK
EEEE_DRJQ
EEEE_DRF6
EEEE_DRF5
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
EEEE_J1_16G
EEEE_J1_32G
EEEE_J1_64G
EEEE_J2_16G
EEEE_J2_32G
EEEE_J2_64G
EEEE_J2_128G
EEEE_J2A_16G
EEEE_J2A_32G
EEEE_J2A_64G
MECHANICAL PARTS
B
PART#
806-2105
806-1857
806-2349
806-1860
806-1865
806-2352
DESCRIPTION
QTY
FENCE,NAND,TOP,MLB,J2
1
FENCE,LARGE,TOP,MLB,J2
1
1
FENCE,SMALLER,TOP,MLB,J2
FENCE,1,BTM,MLB,J2
1
FENCE,2,BTM,MLB,J2
1
FENCE,SMALLER,BTM,MLB,J2
1
REFERENCE DESIGNATOR(S)
PD_FENCE_NAND
PD_FENCE_LARGE
PD_FENCE_SMALL
PD_FENCE_BTM1
PD_FENCE_BTM2
PD_FENCE_BTM3
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
820-2996
085-3058
SOC
PART#
343S0533 CRITICAL
PMU
PART#
343S0561
SDRAM
PART#
333S0579
PART NUMBER
333S0580
NAND
16GB FLASH CONFIGURATIONS
PART#
335S0781 CRITICAL
PART NUMBER
335S0804 335S0781
32GB FLASH CONFIGURATIONS
PART#
335S0781 CRITICAL
PART NUMBER
64GB FLASH CONFIGURATIONS
PART#
335S0782
PART NUMBER
335S0805 335S0782
DESCRIPTION
QTY
PCBF,MLB,J2
DEV BOM,MLB,J2
DESCRIPTION
QTY
IC,SOC,H4G,FCBGA1225
1 ?
DESCRIPTION
QTY
IC,PMU,AMELIA,D1974AB
1
DESCRIPTION
QTY
SDRAM,LPDDR2,512MB,SAMSUNG 46NM
2
ALTERNATE FOR PART NUMBER
333S0579
333S0579333S0581
DESCRIPTION
QTY
HYNIX 26NM PPN1.0 16GB
1
ALTERNATE FOR PART NUMBER
DESCRIPTION
QTY
HYNIX 26NM PPN1.0 16GB
2
ALTERNATE FOR PART NUMBER
335S0781335S0804
DESCRIPTION
QTY
2
HYNIX 26NM PPN1.0 32GB
ALTERNATE FOR PART NUMBER
BOM OPTION
BOM OPTION
16GB_PROD
BOM OPTION
32GB_PROD
BOM OPTION
64GB_PROD
REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S)
U1600,U1700
REF DES
COMMENTS:
U1600,U1700
U1600,U1700
U1400,U1410
U1400,U1410
LPDDR2,HYNIX 44NM
LPDDR2,ELPIDA 45NM
REFERENCE DESIGNATOR(S)
REF DES
COMMENTS:
U1400
TOSHIBA 24NM PPN1.0
REFERENCE DESIGNATOR(S)
U1400,U1410
REF DES
COMMENTS:
TOSHIBA 24NM PPN1.0
REFERENCE DESIGNATOR(S)
U1400,U1410
REF DES
COMMENTS:
TOSHIBA 24NM PPN1.0
SCH1SCH,MLB,J2051-8773
U0600
U8100
U1400
CRITICAL BOM OPTION
CRITICAL
CRITICAL
CRITICAL BOM OPTION
CRITICAL BOM OPTION
CRITICAL
CRITICAL BOM OPTION
CRITICAL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CRITICAL BOM OPTION
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CRITICAL BOM OPTION
CRITICAL
TABLE_ALT_HEAD
TABLE_ALT_ITEM
?1
?1
?1
?
?
16GB_PROD
32GB_PROD
64GB_PROD
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
D
C
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
B
TABLE_5_HEAD
TABLE_5_ITEM
128GB FLASH CONFIGURATIONS
PART#
PART NUMBER
DESCRIPTION
QTY
2
HYNIX 26NM PPN1.0 64GB
ALTERNATE FOR PART NUMBER
BOM OPTION
128GB_PROD335S0806 335S0814
REFERENCE DESIGNATOR(S)
U1400,U1410
REF DES
COMMENTS:
U1400,U1410
TOSHIBA 24NM PPN1.0
CRITICAL BOM OPTION
CRITICAL335S0814
TABLE_ALT_HEAD
TABLE_ALT_ITEM
128GB_PROD
A
6 3
TABLE_5_HEAD
TABLE_5_ITEM
A
D
SYNC_MASTER=MIKE
PAGE TITLE
BOM TABLES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SYNC_DATE=N/A
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
4 OF 157
SHEET
3 OF 48
124578
87 6 5 4 3
12
R0601
A1
A2 A5
A8
A11 A14
A17
A34 A35
D
C
B
A
AA2
AA8 AA10
AA12 AA14
AA16
AA18 AA20
AA22
AA24 AA26
AA35
AB1
AB4
AB8
AB9
AB11
AB13 AB15
AB17
AB19 AB21
AB23
AB25 AB27
AC3
AC8
AC10
AC18 AC20
AC22
AC24 AC28
AC32
AC34
AD2
VSS VSS
AD8
AD9
AD11
AD19 AD21
AD23
AD25 AD27
AD29
AE1
AE8
AE9 AE10
AE18
AE20 AE22
AE24
AE26
AF3
AF8
AF9 AF27
AF30 AF32
AF34
AG2
AG8
AG9
AH1
AH8
AH9
AH10 AH11
AH12 AH17
AH22
AH25 AH26
AJ5
AJ13 AJ20
AJ29
AJ32
U0600
H4G
FCBGA
OMIT
(11 OF 12)
AJ34
AK2 AL1
AM3
AM8 AM19
AM22
AM25 AM28
AM32
AM34 AN7
AN10 AN13
AN16
AP1 AP2
AP6
AP9 AP12
AP15
AP18 AP22
AP25 AP28
AP31
AP34 AP35
AR1
AR2 AR5
AR8
AR11 AR14
AR17 AR19
AR34
AR35 B1
B2
B4 B9
B12
B15 B34
B35 C7
C10
C13 C16
C30
C31 C32
C33
D3 D5
D8 D11
D14
D17 D30
D33
E1 E10
E21
E22 E24
E25 E26
E27
E28 E29
E30
E33 F2
F5
F16 F17
F21 F22
F24
F33 G3
G17
G18 G19
G20
G21
=PP1V1_PLL_H4
4
35
=PP1V1_HSIC_H4
35
=PP1V2_HSIC_H4
35
JTAGSEL
0 - PARALLEL 1 - DAISY CHAIN (FOR USE WITH 5-WIRE JTAG)
PER RADAR #6755237
=PP1V8_H4
4 7
10 35
4
35
27 30 37 45
IN
=PP3V3_USB_H4
RST_AP_L
3.16V
10 35
R0620
100K
12
5%
1/32W
R0621
100K
12
5%
1/32W 01005
R0622
100K
12
5%
1/32W
1
R0640
10K
1% 1/32W MF 01005
2
1
R0641
100K
1% 1/32W MF 01005
2
1.75V
1
R0642
42.2K
1%
1/32W
MF
01005
2
1
1%
MF
2
AP_DDR1_CKEIN_1V2
1.16V
R0643
82.5K
1/32W
01005
1
C0632
0.01UF
10%
2
X5R 01005
=PP1V8_H4
4 7
01005
01005
1
C0640
1000PF
10% 16V
2
X7R 201
DEVELOPMENT_JTAG_TAP
0.00
12
1/32W
01005
R0602
0.00
12
1/32W
01005
R0603
0.00
12
1/32W
01005
R0604
0.00
12
1/32W
01005
1
C0633
0.01UF
10%
2
X5R 01005
BB
30 42
BI
30 42
BI
WLAN
15 40
BI
42
15 40 42
BI
R0608
100K
12
5%
1/32WMF01005
10 42 45
IN
10 42
OUT
10 42
27 42
27 42
10
10
10
10
0%
MF
0%
MF
0%
MF
0%
MF
1
C0634
0.01UF
10%
2
X5R 01005
HSIC0_BB_DATA1 HSIC0_BB_STB1
42 46
42 46
HSIC1_WLAN_DATA1
HSIC1_WLAN_STB1
42 46
42 46
JTAG_AP_SEL
10
46
JTAG_AP_TRST_L JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TMS JTAG_AP_TCK
AP_TESTMODE
IN
AP_TST_STPCLK
OUT
OUT
IN
TP_AP_TST_CLKOUT
AP_FAST_SCAN_CLK
AP_HOLD_RESET
45
RST_AP_1V8_L
1
2
NC_HSIC0_DATA2
NC_HSIC0_STB2
NC_HSIC1_DATA2
NC_HSIC1_STB2
NC_JTAG_AP_TRTCK
1
C0630
0.01UF
10%
2
X5R 01005
C0635
0.01UF
10%
K35
L35 K33
L33 H35
J35
H33 J33
AK29 AM27
AR27
AP30 AN30
AJ27 AN29
AH27
M31
AR28
AR29
AR33
AN28
AR30
AR32
AK10
AF6
W6
L6 F9
1
C0600
0.01UF
10%
2
X5R 01005
1
C0601
0.01UF
10%
2
X5R 01005
1
C0602
0.01UF
10%
2
X5R 01005
1
C0607
0.01UF
10%
2
X5R 01005
1
C0631
0.01UF
10%
2
X5R
01005
HSIC0_DATA1 HSIC0_STB1
HSIC0_DATA2
HSIC0_STB2 HSIC1_DATA1
HSIC1_STB1 HSIC1_DATA2
HSIC1_STB2
JTAG_SEL
JTAG_TRTCK
JTAG_TRST* JTAG_TDO
JTAG_TDI
JTAG_TMS JTAG_TCK
TESTMODE
FUSE1_FSRC
TST_STPCLK
TST_CLKOUT
FAST_SCAN_CLK
HOLD_RESET
RESET*
CFSB0
CFSB1
DDR0_CKEIN
DDR1_CKEIN
DDR2_CKEIN DDR3_CKEIN
HSIC0_VSS122
HSIC0_VSS121
P28
P30
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
P29
HSIC0_VDD121
34MA
HSIC1_VSS121
HSIC0_DVSS
N30
K29
45
PP1V1_PL3_F
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
45
PP1V1_PL2_F
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
PP1V1_PL1_F
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
45
PP1V1_PL0_F
N31
P31
K30
J30
HSIC0_DVDD
7MA
HSIC1_VDD122
HSIC1_VDD121
HSIC0_VDD122
34MA
HSIC1_VSS122
PLL1_AVSS11
PLL0_AVSS11
HSIC1_DVSS
H31
J29
V32
U32
T32
H32
V33
U33
HSIC1_DVDD
PLL0_AVDD11
7MA
U0600
PLL2_AVSS11
PLL5_AVSS11
PLL4_AVSS11
PLL3_AVSS11
R32
P32
N32
T33
R33
P33
PLL4_AVDD11
PLL3_AVDD11
PLL2_AVDD11
PLL1_AVDD11
2.5MA EACH
OMIT
H4G
FCBGA
(1 OF 12)
H24
H25
H26
45
PP1V1_PL4_F
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
45
PP1V1_PL5_F
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
45 45
PP1V1_MIPID_PLL_F
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
F27
F30
N33
PLL5_AVDD11
MIPI1D_VDD11_PLL
MIPI0D_VDD11_PLL
14MA
MIPI_VSS
H27
H28
H29
U29
10MA
USB_DVSS
U28
L31
L30
R28
USB_DVDD
28MA
USB_ANALOGTEST0 USB_ANALOGTEST1
USB_VSSA0
T29
L28
45
PP1V1_PLL_USB_F
M33
M28
USB_VDD330
PLL_USB_AVDD11
2.5MA
USB_DP0
USB_DM0 USB_DP1
USB_DM1
USB11_DP0
USB11_DM0
USB11_DP1 USB11_DM1
USB_VBUS0
USB_VBUS1
USB_ID0
USB_ID1
USB_BRICKID0 USB_BRICKID1
USB_REXT0 USB_REXT1
USB_VSSAC
R29
L29
1
C0603
0.01UF
10%
2
X5R 01005
1
C0604
0.01UF
10%
2
X5R 01005
1
C0620
56PF
5%
2
NP0-C0G 01005
1
C0608
0.01UF
10%
2
X5R 01005
VOLTAGE=1.1V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
AP29
WDOG
W35
XI0
Y35
XO0
U35
T35
N34 M34
T34 R34
N35
P35
R30 J28
T30 J32
T31 K32
T28
K31
NC_USB_BRICKID1
R31 K28
PLL_USB_AVSS11
M32
1
C0621
0.01UF
10%
6.3V 6.3V
2
X5R 01005
1
C0609
0.01UF
10%
2
X5R 01005
1
C0612
0.01UF
10%
2
X5R 01005
AP_WDOG
42
XTAL_24M_I
42
XTAL_24M_O
USB_DK_D0_P
USB_DK_D0_N
NC_USB_D1_P
NC_USB_D1_N
USB11_MUX_D0_P
USB11_MUX_D0_N
NC_USB11_D1_P
NC_USB11_D1_N
NC_USB_ANALOGTEST0
NC_USB_ANALOGTEST1
USB_AP_VBUS0 USB_AP_VBUS1
NC_USB_ID0
NC_USB_ID1
USB_BRICKID
USB_REXT0 USB_REXT1
6 3
1
C0615
0.01UF
10%
2
X5R 01005
MLB
R0652
0.00
12
0%
1/32W
MF
42 46
42 46
42 46
42 46
46
46
10
IN
46
46
46
1
R0612
44.2
1% 1/20W MF 201
2
R0605
0.00
12
0%
1/32W
MF
01005
R0606
0.00
12
0%
1/32W
MF
01005
80-OHM-0.2A-0.4-OHM
1
C0622
1UF
10%
2
1
C0614
1UF
10%
2
R0607
0.00
12
0%
1/32W
MF
01005
RST_PMU_IN
01005
R0650
1.00M
1% MF
010051/32W
12
27 42
27 42
11 42
11 42
1
2
GDZ-0201
37
OUT
1
R0613
44.2
1% 1/20W MF 201
2
4
=PP1V1_PLL_H4
35
FL0600
12
=PP1V1_USB_H4
=PP3V3_USB_H4
=PP1V1_USB_H4
37 45
OUT
R0651
22
12
5%
1/32W
MF
01005
PPVBUS_USB
R0609
100K
5% 1/32W MF 01005
2
GDZT2R5.1B
DZ0600
1
SYNC_MASTER=MIKE
PAGE TITLE
36 45
4
35
4
35
4
35
24.000MHZ-16PF-60PPM
42
24M_O
1
C0650
22PF
5% 16V
2
=PP1V1_MIPI_PLL_H4
AP: MAIN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
CRITICAL
Y0602
13
24
35
1
C0651
22PF
5% 16V
2
DRAWING NUMBER
051-8773
REVISION
BRANCH
SHEET
124578
SYNC_DATE=N/A
10.0.0
6 OF 157
4 OF 48
D
C
B
A
D
87 6 5 4 3
12
U0600
OMIT
H4G
FCBGA
I2C0_SCL I2C0_SDA
I2C1_SCL I2C1_SDA
I2C2_SCL
I2C2_SDA
SWI_DATA
DWI_CLK
DWI_DI
DWI_DO
SDIO0_CLK
SDIO0_CMD
SDIO0_DATA0 SDIO0_DATA1
SDIO0_DATA2
SDIO0_DATA3
SPI3_MISO
SPI3_MOSI SPI3_SCLK
SPI3_SSIN
SPI2_MISO
SPI2_MOSI
SPI2_SCLK SPI2_SSIN
THERM_TEST_OUT
THERM_RES_EXT
VDDA18_TS
VSSA18_TS
AJ23
AK23
AN24 AR25
AH21 AK21
AC13
AN25
AM24 AG23
AL27
NC_SDIO0_WL_CLK
AR31
NC_SDIO0_WL_CMD
AK28
NC_SDIO0_WL_DATA<0>
AL28
NC_SDIO0_WL_DATA<1>
AM29
NC_SDIO0_WL_DATA<2>
AM30
NC_SDIO0_WL_DATA<3>
AL30
AL29
AN32 AP33
AF23 AL23
AH23
AM23
AJ16
TP_THERM_TEST_OUT
AK16
THERM_RES_EXT AF16 AG16
I2C0_SCL_1V8 I2C0_SDA_1V8
I2C1_SCL_1V8 I2C1_SDA_1V8
I2C2_SCL_3V0 I2C2_SDA_3V0
NC_SWI_AP
DWI_AP_CLK DWI_AP_DI
DWI_AP_DO
NC_SPI3_MISO
NC_SPI3_MOSI
NC_SPI3_SCLK
NC_SPI3_CS_L
SPI2_IPC_MISO
SPI2_IPC_MOSI
SPI2_IPC_SCLK
46
46
46
46
46
46
46
46
46
46
46
1
R1030
100K
1% 1/32W MF 01005
2
BI
OUT
BI
OUT
BI
OUT
OUT
IN
OUT
IN
OUT
OUT
10 19 22 37 42
TO CHARLESTON, CODEC AND PMU
10 19 22 37 42
10 25 42
TO SENSOR BOARD
10 25 42
25 42
TO SENSOR BOARD (ALS)
25 42
37 42
37 42
37 42
30 42
30 42
30 42
HSIC_HOST_RDY
1
R0720
100K
5% 1/20W MF 201
2
GPIO0
GPIO1 GPIO2
GPIO3
GPIO4 GPIO5
GPIO6 GPIO7
GPIO8
GPIO9 GPIO10
GPIO11
GPIO12 GPIO13
GPIO14
GPIO15 GPIO16
GPIO17 GPIO18
GPIO19
GPIO20 GPIO21
GPIO22
GPIO23 GPIO24
GPIO25
GPIO26 GPIO27
GPIO28 GPIO29
GPIO30
GPIO31 GPIO32
GPIO33
GPIO34 GPIO35
GPIO36
GPIO37 GPIO38
GPIO39
GPIO_3V0
GPIO_3V1
(2 OF 12)
HOME_EMI_L
5
28 37
IN
ONOFF_L
5
24 37
IN
HSIC_BB_RDY
30 42
IN
37
IN
15
OUT
19
IN
5
30
OUT
30 45
NOTE FOR GPIO12:
- BB_DIAGS_READY (RADAR #9179861)
- BB -> H4G
NOTE FOR GPIO24:
- AP_MODEM_WAKE (RADAR #9179861)
- H4G -> BB
NEW GPIO FOR J2. FILE A RADAR
TO BB
5
30 42
OUT
IN
30 42
IN
24
IN
15 30 45
IN
5
26
OUT
10
IN
24
IN
18
OUT
5
37
OUT
30
OUT
30
IN
10
IN
5
39
IN
5
OUT
10
IN
10
IN
5
15 42
IN
26
OUT
26
IN
5
42
OUT
26
IN
25
IN
26
IN
20
OUT
11
OUT
46
NC_AP_GPIO3
46
IRQ_PMU_L
PM_BT_WAKE
IRQ_CODEC_L
NC_AP_GPIO7
46
NC_AP_GPIO8
46
PM_RADIO_ON
RST_DET_L
NC_AP_GPIO11
46
SPI2_IPC_SRDY
NC_AP_GPIO13
46
AUD_VOL_DOWN_L
GSM_TXBURST_IND
NC_BOARD_ID_3
46
IRQ_GYRO_INT2
BOOT_CONFIG_0
NC_AP_GPIO19
46
AUD_VOL_UP_L
IRQ_GRAPE_HOST_INT_L PM_KEEPACT
BB_EMERGENCY_DWLD IPC_GPIO_X26
BOOT_CONFIG_1
FORCE_DFU DFU_STATUS
BOOT_CONFIG_2
BOOT_CONFIG_3
HSIC_WLAN_RDY
NC_AP_GPIO31
46
IRQ_PROX_INT_L IRQ_GYRO_INT1
HSIC_HOST_READY_WL
NC_AP_GPIO35
46
IRQ_ACCEL_INT1_L
IRQ_ALS_INT_L IRQ_ACCEL_INT2_L
AUD_SPKRAMP_MUTE_L
PORT_DOCK_VIDEO_AMP_EN
NC_AP_GPIO3V1
AJ14
AK15
AL16 AG14
AP19 AH13
AH16
AE13 AE12
AH15
AG17 AD13
AK17
AE14 AL17
AF17 AL18
AK18
AJ18 AD12
AH18
AF18 AM18
AN18
AN19 AG18
AP20 AN20
AR20
AR21 AP21
AK19
AN21 AH19
AG19
AJ19 AR22
AL20 AM20
AN22
AN31
AP32
I2S0_MCK I2S0_BCLK
I2S0_LRCK
I2S0_DIN I2S0_DOUT
I2S1_MCK
I2S1_BCLK
I2S1_LRCK I2S1_DIN
I2S1_DOUT
I2S2_MCK
I2S2_BCLK
I2S2_LRCK I2S2_DIN
I2S2_DOUT
I2S3_MCK
I2S3_BCLK I2S3_LRCK
I2S3_DIN
I2S3_DOUT
SPDIF
SPI0_MISO
SPI0_MOSI SPI0_SCLK
SPI0_SSIN
SPI1_MISO
SPI1_MOSI
SPI1_SCLK SPI1_SSIN
U0600
(3 OF 12)
R0700
33.2
1%
IN
1/32W
MF
01005
12
I2S0_ASP_BCLK
I2S0_ASP_LRCK
I2S0_ASP_DIN I2S0_ASP_DOUT
46
46
46
46
46
46
I2S2_VSP_BCLK
15 19 42
OUT
I2S2_VSP_LRCK
15 19 42
OUT
I2S2_VSP_DIN
15 19 42
IN
I2S2_VSP_DOUT
15 19 42
OUT
46
I2S3_XSP_BCLK
19 42
OUT
I2S3_XSP_LRCK
19 42
OUT
I2S3_XSP_DIN
19 42
IN
I2S3_XSP_DOUT
19 42
OUT
NC_AP_GPIO216
46
BOARD_ID_2
10
IN
BOARD_ID_1
10
IN
BOARD_ID_0
10
IN
NC_SPI_FLASH_CS_L
46
SPI1_GRAPE_MISO
17 42
IN
SPI1_GRAPE_MOSI
17 42
OUT
SPI1_GRAPE_SCLK
17 42
OUT
SPI1_GRAPE_CS_L
17 42
OUT
42
I2S0_ASP_MCK
NC_I2S1_MCK
NC_I2S1_BCLK
NC_I2S1_LRCK
NC_I2S1_DIN
NC_I2S1_DOUT
NC_I2S2_MCK
NC_I2S3_MCK
AR26
AG24 AP26
AK25 AL25
AC15 AC17
AC14
AC16 AF26
AK27 AF24
AN26 AG25
AM26
AP27
AN27
AF25 AK26
AL26
AG27
AF20 AF19
AG20
AM21
U6
W5
T6 W8
D
CODEC ASP
19 42
OUT
I2S0_ASP_MCK_R
19 42
OUT
19 42
OUT
19 42
19 42
OUT
NOT USED
CODEC VSP & BT
CODEC XSP
C
TO GRAPE
3.0V IO
OMIT
H4G
FCBGA
EHCI_PORT_PWR0
EHCI_PORT_PWR1 EHCI_PORT_PWR2
TMR32_PWM0 TMR32_PWM1
TMR32_PWM2
UART0_RXD UART0_TXD
UART1_CTSN UART1_RTSN
UART1_RXD UART1_TXD
UART2_CTSN
UART2_RTSN
UART2_RXD
UART2_TXD
UART3_CTSN
UART3_RTSN
UART3_RXD
UART3_TXD
UART4_CTSN
UART4_RTSN
UART4_RXD
UART4_TXD
UART5_RTXD
UART6_CTSN
UART6_RTSN
UART6_RXD
UART6_TXD
AG26
AE15
AE16
AD16 AD14
AC12
AH14
AG15
AP23
AL21
AG21 AF21
U5 T7
U8 T5
AG22 AJ21
AR24
AR23
Y6
Y7
W7
Y5
AL22
U9
V6
U7
V7
GPIO40_BRD_REV0
GPIO41_BRD_REV1 GPIO42_BRD_REV2
NC_AP_GPIO185
NC_AP_GPIO186
TP_LED_STROBE_EN
UART0_AP_RXD
UART0_AP_TXD
UART1_BB_CTS_L UART1_BB_RTS_L
UART1_BB_RXD UART1_BB_TXD
RST_BB_L
NC_UART2_RXD
NC_UART2_TXD
UART3_BT_CTS_L
UART3_BT_RTS_L
UART3_BT_RXD
UART3_BT_TXD
NC_UART4_CTS_L
NC_UART4_RTS_L
NC_UART4_RXD
NC_UART4_TXD
BATTERY_SWI
NC_UART6_CTSN
NC_UART6_RTSN
UART6_WLAN_RXD
UART6_WLAN_TXD
SRL_L
46
46
10
IN
10
IN
10
IN
46
46
15 42
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
46
46
46
46
OUT
46
46
IN
OUT
15 42
30 42
30 42
30 42
30 42
5
30 45
15 42
15 42
15 42
15 42
34 37
24 37
15 42
15 42
TO DOCK MUX
TO BB USART
TO BT UART
D
C
R1180
0.00
5
28 37
5
24 37
5
24 37
12
HOME_EMI_L
ONOFF_L
SRL_L
0%
1/32W
MF
01005
R0708
220K
12
5%
1/20W
MF
201
R0709
220K
12
5%
1/20W
MF
201
R0710
220K
12
5%
1/20W
MF
201
=PP1V8_VDDA18_TS
35
B
9
35
5
15 42
=PP1V8_VDDIOD_H4
NOSTUFF
R0722
HSIC_WLAN_RDY
100K
1/20W
PM_KEEPACT
IRQ_GYRO_INT2
DFU_STATUS
PM_RADIO_ON
1
R0711
100K
1/20W MF 201
1
1%
MF
201
2
2
1
R0712
100K
5%5% 1/32W MF 01005
2
1
R0713
100K
5% 1/20W MF 201
2
1
R0714
100K
5% 1/20W MF 201
2
1
R0715
100K
5% 1/20W MF 201
2
5
37
5
FORCE_DFU
26
5
39
5
5
30
SYNC_MASTER=JOE
PAGE TITLE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
AP: I/Os
SYNC_DATE=N/A
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
7 OF 157
SHEET
5 OF 48
A
D
124578
45
PP1V8_VDDA18_TS
1
C1188
0.01UF
B
DEFAULT IS TO TIE HSIC_HOST_READY TO BOTH DEVICES
BUT OPTION IS HERE IN CASE THEY NEED TO BE SEPARATE
10%
2
X5R
01005
NOSTUFF
R0730
0.00
1/20W
1
5%
MF
201
2
12
0%
1/32W
MF
01005
R0731
0.00
12
0%
1/32W
MF
01005
HSIC_HOST_READY_WLAN
15 42
=PP1V8_S2R_MISC
5
27 35 39
=PP1V8_ALWAYS
35
=PP1V8_S2R_MISC
5
27 35 39
HSIC_HOST_RDY
5
30 42
HSIC_HOST_READY_WL
5
42
R0885
100K
A
6 3
87 6 5 4 3
PPIO_NAND_H4
6 9
G22 G23
G30
H1
H4
H8 H9
H10
H11
D
C
B
A
H12
H13
H14 H15
H16 H17
H18
H19 H20
H21
H22 H23
H30
H34
J10
J11 J12
J14
J16 J18
J20
J22 J24
J26 J31
J34
K10 K11
K13
K15 K17
K19 K21
K23
K25 K27
K34
L32
L10
L12 L14
L16
L18 L20
L22
L24 L26
M11
M13
M15 M17
M19
M21 M23
M25
M27 M30
L34
N10 N12
N14
N16 N18
N20
N22 N24
N26
J2
J8 J9
K3 K8
K9
L1
L4
L8
M2
M3 M8
M9
N3
N8
U0600
(12 OF 12)
H4G
FCBGA
OMIT
M35 P1
P8 P9
P11
P13 P15
P17
P19 P21
P23
P25 P27
R2 R8
R10
R12 R14
R16
R18 R20
R22
R24 R26
P34 T3
T9
T11 T13
T15
T17 T19
T21
T23 T25
T27 R35
U1
U10 U12
U14
U16 U18
U20
U22 U24
VSSVSS
U26 U30
U31
V9 V11
V13
V15 V17
V19
V21 V23
V25 V27
V29
U34 V35
W1
W3 W10
W12
W14 W16
W18 W20
W22
W24 W26
W34
Y9 Y11
Y13
Y15 Y17
Y19 Y21
Y23
Y25 Y27
Y28
Y31
Y34
CHECK CONNECTION FOR VSSA18_TS
45
FMI1_CE0_L
6
12 44
FMI1_CE1_L
6
12 44
FMI0_CE0_L
6
12 44
FMI0_CE1_L
6
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
6
6
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
6
6
6
6
12 44
6
6
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
6
6
6
6
12 44
1
R0832
100K
5% 1/32W MF 01005
2
FMI0_CE0_L
OUT
FMI0_CE1_L
OUT
NC_FMI0_CE2_L
46
NC_FMI0_CE3_L
46
NC_FMI0_CE4_L
46
NC_FMI0_CE5_L
46
NC_FMI0_CE6_L
46
NC_FMI0_CE7_L
46
FMI0_AD<0>
BI
FMI0_AD<1>
BI
FMI0_AD<2>
BI
FMI0_AD<3>
BI
FMI0_AD<4>
BI
FMI0_AD<5>
BI
FMI0_AD<6>
BI
FMI0_AD<7>
BI
FMI0_ALE
OUT
FMI0_CLE
OUT
FMI0_WE_L
OUT
FMI0_RE_N
OUT
FMI0_DQS_P
OUT
FMI1_CE0_L
OUT
FMI1_CE1_L
OUT
NC_FMI1_CE2_L
46
NC_FMI1_CE3_L
46
NC_FMI1_CE4_L
46
NC_FMI1_CE5_L
46
NC_FMI1_CE6_L
46
NC_FMI1_CE7_L
46
FMI1_AD<0>
BI
FMI1_AD<1>
BI
FMI1_AD<2>
BI
FMI1_AD<3>
BI
FMI1_AD<4>
BI
FMI1_AD<5>
BI
FMI1_AD<6>
BI
FMI1_AD<7>
BI
FMI1_ALE
OUT
FMI1_CLE
OUT
FMI1_WE_L
OUT
FMI1_RE_N
OUT
FMI1_DQS_P
OUT
1
R0836
100K
5% 1/32W MF 01005
2
1
R0831
100K
5% 1/32W MF 01005
2
AH31
AF31 AD28
AG29
AH28
AG28
AM31
AG35
AF35 AH35
AH33 AG31
AG32
AG34 AH32
AE32 AF33
AH34
AE33 AG33
AJ33
AN33
AD30 AE30
AJ31
AJ30 AL31
AK31
AL32
AN35 AK32
AK33
AL33 AK34
AM33
AJ35
AN34
AK35 AM35
AL35 AL34
Y29
1
R0834
100K
5% 1/32W MF 01005
2
FMI0_CEN0
FMI0_CEN1 FMI0_CEN2
FMI0_CEN3 FMI0_CEN4
FMI0_CEN5
FMI0_CEN6 FMI0_CEN7
FMI0_IO0 FMI0_IO1
FMI0_IO2
FMI0_IO3 FMI0_IO4
FMI0_IO5 FMI0_IO6
FMI0_IO7
FMI0_ALE
FMI0_CLE
FMI0_WEN FMI0_REN
FMI0_DQS
FMI1_CEN0
FMI1_CEN1 FMI1_CEN2
FMI1_CEN3
FMI1_CEN4 FMI1_CEN5
FMI1_CEN6
FMI1_CEN7
FMI1_IO0
FMI1_IO1 FMI1_IO2
FMI1_IO3 FMI1_IO4
FMI1_IO5
FMI1_IO6 FMI1_IO7
FMI1_ALE FMI1_CLE
FMI1_WEN
FMI1_REN FMI1_DQS
U0600
H4G
FCBGA
(4 OF 12)
OMIT
FMI2_CEN0
FMI2_CEN1 FMI2_CEN2
FMI2_CEN3 FMI2_CEN4
FMI2_CEN5
FMI2_CEN6 FMI2_CEN7
FMI2_IO0 FMI2_IO1
FMI2_IO2
FMI2_IO3 FMI2_IO4
FMI2_IO5 FMI2_IO6
FMI2_IO7
FMI2_ALE
FMI2_CLE
FMI2_WEN FMI2_REN
FMI2_DQS
FMI3_CEN0
FMI3_CEN1 FMI3_CEN2
FMI3_CEN3
FMI3_CEN4 FMI3_CEN5
FMI3_CEN6
FMI3_CEN7
FMI3_IO0
FMI3_IO1 FMI3_IO2
FMI3_IO3 FMI3_IO4
FMI3_IO5
FMI3_IO6 FMI3_IO7
FMI3_ALE FMI3_CLE
FMI3_WEN
FMI3_REN FMI3_DQS
AE35
AB28 AA28
AB30
AE28 AF28
AA29
AB31
AC31
AB33 AC35
AE34 AD34
AD32
AD35 AD31
AB34 AB32
AB35
AD33 AC33
W31
W28
W29 V30
AG30
AC30 AH30
AE31
AA34
W33 AA33
V34
AA30 V31
W32
Y30
Y33
W30 AA32
AA31 Y32
28 35
=PP3V0_IO_MISC
SPK_ID
NC_FMI2_CE1_L NC_FMI2_CE2_L
NC_FMI2_CE3_L
NC_FMI2_CE5_L
GRAPE_FW_DNLD_EN_L
NC_FMI2_AD<0> NC_FMI2_AD<1>
NC_FMI2_AD<2>
NC_FMI2_AD<3> NC_FMI2_AD<4>
NC_FMI2_AD<5>
NC_FMI2_AD<6> NC_FMI2_AD<7>
NC_FMI2_ALE NC_FMI2_CLE
NC_FMI2_WE_L NC_FMI2_RE_L
NC_FMI2_DQS
NC_FMI3_CE0_L
NC_FMI3_CE1_L
NC_FMI3_CE2_L NC_FMI3_CE3_L
NC_FMI3_CE4_L
NC_FMI3_CE5_L NC_FMI3_CE6_L
NC_FMI3_CE7_L
NC_FMI3_AD<0>
NC_FMI3_AD<1> NC_FMI3_AD<2>
NC_FMI3_AD<3>
NC_FMI3_AD<4> NC_FMI3_AD<5>
NC_FMI3_AD<6>
NC_FMI3_AD<7>
NC_FMI3_ALE NC_FMI3_CLE
NC_FMI3_WE_L
NC_FMI3_RE_L NC_FMI3_DQS
46
46
46
46
46
46
46
46
46
46
1
R0804
100K
5% 1/32W MF 01005
2
46
46
46
PM_LCDVDD_PWREN
46
RST_GRAPE_L
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
46
PPIO_NAND_H4
6 9
12 44
12 44
12 44
12 44
12 44
12 44
12 44
12 44
45
FMI0_WE_L
6
FMI0_RE_N
6
FMI1_WE_L
6
FMI1_RE_N
6
FMI0_ALE
6
FMI0_CLE
6
FMI1_ALE
6
FMI1_CLE
6
NOSTUFF
1
R0800
100K
5% 1/32W MF 01005
2
NOSTUFF
1
R0810
100K
5% 1/32W MF 01005
2
FMI2-3_CEN IS 3.0V
20
IN
NEW GPIO FOR J2. FILE A RADAR
16
OUT
17 45
OUT
CHECK WITH GRAPE ON VOLTAGE FOR THESE TWO SIGNALS
17
OUT
NOSTUFF
1
R0801
100K
5% 1/32W MF 01005
2
NOSTUFF
1
R0811
100K
5% 1/32W MF 01005
2
NOSTUFF
1
R0802
100K
5% 1/32W MF 01005
2
NOSTUFF
1
R0812
100K
5%
1/32W
MF
01005
2
SYNC_MASTER=MIKE
PAGE TITLE
NOSTUFF
1
R0803
100K
5% 1/32W MF 01005
2
NOSTUFF
1
R0813
100K
5% 1/32W MF 01005
2
AP: NAND
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
6 3
12
SYNC_DATE=N/A
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
8 OF 157
SHEET
6 OF 48
124578
D
C
B
A
D
87 6 5 4 3
R0910
0
45
PP1V8_DP_AVDD_AUX
=PP3V0_IO_H4
9
35
D
=PP1V1_MIPI_H4
35
1
C0960
2.2NF
10% 10V
2
X5R 201
1
C0935
1UF
10%
2
45
PP0V4_MIPI1D
45
PP0V4_MIPI0D
1
C0961
2.2NF
10% 10V
2
X5R 201
1
C0908
0.1UF
10%
2
X5R 201
VOLTAGE=0.4V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
VOLTAGE=0.4V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
C
NC_MIPI_VSYNC_H4
46
MIPI0C_AP_DATA_P<0>
25 43
OUT
MIPI0C_AP_DATA_N<0>
25 43
OUT
MIPI0C_AP_DATA_P<1>
25 43
OUT
MIPI0C_AP_DATA_N<1>
25 43
OUT
NC_MIPI0C_AP_DATA_P<2>
43 46
NC_MIPI0C_AP_DATA_N<2>
43 46
NC_MIPI0C_AP_DATA_P<3>
43 46
NC_MIPI0C_AP_DATA_N<3>
43 46
MIPI0C_AP_CLK_P
25 43
OUT
MIPI0C_AP_CLK_N
25 43
OUT
B
AD15
D35
C35
B33
B32
B31 B30
A31 A30
A33 A32
1
C0903
0.1UF
10%
2
X5R 201
F26
F29
G24
MIPI1D_VREG_0P4V
MIPI0D_VREG_0P4V
MIPI_VSYNC
MIPI0C_DPDATA0 MIPI0C_DNDATA0
MIPI0C_DPDATA1 MIPI0C_DNDATA1
MIPI0C_DPDATA2 MIPI0C_DNDATA2
MIPI0C_DPDATA3
MIPI0C_DNDATA3
MIPI0C_DPCLK
MIPI0C_DNCLK
G25
G26
G27
MIPI_VDD11
14MA
OMIT
U0600
H4G
FCBGA
(6 OF 12)
F25
F28
G28
G29
MIPI1D_VDD18
MIPI0D_VDD18
4MA
ISP0_FLASH
ISP0_PRE_FLASH
ISP0_SCL ISP0_SDA
ISP1_FLASH
ISP1_PRE_FLASH
ISP1_SCL
ISP1_SDA
SENSOR0_CLK SENSOR0_RST
SENSOR1_CLK SENSOR1_RST
MIPI1C_DPDATA0 MIPI1C_DNDATA0
MIPI1C_DPDATA1 MIPI1C_DNDATA1
MIPI1C_DPCLK
MIPI1C_DNCLK
=PP1V8_MIPI_H4
1
C0907
0.1UF
10%
2
X5R 201
1
R0930
1.00K
5% 1/32W MF 01005
2
AD17 AF13
AK22
AF22
AF14
NC_ISP_AP_1_FLASH
AE17
NC_ISP_AP_1_PRE_FLASH AP24
AN23
AJ24
42
CLK_CAM_RF_R AK24
AH24
42
CLK_CAM_FF_R AL24
F34
E34
D34
NC_MIPI1C_AP_DATA_P<1> C34
NC_MIPI1C_AP_DATA_N<1>
F35 E35
35
1
R0931
1.00K
5% 1/32W MF 01005
2
46
46
0.00
0.00
R0900
MF 01005
R0940
MF 01005
43 46
43 46
12
0%
1/32W
12
0%
1/32W
MIPI1C_AP_DATA_P<0> MIPI1C_AP_DATA_N<0>
MIPI1C_AP_CLK_P MIPI1C_AP_CLK_N
1
R0932
1.00K
5% 1/32W MF 01005
2
1
R0933
1.00K
5% 1/32W MF 01005
2
CAM0_RESET_L
TP_CAM0_1V2_VDDCORE_EN
ISP_AP_0_SCL ISP_AP_0_SDA
ISP_AP_1_SCL
ISP_AP_1_SDA
PM_REAR_CAM_SHUTDOWN
PM_FRONT_CAM_SHUTDOWN
25 43
OUT
25 43
OUT
25 43
OUT
25 43
OUT
=PP1V8_H4
CLK_CAM_RF
CLK_CAM_FF
25 42
25
25 42
25
7
35
=PP3V0_VIDEO_H4
1
C0951
1UF
10%
2
FL0910
240-OHM-0.2A-0.8-OHM
7
35
4
10 35
26
25 42
OUT
25 42
BI
25 42
OUT
25 42
BI
12
45
DAC_AP_VREF
DAC_AP_IREF
1
C0955
0.1UF
10%
2
X5R 201
1
R0950
6.34K
1% 1/20W MF 201
2
NOTE: 0.6V ANALOG REF
1
C0950
0.01UF
10%
2
X5R 01005
402
DAC_AP_COMP_FTR=PP3V0_VIDEO_H4
TP_DP_AP_ANALOG_TEST
AP_DP_R_BIAS
NOSTUFF
TP_EDP_AP_ANALOG_TEST
NOTE: 0.6V ANALOG REF
AP_EDP_R_BIAS
NOSTUFF
1
C0957
0.01UF
10%
2
X5R 01005
1
C0956
0.1UF
10%
2
X5R 201
DAC_AP_COMP
1
R0920
4.99K
1% 1/32W MF 01005
2
1
R0921
4.99K
1% 1/32W MF 01005
2
1
C0953
0.01UF
10%
2
X5R 01005
1
C0952
0.01UF
10%
2
X5R 01005
G31
D32
D28
DAC_AVDD30D
DAC_AVDD30A
21MA
6MA
DAC_VREF
F31 G35
DAC_IREF DAC_OUT1
E32
DAC_COMP
F23
DP_PAD_DC_TP
E23
DP_PAD_R_BIAS
F20
EDP_PAD_DC_TP
E20
EDP_PAD_R_BIAS
5MA
1
C0927
0.22UF
2
VOLTAGE=1.8V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
C26
C25
D24
D23
DP_PAD_AVDD
332MA
DP_PAD_AVDD_AUX
20%
D27
DP_PAD_AVDDP0
2MA
B29
DP_PAD_AVDDX
1.2MA
5MA
OMIT
U0600
H4G
FCBGA
(5 OF 12)
1
C0926
0.22UF
20%
2
X5R 402
45
PP1V8_EDP_AVDD_AUX
VOLTAGE=1.8V MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.1MM NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
A29C29
D20
DP_PAD_DVDD
EDP_PAD_AVDD_AUX
5MA
1
C0934
0.22UF
20%
2
X5R 402
B18
A18
172MA
1
C0925
0.22UF
20%
2
X5R 402
E19
E18
D19
EDP_PAD_AVDD
EDP_PAD_AVDDP0
2MA
EDP_PAD_AUXP
EDP_PAD_AUXN
EDP_PAD_TX0P
EDP_PAD_TX0N
EDP_PAD_TX1P
EDP_PAD_TX1N
EDP_PAD_TX2P
EDP_PAD_TX2N
EDP_PAD_TX3P
EDP_PAD_TX3N
1
C0933
0.22UF
20%
2
X5R 402
C21
C22
EDP_PAD_DVDDEDP_PAD_DVSS
EDP_PAD_AVDDX
1.2MA
5MA
DAC_OUT3 DAC_OUT2
DP_HPD
DP_PAD_AUXP
DP_PAD_AUXN
DP_PAD_TX0P
DP_PAD_TX0N
DP_PAD_TX1P DP_PAD_TX1N
DP_PAD_TX2P DP_PAD_TX2N
DP_PAD_TX3P DP_PAD_TX3N
EDP_HPD
1
C0924
2
12
5%
1/20W
56PF
5%
MF
201
=PP1V1_DP_PAD_DVDD_H4
1
C0909
0.1UF
10%
2
X5R 201
1
C0932
0.22UF
20%
2
X5R 402
=PP1V1_EDP_PAD_DVDD_H4
1
C0910
0.1UF
10%
2
X5R 201
G33E31 G34
AL15
C28
C27
A28
A27
D26
D25
B26
B25
C24
C23
AJ15
A24 A23
D22 D21
B22 B21
C20
C19
A20
A19
=PP1V8_DP_H4
1
C0923
56PF
5%
2
NP0-C0G 01005
35
R0911
C0931
56PF
5%
1
R0955
200
1% 1/20W MF MF 201
2
12
1
2
DP_AP_HPD
DP_AP_AUX_P
DP_AP_AUX_N
DP_AP_TX_P<0>
DP_AP_TX_N<0>
DP_AP_TX_P<1>
DP_AP_TX_N<1>
DP_AP_TX_P<2> DP_AP_TX_N<2>
DP LANES 2/3 ARE FOR STEVE-NOTE ONLY DP_AP_TX_P<3> DP_AP_TX_N<3>
EDP_AP_HPD
EDP_AP_AUX_P EDP_AP_AUX_N
EDP_AP_TX_P<0>
EDP_AP_TX_N<0>
EDP_AP_TX_P<1>
EDP_AP_TX_N<1>
EDP_AP_TX_P<2>
EDP_AP_TX_N<2>
EDP_AP_TX_P<3>
EDP_AP_TX_N<3>
1/20W
201
35
0
5%
MF
1
2
35
R0956
200
1% 1/20W
201
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
37 43
28 43
28 43
28 43
28 43
28 43
28 43
28 43
28 43
28 43
28 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
16 43
1
2
C0930
56PF
5%
12
=PP1V8_EDP_H4
DAC_AP_OUT3
DAC_AP_OUT2 DAC_AP_OUT1
1
R0957
200
1% 1/20W MF 201
2
D
35
11 43
OUT
11 43
OUT
11 43
OUT
C
B
A
PART NUMBER
132S0279 132S0154
ALTERNATE FOR PART NUMBER
BOM OPTION
REF DES
C0960,C0961
COMMENTS:
RADAR:9624625
DAC_AVSS30A1
DAC_AVSS30A2
DAC_AVSS30D
G32
F32
D31
TABLE_ALT_HEAD
TABLE_ALT_ITEM
DP_PAD_AVSS
DP_PAD_AVSS_AUX
A26
A25
B24
B28
B23
B27
DP_PAD_AVSSX
DP_PAD_AVSSP0
D29
6 3
DP_PAD_DVSS
D18
C18
EDP_PAD_AVSS
EDP_PAD_AVSSP0
F19
F18
B19
EDP_PAD_AVSS_AUX
EDP_PAD_AVSSX
B20
A21
A22
SYNC_MASTER=JOE
PAGE TITLE
AP: TV,DP,MIPI
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED
SYNC_DATE=01/13/2011
DRAWING NUMBER
051-8773
REVISION
10.0.0
BRANCH
9 OF 157
SHEET
7 OF 48
124578
A
D
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
(7 OF 12)
DDR0_CA0 DDR0_CA1
DDR0_CA2
DDR0_CA3 DDR0_CA4
DDR0_CA5
DDR0_CA6 DDR0_CA7
DDR0_CA8
DDR0_CA9
DDR0_CK DDR0_CKB
DDR0_CKE0
DDR0_CKE1
DDR0_CSN0
DDR0_CSN1
DDR0_DM0 DDR0_DM1
DDR0_DM2
DDR0_DM3
DDR0_DQ0 DDR0_DQ1
DDR0_DQ10
DDR0_DQ11 DDR0_DQ12
DDR0_DQ13
DDR0_DQ14 DDR0_DQ15
DDR0_DQ16
DDR0_DQ17 DDR0_DQ18
DDR0_DQ19
DDR0_DQ2
DDR0_DQ20 DDR0_DQ21
DDR0_DQ22 DDR0_DQ23
DDR0_DQ24
DDR0_DQ25 DDR0_DQ26
DDR0_DQ27
DDR0_DQ28 DDR0_DQ29
DDR0_DQ3
DDR0_DQ30
DDR0_DQ31
DDR0_DQ4
DDR0_DQ5
DDR0_DQ6 DDR0_DQ7
DDR0_NDQS0
DDR0_NDQS1
DDR0_NDQS2
DDR0_NDQS3
DDR0_PDQS0
DDR0_PDQS1
DDR0_PDQS2
DDR0_PDQS3
DDR0_VDDQ_CKE
DDR0_VREF_DQ
DDR0_ZQ
DDR1_CA0 DDR1_CA1
DDR1_CA2
DDR1_CA3 DDR1_CA4
DDR1_CA6 DDR1_CA7
DDR1_CA8
DDR1_CA9
DDR1_CK
DDR1_CKB
DDR1_CKE0
DDR1_CSN0
DDR1_CSN1
DDR1_DM0 DDR1_DM1
DDR1_DM2
DDR1_DM3
DDR1_DQ0 DDR1_DQ1
DDR1_DQ10
DDR1_DQ11 DDR1_DQ12
DDR1_DQ13
DDR1_DQ14 DDR1_DQ15
DDR1_DQ16
DDR1_DQ17 DDR1_DQ18
DDR1_DQ19
DDR1_DQ2
DDR1_DQ20 DDR1_DQ21
DDR1_DQ22 DDR1_DQ23
DDR1_DQ24
DDR1_DQ25 DDR1_DQ26
DDR1_DQ27
DDR1_DQ28 DDR1_DQ29
DDR1_DQ3
DDR1_DQ30
DDR1_DQ31
DDR1_DQ4
DDR1_DQ5
DDR1_DQ6 DDR1_DQ7
DDR1_DQ8
DDR1_DQ9
DDR1_NDQS0
DDR1_NDQS1
DDR1_NDQS2
DDR1_NDQS3
DDR1_PDQS0
DDR1_PDQS1
DDR1_PDQS2
DDR1_PDQS3
DDR0_DQ8
DDR0_DQ9
DDR1_CA5
DDR1_VREF_DQ
DDR1_CKE1
DDR1_VDDQ_CKE
DDR1_ZQ
(8 OF 12)
DDR2_DQ0 DDR2_DQ1
DDR2_DQ2
DDR2_DQ3 DDR2_DQ4
DDR2_DQ5
DDR2_DQ6 DDR2_DQ7
DDR2_DQ8
DDR2_DQ9 DDR2_DQ10
DDR2_DQ11 DDR2_DQ12
DDR2_DQ13
DDR2_DQ14 DDR2_DQ15
DDR2_DQ16
DDR2_DQ17 DDR2_DQ18
DDR2_DQ19
DDR2_DQ20 DDR2_DQ21
DDR2_DQ22 DDR2_DQ23
DDR2_DQ24
DDR2_DQ25 DDR2_DQ26
DDR2_DQ27
DDR2_DQ28 DDR2_DQ29
DDR2_DQ30
DDR2_DQ31
DDR2_CA0 DDR2_CA1
DDR2_CA2
DDR2_CA3 DDR2_CA4
DDR2_CA5
DDR2_CA6 DDR2_CA7
DDR2_CA8
DDR2_CA9
DDR2_DM0 DDR2_DM1
DDR2_DM2
DDR2_DM3
DDR2_PDQS0
DDR2_NDQS0 DDR2_PDQS1
DDR2_NDQS1
DDR2_PDQS2 DDR2_NDQS2
DDR2_PDQS3 DDR2_NDQS3
DDR2_VDDQ_CKE
DDR2_VREF_DQ
DDR2_ZQ
DDR2_CK DDR2_CKB
DDR2_CKE0
DDR2_CKE1
DDR2_CSN0
DDR2_CSN1
DDR3_DQ0 DDR3_DQ1
DDR3_DQ2
DDR3_DQ3 DDR3_DQ4
DDR3_DQ5
DDR3_DQ6 DDR3_DQ7
DDR3_DQ8
DDR3_DQ9 DDR3_DQ10
DDR3_DQ11 DDR3_DQ12
DDR3_DQ13
DDR3_DQ14 DDR3_DQ15
DDR3_DQ16
DDR3_DQ17 DDR3_DQ18
DDR3_DQ19
DDR3_DQ20 DDR3_DQ21
DDR3_DQ22 DDR3_DQ23
DDR3_DQ24
DDR3_DQ25 DDR3_DQ26
DDR3_DQ27
DDR3_DQ28 DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_CA0
DDR3_CA1
DDR3_CA2
DDR3_CA3
DDR3_CA4
DDR3_CA5
DDR3_CA6
DDR3_CA7
DDR3_CA8
DDR3_CA9
DDR3_DM0
DDR3_DM1
DDR3_DM2
DDR3_DM3
DDR3_PDQS0
DDR3_NDQS0 DDR3_PDQS1
DDR3_NDQS1
DDR3_PDQS2 DDR3_NDQS2
DDR3_PDQS3 DDR3_NDQS3
DDR3_VDDQ_CKE
DDR3_VREF_DQ
DDR3_ZQ
DDR3_CK
DDR3_CKB
DDR3_CKE0
DDR3_CKE1
DDR3_CSN0
DDR3_CSN1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
998-3125 0.5MM PT
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 40 44
13 40 44
13 44
13 44
13 40 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
13 44
13 44
13 44
13 44
13 44
01005
10%
0.01UF
NOSTUFF
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
1.00K
1%
MF
1/32W
01005
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
1/32W
1%
MF 01005
1.00K
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
10%
01005
0.01UF
NOSTUFF
X5R
13 44
13 44
13 44
13 44
13 44
13 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
1.00K
1% 1/32W MF 01005
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
MF
1.00K
1/32W
1%
01005
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
14 44
H4G
FCBGA
OMIT
H4G
FCBGA
OMIT
0.01UF
01005
10%
NOSTUFF
1/32W
1.00K
1%
MF 01005
MF
1.00K
1/32W
1%
01005
10%
01005
0.01UF
NOSTUFF
X5R
01005
1/32W MF
1%
1.00K
01005
1.00K
MF
1% 1/32W
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
MF
1% 1/20W
240
201
1/20W
240
MF
1%
201
240
1% 1/20W MF 201
240
1% 1/20W MF 201
10%
01005
0.01UF
X5R
NOSTUFF
NOSTUFF
10%
01005
0.01UF
NOSTUFF
0.01UF
10%
01005
X5R
10%
01005
0.01UF
NOSTUFF
X5R
13 40 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 40 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
13 44
SYNC_MASTER=MIKE
AP: DDR
SYNC_DATE=N/A
DDR1_DM<2>
DDR1_DM<0>
H4G_DDR0_ZQ
MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
PPVREF_DDR1_DQ_H4
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
NET_SPACING_TYPE=PWR
PPVREF_DDR1_DQ_H4
PPVREF_DDR0_DQ_H4
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
NET_SPACING_TYPE=PWR
PPVREF_DDR0_DQ_H4
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM
PPVREF_DDR2_DQ_H4
NET_SPACING_TYPE=PWR
PPVREF_DDR2_DQ_H4
PPVREF_DDR3_DQ_H4
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
PPVREF_DDR3_DQ_H4
DDR1_DQ<27>
DDR1_DQ<23>
=PP1V2_VDDIOD_H4
=PP1V2_VDDIOD_H4
=PP1V2_VDDIOD_H4 =PP1V2_VDDIOD_H4
H4G_DDR1_ZQ
=PP1V2_S2R_H4
NC_DDR1_CKE<1>
DDR1_CA<5>
DDR0_DQ<9>
DDR0_DQ<8>
DDR1_DQS_P<3>
DDR1_DQS_P<2>
DDR1_DQS_P<1>
DDR1_DQS_P<0>
DDR1_DQS_N<3>
DDR1_DQS_N<2>
DDR1_DQS_N<1>
DDR1_DQS_N<0>
DDR1_DQ<9>
DDR1_DQ<8>
DDR1_DQ<7>
DDR1_DQ<6>
DDR1_DQ<5>
DDR1_DQ<4>
DDR1_DQ<31>
DDR1_DQ<30>
DDR1_DQ<3>
DDR1_DQ<29>
DDR1_DQ<28>
DDR1_DQ<26>
DDR1_DQ<25>
DDR1_DQ<24>
DDR1_DQ<22>
DDR1_DQ<21>
DDR1_DQ<20>
DDR1_DQ<2>
DDR1_DQ<19>
DDR1_DQ<18>
DDR1_DQ<17>
DDR1_DQ<16>
DDR1_DQ<15>
DDR1_DQ<14>
DDR1_DQ<13>
DDR1_DQ<12>
DDR1_DQ<11>
DDR1_DQ<10>
DDR1_DQ<1>
DDR1_DQ<0>
DDR1_DM<3>
DDR1_DM<1>
NC_DDR1_CSN<1>
DDR1_CSN<0>
DDR1_CKE<0>
DDR1_CK_N
DDR1_CK_P
DDR1_CA<9>
DDR1_CA<8>
DDR1_CA<7>
DDR1_CA<6>
DDR1_CA<4>
DDR1_CA<3>
DDR1_CA<2>
DDR1_CA<1>
DDR1_CA<0>
=PP1V2_S2R_H4
DDR0_DQS_P<3>
DDR0_DQS_P<2>
DDR0_DQS_P<1>
DDR0_DQS_P<0>
DDR0_DQS_N<3>
DDR0_DQS_N<2>
DDR0_DQS_N<1>
DDR0_DQS_N<0>
DDR0_DQ<7>
DDR0_DQ<6>
DDR0_DQ<5>
DDR0_DQ<4>
DDR0_DQ<31>
DDR0_DQ<30>
DDR0_DQ<3>
DDR0_DQ<29>
DDR0_DQ<28>
DDR0_DQ<27>
DDR0_DQ<26>
DDR0_DQ<25>
DDR0_DQ<24>
DDR0_DQ<23>
DDR0_DQ<22>
DDR0_DQ<21>
DDR0_DQ<20>
DDR0_DQ<2>
DDR0_DQ<19>
DDR0_DQ<18>
DDR0_DQ<17>
DDR0_DQ<16>
DDR0_DQ<15>
DDR0_DQ<14>
DDR0_DQ<13>
DDR0_DQ<12>
DDR0_DQ<11>
DDR0_DQ<10>
DDR0_DQ<1>
DDR0_DQ<0>
DDR0_DM<3>
DDR0_DM<2>
DDR0_DM<1>
DDR0_DM<0>
NC_DDR0_CSN<1>
DDR0_CSN<0>
NC_DDR0_CKE<1>
DDR0_CKE<0>
DDR0_CK_N
DDR0_CK_P
DDR0_CA<9>
DDR0_CA<8>
DDR0_CA<7>
DDR0_CA<6>
DDR0_CA<5>
DDR0_CA<4>
DDR0_CA<3>
DDR0_CA<2>
DDR0_CA<1>
DDR0_CA<0>
NC_DDR3_CSN<1>
DDR3_CSN<0>
NC_DDR3_CKE<1>
DDR3_CKE<0>
DDR3_CK_N
DDR3_CK_P
H4G_DDR3_ZQ
=PP1V2_S2R_H4
DDR3_DQS_N<3>
DDR3_DQS_P<3>
DDR3_DQS_N<2>
DDR3_DQS_P<2>
DDR3_DQS_N<1>
DDR3_DQS_P<1>
DDR3_DQS_N<0>
DDR3_DQS_P<0>
DDR3_DM<3>
DDR3_DM<2>
DDR3_DM<1>
DDR3_DM<0>
DDR3_CA<9>
DDR3_CA<8>
DDR3_CA<7>
DDR3_CA<6>
DDR3_CA<5>
DDR3_CA<4>
DDR3_CA<3>
DDR3_CA<2>
DDR3_CA<1>
DDR3_CA<0>
DDR3_DQ<31>
DDR3_DQ<30>
DDR3_DQ<29>
DDR3_DQ<28>
DDR3_DQ<27>
DDR3_DQ<26>
DDR3_DQ<25>
DDR3_DQ<24>
DDR3_DQ<23>
DDR3_DQ<22>
DDR3_DQ<21>
DDR3_DQ<20>
DDR3_DQ<19>
DDR3_DQ<18>
DDR3_DQ<17>
DDR3_DQ<16>
DDR3_DQ<15>
DDR3_DQ<14>
DDR3_DQ<13>
DDR3_DQ<12>
DDR3_DQ<11>
DDR3_DQ<10>
DDR3_DQ<9>
DDR3_DQ<8>
DDR3_DQ<7>
DDR3_DQ<6>
DDR3_DQ<5>
DDR3_DQ<4>
DDR3_DQ<3>
DDR3_DQ<2>
DDR3_DQ<1>
DDR3_DQ<0>
NC_DDR2_CSN<1>
DDR2_CSN<0>
NC_DDR2_CKE<1>
DDR2_CKE<0>
DDR2_CK_N
DDR2_CK_P
H4G_DDR2_ZQ
=PP1V2_S2R_H4
DDR2_DQS_N<3>
DDR2_DQS_P<3>
DDR2_DQS_N<2>
DDR2_DQS_P<2>
DDR2_DQS_N<1>
DDR2_DQS_P<1>
DDR2_DQS_N<0>
DDR2_DQS_P<0>
DDR2_DM<3>
DDR2_DM<2>
DDR2_DM<1>
DDR2_DM<0>
DDR2_CA<9>
DDR2_CA<8>
DDR2_CA<7>
DDR2_CA<6>
DDR2_CA<5>
DDR2_CA<4>
DDR2_CA<3>
DDR2_CA<2>
DDR2_CA<1>
DDR2_CA<0>
DDR2_DQ<31>
DDR2_DQ<30>
DDR2_DQ<29>
DDR2_DQ<28>
DDR2_DQ<27>
DDR2_DQ<26>
DDR2_DQ<25>
DDR2_DQ<24>
DDR2_DQ<23>
DDR2_DQ<22>
DDR2_DQ<21>
DDR2_DQ<20>
DDR2_DQ<19>
DDR2_DQ<18>
DDR2_DQ<17>
DDR2_DQ<16>
DDR2_DQ<15>
DDR2_DQ<14>
DDR2_DQ<13>
DDR2_DQ<12>
DDR2_DQ<11>
DDR2_DQ<10>
DDR2_DQ<9>
DDR2_DQ<8>
DDR2_DQ<7>
DDR2_DQ<6>
DDR2_DQ<5>
DDR2_DQ<4>
DDR2_DQ<3>
DDR2_DQ<2>
DDR2_DQ<1>
DDR2_DQ<0>
C1056
1
2
R1055
1
2
R1056
1
2
C1054
1
2
R1053
1
2
R1054
1
2
C1084
1
2
R1083
1
2
R1084
1
2
C1096
1
2
R1095
1
2
R1096
1
2
C1020
1
2
C1021
1
2
C1022
1
2
C1023
1
2
R1020
1
2
R1021
1
2
R1022
1
2
R10234
1
2
C1057
1
2
C1058
1
2
C1095
1
2
C1085
1
2
U0600
G5
G6 H5
H6
J5 M5
M6
N6 P5
P6
P4
N4 J1
K1
K6
J6
E12
E9
C14
D6
B14
B13
B8
C8
B7 B6
C6
D7 B17
C17
B16 E17
D13
D16 E16
C15
D15
E6
B5
C5
E5
C4
D4
C12
B3
C3
D12 B11
C11
B10
C9
D9
A12
A7
A15
A4
A13
A6
A16
A3
G11
D10
M4
E15
F15 F14
E14
F13 E8
F8
F7 E7
F6
F11
F12 A10
A9
F10
E13
L5
N5 G4
R5
H2
H3
P3
R3
U3 T2
U2
R4 C2
D2
E2 E4
J3
E3 F3
F4
G2 R6
T4
U4 V1
V2
V3
J4
V4
V5
K2 L2
K4
K5 N2
P2
G1
M1
D1
R1
F1
N1
C1
T1
N7
L3
E11
U0600
AL6
AK6 AL7
AK7
AL8 AL11
AK11
AK12 AL12
AK13
AM13
AM12 AR10
AR9
AK9
AK8
AD4
AG4
AA6
AK4
AB2
AB3
AH3
AF4
AJ3
AJ2
AK3
AF5
Y2
W2
Y3 W4
AC2
Y4 AA3
AA5
AA4 AL2
AL3
AL4 AM2
AN2
AN3
AC4
AL5
AK5
AE2 AD3
AF2
AE3 AG3
AH2
AD1
AJ1
AA1
AM1
AC1
AK1
Y1
AN1
AE7
AE4
AL9
AB5
AB6 AC5
AC6
AD5 AG5
AG6
AH6 AH5
AJ6
AH4
AJ4 AF1
AG1
AE6
AD6
AM11
AL13 AM6
AK14
AP7
AM7
AL10
AP13
AP14 AM14
AL14
AN14 AP4
AP3
AN4 AM4
AP8
AP5 AN5
AN6
AM5 AN15
AM15
AP16 AM16
AR18
AP17
AN8
AN17
AM17
AN9 AP10
AP11
AN11 AN12
AM10
AR7
AR12
AR4
AR15
AR6
AR13
AR3
AR16
AJ12
AM9
AE5
051-8773
10.0.0
10 OF 157
8 OF 48
8
45
8
45
8
45
8
45
8
45
8
45
8
45
8
45
8 9
35
8 9
35
8 9
35
8 9
35
8
35
46
46
8
35
46
46
46
46
8
35
46
46
8
35
(9 OF 12)
VDD
VDD
VDDIO18_GPIO
VDDIO18_UART1_TXD0
VDD_CPU
VDDIOD
VDDIOD7
VDDIOD6
VDDIOD5
VDDIOD4
VDDIOD3
VDDIOD2
VDDIOD1
VDDIOD0
VDDIO18_XO0
VDDIO18_FUSE0_FSRC
VDDIO18_UART2_TXD
VDDIO30_USB11
VDDIO30_GPIO_3V0
VDDIO30_DP_HPD
VDDIO30_CFSB
(10 OF 12)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
FMI0-1 88MA
FMI2-3 88MA
1000MA
160MA
44MA
FMI2-3_CEN 2MA
ISP FLASH, SPI3 3MA
UART4 ?MA
GPIO30-39 4MA
2300MA
3800MA
SPI1 1MA
I2C2 1MA
C1100, C1102, C1103, C1117, C1121, C1122, C1124, C1153, C1154, C1155, C1156, C1158, C1191, C1615, C1621, C1715, C1721
10%
1UF
402
10%
1UF
402
6.3V 6.3V X5R 0201
0.22UF
20%
0.22UF
20%
402
10%
1UF
0.22UF
20%
0.22UF
20%
0.22UF
20%
603
10UF
X5R
20%
20%
4V
X5R-CERM
4.3UF
603
10UF
X5R
20%
20%
4V
X5R-CERM
4.3UF
01005
10%
0.01UF
01005
10%
0.01UF
01005
10%
0.01UF
01005
10%
0.01UF
01005
0.01UF
X5R
10%
0.22UF
X5R
20%
20%
0.22UF
20%
0.22UF
20%
0.22UF
0.22UF
X5R
20%
0.22UF
X5R
20%
01005
10%
0.01UF
4.3UF
4V
X5R-CERM
20%
10UF
603
20%
X5R-CERM
4.3UF
4V
20%
20%
0.22UF
0402-1
CERM-X5R
10UF
20%
0.22UF
X5R
20%
0.22UF
20%
56PF
5%
NP0-C0G
01005
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0
5%
NAND_IO_1V8
MF
1/20W
201
NAND_IO_3V3
MF
1/20W
0
5%
201
H4G
FCBGA
OMIT
FCBGA
H4G
OMIT
01005
5%
NP0-C0G
56PF
01005
56PF
NP0-C0G
5%
01005
NP0-C0G
5%
56PF
01005
NP0-C0G
5%
56PF
01005
NP0-C0G
5%
56PF
01005
NP0-C0G
5%
56PF
56PF
5%
NP0-C0G 01005
0.22UF
20%
20%
4V
X5R-CERM
4.3UF
20%
4V
X5R-CERM
4.3UF
0.22UF
X5R
20%
0.22UF
20%
0.22UF
X5R
20%
4V
X5R-CERM
4.3UF
20%
0.22UF
20%
20%
4V
X5R-CERM
4.3UF
603
10UF
20%
4.3UF
X5R-CERM
4V
20%
0.22UF
X5R
20%
20%
0.22UF
20%
0.22UF
01005
10%
0.01UF
0.22UF
20%
0.22UF
X5R
20%
0.22UF
20%
0.22UF
20%
4.3UF
X5R-CERM
4V
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
X5R-CERM
4V
4.3UF
20%
4V
4.3UF
X5R-CERM
20%
4.3UF
X5R-CERM
4V
20%
56PF
5%
NP0-C0G
0100501005
NP0-C0G
5%
56PF
0.22UF
20%
138S0657138S0702
QTY 17 RADAR:8837828
C1100,C1102
SYNC_MASTER=MIKE
SYNC_DATE=N/A
AP: POWER
=PPVDD_SOC_H4
=PPVDD_CPU_H4
=PPVDD_SOC_H4
=PP1V2_VDDIOD_H4
=PP3V0_VDDIOD_H4
MAX_NECK_LENGTH=3 MM
VOLTAGE=1.8V
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
PPIO_NAND_H4
=PP1V8_VDDIOD_H4
=PP1V8_VDDIO18_H4
=PP3V0_IO_H4
=PP1V8_NAND_H4
=PP3V3_NAND_H4
C1197
1
2
C1196
1
2
C1192
1
2
C1195
1
2
C1124
1
2
C1132
1
2
C1131
1
2
C1122
1
2
C1121
1
2
C1130
1
2
C1129
1
2
C1191
1
2
C1194
1
2
C1103
1
2
C1102
1
2
C1111
1
2
C1110
1
2
C1109
1
2
C1104
1
2
C1108
1
2
C1159
1
2
C1160
1
2
C1161
1
2
C1162
1
2
C1163
1
2
C1164
1
2
C1165
1
2
C1166
1
2
C1154
1
2
C1155
1
2
C1156
1
2
C1152
1
2
C1151
1
2
C1184
1
2
C1170
1
2
C1171
1
2
C1174
1
2
C1173
1
2
C1172
1
2
C1183
1
2
C1181
1
2
C1182
1
2
C1101
1
2
C1100
1
2
C1123
1
2
C1117
1
2
C1105
1
2
C1107
1
2
C1106
1
2
C1126
1
2
C1125
1
2
C1135
1
2
C1134
1
2
C1133
1
2
C1138
1
2
C1137
1
2
C1136
1
2
C1150
1
2
C1153
1
2
C1157
1
2
C1158
1
2
C1175
1
2
C1190
1
2
C1193
1
2
C1177
1
2
C1176
1
2
C1199
1
2
C1198
1
2
R1100
12
R1101
12
U0600
AA9
AA11
AC11
U25
U27 V10
V12 V14
V16
W9 W11
W13
W15
AD10
W17
Y10
Y12 Y14
Y16
AE11
AF10
AF11 AF12
AG10
AG11 AG12
AG13
AA13
J13
J15
J17 J19
J21
J23 J25
J27
K12 K14
AA15
K16 K18
K20
K22 K24
K26
L9 L11
L13
L15
AA17
L17
L19 L21
L23
L25 L27
M10
M12 M14
M16
AB10
M18 M20
M22 M24
M26
N9 N11
N13
N15 N17
AB12
N19
N21
N23 N25
N27
P10 P12
P14
P16 P18
AB14
P20 P22
P24
P26 R9
R11
R13 R15
R17
R19
AB16
R21
R23 R25
R27
T10 T12
T14
T16 T18
T20
AC9
T22 T24
T26 U11
U13
U15 U17
U19
U21 U23
U0600
AA19 AA21
AC19
AC21 AC23
AC25 AC26
AC27
AD18 AD20
AD22
AD24
AA23
AD26
AE19
AE21 AE23
AE25 AE27
V18
V20 V22
V24
AA25
V26 W19
W21
W23 W25
W27 Y18
Y20
Y22 Y24
AA27
Y26
AB18 AB20
AB22
AB24 AB26
N29
AJ17 AJ22
AJ25
AJ26 T8
V28
V8 AF15
AJ28
M29 N28
Y8
AH20 AK20
AL19
AK30 AH29
AE29
AF29 AB29
AC29
AA7 AB7
AJ10
AJ11 G7
G8
G9 G10
G12
G13 G14
G15
AC7
G16
H7
J7 K7
L7
M7 P7
R7
AD7 AF7
AG7
AH7 AJ7
AJ8 AJ9
C1140
1
2
C1141
1
2
C1142
1
2
C1144
1
2
C1143
1
2
C1145
1
2
C1146
1
2
051-8773
10.0.0
11 OF 157
9 OF 48
9
35
35
9
35
8
35
35
6
45
5
35
35
7
35
35
35
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
0101
0100
J2A DEV
J2A AP
1111 RESERVED
1101 FMI0/1 4/4 CS
010
CURRENT SETTING ->
001
011
EVT
PROTO 2
100
0100 FMI0 2CS
0010 SPI0 W/TEST 0011 SPI1 W/TEST
0000 SPI0
0101 FMI0 4CS
0111 RESERVED 1000 FMI1 2 CS
BOOT_CONFIG[3:0]
0110 FMI0 4CS W/TEST
1010 FMI1 4CS W/TEST
1001 FMI1 4 CS
1100 FMI0/1 2/2 CS
FOR REFERENCE
0001 SPI1
PROTO 1 CHINA
PROTO 1 LOCAL
3. READ
BOARD REVISION
PROTO 0
000
BRD_REV[2-0]
1110 FMI0/1 4/4 CS W/TEST
2. ENABLE PU AND DISABLE PD
1. SET GPIO AS INPUT
S/W READ FLOW
0001
J2 DEV
J2 AP
J1 AP
0000
BOARD_ID[2]
BOARD_ID[1]
BOARD_ID[0]
BOARD_ID[3-0]
J1 DEV
BOARD_ID_3
BOARD ID
DEVELOPMENT_JTAG
2-WIRE DAP
SCAN DUMP
JTAG_DAP
PRODUCTION
3. READ
3. READ
JTAG_DAP
DEVELOPMENT_JTAG
S/W READ FLOW
JTAG
I2C PULL-UPS
0010 0011
1. SET GPIO AS INPUT
1110
1101
1100
FMI0/1 4/4 CS
BOOT_CONFIG[3-0]
BOOT_CONFIG[3] (GPIO29)
BOOT_CONFIG[0] (GPIO18)
BOARD_ID[3]
2. DISABLE PU AND ENABLE PD
FMI0/1 4/4 CS WITH TEST
FMI0/1 2/2 CS
BOOT_CONFIG[1] (GPIO25)
BOOT_CONFIG[2] (GPIO28)
S/W READ FLOW
BOOT CONFIG ID
2. DISABLE PU AND ENABLE PD
DEVELOPMENT_JTAG_TAP
1. SET GPIO AS INPUT
MF
5%
01005
1/32W
10K
J2
4
42
4
42
4
10 42 45
11 27 43
11 27 43
11 27 43
4
4
10 42 45
201
5% 1/20W
10K
MF
5% 1/20W
10K
201
MF
1/32W MF
5%
01005
10K
NOSTUFF
5%
01005
1/32W MF
DEV
10K
J2A
1/32W
10K
MF
5%
01005
SHORT-01005
NOSTUFF
SHORT-01005
NOSTUFF
NOSTUFF
SHORT-01005
100K
MF
1/32W
01005
5%
01005
5%
MF
1/32W
10K
1.00K
5% 1/32W MF 01005
1.00K
5% 1/32W MF 01005
1.00K
1/32W MF 01005
5%5%
01005
MF
1/32W
1.00K
5% 1/32W MF 01005
1.00K
5% 1/32W MF
1.00K
01005
NOSTUFF
201
5% MF
1/20W
10K
JTAG_DAP
100
DEVELOPMENT_JTAG_TAP
1/32W
0.00
0%
MF
01005
1/32W
0.00
0%
MF
DEVELOPMENT_JTAG_TAP
01005
100
JTAG_DAP
1/32W
0.00
0% MF
DEVELOPMENT_JTAG_TAP
01005
1/20W
10K
MF 201
5%
201
MF
1/20W
5%
10K
NOSTUFF
MF
10K
201
5% 1/20W
SYNC_DATE=N/A
AP: MISC & ALIASES
SYNC_MASTER=ALEX
=PP1V8_H4
PP3V0_SENSOR_FLT
I2C0_SCL_1V8
I2C1_SDA_1V8
I2C2_SDA_3V0_ALS
I2C1_SCL_1V8
AP_TESTMODE
BOARD_ID_1
BOOT_CONFIG_1
BOOT_CONFIG_2
=PP1V8_H4
=PP1V8_H4
BOOT_CONFIG_0
BOOT_CONFIG_3
JTAG_AP_TRST_L
AP_FAST_SCAN_CLK
VIDEO_EMI_C_Y
VIDEO_EMI_Y_PR
VIDEO_EMI_CVBS_PB
JTAG_AP_TDO
JTAG_AP_TDI
JTAG_AP_TRST_L
AP_TST_STPCLK
JTAG_AP_SEL
AP_HOLD_RESET
USB_AP_VBUS1
BOARD_ID_2
I2C2_SCL_3V0_ALS
I2C0_SDA_1V8
BOARD_ID_0
GPIO42_BRD_REV2 GPIO41_BRD_REV1 GPIO40_BRD_REV0
R1205
1
2
R1202
1
2
R1210
12
R1212
12
R1213
12
R1211
12
R1214
12
R1207
1
2
R1208
1
2
R1209
1
2
R1201
1
2
R1200
1
2
R1203
1
2
R1206
1
2
R1204
1
2
XW1201
12
XW1200
12
XW1202
12
R1260
12
R1261
12
R0706
1
2
R0705
1
2
R0704
1
2
R0703
1
2
R0702
1
2
R0701
1
2
051-8773
10.0.0
12 OF 157
10 OF 48
4 7
10 35
24 26 45
5
19 22 37 42
5
25 42
24 25 42
5
25 42
4
5
5
5
4 7
10 35
4 7
10 35
5
5
4
4
4
4
5
24 25 42
5
19 22 37 42
5
5
5
5
RX_VHIGH/USB_2D+ TX_VHIGH/USB_2D-
CH.3_OUT
CH.2_OUT
CH.1_OUT
VID_EN
USB_1D-
USB_1D+
SEL
DGNDAGND
CH.1_IN
CH.2_IN
CH.3_IN
USB_D-
USB_D+
RX_VLOW
TX_VLOW
VA_1
VDH
VA_0
VDL
OUT
OUT
OUT
OUT
IN
OUT
IN
BI
BI
BI
BI
IN
IN
IN
IN
IN
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
CVBSIN
BB USB <-> H4P FS USB
DOCK_BB_EN = 0:
DOCK_BB_EN = 1:
BB USB <-> DOCK SERIAL
NOTE:
H4P UART0 <-> DOCK SERIAL
NOTE: PLACE R0960-62 NEAR U0900
CIN
YIN
~15MA
THS7380IZSYR
UCSP
CRITICAL
10 27 43
10 27 43
75
1/20W
MF
1%
201
JTAG_DAP
201
MF
1%
75
JTAG_DAP
1/20W
201
1%
MF
75
JTAG_DAP
1/20W
10 27 43
0.1UF
10%
X5R 201
MF
100K
5%
1/32W
01005
27 42
27 42 15 42
15 42
30 42
30 42
4
42
4
42
7
43
7
43
7
43
01005
5%
NP0-C0G
56PF
0.1UF
10%
X5R 201
100K
5%
MF 01005
1/32W
5
37
1/32W
01005
5%
1.00M
MF
RADAR:9009078
U1300
343S0539 343S0520
AP: VIDEO BUFFER,BB USB MUXES
SYNC_DATE=12/10/2010
SYNC_MASTER=CHOPIN
=PP3V0_VIDEO_BUF
BUF_C_Y
USB11_ACC_RX_P
=PP3V2_S2R_USBMUX
BUF_Y_PR
PORT_DOCK_VIDEO_AMP_EN
DAC_AP_OUT1
DAC_AP_OUT3
DAC_AP_OUT2
VIDEO_EMI_CVBS_PB
VIDEO_EMI_Y_PR
VIDEO_EMI_C_Y
USB11_MUX_D0_N
DOCK_BB_EN
BUF_CVBS_PB
USB11_MUX_D0_P
USB11_ACC_TX_N
USB_BB_D_N
USB_BB_D_P
UART0_MUX_RXD
UART0_MUX_TXD
U1300
B2
B3
A3 A2
A4 A1 B4 B1
D3
E3
E1
E4
C2
D1
D4
F1
F2
F4
F3
C1
C4E2D2
C3
R1360
12
R1361
12
R1362
12
C1370
1
2
R1372
1
2
C1301
1
2
C1300
1
2
R1320
1
2
R1315
1
2
051-8773
10.0.0
13 OF 157
11 OF 48
35
43
35
43
43
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO0-1
IO7-1
IO6-1
IO3-1 IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0
IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1 WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQ
VSS
VCCQ
VDDI
TMSC
TCKC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO0-1
IO7-1
IO6-1
IO3-1
IO4-1
IO5-1
IO1-1
IO2-1
IO7-0
IO5-0 IO6-0
IO4-0
IO2-0
IO3-0
IO1-0
IO0-0
VCC
CLE1
CE1*
CLE0
CE0*
WE0*
ALE0
RE0
RE0*
DQS0*
R/B0*
DQS0
ALE1 WE1*
RE1
RE1*
DQS1
DQS1*
R/B1*
ZQ
VREF
VSSQ
VSS
VCCQ
VDDI
TMSC
TCKC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
NC
NC
NC
NC
NC
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
LEAVE VREF AS TP FOR MLB
DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA
TEST POINTS
LEAVE VREF AS TP FOR MLB
10UF
CERM-X5R 0402-1
20%
2.2UF
20%
0.1UF
10%
201
6
12 44
6
44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
44
6
12 44
6
12 44
6
12 44
6
12 44
MF
1/20W
1%
243
201
0.1UF
10%
201
CERM-X5R 0402-1
10UF
20%
0402-1
CERM-X5R
10UF
20%
0402-1
CERM-X5R
20%
10UF
LGA
OMIT
XXNM-XGBX8-MLC-PPN1.5-ODP
1.0UF
20%
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
MF
1/20W
5%
1K
NOSTUFF
201
1K
5% 1/20W MF
NOSTUFF
201
0402-1
CERM-X5R
10UF
20%
402-LF
2.2UF
20%
0.1UF
10%
201
0.1UF
10%
201
CERM-X5R 0402-1
10UF
20%
CERM-X5R 0402-1
10UF
20%
0402-1
CERM-X5R
10UF
20%
6
44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
OMIT
XXNM-XGBX8-MLC-PPN1.5-ODP
LGA
MF
1/20W
1%
243
201
1.0UF
20%
0201-MUR
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
MF
1/20W
5%
1K
NOSTUFF
201
1K
MF
5% 1/20W
NOSTUFF
201
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
5% 1/32W MF 01005
100K
01005
MF
1/32W
5%
100K
NAND_IO_3V3
MF
1/20W
0
5%
201
MF
0
5%
NAND_IO_1V8
201
1/20W
20%
1.0UF
1.0UF
20%
SYNC_DATE=N/A
NAND
SYNC_MASTER=MIKE
FMI0_AD<0>
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
VOLTAGE=1.8V
PPVCCQ_NAND
=PP3V3_NAND
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
MAX_NECK_LENGTH=3MM
PPVDDI_NAND_U1400
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.2MM
FMI1_AD<0>
FMI0_ALE
FMI0_WE_L
=PP3V3_NAND
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM
MIN_NECK_WIDTH=0.1MM
PPVDDI_NAND_U1410
PPVCCQ_NAND
VOLTAGE=1.8V
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM
FMI1_RE_N
FMI0_RE_N
FMI0_AD<1>
=PP1V8_NAND
FMI0_AD<7>
FMI1_CLE
FMI0_RE_N
FMI0_AD<2>
FMI0_AD<1>
FMI1_AD<2>
FMI1_AD<1>
FMI1_AD<0>
FMI0_AD<7>
FMI0_AD<6>
FMI0_AD<5>
FMI0_AD<4>
FMI0_AD<0>
FMI0_ALE FMI0_CLE
FMI0_WE_L
FMI0_CE1_L
FMI0_CLE
FMI0_ALE
FMI0_WE_L
FMI0_RE_N
FMI1_CLE
FMI1_ALE
FMI1_WE_L
FMI1_RE_N
FMI1_DQS_P
TP_VREF_SLOT1
FMI_ZQ_U1410
FMI_TCKC_U1400
FMI1_DQS_P
FMI1_ALE
FMI0_DQS_P
FMI0_CE0_L
FMI1_CE0_L
FMI0_AD<0>
FMI0_AD<3>
FMI0_AD<2>
FMI0_AD<4>
FMI1_AD<5>
FMI1_AD<4>
FMI1_AD<3>
FMI1_AD<6>
FMI1_AD<7>
FMI1_AD<1>
FMI1_AD<0>
FMI0_AD<5>
FMI0_CLE
FMI1_AD<2>
FMI1_RE_N
FMI1_ALE
FMI1_WE_L
FMI1_CLE
FMI_TMSC_U1400
FMI0_AD<6>
FMI1_AD<5>
FMI_ZQ_U1400
TP_VREF_SLOT0
FMI1_WE_L
FMI_TMSC_U1410
FMI_TCKC_U1410
FMI1_AD<7>
FMI1_AD<6>
FMI1_CE1_L
FMI0_DQS_P
NAND_SLOT1_RDYBSY_L
FMI1_AD<4>
FMI1_AD<3>
FMI0_AD<3>
NAND_SLOT0_RDYBSY_L
=PP3V3_NAND
TP1400
1
TP1401
1
TP1402
1
TP1403
1
TP1404
1
TP1405
1
TP1406
1
TP1407
1
TP1408
1
TP1409
1
C1432
1
2
C1431
1
2
C1430
1
2
R1474
1
2
C1424
1
2
C1422
1
2
C1421
1
2
C1420
1
2
U1410
C1
D2
A5
C5
A3
C3
H4 F4
M4 K4
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
E5
E7
B4 C7
D4 D6
OA0
OB0
B6F2M6N1N7
OC8
OD8
OE0
OF8G0OA8
OB8
G5
B2F6L3A7M2
OC0
OD0
OE8
OF0
G8
E3
E1
A1
C1470
1
2
R1473
1
2
R1472
1
2
C1412
1
2
C1411
1
2
C1410
1
2
C1404
1
2
C1402
1
2
C1401
1
2
C1400
1
2
U1400
C1
D2
A5
C5
A3
C3
H4
F4
M4
K4
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
E5
E7
B4
C7
D4
D6
OA0
OB0
B6F2M6N1N7
OC8
OD8
OE0
OF8G0OA8
OB8
G5
B2F6L3A7M2
OC0
OD0
OE8
OF0
G8
E3
E1
A1
R1454
1
2
C1450
1
2
R1453
1
2
R1452
1
2
C1413
1
2
C1414
1
2
C1434
1
2
C1433
1
2
C1406
1
2
C1405
1
2
C1426
1
2
C1425
1
2
R1455
1
2
R1475
1
2
R1401
12
R1400
12
C1451
1
2
C1471
1
2
051-8773
10.0.0
14 OF 157
12 OF 48
12 45
12 35
45
6
12 44
12 35
12 45
6
12 44
35
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
6
12 44
12 35
CK_1
DQ13_2
DQ14_2
DQ2_2
DQ1_2
DQ0_2
CKB_2 CKE_2
DQ21_1
DQ12_1
DQ11_1
DQ10_1
DQ0_1 DQ1_1
DQ2_1
DQ3_1 DQ4_1
DQ5_1
CSB_1
CKE_1
CKB_1
CA9_1
CA8_1
CA7_1
CA6_1
CA5_1
CA4_1
CA3_1
CA2_1
CA1_1
CA0_1
DQSB2_1
DQS2_1
DQ20_1
DQ19_1
DQ22_1 DQ23_1
DQ18_1
DQ16_1
DQ17_1
DQ15_1
DQ14_1
DQ13_1
DQ9_1
DQ7_1
DQ8_1
DQ6_1
DQ24_1
DQ31_1
DQ30_1
DQ31_2
DQ29_2
DQ30_2
DQ28_2
DQ26_2
DQ27_2
DQ25_2
DQ24_2
DQ23_2
DQ21_2
DQ22_2
DQ20_2
DQ19_2
DQ18_2
DQ17_2
DQ16_2
DQ15_2
DQ12_2
DQ11_2
DQ10_2
DQ8_2
DQ9_2
DQ6_2 DQ7_2
DQ5_2
DQ4_2
DQ3_2
DQSB3_2
DQS3_2
CA7_2
CA8_2
CA9_2
CK_2
DQS1_2
VREFCA_1 VREFCA_2
VREFDQ_1 VREFDQ_2
ZQ_1 ZQ_2
DQSB3_1
DQSB2_2
DQSB1_2DQSB1_1
DQSB0_2DQSB0_1
DQS3_1
DQS2_2
DQS1_1
DQS0_2DQS0_1
DQ29_1
DQ28_1
DQ27_1
DQ26_1
DQ25_1
CA6_2
CA5_2
CA4_2
CA3_2
CA2_2
CA1_2
CA0_2
DM0_1 DM1_1
DM2_1
DM3_1
CSB_2
DM0_2 DM1_2
DM2_2
DM3_2
DDR_1
DDR_2
SYM 1 OF 2
VDD1_3
VDD1_1
VSS55
VSS51
VSS6
VSS49
VSS4
VSS3
VDDQ33
VDDCA1
VDDCA2
VSS46
VDD1_0
VDD1_8
VDD1_5 VDD1_6
VDD1_7
VSS52
VSS0
VSS2
VSS7
VSS9
VSS10
VSS13
VSS18
VSS20
VSS32
VSS33 VSS34
VSS42
VSS43
VSS44
VSS29
VSS28
VSS27
VSS26
VSS25
VSS23
VSS22
VSS47
VSS53
VSS48
VSS50
VSS1
VSS12
VDD1_11
VDD2_3
VDD2_2
VDD1_2
VDD2_6
VDD2_7
VDD2_13 VDD2_14
VDD2_16
VDDQ27 VDDQ32
VDDQ31
VDDQ
VDDQ6
VDDQ23
VDDQ30
VDDQ22
VDDQ16
VDDQ34
VDDQ17 VDDQ21
VDDQ19
VDDQ24
VDDQ20
VDDQ28
VDDCA3 VDDCA4
VDDCA5
VDDCA6 VDDCA7
VDDCA8
VDD2_1
VDDQ26
VDDQ25
VSS24
VDD2_9
VDD2_8
VDDQ1
VDD1_9
VDD1_10
VDDCA9
VDDCA10
VDDQ29
VDDQ3
VDD1_4
VDD2_5
VDD2_4
VDD2_15
VSS41
VSS40
VSS39
VSS54
VSS36
VSS35
VDD2_10 VDD2_11
VDD2_12
VSS45
VDD2VDDQ
VDDCA
VDD1
VSS
SYM 2 OF 2
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC.
124578
B
D
87 6 5 4 3
C
B
A
NOTICE OF PROPRIETARY PROPERTY:
12
D
A
C
PAGE TITLE
SHEET
IV ALL RIGHTS RESERVED
R
D
DRAWING NUMBER
REVISION
BRANCH
6 3
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
0.22UF
20%
0.22UF
20%
XXXMB
BGA
H4G-DRAM
OMIT
XXXMB
H4G-DRAM
BGA
OMIT
4.3UF
4V
X5R-CERM
20%
603
10UF
20%
56PF
NP0-C0G
01005
5%
0.22UF
20%
56PF
NP0-C0G
01005
5%
0.01UF
10%
01005
0.22UF
20%
10V
10%
0.01UF
X5R 201
01005
0.01UF
10%
0.22UF
20%
0.22UF
20%
1UF
10%
402
10%
1UF
402
10%
1UF
402
402
10%
1UF
X5R-CERM
4V
4.3UF
20%
10UF
603
20%
603
10UF
20%
NP0-C0G
01005
56PF
5%
6.3V6.3V
X5R
0.22UF
20%
0.22UF
20%
0.22UF
20%
10%
01005
0.01UF
5%
56PF
01005
NP0-C0G
0.01UF
01005
10%
0.22UF
20%
10%
402
1UF
0.22UF
20%
10%
402
1UF
0.22UF
20%
603
10UF
20%
MF
1/20W
1%
240
201
MF
1/20W
1%
240
201
2.21K
1% 1/32W MF 01005
NOSTUFF
10%
01005
0.01UF
X5R
01005
MF
2.21K
1% 1/32W
01005
MF
1% 1/32W
2.21K
NOSTUFF
10%
01005
0.01UF
01005
2.21K
1%
MF
1/32W
01005
MF
1%
1.00K
1/32W
NOSTUFF
10%
01005
0.01UF
01005
1% 1/32W
1.00K
MF
01005
1/32W MF
1%
1.00K
NOSTUFF
0.01UF
10%
01005
0.01UF
10%
01005
01005
1.00K
MF
1% 1/32W
NOSTUFF
0.01UF
01005
10%
0.01UF
01005
10%
NOSTUFF
X5R
0.01UF
01005
10%
NOSTUFF
X5R
0.01UF
01005
10%
NOSTUFF
X5R
0.22UF
20%
SYNC_MASTER=MIKE
DDR 0 AND 1
SYNC_DATE=06/21/2010
PPVREF_DDR0_CA
NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
PPVREF_DDR0_CA
MAX_NECK_LENGTH=3 MM
VOLTAGE=0.6V
PPVREF_DDR0_DQ
NET_SPACING_TYPE=PWR
PPVREF_DDR0_DQ
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.3MM
MAX_NECK_LENGTH=3 MM
PPVREF_DDR1_CA
NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.2MM
PPVREF_DDR1_CA
PPVREF_DDR1_DQ NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.6V
PPVREF_DDR1_DQ
DDR1_DM<3>
DDR1_DM<1>
DDR0_DQ<8>
=PP1V2_VDDQ_DDR
DDR0_DQ<30>
DDR0_DQ<27>
DDR1_DQ<5>
DDR0_DQ<1> DDR0_DQ<2>
DDR0_DQ<3>
DDR0_DQ<4> DDR0_DQ<5>
DDR0_DQ<6>
DDR0_DQ<10>
DDR0_DQ<13>
DDR0_DQ<24>
DDR0_DQ<25> DDR0_DQ<26>
DDR0_DQ<28>
DDR0_DQ<12>
DDR0_DQ<11>
DDR0_DQ<0>
DDR0_DM<2>
DDR0_DM<3>
DDR0_DM<0>
DDR0_DQ<7>
DDR0_DQS_N<2>
=PP1V2_S2R_DDR
DDR1_DQ<30>
DDR1_DQ<26>
DDR0_DQ<18>
DDR1_DQ<25>
DDR0_DQ<14>
DDR0_DQ<9>
DDR0_DQ<15>
DDR1_DQ<7>
DDR1_DQ<6>
DDR1_DQ<4>
DDR1_DQ<3>
DDR1_DQ<2>
DDR1_DQ<1>
DDR1_DQ<0>
DDR1_DQ<8>
DDR1_DQ<9>
DDR1_DQ<10>
DDR1_DQ<11>
DDR1_DQ<12>
DDR1_DQ<14>
DDR1_DQ<15>
DDR1_DQ<13>
DDR0_DQS_P<3>
=PP1V2_S2R_DDR
=PP1V8_S2R_DDR
DDR1_DQS_P<0>
DDR1_DQS_N<1>
=PP1V2_VDDQ_DDR
=PP1V2_VDDQ_DDR
=PP1V2_S2R_DDR
=PP1V2_S2R_DDR
DDR0_CSN<0>
DDR1_DM<2>
DDR1_DM<0>
DDR0_CA<0>
DDR0_CA<1> DDR0_CA<2>
DDR0_CA<3>
DDR0_CA<4> DDR0_CA<5>
DDR0_CA<6>
DDR1_DQ<17>
DDR1_DQ<18>
DDR1_DQ<19>
DDR1_DQ<20>
DDR1_DQ<21>
DDR1_DQS_P<1>
DDR1_DQS_P<2>
DDR1_DQS_N<0>
DDR0_DQS_N<1>
DDR0_DQS_N<3>
DDR1_DQS_N<2>
DDR0_ZQDDR1_ZQ
DDR0_CK_P
DDR0_CA<9>
DDR0_CA<8>
DDR0_CA<7>
DDR0_DQS_P<2>
DDR0_DQ<29>
DDR0_DQ<31>
DDR0_DQ<23>
DDR1_DQ<22>
DDR1_DQ<23>
DDR1_DQ<16>
DDR1_DQ<24>
DDR1_DQ<31>
DDR1_DQ<27>
DDR1_DQ<28>
DDR1_DQS_P<3>
DDR1_DQS_N<3>
DDR1_CA<0>
DDR1_CA<1>
DDR1_CA<4>
DDR1_CA<5>
DDR1_CA<6>
DDR1_CA<7>
DDR1_CA<8>
DDR1_CA<9>
DDR1_CK_N
DDR1_CKE<0>
DDR1_CSN<0>
DDR1_DQ<29>
DDR0_CKE<0>
DDR0_CK_N
DDR1_CK_P
DDR0_DM<1>
DDR1_CA<3>
DDR1_CA<2>
DDR0_DQ<16>
DDR0_DQ<22>
DDR0_DQ<19>
DDR0_DQ<20> DDR0_DQ<17>
DDR0_DQS_P<1>
DDR0_DQS_N<0>
DDR0_DQS_P<0>
DDR0_DQ<21>
C1622
1
2
C1621
1
2
C1620
1
2
C1623
1
2
C1613
1
2
C1619
1
2
C1605
1
2
C1612
1
2
C1618
1
2
C1604
1
2
C1611
1
2
C1610
1
2
C1617
1
2
C1603
1
2
C1616
1
2
C1602
1
2
C1615
1
2
C1601
1
2
C1614
1
2
C1609
1
2
C1608
1
2
C1607
1
2
C1606
1
2
C1631
1
2
C1635
1
2
C1630
1
2
C1634
1
2
C1629
1
2
C1633
1
2
C1628
1
2
C1632
1
2
C1627
1
2
R1620
1
2
R1621
1
2
R1605
1
2
C1650
1
2
R1606
1
2
R1651
1
2
C1652
1
2
R1652
1
2
R1653
1
2
C1654
1
2
R1654
1
2
R1655
1
2
C1656
1
2
R1656
1
2
C1660
1
2
C1662
1
2
C1663
1
2
C1661
1
2
C1626
1
2
C1625
1
2
C1624
1
2
U1600
T15 G16
U15 G17 U14 H17
V14 H18
T13 J16
T9 N16
U9 N17
U8 P17 V8 P18
T7 R16
U12 K17
U11 L17 V13 J18
U13 J17
C12 K3
B10 M2 B16 G4
D7 T2
C15 G3
B8 P5
C8 P4
D8 P3 E8 P2
B7 R4
C7 R3 B18 B2
C18 C2
D18 D3 E18 D2
D15 G2
B17 E4 D17 E3
E17 E2
E16 F2
B6 T5
B5 U5
C5 U4
D5 U2
B4 V5
C4 V4
B14 H5
B3 V3
C3 V2
C14 H4
D14 H3 E14 H2
B13 J3
C13 J2
C9 N4
D9 N3
D13 J4
D10 M4
C16 F4
D6 T3
D12 K4
C10 M3
D16 F3
C6 T4
U10 M17 D11 L4
U7 R17
U1600
A2
B1
W17
U19
B11
F17
L2
M16
T10 U18
V17
V6
E11
W5
W16 W19
W18 V19
A3
T19
E19
L5
M18
U17 T18
V10
V16 V18
F18
T8
H16
K16
L16 P16
T11 T12
T14
V7
E1
U1
J5
K2
N2
R5
A8
A10
A14
A13
C17
C19
H1
E10
E15
B12
U3
W3
M1
P1
A17
D4
A16
A1
D19
E12 E13
F16
A4
G18
J1
K18 K5
L18 L3
M5
N18 N5
A6
R18
R2
T1 T17
U16
U6
B15
V11
V12
V15 T6
V9
W1 W4
A18
B19
C1
E7
G5
T16
V1
W2
A19
B9 C11
D1
051-8773
10.0.0
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