1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7
VICE MLB
2/4/2010 PVT
K48-DRI
3456
B
ECNREV
0000854735
DESCRIPTION OF REVISION
PRODUCTION RELEASED
12
CK
APPD
DATE
2010-02-04
PDFCSA
TABLE_TABLEOFCONTENTS_HEAD
D
C
B
1
TABLE_TABLEOFCONTENTS_ITEM
2
TABLE_TABLEOFCONTENTS_ITEM
3
TABLE_TABLEOFCONTENTS_ITEM
4
TABLE_TABLEOFCONTENTS_ITEM
5
TABLE_TABLEOFCONTENTS_ITEM
6
TABLE_TABLEOFCONTENTS_ITEM
7
TABLE_TABLEOFCONTENTS_ITEM
8
TABLE_TABLEOFCONTENTS_ITEM
9
TABLE_TABLEOFCONTENTS_ITEM
10
TABLE_TABLEOFCONTENTS_ITEM
11
TABLE_TABLEOFCONTENTS_ITEM
12
TABLE_TABLEOFCONTENTS_ITEM
13
TABLE_TABLEOFCONTENTS_ITEM
14
TABLE_TABLEOFCONTENTS_ITEM
15
TABLE_TABLEOFCONTENTS_ITEM
16
TABLE_TABLEOFCONTENTS_ITEM
17
TABLE_TABLEOFCONTENTS_ITEM
18
TABLE_TABLEOFCONTENTS_ITEM
19
TABLE_TABLEOFCONTENTS_ITEM
20
TABLE_TABLEOFCONTENTS_ITEM
21
TABLE_TABLEOFCONTENTS_ITEM
22
TABLE_TABLEOFCONTENTS_ITEM
23
TABLE_TABLEOFCONTENTS_ITEM
24
TABLE_TABLEOFCONTENTS_ITEM
25
TABLE_TABLEOFCONTENTS_ITEM
26
TABLE_TABLEOFCONTENTS_ITEM
27
TABLE_TABLEOFCONTENTS_ITEM
28
TABLE_TABLEOFCONTENTS_ITEM
29
TABLE_TABLEOFCONTENTS_ITEM
30
TABLE_TABLEOFCONTENTS_ITEM
31
TABLE_TABLEOFCONTENTS_ITEM
1
2
3
4
5
6
7
8
9
10
11
12
14
15
17
18
19
20
21
24
26
29
30
31
32
34
35
36
37
38
39
CONTENTS
TABLE OF CONTENTS
SYSTEM BLOCK DIAGRAM
POWER BLOCK DIAGRAM
CONFIGURATION OPTIONS
FUNC/ICT TEST/BRACKETS
AP MAIN
AP PWR,AP BB&WIFI
AP NAND & GPIO, NOR
AP RGB/CLCD,CAMERA
AP TVOUT
3G AND DEBUG MUXES
AP MISC & ALIASES
MLC
MLC ALIASES
Power Conn / Alias
DCIN POWER PATH
CHARGER
PMU
PMU
3.3V SUPPLY
LED BACKLIGHT CONTROLLER
DEBUG RESET ACCESS
GRAPE 1 OF 2
GRAPE 2 OF 2
LVDS CONNECTOR
MOTION,GYRO,COMPASS/THERM
USB MUX/BRK DET
L61 AUDIO INTERFACE
AUDIO: SPEAKER AMP
AUDIO:HEADPHONE OUT
AUDIO: LINE OUT DOCK ESD CIRCUIT
SYNC MASTER
ALEX
MARK
MARK
MARK
MARK
MARK
MARK
MARK
MARK
DATE
05/02/2009
12/04/2009
08/06/2009MIAMI
09/16/2009MIAMI
12/21/2009JAMES
12/21/2009JAMES
12/21/2009JAMES
12/21/2009JAMES
12/21/2009JAMES
12/21/2009JAMES
12/21/2009JAMES
09/16/2009MIAMI
09/16/2009MIAMI
12/04/2009
12/04/2009
12/04/2009
12/04/2009
12/04/2009
12/04/2009
12/04/2009
09/16/2009MIAMI
12/21/2009JAMES
12/21/2009JAMES
09/16/2009MIAMI
09/16/2009MIAMI
09/16/2009MIAMI
12/04/2009AUDIO
12/04/2009AUDIO
12/04/2009AUDIO
12/04/2009AUDIO
TABLE_TABLEOFCONTENTS_HEAD
32
TABLE_TABLEOFCONTENTS_ITEM
33
TABLE_TABLEOFCONTENTS_ITEM
34
TABLE_TABLEOFCONTENTS_ITEM
35
TABLE_TABLEOFCONTENTS_ITEM
36
TABLE_TABLEOFCONTENTS_ITEM
37
TABLE_TABLEOFCONTENTS_ITEM
38
TABLE_TABLEOFCONTENTS_ITEM
39
TABLE_TABLEOFCONTENTS_ITEM
40
TABLE_TABLEOFCONTENTS_ITEM
41
TABLE_TABLEOFCONTENTS_ITEM
42
TABLE_TABLEOFCONTENTS_ITEM
43FLASH
TABLE_TABLEOFCONTENTS_ITEM
44
TABLE_TABLEOFCONTENTS_ITEM
45
TABLE_TABLEOFCONTENTS_ITEM
46
TABLE_TABLEOFCONTENTS_ITEM
47
TABLE_TABLEOFCONTENTS_ITEM
48
TABLE_TABLEOFCONTENTS_ITEM
49
TABLE_TABLEOFCONTENTS_ITEM
50
TABLE_TABLEOFCONTENTS_ITEM
51
TABLE_TABLEOFCONTENTS_ITEM
52
TABLE_TABLEOFCONTENTS_ITEM
53
TABLE_TABLEOFCONTENTS_ITEM
CSAPDF
40
42
43
45
48
49
50
51
54
55
57
67
100
101
106
113
114
115
116
117
118
119
CONTENTS
AUDIO: AUDIENCE
AUDIO: DETECT/MIC BIAS
AUDIO: HP CONN
ALS CONNECTOR
I/O EXPANDER
DISPLAY PORT SWITCH
44-PIN LANDSCAPE DOCK CONN
60-PIN PORTRAIT DOCK CONN
BUTTONS CONNECTOR
3G CONNECTOR
PROX SENSOR
CONSTRAINTS
MORE CONSTRAINTS
PHYSICAL/SPACING RULES
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
Cross Reference Page
SYNC MASTER
AUDIO
AUDIO
AUDIO
JAMES
JAMES
JAMES
JAMES
MIAMI
MIAMI
MARKSIN
MIAMI
MIAMI
MIAMI
MIAMI
DATE
12/04/2009
12/04/2009
12/04/2009
09/16/2009MIAMI
12/21/2009
12/21/2009
12/21/2009
12/21/2009
09/16/2009
09/16/2009
10/14/2009
09/16/2009
09/16/2009
09/16/2009
09/16/2009
D
C
B
A
DRAWING
TITLE=U230
ABBREV=DRAWING
LAST_MODIFIED=Thu Feb 4 00:41:44 2010
87 6 5 421
3
DRAWING TITLE
VICE MLB
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
1 OF 119
SHEET
1 OF 53
SIZE
A
D
345678
21
Voltage Rails
VICE BLOCK DIAGRAM
D
COMPOSITE
COMP/SVIDEO
L. DOCK
PAGE 50
P. DOCK
PAGE 51
C
STERO SPEAKERS
VIDEO AMP
PAGE 10
VIDEO AMP
PAGE 10
DP MUX
PAGE 49
AMP
P37
COMPOSITE
COMP/SVIDEO
DISPLAYPORT
I2S0
MDDR
PG 10
PG 7
H3P
256MB
FMI0-1
PG 8
PG 9
I2C2
SERIAL BOOT
FLASH 8MBIT
PG 8
SPI0
NAND FLASH
8/16/32/64
MIPI->LVDS
MIPI
SPI1
PROX SENS.
MLC
PAGE 14-15
PAGE 57
PG 67
POWER PLANE
LVDS
GYRO SENSOR
PAGE 34
ALS SENSOR
PAGE 45
CAMERA SENSOR FLEX
LAND. 4099
PAGE 19
ON STATE
D
LCD PANEL
P32
C
GRAPE/GROUNDHOG
PAGE 30-31
MOTION SENSOR
PAGE 34
AMP
P37
B
HEADSET L
P39
MIKEY L.
P42
I2S AUDIO
CIRRUS L61
PG 36
PG 7
USB2.0
UART0
PG 6
SERIAL BUFF/MUX
PG 11
USB DOCK MUX
PG 35
UART
JTAG/UART
USB2.0
USB2.0
L. DOCK
PAGE 50
B
P. DOCK
PAGE 51
UART4
MICROPHONE
P39
UART1
SPI2
X15 MODULE
PAGE 55
HIGHWAY BOARD
I2C0
AMANDA PMU
PAGE 20
PG 7
PORTRAIT 4099
PAGE 19
A
COMPASS
PAGE 34
I2S1
I2S2
IO EXPANDER
PAGE 20
875 421
UART3
SDIO
X7 AIRPORT +BT
PAGE 51
HIGHWAY BOARD
SIZE
A
D
SYNC_MASTER=ALEX
PAGE TITLE
SYSTEM BLOCK DIAGRAM
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=05/02/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
2 OF 119
SHEET
2 OF 53
36
POWER BLOCK DIAGRAM
345678
21
DC INPUT PATH
BUCK / CHARGER
B9 ADAPTER (5V)
USB (5V)
D
USB(5V)
LTC4099
PAGE 19
VCC_MAIN/3.0-4.7V
EN
BUCK / CHARGER
LTC4099
PAGE 19
EN
1.2V POWER
RP200Z121D
LDO
PAGE 20
3V3 POWER
LTC3442
BUCK/BOOST
PAGE 24
1.2V/0.3A
D
3V3/1.2A
LED DRIVER
APP001
EN
BOOST
PAGE 26
C
LED/0.12A
C
GRAPE POWER
BATTERY PACK
EN
TPS61045
BOOST
PAGE 30
18V/1MA
3.0-4.2V
ASHLEY
B
PAGE 20-21
CORE/2.0A MAX
1V8/1.5A MAX
BUCKS
3V3_LAND_ACC/0.15A MAX
B
1V7_VA_VCP/0.10A MAX
3V0_OPTICAL/0.05A MAX
3V0_VIDEO/0.10A MAX
LDOS
3V1_AUDIO/0.25A MAX
3V3_PORT_ACC/0.15A MAX
3V0_IO/0.10A MAX
3V0_LCD/0.01A MAX
1V2_H3/0.30A MAX
3V0_HP_BIAS/0.20A MAX
A
875 421
3V0_GRAPE/0.15A MAX
1V1_H3_PHY/0.10A MAX
1V8_ALWAYS/0.002A MAX
36
SYNC_MASTER=MARK
PAGE TITLE
POWER BLOCK DIAGRAM
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8GB_FLASH
8GB_FLASH_SAM
BKLT_PLL
CAMERA
JTAG_2_WIRE
JTAG_5_WIRE
PRODUCTION
DEVELOPMENT
AUD10
MIKEY
INTERNAL_MIC
LANDSCAPE_DOCK
LEFT_HS
LINE_OUT_1
LINE_OUT_2
PORTRAIT_DOCK
SPEAKER
ADD DEVELOPMENT AND OTHER BOMS ONCE YOU GET BOM NUMBERS
345678
21
BOM OPTIONS
PROGRAMMABLE PARTS
QTY
PART#
DESCRIPTION
SCH AND BOARD P/N
QTY
PART#
051-8245SCH1
820-2740
PART#
085-1028
DESCRIPTION
SCHEM,VICE,MLB,K48
1
1
PCBA,VICE,MLB,K48
QTY
DESCRIPTION
DEV,VICE,MLB,K48
1
1
DEV,VICE,MLB,K48M
REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S)
PCB1
DEV1
DEV1K48M_DEV085-1133
BOM OPTION
BOM OPTION
BOM OPTION
K48_DEV
TABLE_5_HEAD
VICE
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
D
BOM
OPTIONS
BOM GROUP
BASIC
AUDIO
BOM OPTIONS
COMMON,ALTERNATE
LEFT_HS,SPEAKER,INTERNAL_MIC
C
USE SCHUTIL BOMCONFIG TO GENERATE CONFIG FILE.
PUT CONFIG FILE AT SAME LEVEL AS .CPM FILE
USE "READ BOM-CONFIG" BUTTON ON DMS TO READ IN BOMS
B
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
USE 825-6447
NEED MORE LINE ITEMS FOR OTHER CONFIGURATIONS
BARCODE LABEL/EEE CODES
PART#
825-7456
825-7456
825-7456
825-7456
825-7456
825-7456
DESCRIPTION
QTY
EEE FOR 639-0455 (16G)
1
EEE FOR 639-0601 (32G)
1
EEE FOR 639-0598 (64G)
1
EEE FOR 639-0602 (16G)M
EEE FOR 639-0599 (32G)M
1
EEE FOR 639-0600 (64G)M
1
REFERENCE DESIGNATOR(S)
EEE_BWY
EEE_D66
EEE_D61
EEE_D67
EEE_D62
EEE_D63
CRITICALBOM OPTION
CRITICAL
CRITICAL
CRITICAL
CRITICAL1EEE_16G_M
CRITICAL
CRITICAL
EEE_16G
EEE_32G
EEE_64G
EEE_32G_M
EEE_64G_M
C
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
B
A
SYNC_MASTER=MIAMI
PAGE TITLE
CONFIGURATION OPTIONS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=08/06/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
4 OF 119
SHEET
4 OF 53
SIZE
A
D
345678
21
D
NOSTUFF
J0501
TH
J0502
TH
J0503
TH
J0504
TH
1
NOSTUFF
1
NOSTUFF
1
NOSTUFF
1
SL-1.2X0.40-1.95X1.15
C
SL-1.2X0.40-1.95X1.15
SL-1.2X0.40-1.95X1.15
CRITICAL
J0500
MLB-MNT-TAB-K48
SM
1
2
3
4
SL-1.2X0.40-1.95X1.15
D
C
CRITICAL
B
1
J0510
TOP-SM
SHLD-K48-FENCE-MLB-TOP
SHLD-K48-FENCE-MLB-BOT
A
875 421
1
J0520
CRITICAL
BOT-SM
B
SIZE
A
D
SYNC_MASTER=MIAMI
PAGE TITLE
SYNC_DATE=09/16/2009
FUNC/ICT TEST/BRACKETS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
5 OF 119
SHEET
5 OF 53
36
345678
R0671
=PP1V8_SDRAM_H3
6 8
15
HSIC1_DATA
HSIC1_STB
HSIC2_DATA
HSIC2_STB
TESTMODE
RESETN
JTAG_SEL
JTAG_TRSTN
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRTCK
FUSE1_FSRC
CFSB
DDR1_CKEIN
TST_CLKOUT
TST_STPCLK
15
19 39
=PP1V8_ALWAYS
15 19
6
19 40
=PP1V8_SDRAM_H3
6 8
6
19 40
PP1V1_PLL3_F
PP1V1_PLL2_F
PP1V1_PLL1_F
PP1V1_PLL0_F
1
C0642
0.01UF
10%
10V
2
X5R
201
(INT PD)
(INT PU)
(INT PU)
(INT PU)
HSIC_DVSS
L26
HOME_L
6
ONOFF_L
RINGER_A
N17
HSIC_VDD121
1.2V
N16
PART NUMBER
339S0100339S0084
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
U0652
COMMENTS:
HYNIX DDR
TABLE_ALT_HEAD
TABLE_ALT_ITEM
D
=PP1V1_PLL
C
JTAGSEL
0 - PARALLEL
1 - DAISY-CHAIN (FOR USE WITH 5-WIRE JTAG)
PER RADAR #6755237
=PP3V3_H3_USB
6
B
15
1
R0617
10K
1%
1/20W
R0632
MF
201
2
100K
19 39
RESET_L
12
1%
1/20W
MF
201
1
R0688
42.2K
1%
1/20W
MF
201
2
1
C0618
1000PF
10%
16V
2
X7R
201
AP_DDR1_CKEIN_1V2
1
R0689
84.5K
1%
1/20W
MF
201
2
FL0607
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0606
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0605
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0604
80-OHM-0.2A-0.4-OHM
12
0201-1
=PP1V8_H3
6 7 9
12 15 37
NC_HSIC1_DATA
NC_HSIC1_STB
NC_HSIC2_DATA
NC_HSIC2_STB
RESET_1V8_N
12
AP_TRSTN
12
AP_TCK
6
39 44
AP_TMS
6
39 44
AP_TDI
6
12 44
NC_AP_TDO
12
NC_AP_RTCK
TP_TST_CLKOUT
1
C0647
1UF
10%
6.3V
2
CERM
402
1
C0645
1UF
10%
6.3V
2
CERM
402
1
C0643
1UF
10%
6.3V
2
CERM
402
1
C0606
1UF
10%
6.3V
2
CERM
402
R0664
R0677
R0786
R0602
1
C0648
0.01UF
10%
10V
2
X5R
201
1
C0646
0.01UF
10%
10V
2
X5R
201
1
C0644
0.01UF
10%
10V
2
X5R
201
1
C0608
0.01UF
10%
10V
2
X5R
201
JTAG_TAP
R0662
100K
12
NOSTUFF
R0624
3.92K
12
12
12
12
12
15
15
0
0
0
0
=PP1V1_HSIC
=PP1V2_HSIC
AP_JTAG_SEL
12
AP_TESTMODE
AP_CFSB
AP_DDR1_CKEIN
AP_TST_STPCLK
1
C0641
0.01UF
10%
10V
2
X5R
201
P25
R25
M27
M26
F23
B19
C18
B18
B15
D18
A19
C19
D19
F19
V26
N7
K20
J20
A
12 15 37
=PP1V8_H3
6 7 9
R0645
100K
12
R0646
100K
12
R0647
100K
12
AP_TCK
AP_TMS
AP_TDI
6
39 44
6
39 44
6
12 44
875 421
12
R0670
12
R0665
12
0.6MM
0.2MM
0.6MM
0.2MM
0.6MM
0.2MM
0.6MM
0.2MM
L27
E14
N18
HSIC_DVDD
HSIC_VDD122
PLL0_AVDD11
U0652
H3P
256MB-DDR-FC
FBGA
SYMBOL 1 OF 9
HSIC_VSS121
HSIC_VSS122
PLL0_AVSS11
PLL1_AVSS11
N19
E15
E13
220K
1%
1/20W
MF
201
220K
1%
1/20W
MF
201
100K
1%
1/20W
MF
201
D13
F15
N23
PLL2_AVDD11
PLL3_AVDD11
PLL1_AVDD11
CRITICAL
USB_VSSAC
PLL2_AVSS11
PLL3_AVSS11
N22
F14
N24
1
C0627
0.01UF
10%
10V
2
X5R
201
PPVDD330_USB_AP
0.6MM
0.2MM
P22
R20
USB_DVDD
USB_VDD330
USB_VSSA0
USB_DVSS
R24
R21
=PP1V8_SDRAM_H3
6 8
15
AUD_MIKEY_ENA
33
=PP1V1_USB
USB11_D+
USB11_D-
EHCI_PORT_PWR0
EHCI_PORT_PWR1
EHCI_PORT_PWR2
WDOG
USB_ANALOGTEST
USB_ID
USB_DP
USB_DM
USB_REXT
USB_VBUS
USB_BRICKID
BB_RST
12
12
15
R26
R27
Y10
Y9
AA9
F22
B12
XI0
A12
XO0
N20
R22
P26
P27
N21
N25
R23
1
R0630
100K
1%
1/20W
MF
201
2
1
R0631
100K
1%
1/20W
MF
201
2
JTAG_TRSTN_CTRL
1
R0721
100K
1%
1/20W
MF
201
2
1
C0640
1UF
10%
6.3V
2
CERM
402
AP_GPIO39_BRD_REV0
AP_GPIO40_BRD_REV1
AP_GPIO41_BRD_REV2
TP_USB_ANALOGTEST
USB_REXT
1
C0630
0.01UF
10%
10V
2
X5R
201
NC_USB11_DP
NC_USB11_DM
AP_WDOG
XTAL_24M_I
XTAL_24M_O
TP_USB_ID
USB_DP
USB_DM
1
R0642
44.2
1%
1/20W
MF
201
2
HOME_L
6
19 39
ONOFF_L
6
19 40
AUD_VOL_UP_L
40
AUD_VOL_DOWN_L
40
RINGER_A
6
19 40
AUD_SPKRAMP_MUTE_N
29
PORT_USB_CHINA_DET
27
BT_WAKE
39
LAND_USB_CHINA_DET
27
RADIO_ON
6
41
RESET_DET_N
41
IPC_SRDY
41
PMU_IRQ_L
19
RESET_L61_N
28
GRAPE_FW_DNLD_EN_L
23
TP_AUDIENCE_RESET_L
IO_XPNDR_INT_L
19 36
CODEC_IRQ_N
28
KEEPACT
6
19
GRAPE_RESET_N
23
AP_GRAPE_HOST_INT_N
23
GPS_STANDBY_L
41
COMPASS_RST_L
6
26 35
AP_GPIO25_BOARD_ID_1
12
FORCE_DFU
6
22
DFU_STATUS
6
AP_GPIO28_BOARD_ID_2
12
AP_GPIO29_BOARD_ID_3
12
GPS_SYNC
41
AP_GPIO32_4_DIAG
GYRO_INT_L
26
LO_LS_REF_SEL
30
COMPASS_INT_L
26 35
ACCEL_INT1_L
26
ALS_INT_L
35
ACCEL_INT2_L
26
PORT_DOCK_VIDEO_AMP_EN
10
TP_CAM_EN
R0680
0
201
12
=PP3V3_H3_USB
NOSTUFF
R0681
0
201
12
EHCI_PORT_PWR[0-2] NOT USED
PER MICHAEL FRANK (EMAIL 2/25/09)
27 44
27 44
12
12
12
=PP3V0_IO_USB
USB_VBUS
2
DZ0600
GDZT2R5.1B
GDZ-0201
1
AP_USB_BRICKID
F6
GPIO0
B6
GPIO1
B7
GPIO2
D9
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO_3V0
GPIO_3V1
6
15
15
JTAG_TAP_NOT
R0652
12
R0655
12
USB_BRICKID
256MB-DDR-FC
(INT PD)
(INT PD)
(INT PD)
(INT PD)
(INT PD)
(INT PD)
(INT PD)
(INT PD)
(INT PD)
0
5%
1/20W
MF
201
1M
1%
1/20W
MF
201
VBUS_P
D5
A6
A7
B9
E6
A9
C5
C9
C6
D6
F5
E5
F9
F3
F4
C10
F10
E10
A4
B4
E4
E2
D10
E9
L2
G1
G2
E3
B3
A3
B2
H2
L1
H1
E1
W24
W25
(NOSTUFF FOR SCAN DUMP CONFIG)
R0651
100K
12
1%
1/20W
MF
201
R0650
0
12
5%
1/20W
MF
201
36
CRITICAL
U0652
H3P
FBGA
SYMBOL 6 OF 9
SENSOR_CLK
SENSOR_RST
TMR32_PWM0
TMR32_PWM1
TMR32_PWM2
SMII_CLKSEL0
SMII_CLKSEL1
SMII_TXD
SMII_RXD
3.0V
SMII_SYNC
SMII_CLK
SMII_RRDY
SMII_SRDY
SMII_WAKE
SMII_PWR
3.0V
PMU_RESET_IN
C0607
18PF
5%5%
25V
NP0-C0G
201
16
19 27
1
2
W20
V21
R18
SPDIF
AB25
AB27
AB26
K18
K19
G18
J18
G19
K23
K21
K22
J19
H19
1
R0635
100K
1%1%
1/20W
MF
201
2
19
CRITICAL
Y0602
SM-2
24.000MHZ-16PF-60PPM
13
24
TP_CAM_SHUTDOWN_L
PORT_DK_DDIS_CHG
LAND_DK_DDIS_CHG
DP_SW_SHUTDOWN_L
1
R0633
100K
1%
1/20W
MF
201
2
1
R0636
100K
1/20W
MF
201
2
21
TP_CAM_CLK
GPS_RESET_L
AP_6MHZ_REFCLK
IO_XPNDR_RST_L
PROX_INT_L
AP_PT_DK_ADPTR
AP_LD_DK_ADPTR
USB_MUX_OE_L
USB_MUX_SEL
BACKLIGHT_EN
MLC_RESET_L
1
R0640
22
5%
1/20W
MF
201
2
24M_O
1
C0613
18PF
25V
2
NP0-C0G
201
41
36
42
12
12
17
17
DP_SW_SEL
37
37
27
27
21
13
1
R0637
100K
1%
1/20W
MFMF
201
2
SYNC_MASTER=JAMES
PAGE TITLE
1
R0638
100K
1%
1/20W
201
2
R0691
0
12
1
R0639
100K
1%
1/20W
MF
201
2
AP MAIN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
L61_6MHZ_REFCLK
COMPASS_RST_L
FORCE_DFU
DFU_STATUS
SYNC_DATE=12/21/2009
28 15
KEEPACT
RADIO_ON
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
6 OF 119
SHEET
6 OF 53
6
19
6
26 35
6
22
6
6
41
SIZE
D
C
B
A
D
345678
21
PLACE NEAR U0652
R0760
0
WLAN_SDIO_CLK
39 45
D
C
B
12
1/20W
WLAN_SDIO_DATA<0>
39 45
WLAN_SDIO_DATA<1>
39 45
WLAN_SDIO_DATA<2>
39 45
WLAN_SDIO_DATA<3>
39 45
WLAN_SDIO_CMD
39 45
H3_SDIO_CLK
7
FLASH_CLK
7
FLASH_DIN
12
7
FLASH_DOUT
7
FLASH_CS_N
7
AP_GRAPE_SCLK
23
AP_GRAPE_MOSI
23
AP_GRAPE_MISO
23
AP_GRAPE_CS_N
23
IPC_SCLK
41
IPC_MOSI
41
IPC_MISO
41
IPC_MRDY
41
12 15 37
17 19 26 28 33 36 44
17 19 26 28 33 36 44
44
44
12 13 17 26 35 44
12 13 17 26 35
AP_UART0_TXD
12
AP_UART0_RXD
12
AP_UART1_TXD
11
AP_UART1_RXD
11
AP_UART1_RTS_L
11
AP_UART1_CTS_L
11
AP_UART2_TXD
11
AP_UART2_RXD
11
BB_USART0_RXD_CTRL
11
UMTS_RXD_CTRL
11
AP_UART3_TXD
12
AP_UART3_RXD
12
AP_UART3_RTS_L
12
AP_UART3_CTS_L
12
AP_UART4_TXD
12
AP_UART4_RXD
12
MLC_WC_L
14
PROX_GPIO
42
H3_SDIO_CLK
5%
MF
201
1
R0720
100K
1%
1/20W
MF
201
2
=PP1V8_H3
6 7 9
I2C0_SDA_1V8
7
I2C0_SCL_1V8
7
I2C1_SDA_1V8
7
I2C1_SCL_1V8
7
I2C2_SDA_3V0
7
I2C2_SCL_3V0
7
7
J24
J25
J26
J27
K25
J21
V4
W7
V6
W3
V3
W8
U2
V2
AA2
AA1
V7
W6
1
R0700
1K
1%
1/20W
MF
201
2
Y27
V27
U1
Y2
V1
Y1
V5
W5
V10
V9
R3
P3
R1
AD5
AD2
AD6
W4
AD1
SDIO0_DATA0
SDIO0_DATA1
SDIO0_DATA2
SDIO0_DATA3
SDIO0_CMD
SDIO0_CLK
SPI0_SCLK
SPI0_MOSI
SPI0_MISO
SPI0_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPI1_SSIN
SPI2_SCLK
SPI2_MOSI
SPI2_MISO
SPI2_SSIN
UART0_TXD
UART0_RXD
UART1_TXD
UART1_RXD
UART1_RTSN
UART1_CTSN
UART2_TXD
UART2_RXD
UART2_RTSN
UART2_CTSN
UART3_TXD
UART3_RXD
UART3_RTSN
UART3_CTSN
UART4_TXD
UART4_RXD
UART4_RTSN
UART4_CTSN
1.8V SERIAL FLASH
A
FLASH_DIN
7
12
FLASH_CLK
7
SERIAL-SPI-8MB-1.8V
D3
WP*
E2
SI
D2
SCK
C2
HOLD*
875 421
CRITICAL
U0652
H3P
256MB-DDR-FC
FBGA
SYMBOL 5 OF 9
(INT PU)
1
R0701
1K
1%
1/20W
MF
201
2
CRITICAL
U0652
H3P
256MB-DDR-FC
FBGA
SYMBOL 7 OF 9
3.0V
3.0V
B2
VCC
U0808
WLCSP11
AT25DF081UUN
CRITICAL
GND
E3
1
R0702
1K
1%
1/20W
MF
201
2
I2S0_DIN
I2S0_DOUT
I2S0_BCLK
I2S0_LRCK
I2S0_MCK
I2S1_DIN
I2S1_DOUT
I2S1_BCLK
I2S1_LRCK
I2S1_MCK
I2S2_DIN
I2S2_DOUT
I2S2_BCLK
I2S2_LRCK
I2S2_MCK
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
I2C2_SDA
I2C2_SCL
1
R0703
1K
1%
1/20W
MF
201
2
UART5_RTXD
UART6_TXD
UART6_RXD
UART6_RTSN
UART6_CTSN
CS*
SO
NC
V8
AC5
AC6
AC3
AC4
B3
C3
A4
F1
F4
W21
W22
V23
V18
V20
V24
W19
V25
V15
AB22
R17
R16
Y26
AB23
W23
AB6
AB5
AB4
AB3
AD15
AC15
BATTERY_SWI
AP_UART6_TXD
AP_UART6_RXD
AP_UART6_RTS_L
AP_UART6_CTS_L
1
C0820
0.1UF
10%
6.3V
2
X5R
201
SFLASH_DOUT
I2S0_DIN
I2S0_DOUT
I2S0_BCLK
I2S0_LRCLK
TP_I2S0_MCK
I2S1_DIN
I2S1_DOUT
I2S1_BCLK
I2S1_LRCLK
I2S1_MCK
I2S2_DIN
I2S2_DOUT
I2S2_BCLK
I2S2_LRCK
TP_I2S2_MCK
I2C0_SDA_1V8
I2C0_SCL_1V8
I2C1_SDA_1V8
I2C1_SCL_1V8
I2C2_SDA_3V0
I2C2_SCL_3V0
=PP3V0_IO_H3
7
11 13 15 37
17 19
12
12
=PP1V8_NOR_FLASH
1
R0750
100K
1%
1/20W
MF
201
2
33
12
R0826
1%
1/20W
MF
201
12
12
12
12
12 44
12 44
12 44
12 44
12
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
7
17 19 26 28 33 36 44
7
17 19 26 28 33 36 44
7
44
7
44
7
12 13 17 26 35 44
7
12 13 17 26 35
12
12
15
(PU IN H3)
FLASH_CS_N
FLASH_DOUT
BB_I2S2_TX
BB_I2S2_RX
BB_I2S2_CLK
BB_I2S2_WA0
1
R0704
1K
1%
1/20W
MF
201
2
A1
A18
C15
A2
A23
AD26
AE22
AD9
AE17
AE2
AF10
AB13
AE9
AF1
41
41
41
41
1
R0705
1K
1%
1/20W
MF
201
2
7
7
AF11
AF23
AF16
AF17
AG12
AB14
AF24
AF27
AG23
AG26
AG27
AA17
AA10
AA11
AA15
AA26
AB11
AB17
AC11
AC13
AC17
AD11
AD17
AF2
AG1
AF4
AF7
AG2
B10
B11
B16
B17
B20
B21
B24
B26
B27
C11
C17
D26
D11
D17
E11
F26
E17
F11
F17
G10
G11
G15
H17
H26
G17
H11
H13
H15
J11
K13
K11
A26
A27
AB2
AB9
AC2
AC9
B1
B5
C2
B8
D2
F2
G9
J1
J2
J3
J4
J5
CRITICAL
U0652
H3P
256MB-DDR-FC
FBGA
VSS
(GPIO_3VX,UART0,CFSB,USB11)
(3.0V - FMI0_CEN[4-5],ENET)
BASE PKG
MDDR CKE
RETENTION
SYMBOL 8 OF 9
1.1V - 800MHZ
1.2V - 1GHZ
BOTTOM PKG
MDDR I/O
(3.0V - UART4)
(3.0V - I2C2)
(3.3V - FMI0)
(3.3V - FMI1)
(3.0V - SMII)
CORE
40 PINS
I/O
(1.2V)
VDDIO30
DDR0VDDQ
DDR1VDDQ
VDD
VDDIO18
I/O
VDDIOD
VDDIOD0
VDDIOD1
VDDIOD2
VDDIOD3
VDDIOD4
VDDIOD5
F13
N6
J10
J12
L12
N12
T12
T13
T14
T15
T16
T17
J13
J14
J15
J16
J17
J9
K10
K12
K9
L10
L13
L14
L15
L16
L17
L9
M10
M12
M9
N10
N13
N14
N15
P10
P12
R10
R12
R14
T10
U12
A10
A16
F1
N1
V22
W10
AB10
AC10
AD10
AE10
T21
U27
G13
H10
H9
J6
J7
J8
K8
N8
R8
AB15
W18
AD22
V19
F18
H18
1
C0718
0.22UF
20%
6.3V
2
X5R
201
C0724
1
0.22UF
20%
6.3V
2
X5R
201
0.22UF
20%
6.3V
X5R
201
1
C0774
27PF
5%
25V
2
NP0-C0G
201
C0732
C0745
1
0.47UF
20%
4V
2
CERM-X5R-1
201
C0755
1
0.47UF
20%
4V
2
CERM-X5R-1
201
C0731
1
2
PLACE THE 27PF IN PAIRS AROUND THE IC
C0700
1
2
1
C0760
82PF
5%
25V
2
CERM
0201
C0725
1
0.22UF
20%
6.3V
2
X5R
201
1
0.22UF
20%
6.3V
2
X5R
201
1
C0775
27PF
5%
25V
2
NP0-C0G
201
0.47UF
20%
4V
CERM-X5R-1
201
1
C0712
0.22UF
20%
6.3V
2
X5R
201
1
C0710
20%
6.3V
2
X5R
201
=PP1V2_SDRAM_MDDR
1
C0719
0.22UF
20%
6.3V
2
X5R
201
C0726
1
0.22UF
20%
6.3V
2
X5R
201
C0733
1
0.22UF
20%
6.3V
2
X5R
201
C0746
1
0.47UF
20%
4V
2
CERM-X5R-1
201
C0757
1
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C0776
27PF
5%
25V
2
NP0-C0G
201
C0701
1
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C0713
0.22UF
20%
6.3V
2
X5R
201
1
2
C0734
1
2
C0747
1
0.47UF
20%
4V
2
CERM-X5R-1
201
C0784
1
0.47UF
20%
4V
2
CERM-X5R-1
201
1
2
C0702
1
2
C0711
0.22UF0.22UF
20%
6.3V
X5R
201
8
C0727
1
0.22UF
20%
6.3V
2
X5R
201
0.22UF
20%
6.3V
X5R
201
C0777
27PF
5%
25V
NP0-C0G
201
0.47UF
20%
4V
CERM-X5R-1
201
1
C0714
0.22UF
20%
6.3V
2
X5R
201
15
C0728
1
0.22UF
20%
6.3V
2
X5R
201
C0735
1
0.22UF
20%
6.3V
2
X5R
201
C0748
1
0.47UF
20%
4V
2
CERM-X5R-1
201
C0785
1
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C0765
0.22UF0.22UF
20%
6.3V
2
X5R
201
C0703
1
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C0715
2
=PP3V3_NAND
1
C0758
4.7UF
20%
6.3V
2
X5R-CERM
402
1
C0749
2
C0786
1
2
0.22UF
20%
6.3V
X5R
201
C0729
1
2
C0736
1
0.22UF
20%
6.3V
2
X5R
201
0.22UF
20%
6.3V
X5R
201
0.47UF
20%
4V
CERM-X5R-1
201
1
C0766
20%
6.3V
2
X5R
201
1
2
C0704
1
0.47UF
20%
4V
2
CERM-X5R-1
201
0.22UF
20%
6.3V
X5R
201
C0750
1
0.22UF
20%
6.3V
2
X5R
201
C0787
1
0.47UF
20%
4V
2
CERM-X5R-1
201
C0779
0.1UF
10%
6.3V
X5R
201
1
C0723
4.7UF
20%
6.3V
2
X5R
402
8
15 43
1
2
1
C0737
27PF
5%
25V
2
NP0-C0G
201
1
C0767
0.22UF
20%
6.3V
2
X5R
201
1
2
1
C0705
1UF
10%
6.3V
2
CERM
402
=PP3V0_IO_H3
XW0740
C0730
0.22UF
20%
6.3V
X5R
201
1
C0751
0.22UF
20%
6.3V
2
X5R
201
C0798
1
2
=PP3V0_IO_H3
C0780
0.1UF
10%
6.3V
X5R
201
NOSTUFF
SM
12
PPVCORE_FB
PLACE THE 27PF IN PAIRS AROUND THE IC
1
2
0.47UF
20%
4V
CERM-X5R-1
201
1
C0720
2
C0738
27PF
5%
25V
NP0-C0G
201
20%
6.3V
X5R
201
1
C0706
1UF
10%
6.3V
2
CERM
402
1
2
7
11 13 15 37
1
C0739
5%
25V
2
NP0-C0G
201
C0752
10UF
20%
6.3V
X5R
603
C0789
1
0.47UF
20%
4V
2
CERM-X5R-1
201
1
C0721
0.22UF0.22UF
20%
6.3V
2
X5R
201
7
11 13 15 37
1
27PF
2
1
C0753
10UF
20%
6.3V
2
X5R
603
1
C0707
1UF
10%
6.3V
2
CERM
402
SYNC_MASTER=JAMES
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
36
CRITICAL
U0652
256MB-DDR-FC
SYMBOL 9 OF 9
TOP PKG
MDDR CORE
(1.8V)
TOP PKG
MDDR I/O
(1.2V)
Apple Inc.
R
H3P
FBGA
K14
K15
K16
K17
K2
K26
K3
K4
K5
K6
K7
L11
M11
M13
M14
M15
M16
M17
M2
N11
N2
N26
N3
N4
N5
N9
P11
P13
P14
VSS
P15
P16
P17
P2
P23
P24
P4
P5
P6
P9
R11
R13
R15
R2
R4
R5
R6
R7
R9
T11
T2
T26
U11
U13
U14
U15
U16
U17
U19
U22
U26
W17
W2
W26
W9
SYNC_DATE=12/21/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
8 OF 119
SHEET
8 OF 53
SIZE
D
C
B
A
D
345678
FL0907
80-OHM-0.2A-0.4-OHM
H3_DP_AVDD_AUX
0.4MM
0.2MM
H3_DP_AVDD
0.4MM
0.2MM
D
H3_DP_AVDDP0
0.4MM
0.2MM
H3_MIPID_0P4V
1
=PP1V8_MIPI
15
=PP1V1_MIPI_PLL
15
1
C0907
0.01UF
10%
10V
2
X5R
201
FL0900
80-OHM-0.2A-0.4-OHM
12
1
C0906
27PF
5%
25V
2
NP0-C0G
201
0201-1
1
C0905
0.1UF
10%
6.3V
2
X5R
201
1
C0904
27PF
5%
25V
2
NP0-C0G
201
PP1V1_MIPI_PHY
0.4MM
0.2MM
C0902
2.2NF
10%
10V
2
X5R
201
H3_DP_AVDDX
0.4MM
0.2MM
H3_DP_DVDD
0.4MM
0.2MM
H3_SMIA_VDD18
0.4MM
0.2MM
C
=PP1V1_MIPI
15
B
1
C0908
0.47UF
20%
4V
2
CERM-X5R-1
201
DIFF_MIC_SEL
34
H3_MIPID_DATA_P<0>
14 45
H3_MIPID_DATA_N<0>
14 45
H3_MIPID_DATA_P<1>
14 45
H3_MIPID_DATA_N<1>
14 45
H3_MIPID_DATA_P<2>
14 45
H3_MIPID_DATA_N<2>
14 45
H3_MIPID_DATA_P<3>
14 45
H3_MIPID_DATA_N<3>
14 45
H3_MIPID_CLK_P
14 45
H3_MIPID_CLK_N
14 45
TP_H3_MIPIC_DATA_P<0>
TP_H3_MIPIC_DATA_N<0>
TP_H3_MIPIC_DATA_P<1>
TP_H3_MIPIC_DATA_N<1>
TP_H3_MIPIC_CLK_P
TP_H3_MIPIC_CLK_N
1
C0903
0.01UF
10%
10V
2
X5R
201
AG13
AF3
AG6
AF5
AG5
AF13
AF12
AE13
AE14
AG3
AE6
AE5
AF6
AF8
AG8
AG9
AF9
MIPI_VSYNC
MIPID_DPDATA0
MIPID_DNDATA0
MIPID_DPDATA1
MIPID_DNDATA1
MIPID_DPDATA2
MIPID_DNDATA2
MIPID_DPDATA3
MIPID_DNDATA3
MIPID_DPCLK
MIPID_DNCLK
MIPIC_DPDATA0
MIPIC_DNDATA0
MIPIC_DPDATA1
MIPIC_DNDATA1
MIPIC_DPCLK
MIPIC_DNCLK
Y18
Y15
MIPI_VDD11
Y13
C23
V13
W13
MIPID_VDD18
MIPID_VDD11_PLL
MIPID_VREG_0P4V
DP_PAD_AVDD_AUX
U0652
H3P
256MB-DDR-FC
FBGA
SYMBOL 2 OF 9
E22
F24
E23
DP_PAD_AVDD0
DP_PAD_AVDD1
DP_PAD_AVDDP0
CRITICAL
C22
DP_PAD_AVDDX
AA18
AC14
G27
SMIA_VDD18
DP_PAD_DVDD
DP_PAD_DC_TP
DP_PAD_R_BIAS
SMIA_RX_DATA+
SMIA_RX_DATA-
SMIA_RX_CLK+
SMIA_RX_CLK-
H3_SMIA_VDD11
0.4MM
0.2MM
SMIA_VDD11
SWI_DATA
DP_HPD
DP_PAD_AUXP
DP_PAD_AUXN
DP_PAD_TX0+
DP_PAD_TX0-
DP_PAD_TX1+
DP_PAD_TX1-
AA19
R19
E27
E26
A22
E25
C27
C26
A25
B25
AD14
AD13
AF14
AG14
1
C0927
1UF
10%
6.3V
2
CERM
402
1
C0926
1UF
10%
6.3V
2
CERM
402
1
C0925
1UF
10%
6.3V
2
CERM
402
1
C0924
1UF
10%
6.3V
2
CERM
402
1
C0923
1UF
10%
6.3V
2
CERM
402
1
C0922
1UF
10%
6.3V
2
CERM
402
1
C0921
1UF
10%
6.3V
2
CERM
402
H3_DP_R_BIAS
1
C0913
0.1UF
10%
6.3V
2
X5R
201
1
C0912
0.1UF
10%
6.3V
2
X5R
201
1
C0911
0.1UF
10%
6.3V
2
X5R
201
1
C0910
0.1UF
10%
6.3V
2
X5R
201
1
C0909
0.1UF
10%
6.3V
2
X5R
201
1
C0901
0.1UF
10%
6.3V
2
X5R
201
80-OHM-0.2A-0.4-OHM
1
C0900
0.1UF
10%
6.3V
2
X5R
201
AP_SWI
TP_DP_ANALOG_TEST
1
R0920
4.99K
2
12
0201-1
FL0906
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0905
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0904
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0903
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0902
80-OHM-0.2A-0.4-OHM
12
0201-1
FL0901
12
0201-1
H3_DP_HPD
H3_DP_AUX_P
H3_DP_AUX_N
(ANALOG DC TEST PORT)
NOTE: 0.6V ANALOG REF
H3_DP_TX_P<0>
H3_DP_TX_N<0>
H3_DP_TX_P<1>
H3_DP_TX_N<1>
TP_CAM_SMIA_DATA_P
TP_CAM_SMIA_DATA_N
TP_CAM_SMIA_CLK_P
TP_CAM_SMIA_CLK_N
1%
1/20W
MF
201
37
37 45
37 45
37 45
37 45
37 45
37 45
=PP1V8_H3
=PP1V8_H3
=PP1V8_H3
=PP1V8_H3
=PP1V1_DPORT
=PP1V8_SMIA
=PP1V1_SMIA
12 15 37
6 7 9
12 15 37
6 7 9
12 15 37
6 7 9
12 15 37
6 7 9
12 15 37
15
15
15
=PP1V8_H3
6 7 9
R0952
0
12
5%
1/20W
MF
201
R0953
0
5%
1/20W
MF
12
201
1
2
AP_SWI_R
21
=PP3V3_MLC
1
A2
C0951
0.1UF
10%
6.3V
2
X5R
201
P/N 311S0487
C0950
0.1UF
10%
6.3V
X5R
201
SWI_BLCTRL
1
R0950
10K
5%
1/20W
MF
201
2
19
SAME PART AS APN:353S2652 BUT CE PREFERRED PART NUMBER
A1
VCCBVCCA
U0901
SN74AVCH1T45
BGA1
C1C2
AB
CRITICAL
B2
DIR
GND
B1
MLC_SWI
13 14 15 25
13
D
C
B
A
MIPI_VSS
DP_PAD_AVSS1
DP_PAD_AVSS0
DP_PAD_AVSS_AUX
B23
D22
AA13
E24
W15
875 421
DP_PAD_DVSS
DP_PAD_AVSSP0
DP_PAD_AVSSX
G26
D23
B22
SMIA_VSS18
Y19
36
SYNC_MASTER=JAMES
PAGE TITLE
AP RGB/CLCD,CAMERA
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/21/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
9 OF 119
SHEET
9 OF 53
SIZE
A
D
345678
FL1000
240-OHM-0.2A-0.8-OHM
=PP3V0_VIDEO_H3
15
D
=PP3V0_VIDEO_BUFFER
10 15
JTAG_DAP
R1003
75
12 39 45
DOCK2_C_Y
12 39 45
DOCK2_CVBS_PB
PORT_DOCK_C_Y
MAKE_BASE=TRUE
PORT_DOCK_COMP_PB
MAKE_BASE=TRUE
C
12 39 45
DOCK2_Y_PR
B
38 45
DOCK1_Y_PR
DOCK1_CVBS_PB
38 45
DOCK1_C_Y
38 45
PORT_DOCK_Y_PR
MAKE_BASE=TRUE
LAND_DOCK_Y_PR
MAKE_BASE=TRUE
LAND_DOCK_COMP_PB
MAKE_BASE=TRUE
LAND_DOCK_C_Y
MAKE_BASE=TRUE
12
1%
1/20W
MF
201
JTAG_DAP
R1004
75
12
1%
1/20W
MF
201
JTAG_DAP
R1043
75
12
1%
1/20W
MF
201
LANDSCAPE_DOCK
R1050
75
12
1%
1/20W
MF
201
LANDSCAPE_DOCK
R1051
75
12
1%
1/20W
MF
201
LANDSCAPE_DOCK
R1052
75
12
1%
1/20W
MF
201
45
PORT_COUT
45
PORT_CVBS_OUT
45
PORT_YOUT
=PP3V0_VIDEO_BUFFER
10 15
45
LAND_YOUT
LAND_CVBS_OUT
45
45
LAND_COUT
10
VIDEO_AGND
PORTRAIT_DOCK
1
C1026
0.1UF
10%
6.3V
2
X5R
201
LANDSCAPE_DOCK
1
C1030
0.1UF
10%
6.3V
2
X5R
201
CH.1OUT
CH.2OUT
CH.3OUT
U1009
THS7319
CH.1OUT
CH.2OUT
CH.3OUT
U1010
THS7319
CRITICAL
PORTRAIT_DOCK
VS+
BGA
CH.1IN
CRITICAL
CH.2IN
CH.3IN
GND
A2C2
LANDSCAPE_DOCK
VS+
BGA
CH.1IN
CH.2IN
CH.3IN
GND
A2C2
LANDSCAPE_DOCK
EN
EN
A1A3
B1B3
C1C3
B2
A1A3
B1B3
C1C3
B2
R1008
100K
R1053
100K
1/20W
PORT_DOCK_VIDEO_AMP_EN
1
5%
1/20W
MF
201
2
DAC_OUT3
DAC_OUT2
DAC_OUT1
LAND_DOCK_VIDEO_AMP_EN
1
5%
MF
201
2
10 45
10 45
10 45
(YIN)
(CVBSIN)
(CIN)
CIN
CVBSIN
YIN
10 45
DAC_OUT1
10 45
DAC_OUT2
10 45
DAC_OUT3
6
NOTE: PLACE R1005,R1046-47 NEAR U0652
8
12
0201
VIDEO_AGND
10
R1005
1
200
1%
1/20W
MF
201
2
R1046
1
200
1%
1/20W
MF
201
2
0.4MM
0.2MM
D14
C13
DAC_AVDD30D
DAC_AVDD30A
CRITICAL
1
C1020
0.1UF
10%
6.3V
2
X5R
201
1
C1028
1UF
10%
6.3V
2
CERM
402
1
C1071
0.1UF
10%
6.3V
2
X5R
201
U0652
H3P
256MB-DDR-FC
A15
DAC_OUT1
A14
DAC_OUT2DAC_IREF
B13
DAC_OUT3
R1047
1
200
1%
1/20W
MF
2
201
NOSTUFF
XW1000
SM
12
PART NUMBER
353S2684INTERSIL
ALTERNATE FOR
PART NUMBER
353S2493
BOM OPTION
FBGA
SYMBOL 3 OF 9
DAC_AVSS30D
DAC_AVSS30A2
DAC_AVSS30A1
B14
C14
D15
REF DES
U1009,U1010
COMMENTS:
DAC_VREF
DAC_COMP
E19
A13
E18
10
VIDEO_AGND
TABLE_ALT_HEAD
TABLE_ALT_ITEM
21
PP3V0_DAC_AVDD_A
1
C1014
0.1UF
10%
6.3V
2
X5R
201
DAC_VREF
DAC_IREF
DAC_COMP
0.3MM
0.175MM
1
R1012
6.34K
1%
1/20W
MF
201
2
1
C1015
0.1UF
10%
6.3V
2
X5R
201
D
C
B
A
SYNC_MASTER=JAMES
PAGE TITLE
AP TVOUT
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=12/21/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
10 OF 119
SHEET
10 OF 53
SIZE
A
D
345678
21
AP_UART1_CTS_L
7
7
D
BB_USART0_TXD
11 12
AP_UART2_RXD
7
12
UMTS_TXD
DOCK_UART_CTRL
19
U1100
74LVC2G125
2
A1
1
1OE*
5
A2
7
2OE*
VCC
SOT833
GND
K48M
8
CRITICAL
4
Y1
Y2
=PP1V8_SDRAM_MISC
1
C1100
2
6
3
11 15 36
0.1UF
10%
6.3V
X5R
201
LAND_DOCK_POD_TO_ACC
LAND_DOCK_ACC_TO_POD
1
R1101
1M
1%
1/20W
MF
201
2
11 38
11 38
=PP3V0_HP_DET_BIAS
1
R1100
100K
1%
1/20W
MF
201
2
15 27 33 34 36 39
AP_UART1_TXD
7
LAND_DOCK_P17
38
BB_USART0_RXD_CTRL
7
C
K48M
8
CRITICAL
VCC
U1101
74LVC2G126GT/S500
SOT833
AP_UART4_TXD_MUX
11 12
AP_UART4_TXD_MUX
11 12 11 38
2
A1Y1
1
1OE
5
A2
7
2OE
GND
R1130
12
1/20W
K48
201
6
3
Y2
4
0
5%
MF
LAND_DOCK_POD_TO_ACC
=PP3V0_IO_H3
1
C1101
0.1UF
10%
6.3V
2
X5R
201
AP_UART4_RXD_MUX
11 12
7
13 15 37
AP_UART2_TXD
7
LAND_DOCK_P14
38
UMTS_RXD_CTRL
7
B
K48
R1131
0
LAND_DOCK_ACC_TO_POD
11 38 11 12
12
5%
1/20W
MF
201
AP_UART4_RXD_MUX
AP_UART1_RTS_L
AP_UART1_RXD
7
K48M_DEVELOPMENT
1
R1154
100K
1%
1/20W
MF
201
2
K48M_DEVELOPMENT
1
R1155
100K
1%
1/20W
MF
201
2
K48M_PRODUCTION
1
I1
SELECTOR
3
I0
S
6
K48M_DEVELOPMENT
1
R1104
100K
1%
1/20W
MF
201
2
K48M_PRODUCTION
R1105
I1
1
SELECTOR
I0
3
S
6
K48M_DEVELOPMENT
1
R1106
100K
1%
1/20W
MF
201
2
BB_USART0_RTS_L
BB_USART0_CTS_L
R1103
0
12
5%
1/20W
MF
201
K48M_DEVELOPMENT
U1104
74LVC1G157
SOT891
5
VCC
MUX
OUTPUT
GND
2
0
12
5%
1/20W
MF
201
K48M_DEVELOPMENT
U1105
74LVC1G157
SOT891
5
VCC
MUX
Y
OUTPUT
GND
2
BB_USART0_TXD
4
Y
4
12
12
11 12
=PP1V8_SDRAM_MISC
K48M_DEVELOPMENT
1
C1104
0.1UF
10%
6.3V
2
X5R
201
BB_USART0_RXD
=PP1V8_SDRAM_MISC
K48M_DEVELOPMENT
1
C1105
0.1UF
10%
6.3V
2
X5R
201
UMTS_RXD
D
11 15 36
12
C
11 15 36
12
B
A
SYNC_MASTER=JAMES
PAGE TITLE
3G AND DEBUG MUXES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
BOARD_ID[2:0]
010 K48AP
011 K48 DEV
BOARD_REV[2:0]
000 PROTO3
SYNC_DATE=12/21/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
12 OF 119
SHEET
12 OF 53
SIZE
A
D
36
345678
PART#
341S2604
341S2606
=PP3V3_MLC_EEPROM
14
MLC
MLC_DEV
D
=PP3V3_MLC
9
13 14 15
25
1
C1416
82PF
5%
25V
2
C
NOSTUFF
PP1400
P4MM
SM
1
PP
NOSTUFF
PP1401
P4MM
SM
1
PP
NOSTUFF
PP1408
P4MM
SM
1
PP
NOSTUFF
PP1409
P4MM
SM
1
PP
NOSTUFF
PP1410
P4MM
SM
1
PP
NOSTUFF
PP1411
B
P4MM
SM
1
PP
NOSTUFF
PP1412
P4MM
SM
1
PP
CERM
0201
MLC_MIPID_CLK_P
MLC_MIPID_CLK_N
MLC_MIPID_DATA_P<3>
MLC_MIPID_DATA_N<3>
MLC_SWI
MLC_MIPID_DATA_P<0>
MLC_MIPID_DATA_N<0>
13 14
13 14
13 14
13 14
9
13 14
13 14
WHEN WC_L IS LOW, CAN WRITE TO EEPROM
WHEN WC_L IS HIGH, CANNOT WRITE TO EEPROM
MLC_2WC_L
13 14
FL1400
80-OHM-0.2A-0.4-OHM
12
0201-1
FL1401
80-OHM-0.2A-0.4-OHM
12
0201-1
FL1402
80-OHM-0.2A-0.4-OHM
12
0201-1
C1410
X5R-CERM
13
=PP3V3_MLC
9
13 14 15 25
4.7UF
6.3V
1
20%
2
402
NOSTUFF
R1408
100K
1/20W
R1402
100K
1/20W
MLC_DEV
Q1490
SSM3K15FV
SOD-VESM-HF
PP3V3_MLC_18LDO_12LDO
PP3V3_MLC_DIG_12LDO
1
C1413
0.1UF
20%
10V
2
CERM
402
1
1%
MF
201
2
1
1%
MF
201
2
A
1
R1497
100K
1%
1/20W
MF
201
2
3
D
1
GS
2
PP3V3_MLC_LVDS
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
C1411
4.7UF
X5R-CERM
1
C1404
2.2NF
10%
10V
2
X5R
201
1
R1403
100K
1%
1/20W
MF
201
2
R1406
20%
6.3V
402
10K
1/20W
201
R1407
MLC_WC
1
2
R1410
100K
1/20W
1
1%
MF
2
1
110K
1%
1/20W
MF
201
2
1
C1414
0.1UF
20%
10V
2
CERM
402
MLC_VREG_0V4
NC_MASTER_MIPI_CLK_P
NC_MASTER_MIPI_CLK_N
NC_MASTER_MIPI_DAT_P
NC_MASTER_MIPI_DAT_N
MLC_MIPID_CLK_P
13 14
MLC_MIPID_CLK_N
13 14
MLC_MIPID_DATA_P<0>
13 14
MLC_MIPID_DATA_N<0>
13 14
MLC_MIPID_DATA_P<1>
14
MLC_MIPID_DATA_N<1>
14
MLC_MIPID_DATA_P<2>
14
MLC_MIPID_DATA_N<2>
14
MLC_MIPID_DATA_P<3>
13 14
MLC_MIPID_DATA_N<3>
13 14
MLC_BIST
MLC_TEST
MLC_RESET_L
6
9
13
MLC_MONITOR0_PD
1
1%
MF
201
2
1
C1417
0.1UF
20%
10V
2
CERM
402
13
MLC_SWI
OMIT
VCC
U1401
M24C64
EEPROM
3
MLP
E2
2
E1
1
E0
7
WC*
65
C1412
4.7UF
20%
6.3V
X5R-CERM
402
NC_MONITOR1
NC_MONITOR2
NC_MONITOR3
VSS
1
2
SDASCL
THM_P
1
2
984
C1415
0.1UF
20%
10V
CERM
402
B3
M_VREG_0P4V
C1
M_DPCLK
C2
M_DNCLK
B1
M_DPDATA0
B2
M_DNDATA0
F1
S_DPCLK
F2
S_DNCLK
D1
S_DPDATA0
D2
S_DNDATA0
E1
S_DPDATA1
E2
S_DNDATA1
G1
S_DPDATA2
G2
S_DNDATA2
H1
S_DPDATA3
H2
S_DNDATA3
B7
BIST
B8
TEST
B5
RESET*
H6
SWI
H5
MONITOR0
G3
MONITOR1
G4
MONITOR2
G5
MONITOR3
DESCRIPTION
QTY
1
MLC EEPROM 54MHZ LVDS,2MHZ SWI
MLC EEPROM 100MHZ LVDS,2MHZ SWI
1
REFERENCE DESIGNATOR(S)
U1401
U1401
MLC EEPROM:RAW APN 335S0661
MLC_MUX_SDA_3V3
MLC_MUX_SCL_3V3
F3H8B4A2C6H4E5
VDD33A_OSC
VDD33A_18LDO
U1400
FBGA1
S6T2MLC
VSS12D_PLL
VSS33A_18LDO
A3
H3C4A1
14
14
D5
VDD33P_LVDS
VDD33A_12LDO_1
VDD33A_12LDO_0
VDD33A_12LDO_2
CAP_12LDO_0
CAP_12LDO_1
CAP_12LDO_3
CAP_12LDO_5
VSS33P_LVDS
VSS33A_12LDO_0
VSS33A_12LDO_1
VDD33A_LVDS
VDD33D_LVDS
CAP_18LDO
MLC_SCL
MLC_SDA
EDID_SCL
EDID_SDA
TCLKP
TCLKN
TAP
TAN
TBP
TBN
TCP
TCN
TDP
TDN
ROUT_LVDS
VSYNC
PWM
PPC
MONITOR4
MONITOR5
MONITOR6
VSS33A_LVDS
VSS33D_LVDS
D6F6E6
13
C3
E3
H7
A7
A4
A6
A5
A8
B6
C8
C7
G8
G7
F8
F7
E8
E7
D8
D7
C5
F5
D4
G6
F4
E4
D3
MLC_SDA_3V3
NC_LVDS_DATA_P<3>
NC_LVDS_DATA_N<3>
ROUT_LVDS
13 14 15 25
CRITICALBOM OPTION
CRITICAL
CRITICAL
I2C2_SDA_3V0
7
12 17 26 35 44
11 13 15 37
MLC_WC
13
=PP3V3_MLC
9
R1404
7
11 13 15 37
MLC_2WC_L
13 14
MLC_SCL_3V3
MLC_SDA_3V3
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CLK_P
LVDS_CLK_N
LVDS_DATA_P<0>
LVDS_DATA_N<0>
LVDS_DATA_P<1>
LVDS_DATA_N<1>
LVDS_DATA_P<2>
LVDS_DATA_N<2>
TP_MLC_VSYNC
NC_MONITOR4
NC_MONITOR5
NC_MONITOR6
=PP3V0_IO_H3
7
1
4.7K
5%
1/20W
MF
201
2
=PP3V0_IO_H3
13
13
25
25
25 45
25 45
25 45
25 45
25 45
25 45
25 45
25 45
LCD_BKLT_PWM
MLC_PPC_OUT
54MHZ_PANEL
100MHZ_PANEL
D2C2
C1
A1B1
B2
MLC_CAP_1V8LDO
MLC_CAP_1V2LDO_0
MLC_CAP_1V2LDO_1_3
875 421
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
SN74LVC2G66YZPR
A2
D1
SN74LVC2G66YZPR
A2
D1
MLC_PROD
R1499
0
12
5%
1/20W
MF
201
MLC_CAP_1V2_LDO_5
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
21
25
I2C MUXING CIRCUITRY
MLC_DEV
U1402
BGA
MLC_DEV
MLC_2MUX_SDA_3V3
U1402
BGA
STUFF R1499/R1498 TO BYPASS I2C SWITCHES
PLACE ON TOP OF PADS FOR U1402/U1403
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
1
C1400
4.7UF
6.3V
X5R-CERM
1
R1401
8.45K
1%
1/20W
MF
201
2
20%
2
402
C1401
36
13
4.7UF
X5R-CERM
MLC_SCL_3V3
1
20%
6.3V
2
402
I2C2_SCL_3V0
7
12 17 26 35
14
13
9
13 14 15 25
=PP3V0_IO_H3
7
11 13 15 37
MLC_WC
=PP3V3_MLC
R1405
7
11 13 15 37
MLC_2WC_L
13 14
WC_L
0
1
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
C1402
4.7UF
X5R-CERM
4.7K
5%
1/20W
MF
201
=PP3V0_IO_H3
USB MUX TABLE
SELECTED I2C
H3P CAN WRITE
MLC CAN READ
20%
6.3V
402
21
MLC_DEV
U1403
SN74LVC2G66YZPR
D2C2
A2
C1
D1
1
2
A1B1
B2
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR
1
2
SYNC_MASTER=MIAMI
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SN74LVC2G66YZPR
A2
D1
MLC_PROD
R1498
12
C1403
0
5%
1/20W
MF
201
4.7UF
X5R-CERM
R
BGA
MLC_DEV
U1403
BGA
1
20%
6.3V
2
402
Apple Inc.
MLC
MLC_2MUX_SCL_3V3
SYNC_DATE=09/16/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
14 OF 119
SHEET
13 OF 53
14
SIZE
D
C
B
A
D
345678
21
D
D
MLC ALIASES
H3_MIPID_CLK_P
9
45
H3_MIPID_CLK_N
9
C
45
H3_MIPID_DATA_P<0>
9
45
H3_MIPID_DATA_N<0>
9
45
H3_MIPID_DATA_P<1>
9
45
H3_MIPID_DATA_N<1>
9
45
H3_MIPID_DATA_P<2>
9
45 13
H3_MIPID_DATA_N<2>
9
45
H3_MIPID_DATA_P<3>
9
45
H3_MIPID_DATA_N<3>
9
45
MLC_MUX_SDA_3V3
13
MLC_MUX_SCL_3V3
13
MLC_2WC_L
13
=PP3V3_MLC_EEPROM
13
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MLC_MIPID_CLK_P
MLC_MIPID_CLK_N
MLC_MIPID_DATA_P<0>
MLC_MIPID_DATA_N<0>
MLC_MIPID_DATA_P<1>
MLC_MIPID_DATA_N<1>
MLC_MIPID_DATA_P<2>
MLC_MIPID_DATA_N<2>
MLC_MIPID_DATA_P<3>
MLC_MIPID_DATA_N<3>
MLC_2MUX_SDA_3V3
MLC_2MUX_SCL_3V3
MLC_WC_L
=PP3V3_MLC
13
13
13
13
13
13
13
13
13
13
13
7
9
13 15 25
C
SIZE
B
A
D
B
A
SYNC_MASTER=MIAMI
PAGE TITLE
MLC ALIASES
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=09/16/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
15 OF 119
SHEET
14 OF 53
POWER CONN / ALIAS
345678
21
LDO RAILS
PROGRAMMABLE ON/OFF
PP3V1_AUDIO
18 28 30
MAKE_BASE=TRUE
VOLTAGE=3.1V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
D
C
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V0_GRAPE
18
MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V0_VIDEO
18
MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V0_OPTICAL
18
MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V3_LAND_ACC
18 38
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V3_PORT_ACC
18 39
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V0_IO
18
MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
=PP3V1_AUDIO
=PP3V0_GRAPE
=PP3V0_GRAPE_Z1
=PP3V0_GRAPE_Z2
=PP3V0_GRAPE_MARIO1
=PP3V0_GRAPE_MARIO2
=PP3V0_GRAPE_MARIO3
=PP3V0_VIDEO_BUFFER
=PP3V0_VIDEO_H3
=PP3V0_DPMUX
=PP3V0_OPTICAL
=PP3V3_LAND_ACC
=PP3V3_PORT_ACC
=PP3V0_IO_SMS
=PP3V0_IO_H3
=PP3V0_IO_3V3
=PP3V0_IO_CHGR
=PP3V0_IO_USB
23 24
24
24
23
10
10
37
35
26 42
7
11 13 37
20
17
6
PPVCORE_H3
18
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V8_SDRAM
18
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V8_GRAPE
18 23
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V8
18 19
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PPLED_OUT
21 25
MAKE_BASE=TRUE
VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
PP5V1_OUT
18 21
MAKE_BASE=TRUE
VOLTAGE=5.1V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
BUCK RAILS
=PPVCORE_H3
=PP1V8_SDRAM_H3
=PP1V8_SDRAM_WL
=PP1V8_SDRAM_MISC
=PP1V8_SDRAM_1V2
=PP1V8_SDRAM_GPS
=PP1V8_GRAPE
=PP1V8_CAM
=PP1V8_SMS
=PP1V8_CHGR
=PP1V8_AUDIO
=PP1V8_H3
=PP1V8_NOR_FLASH
=PP1V8_SMIA
=PP1V8_MIPI
=PPLED_REG
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
=PP5V1_LED
7
6 8
39
11 36
18
41
26 42
17
28
6 7 9
7
9
9
12 37
CHARGER MAIN
PPVCC_MAIN
17
MAKE_BASE=TRUE
VOLTAGE=4.7V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
=VCC_MAIN_3V3
=VCC_MAIN_LED
=VCC_MAIN_AUDIO
=VCC_MAIN_WL
=VCC_MAIN_DOCK
=VCC_MAIN_ASH
20
21
22 29
39
38 39
18
BATTERY
BATT_POS_F
15 17 41
MAKE_BASE=TRUE
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
(REPLACE WITH 155S0243 IF NEED FILTER)
BATT_POS
17 15 17
=BATT_POS_F_3G
R1940
0
12
5%
1/4W
FF-LF
1206
BATT_POS_F
D
C
PP3V0_LCD
18 21
MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V2_AUDIENCE
18
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V0_HP_DET_BIAS
18
MAKE_BASE=TRUE
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
B
PP1V7_VA_VCP
18 28
MAKE_BASE=TRUE
VOLTAGE=1.7V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V2_H3
18
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V1_H3_PHY
18
MAKE_BASE=TRUE
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V8_ALWAYS
18
MAKE_BASE=TRUE
A
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP1V2_SDRAM
18
MAKE_BASE=TRUE
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
875 421
=PP3V0_LCD
=PP1V2_AUDIO
=PP3V0_HP_DET_BIAS
=PP1V7_VA_VCP
=PP1V2_HSIC
=PP1V2_VDDIOD_H3
=PP1V1_SMIA
=PP1V1_PLL
=PP1V1_MIPI
=PP1V1_MIPI_PLL
=PP1V1_DPORT
=PP1V1_HSIC
=PP1V1_USB
=PP1V8_ALWAYS
=PP1V2_SDRAM_MDDR
11 27 33 34 36 39
6
7
9
6
9
9
9
6
6
6
19
7 8
PP3V3_OUT
20
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
PP3V3_MLC_OUT
20
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
=PP3V3_LCD
=PP3V3_NAND
=PP3V3_H3_USB
=PP3V3_AUDIO
=PP3V3_MLC
GND
MAKE_BASE=TRUE
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=GND
MAX_NECK_LENGTH=5 MM
25
7 8
6
28
9
43
13 14 25
B
SIZE
A
D
SYNC_MASTER=MARK
PAGE TITLE
Power Conn / Alias
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
17 OF 119
SHEET
15 OF 53
36
TRUE
345678
21
SO-8 DUAL P/N FETS
DCIN POWER PATH
XW1820
SHORT-0201
LANDSCAPE
D
NOTE: PROTECTED UP TO 26.5V
USB_PWR_A
12
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
USB_PWRA_VIN
19
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
12
C
PORTRAIT
NOTE: PROTECTED UP TO 26.5V
USB_PWR_B
B
39
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
USB_PWRB_VIN
18
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
12
PORT_DK_ADPTR
LAND_DK_ADPTR
12
NOSTUFF
7
8
5
6
XW1810
SHORT-0201
12
NOSTUFF
CRITICAL
LANDSCAPE_DOCK
Q1820
SI4563DY
SOI
N-CH
P-CH
LANDSCAPE_DOCK
CRITICAL
PORTRAIT_DOCK
Q1810
SI4563DY
SOI
7
8
N-CH
5
6
P-CH
2
1
4
3
1
R1820
100K
1%
1/20W
MF
201
2
SSM3K15FV
LANDSCAPE_DOCK
CRITICAL
LANDSCAPE_DOCK
1
R1821
10K
1%
1/20W
MF
201
2
2
1
4
3
PORTRAIT_DOCK
R1810
100K
1/20W
USB_PWRA_GATE
Q1821
SOD-VESM-HF
201
PORTRAIT_DOCK
CRITICAL
A
PORTRAIT_DOCK
1
R1811
10K
1%
1/20W
MF
201
2
875 421
C1820
0.01UF
10%
10V
X5R
201
1
GS
USB_PWRB_GATE
1
C1810
0.01UF
1%
MF
2
Q1811
SSM3K15FV
SOD-VESM-HF
LAND_DK_OVSENS
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=ANLG
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
1
2
1
CRITICAL
D1810
1SS418
SOD-723-HF
2
XW1800
SHORT-0201
12
NOSTUFF
NOSTUFF
R1822
470K
1%
1/20W
MF
201
17
5
4
12
VBUS_P
PORT_DK_VBUS
(PULLUP ON PAGE 19)
PORT_DK_STAT
1%
1/10W
MF-LF
603
DOCK_VBUS
13
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=6V
CRITICAL
DZ1800
MMBZ5232B-350MW
5.6V ZENER
SOT23
17
17
18
6
17
17
SYNC_MASTER=MARK
PAGE TITLE
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
36
MOSFET
CHANNEL
RDS(ON)
IMAX
VGS MAX +/- 16V
SO-8 DUAL P/N FETS
MOSFET
CHANNEL
RDS(ON)
IMAX8 A
VGS MAX
DCIN POWER PATH
Apple Inc.
R
SI4563DY
N-TYPE
15 MOHM @4.5V
8 A
SI4563DY
P-TYPE
25 MOHM @-4.5V
+/- 16V
SYNC_DATE=12/04/2009
DRAWING NUMBER
REVISION
BRANCH
PAGE
SHEET
051-8245
B.0.0
18 OF 119
16 OF 53
SIZE
D
C
B
A
D
345678
NOSTUFF
PP1900
P4MM
SM
1
PP
PORT_DK_VBUS
16
DZ1900
GDZT2R6.8
GDZ-0201
CRITICAL
12
PORT_OVP_B
1
R1916
D
20K
1%
1/20W
MF
201
2
15
C1901
0.01UF
17
8
IN
6
IN
=PP1V8_CHGR
1
10%
10V
2
X5R
201
BATT_NTC_CONN
PORT_DK_HI_I
PORT_DK_DDIS_CHG
C
LAND_DK_VBUS
16
DZ1950
GDZT2R6.8
GDZ-0201
CRITICAL
12
LAND_OVP_B
1
R1966
20K
1%
1/20W
MF
201
2
=PP3V0_IO_CHGR
15
0.01UF
17
1
10%
10V
2
X5R
201
BATT_NTC_CONN
C1951
3
CRITICAL
1
Q1904
ZXTN26020DMF
DFN1411-3
2
(MAKE SURE THERE IS A PULLUP)
R1930
10K
12
1%
1/20WMF201
NOSTUFF
1
R1902
10K
1%
1/20W
MF
201
2
R1912
100K
1/20W
3
CRITICAL
1
Q1954
ZXTN26020DMF
DFN1411-3
2
(CHANGE I2C BUS)
(MAKE SURE THERE IS A PULLUP)
(FIGURE OUT NTC BIAS VALUE)
1%
MF
201
B
LAND_DK_HI_I
8
IN
LAND_DK_DDIS_CHG
6
IN
R1962
100K
1%
1/20W
MF
201
16
OUT
7
19 26 28 33 36 44
IN
7
19 26 28 33 36 44
IN
19
OUT
R1903
3.01K
PORT_DK_CLPROG_F
1
R1914
100K
1/20W
2
16
OUT
7
12 13 26 35
IN
7
12 13 26 35 44
IN
19
OUT
R1953
3.01K
LAND_DK_CLPROG_F
1
R1964
100K
1/20W
2
CRITICAL
1
C1900
10UF
10%
25V
2
X5R
805
PORT_DK_OVGATE
PORT_DK_OVSENS
16
(PULLUPS ON PAGE 10)
I2C0_SCL_1V8
(PULLUPS ON PAGE 10)
I2C0_SDA_1V8
PORT_PMU_IRQ_L
PORT_DK_CLPROG_R
1
1
R1911
1%
1/20W
MF
201
2
2
(1.78K OHM FOR 2.1A)
(3.09K OHM FOR 1.26A)
1
1%
MF
201
2
1
GS
CRITICAL
1
C1950
10UF
10%
25V
2
X5R
805
LAND_DK_OVGATE
LAND_DK_OVSENS
16
(PULLUPS ON PAGE 10)
I2C2_SCL_3V0
(PULLUPS ON PAGE 10)
I2C2_SDA_3V0
LAND_PMU_IRQ_L
LAND_DK_CLPROG_R
1
1
R1961
1%
1/20W
MF
201
2
2
(1.78K OHM FOR 2.1A)
(3.09K OHM FOR 1.26A)
1
1%
MF
201
2
1
GS
C1906
0.01UF
4.42K
1%
1/20W
MF
201
D
C1956
0.01UF
4.42K
1%
1/20W
MF
201
D
10%
10V
X5R
201
R1900
6.04K
12
1%
1/16W
R1901
12
5%
1/20W
R1915
12
1/20W
1
C1902
0.1UF
10%
25V
2
X5R
402
3
Q1902
SSM3K15FV
SOD-VESM-HF
2
10%
10V
X5R
201
R1950
6.04K
12
1%
1/16W
R1951
12
5%
1/20W
R1965
12
5%
1/20W
1
C1952
0.1UF
10%
25V
2
X5R
402
3
Q1952
SSM3K15FV
SOD-VESM-HF
2
1
2
MF-LF
402
0
MF
201
17
0
MF5%
201
1
2
MF-LF
402
0
MF
201
17
0
MF
201
1
R1910
17.4K
1%
1/20W
MF
201
2
PD_OVSENS_R
NET_SPACING_TYPE=ANLG
VOLTAGE=6V
PORT_DK_IRQ_L
CHGR_NTCBIAS
PORT_DK_CLPROG
PORT_DK_PROG
1
R1960
17.4K
1%
1/20W
MF
201
2
LD_OVSENS_R
NET_SPACING_TYPE=ANLG
VOLTAGE=6V
LAND_DK_IRQ_L
CHGR_NTCBIAS
LAND_DK_CLPROG
LAND_DK_PROG
MAIN SUPPLY/BATTERY CHARGER
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=6.1V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
1
OVGATE
13
VBUS
20
OVSENS
15
DVCC
16
SCL
17
SDA
8
IRQ*
3
NTCBIAS
2
NTC
19
CLPROG
7
1
R1904
825
1%
1/20W
MF
201
2
1
GS
1
R1954
825
1%
1/20W
MF
201
2
1
GS
PROG
1
R1913
2.94K
1%
1/20W
MF
201
2
PORT_DK_PROG_R
(825 OHM FOR 1.5A)
(644 OHM FOR 0.16A FOR DEEP DISCHG)
3
D
Q1903
SSM3K15FV
SOD-VESM-HF
2
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=6.1V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
1
OVGATE
13
VBUS
20
OVSENS
15
DVCC
16
SCL
17
SDA
8
IRQ*
3
NTCBIAS
2
NTC
19
CLPROG
7
PROG
1
R1963
2.94K
1%
1/20W
MF
201
2
LAND_DK_PROG_R
(825 OHM FOR 1.5A)
(644 OHM FOR 0.16A FOR DEEP DISCHG)
3
D
Q1953
SSM3K15FV
SOD-VESM-HF
2
U1900
LTC4099
QFN
CRITICAL
GND
9
NOSTUFF
PP1950
U1950
LTC4099
QFN
CRITICAL
GND
9
THRML
P4MM
THRML
IDGATE
BATSENS
PAD
21
SM
1
PP
IDGATE
BATSENS
PAD
21
WALL
ACPR*
VOUT
WALL
ACPR*
VOUT
BAT
BAT
Q1900
2
CMLDM8002AG
SOT563
1
S
4
NC
VC
5
18
NC
PORT_DK_SW
14
SW
DIDT=TRUE
12
10
11
6
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
PORT_DK_IDGATE
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=ANLG
C1907
1000PF
10%
16V
X7R
201
CRITICAL
L1900
3.3UH-3.25A
12
IHLP2525AH-SM
DCR=60.1 MOHM
1
2
4
PORT_DK_WALL
123
S
G
D
RDSON=0.015@VGS=-2.5V
5
ID=7.8A
R1905
12
1%
1/20W
17
100K
MF
201
CRITICAL
Q1901
SI7107DN
PWRPK-1212-8
(NEEDED TO DISCHARGE BEYOND 2A)
G
D
6
PPVCC_MAIN_FUSE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=4.7V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
1
C1903
22UF
20%
6.3V
2
X5R-CERM
603
1
C1904
0.1UF
10%
6.3V
2
X5R
201
(MAKE SURE WE HAVE A LARGE COPPER
POUR TO DISSIPATE HEAT)
Q1900
5
CMLDM8002AG
SOT563
S
4
4
VC
NC
5
18
NC
LAND_DK_SW
14
SW
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
12
10
LAND_DK_IDGATE
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
11
NET_SPACING_TYPE=ANLG
C1957
1000PF
6
10%
16V
X7R
201
ECHGR_BATTSNS
NET_SPACING_TYPE=ANLG
CRITICAL
L1950
3.3UH-3.25A
12
IHLP2525AH-SM
DCR=60.1 MOHM
1
2
4
LAND_DK_WALL
123
S
G
D
RDSON=0.015@VGS=-2.5V
5
ID=7.8A
R1955
12
1%
1/20W
17
100K
MF
201
CRITICAL
Q1951
SI7107DN
PWRPK-1212-8
(NEEDED TO DISCHARGE BEYOND 2A)
G
D
3
PPVCC_MAIN_FUSE
1
C1953
22UF
20%
6.3V
2
X5R-CERM
603
BATT_POS
1
C1954
0.1UF
10%
6.3V
2
X5R
201
7
19
BI
1
2
1
2
BATTERY_SWI
BATT_NTC_CONN
17
NET_SPACING_TYPE=ANLG
1
R1906
470K
1%
1/20W
MF
201
2
LAND_DK_STAT
LAND_DK_WALL
C1905
1000PF
10%
16V
X7R
201
1
R1956
470K
1%
1/20W
MF
201
2
PORT_DK_STAT
PORT_DK_WALL
C1955
1000PF
10%
16V
X7R
201
16
17
16
17
240-OHM-0.2A-0.8-OHM
TP1900
A
TP-1P0-TOP
NOSTUFF
FUNC_TEST=TRUE
PART NUMBER
110S0550
CHANGE TO A SMALLER FUSE FOR H3
F1900
5AMP-32V
12
FL1900
12
0201-1
R1941
0
12
5%
1/20W
1
MF
201
BATT_POS_F
C1922
33PF
NP0-C0G
OMIT
0603
CRITICAL
C1910
150UF
TANT-1
1
C1908
22UF
20%
6.3V
2
X5R-CERM
603
1
R1907
0.5
1%
1/16W
MF
402
2
1
5%
25V
2
201
15 17
RES,FF,0 OHM,1/10W,0603,5%SMD,LF,0.020
NOSTUFF
CRITICAL
C1911
150UF
6.3V
TANT-1
B15G
BATT_POS
1
C1909
22UF
20%
6.3V
2
X5R-CERM
603
SM
1
5%
25V
2
201
DESCRIPTION
NOSTUFF
CRITICAL
1
C1912
150UF
20%
2
15
C1924
1000PF
20%
6.3V
TANT-1
B15G
(REPLACE SENSE SHORTS WITH 0 OHM RESISTORS TO REMOVE AMANDA???)
R1920
0
12
5%
1/20W
MF
201
NOSTUFF
R1921
0.050
12
1%
1/6W
MF-HF
402
BATT_SWI_CONN_R
BATT_NTC_CONN_R
NET_SPACING_TYPE=ANLG
1
C1925
82PF
10%
16V
X7R
201
25V
2
CERM
0201
QTY
1
1
20%
6.3V
2
B15G
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
VOLTAGE=4.2V
BATT_POS_RC
(ONLY NEEDED WHEN BATTERY ISN’T PRESENT)
(CAN REMOVE FOR PRODUCTION)
XW1900
12
C1923
33PF
NP0-C0G
21
REFERENCE DES
SYSTEM CURRENT 3.0A MAX
1
C1913
27PF
5%
25V
2
NP0-C0G
201
NOSTUFF
1
C1938
0.1UF
10%
6.3V
2
X5R
201
NOTE:
F1900
PPVCC_MAIN
1
2
XW1920
12
SM
CRITICAL
CRITICAL
15
BATTSNS
NET_SPACING_TYPE=ANLG
BATTSNS_S
NET_SPACING_TYPE=ANLG
BATT_VCC_CURSNS
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
BOM OPTION
18
18
18
VERIFY PINOUT OF
BATTERY CONNECTOR
BATT_POS_F
VOLTAGE=4.2V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
1
5%
2
APN:998-2616
CRITICAL
J1900
BATT-K48
FC-SM
1
2
3
4
NOSTUFF
15 17
D
C
B
A
SYNC_MASTER=MARK
PAGE TITLE
CHARGER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
19 OF 119
SHEET
17 OF 53
SIZE
A
D
Q2000
CMLDM8002AG
SOT563
3
USB_PWRB_VIN
DS
G
R2003
0
12
USB_PWRB_VIN_GATE
D
5%
1/20WMF201
(REVERSE VOLTAGE PROTECTION)
5
USB_PWRB_VIN_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
4
C2043
NOSTUFF
R2019
12
5%
DOCK_VBUS
16
=VCC_MAIN_ASH
15 18
(CHECK WHICH NEED TO BE TIED TO 1.8V???)
PP1V8_SDRAM
15 18
1/16W
R2020
12
5%
1/20WMF201
C
(CAN I LEAVE VDD_VIB UNCONNECTED TO REDUCE STATIC POWER DRAIN?)
B
R2031
100K
1%
1/20W
MF
201
10UF
12
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
20%
VOLTAGE=5V
6.3V
NET_SPACING_TYPE=PWR
X5R
MAX_NECK_LENGTH=3 MM
603
0
MF-LF
402
0
27 16
1
TP_PMU_CHG_OUT
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
2
VOLTAGE=4.7V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
TP_VSW_CHG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
(250MA; 2.5-3.6V; CAN BE USED IN HIB; CAN BE 300MA BYPASS)
(150MA; 2.5-3.6V; CAN BE 1 OHM BYPASS WITH 300MA LIMIT)
(100MA; 1.5-4.6V)
(10MA; 2.0-3.55V; CAN BE USED IN HIB)
(300MA; 1.2-1.5V; ONLY SUPPLIED FROM BUCK2; CAN BE USED IN HIB)
(200MA; 2.5-3.55V; CAN BE 300MA BYPASS; CAN BE USED IN HIB)
(150MA; 1.7-3.0V; LOW NOISE; CAN BE SUPPLIED FROM BUCK2)
(100MA; 0.6-1.3V; SUPPLIED FROM BUCK2; CAN BE USED IN HIB)
(RON=2.5 OHM)
(2MA; USED FOR 100K PULLUPS)
1
C2023
2.2UF
10%
6.3V
2
X5R
402
(CHANGED
TO 2.2UF)
D2000
12
PMEG2005AEL
CRITICAL
21
C2040
1
10UF
20%
6.3V
2
X5R
603
1
10%
2
X5R
402
C2026
2.2UF
6.3V
(CHANGED(CHANGED
TO 2.2UF)
1
C2046
1UF
10%
16V
2
X5R
402
10%
X5R
402402
1
C2041
0.1UF
10%
6.3V
2
X5R
201
1
2
(CHANGED
1
2
C2027
2.2UF
6.3V
PP5V1_OUT
C2047
22PF
5%
50V
CERM
201
PPVCORE_H3
PP1V8_SDRAM
10%
X5R
402
1
2
C2028
1UF
6.3V
CERM
15
15
15 18
PP3V3_LAND_ACC
PP1V7_VA_VCP
PP3V0_OPTICAL
PP3V0_VIDEO
PP3V1_AUDIO
PP3V3_PORT_ACC
PP3V0_IO
PP3V0_LCD
PP3V0_HP_DET_BIAS
PP3V0_GRAPE
PP1V1_H3_PHY
PP1V2_AUDIENCE
PP1V8_ALWAYS
C2029
1UF
6.3V
CERM
1
C2030
0.22UF
10%
2
402
1
10%
2
402
PP1V2_H3
20%
6.3V
X5R
201
15
15
15
15
15
15
15
15
15
15
15
15
15
15
1
2
D
C
B
(PLACE ONE 1UF CAP AT EACH VDD INPUT)
CRITICAL
C2056
150UF
6.3V
TANT-1
B15G
1
1
20%
2
2
C2001
10UF
20%
6.3V
X5R
603
1
C2002
10UF
20%
6.3V
2
X5R
603
1
C2003
1UF
10%
6.3V
2
CERM
402
1
C2004
1UF
10%
6.3V
2
CERM
402
1
C2005
1UF
10%
6.3V
2
CERM
402
1
C2006
1UF
10%
6.3V
2
CERM
402
1
C2007
1UF
10%
6.3V
2
CERM
402
1
C2008
1UF
10%
6.3V
2
CERM
402
1
2
17 18
A
PART NUMBER
338S0805
QTY
DESCRIPTION
1
IC,PMU,ASHLEY,D1815A2,OTPXX,UFBGA121,K48
REFERENCE DES
U2000
CRITICAL
CRITICAL
BOM OPTION
875 421
(1.26A MAX)
1
C2009
1UF
10%
6.3V
CERM
402
BATT_VCC_CURSNS
PLACEMENT_NOTE=PLACE NEAR U0652
C2010
82PF
5%
25V
2
CERM
0201
=PP1V8_SDRAM_1V2
15
1
C2011
18PF
5%
25V
2
NP0-C0G
201
C2050
1UF
6.3V
CERM
NOTE: DELAY 0.1MS
=VCC_MAIN_ASH
NOTE: SUPPLY ASHLEY INTERNAL POWER
1
R2042
0
5%
1/16W
MF-LF
402
2
1
10%
2
402
15 18
1
R2043
10K
1%
1/20W
MF
201
2
P1V8_1V2_SSPP1V2_SDRAM
C2054
0.01UF
10%
10V
X5R
201
B1
1
2
CE
RP106Z121D
LAYOUT NOTE: PLACE NEAR U0652
PLACEMENT_NOTE=PLACE NEAR U0652
A1
VDD
U2001
CRITICAL
WLCSP4
GND
B2
(400MA)
A2
VOUT
PLACEMENT_NOTE=PLACE NEAR U0652
C2051
4.7UF
20%
6.3V
X5R-CERM
402
36
SIZE
A
D
SYNC_MASTER=MARK
PAGE TITLE
PMU
1
2
15
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Apple Inc.
R
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
20 OF 119
SHEET
18 OF 53
345678
21
D
CRITICAL
Y2100
32.768K-20PPM-12.5PF
PMU_XTAL
1
C2105
15PF
5%
25V
2
NPO
201
(REVERSE VOLTAGE PROTECTION)
Q2000
CMLDM8002AG
SOT563
DS
USB_PWRA_VIN_GATE
R2101
10KOHM-1%
0201
C2110
100PF
5%
25V
CERM
201
6
1
2
USB_PWRA_VIN
16
C
C2111
100PF
5%
25V
CERM
201
1
2
R2110
0
12
5%
1/20W
MF
201
1
2
G
1
1
2
MIN_LINE_WIDTH=0.3 MM
VOLTAGE=5V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
2
USB_PWRA_VIN_FET
1
R2111
100K
1%
1/20W
MF
201
2
R2102
10KOHM-1%
0201
1
C2109
100PF
5%
25V
2
CERM
201
R2113
210
12
1%
1/20W
MF
201
1
R2103
10KOHM-1%
0201
2
C2108
100PF
12
1
5%
25V
2
CERM
201
DZ2100
B
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MMMIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
USB_PWRA_VIN_R
GDZT2R5.1B
GDZ-0201
CRITICAL
1
R2104
10KOHM-1%
0201
2
NOTE: WILL WAKE FROM STANDBY ON INSERTION/EXTRACTION)
(DESENSE AND VCC_MAIN PULLUP EXT)
(DESENSE AND VCC_MAIN PULLUP EXT)
(DESENSE AND VCC_MAIN PULLUP EXT)
USB_BRICKID
6
27
IN
C2107
12
10V201
=PP1V8_ALWAYS
6
15
NOSTUFF
1
R2107
100K
1%
1/20W
MF
(PULLDOWN INT)
(DIFFER FROM N90)
(PULLDOWN INT)
(ASRTD IN STDBY OR HIB; 3.0V IO PULLUP EXT)
(H3 PULLUP INT)
(H3 PULLUP EXT)
6
6
IN
IN
201
2
KEEPACT
PMU_RESET_IN
15 18
(INPUT TO ADC / 0.5)
0.01UF
X5R10%
PP1V8
HOME_L
6
39
IN
ONOFF_L
6
40
IN
RINGER_A
6
40
IN
PORT_DOCK_ACC_DET_L
39
IN
PORT_DOCK_ACCID
39
IN
ADC_IN7
38
IN
BOARD_TEMP1
BOARD_TEMP2
BOARD_TEMP3
BOARD_TEMP4
(50UA CURRENT SOURCE)
PMU_NTC
NET_SPACING_TYPE=PWR
PMU_TCAL
PMU_SHDWN
22
IN
RESET_L
6
39
OUT
PMU_IRQ_L
6
OUT
I2C0_SCL_1V8
7
17 26 28 33 36 44
IN
I2C0_SDA_1V8
7
17 26 28 33 36 44
IN
SWI_BLCTRL
9
IN
NOSTUFF
R2112
100K
12
1%
1/20W
MF
201
(DISABLE CHARGER)
R2108
4.02K
1/20W
C2112
100PF
J10
FW_DET
H8
BUTTON1
J8
BUTTON2
K10
BUTTON3
K9
ACC_DET
F3
ACC_ID
C8
BRICK_ID
F10
ADC_IN7
B10
T1
D10
T2
B4
T3
A9
T4
E9
TBAT
C9
TCAL
H9
KEEPACT
C10
SHDN
B7
RESET_IN
C7
RESET*
C4
IRQ*
B3
SCL
C3
SDA
J7
SWI
1
1
R2109
3.92K
1%
MF
201
CERM
0.1%
1/16W
MF
402
2
2
(R FOR TEMP CALIBRATION)
DO WE NEED NTC???
1
5%
25V
2
201
12
2012
G1
CRITICAL
XTAL1
U2000
ASHLEY
UFBGA
(1 OF 2)
DIGITAL
ANALOG
PMU_EXTAL
NET_SPACING_TYPE=CRYSTALNET_SPACING_TYPE=CRYSTAL
H1
XTAL2
IREF
VREF
VDD_REF
VDD_RTC
ADC_REF
INPUT
REFERENCES
GPIO1
GPIO2
GPIO3
INPUT
GPIO4
GPIO5
GPIO6
GPIO
GPIO7
GPIO8
GPIO9
GPIO10
TEMPERATURE
WDOG
RESET
I2C
F9
G9
H2
F1
38 39
G2
C2
C1
D3
D4
H4
K1
H3
E4
D2
D1
1
C2106
15PF
5%
25V
2
NPO
201
PMU_IREF
NET_SPACING_TYPE=PWR
PMU_VREF
NET_SPACING_TYPE=PWR
PMU_VDD_REF
NET_SPACING_TYPE=PWR
PMU_VDD_RTC
NET_SPACING_TYPE=PWR
PMU_ADC_REF
NET_SPACING_TYPE=ANLG
CLK_32K_PMU
CLK_32K_X17
IO_XPNDR_INT_L
LAND_DOCK_ACC_DET_L
BB_PMU_ON_R_L
BATTERY_SWI
LAND_PMU_IRQ_L
DOCK_UART_CTRL
PORT_PMU_IRQ_L
AUD_MIK_HS1_INT_L
(TEMPERATURE SUPERVISION)
(1.2V)
24 44
OUT
39
OUT
6
36
IN
38
IN
41
OUT
7
17
BI
17
IN
11
OUT
17
IN
33
IN
(TEMPERATURE SUPERVISION)
(ALWAYS ON RAIL)
(SUPPLY FOR ADC, OTC)
(I2C REGS, AND REF)
(FOR ACC IDENTIFY)
(1.8V_SDRAM PULLUP EXT)
(VCC_MAIN PULLUP EXT)
(I-LIM R ON CONN PAGE; BATT_POS PULLUP EXT)
(2.5V ALWAYS ON PULLUP IN BMU)
(VCC_MAIN PULLUP INT)
(3.0V_HP_DET PULLUP EXT)
(VCC_MAIN PULLUP INT)
(3.0V_HP_DET PULLUP EXT)
1
C2101
1000PF
10%
16V
2
X7R
201
1
C2102
0.1UF
10%
6.3V
2
X5R
201
1
C2103
0.22UF
10%
10V
2
CERM
402
1
C2104
0.1UF
10%
6.3V
2
X5R
201
1
R2100
200K
1%
1/20W
MF
201
2
D
C
B
A
875 421
36
SYNC_MASTER=MARK
PAGE TITLE
PMU
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
21 OF 119
SHEET
19 OF 53
SIZE
A
D
345678
21
D
CRITICAL
U2400
LTC3442
=VCC_MAIN_3V3
15 20
22UF
20%
6.3V
X5R-CERM
603
1
SSM6N15FEAPE
1%
MF
2
BB_3V3_VC_L
6
D
SG
1
1
2
0.022UF
C2408
C2400
C
=VCC_MAIN_3V3
15 20
R2406
100K
1/20W
201
=PP3V0_IO_3V3
15
R2408
100K
1/20W
1
1%
MF
201
2
Q2400
SSM6N15FEAPE
BB_3V3_EN
SOT563
2
R2400
1/20W
10%
16V
CERM-X5R
402
Q2400
SOT563
1
1M
1%
MF
201
2
1
2
5
BB_3V3_SS
BB_3V3_RT
1
R2401
43.2K
1%
1/20W
MF
201
2
3
D
SG
4
98
VIN
14
SHDN*/SS
10
RLIM
2
RT
F=1KHZ
T(SS)=~1MS
DFN
SGND PGND
5
3
B
3.3V SUPPLY
THRM
PAD
13
VOUT
BURST
SW1
SW2
FB
VC
6
12
11
7
BB_3V3_BURST
1
R2409
249K
1%
1/20W
MF
201
2
C2409
0.01UF
NOSTUFF
1
R2410
0
5%
1/20W
MF
201
2
1
10%
25V
2
X7R
402
BB_3V3_PHASE1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
BB_3V3_PHASE2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
BB_3V3_FB
NET_SPACING_TYPE=PWR
BB_3V3_VC
NET_SPACING_TYPE=PWR
CRITICAL
L2400
4.7UH-4A
12
PIMB051H-SM
DCR=85 MOHM
1
C2405
10PF
5%
25V
2
NPO
201
1
C2401
470PF
10%
16V
2
X5R-X7R
201
BB_3V3_FB_RC
1
R2402
10K
1%
1/20W
MF
201
2
1
R2403
10K
1%
1/20W
MF
201
2
BB_3V3_VOUT_RC
1
C2402
220PF
10%
25V
2
X7R-CERM
201
1
R2404
340K
1%
1/20W
MF
201
2
<R1>
1
R2405
200K
1%
1/20W
MF
201
2
<R2>
VOUT=1.22*(1+R1/R2)
CRITICAL
1
C2403
150UF
20%
6.3V
2
TANT-1
B15G
POWER BUDGET
3.3V
K48
PEAK=1.5A
AVG=1.25A
3.29V NOMINAL
1
C2410
1000PF
10%
16V
2
X7R
201
MLC_PWR_EN
8
IN
PP3V3_OUT
1
2
P3V3MLC_EN
1
R2450
100K
1%
1/20W
MF
201
2
C2411
82PF
25V
CERM
0201
1
GS
1
C2460
100PF
5%
25V25V
2
CERM
201
NOSTUFF
1
R2451
10K
1%
1/20W
MF
201
2
R2452
47K
12
1/20W
3
D
Q2451
SSM3K15FV
SOD-VESM-HF
2
1
2
1%
MF
201
C2461
100PF
5%5%
CERM
201
1
2
R2453
39K
1%
1/20W
MF
201
P3V3MLCWR_SS
15
47
CRITICAL
Q2450
SIA413DJ
SC70-6L
S
G
3
C2451
0.015UF
12
10%
6.3V
X5R
0201
1
D
3.3V MLC
K48
POWER BUDGET
PEAK=0.12A
AVG=0.12A
3.32V NOMINAL
1
2
MOSFET
CHANNEL
RDS(ON)
PP3V3_MLC_OUT
1
C2452
4.7UF
10%
6.3V
X5R-CERM
603
C2453
1000PF
10%
16V
2
X7R
201
SIA413DJ
SIA413DJ
P-TYPE
100MOHM @-1.5V
3 AIMAX
+/- 8VVGS MAX
15
D
C
B
A
875 421
36
SYNC_MASTER=MARK
PAGE TITLE
3.3V SUPPLY
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
24 OF 119
SHEET
20 OF 53
SIZE
A
D
345678
21
LED BOOST/BACKLIGHT CONTROLLER
CRITICAL
Q2600
SI7107DN
PWRPK-1212-8
Q2601
3
2
1
R2616
10K
1/20W
1
GS
S
G
4
1
5%
MF
201
2
3
D
=VCC_MAIN_LED
D
15
C2603
82PF
CERM
0201
1
R2614
1
5%
25V
2
=PP3V0_LCD
15 21
100K
1/20W
201
C2607
0.047UF
1%
MF
2
VCC_MAIN_LED_EN
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
R2618
100K
12
1%
1/20W
MF
201
1
10%
16V
2
X7R
402
SSM3K15FV
SOD-VESM-HF
VCC_MAIN_LED_EN_G
C
LED_VSYNC
25
RDSON=0.015@VGS=-2.5V
5
D
NOSTUFF
C2608
0.0047UF
10%
25V402
VCC_MAIN_LED_EN_R
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
2
(IS THIS NEEDED??)
BKLT_PLL
R2609
201
GND_LED_PWRGND
21
0
5%
1/20W
MF
ID=7.8A
12
CERM
=PP5V1_LED
15 21
12
VCC_MAIN_FET
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
NOSTUFF
1
R2601
0
5%
1/20W
MF
201
2
R2635
10K
1%
1/20W
MF
201
12
(SET TO 20.07MA)
R2607
402-HF
R2602
3.01K
1/20W
12
0.1
1%
1/6W
MF
1%
MF
201
1
2
1
6
2
IN
GND_LED_PWRGND
21
CRITICAL
C2602
22UF
20%
6.3V
CERM-X5R
805
BACKLIGHT_EN
VCC_MAIN_FET_R
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
=PP3V0_LCD
15 21
NOSTUFF
R2615
R2613
100K
1% MF
201
10K
1/20W
1/20W
1%
MF
201
12
1
2
LED_VSYNC_R
NET_SPACING_TYPE=PWR
LED_ISET
LED_RT
LED_SSTCMP
NET_SPACING_TYPE=PWR
LED_DIM
NET_SPACING_TYPE=ANLG
LED_LPF
NET_SPACING_TYPE=PWR
BKLT_PLL
LED_LRT
1%
1/20W
MF
201
BKLT_PLL
C2611
0.1UF
10%
25V
X5R
402
21
IC,APP001A,WHT LED BKLGHT CTR,SCRN,QFN20
DESCRIPTION
R2622
R2623
0
5%
1/20W
MF
201
100K
201
1%
1/20W
MF
12
12
1
C2609
0.1UF
10%
25V
2
X5R
402
BKLT_PLL
1
C2610
1000PF
10%
16V
2
X7R
201
PART NUMBER
353S2413CRITICAL
1
R2624
10K
2
LED_LRT_RC
1
2
QTY
1
1
1%
MF
201
2
1
1%
MF
201
2
GND_LED_PWRGND
LED_PWM_RC
NET_SPACING_TYPE=ANLG
NOSTUFF
1
C2606
2.2NF
10%
10V
2
X5R
201
=PP5V1_LED
15 21
TO SET BL INTENSITY INDEPENDENT OF H2:
FOR 100 PERCENT BL (>=3.3V): R2627=953
FOR 75 PERCENT BL (2.5V): R2627=2.55K
FOR 50 PERCENT BL (1.7V): R2627=5.90K
21
NOSTUFF
R2620
100K
1%
1/20W
MF
201
(FREQ=580KHZ)
12
B
GND_LED_PWRGND
21
R2632
0
VOUT
12
1/20W
MF
201
2
P4V096_REF
NET_SPACING_TYPE=ANLG
C2615
1000PF
10%
16V
X7R
201
NOSTUFF
R2633
0
12
5%
1/20W
MF
201
LCD_BKLT_PWM_R
NET_SPACING_TYPE=ANLG
5%
1
C2616
4.7UF
2
1
R2636
10K
1%
1/20W
MF
201
2
1
20%
6.3V
2
X5R
402
LED_PWR_REF
NET_SPACING_TYPE=ANLG
1
R2626
10K
1%
1/20W
MF
201
2
LED_PWR_EN_L
1
R2634
0
5%
1/20W
MF
201
2
LCD_BKLT_PWM
13
IN
NET_SPACING_TYPE=ANLG
(3.3V DRIVER)
VIN
U2601
X60003D-41
SOT23-3
CRITICAL
GND
31
A
=PP5V1_LED
15 21
1
C2613
10UF
20%
6.3V
2
X5R
603
1
C2614
0.1UF
10%
6.3V
2
X5R
201
R2600
10K
1%
1/20W
MF
201
12
LED_SSTCMP_RC
1
C2612
0.01UF
10%
25V
2
X7R
402
CRITICAL
Q2603
NTUD3169CZ
SOT-963
N-CHANNEL
G
2
1
G
5
4
P-CHANNEL
D
S
D
S
R2621
2M
5%
1/20W
MF
201
12
6
3
LED_PWR_IN_5V
NET_SPACING_TYPE=ANLG
R2627
475
1/20W
R2628
1.40K
1/20W
875 421
CRITICAL
L2600
10UH-3A
12
PIMB051H-SM
DCR=155.0 MOHM
PLACEMENT_NOTE=PLACE NEAR Q2602
1
C2601
1UF
10%
16V
2
X5R
402
GND_LED_PWRGND
21
CRITICAL
4
VREF
5
ENA
17
VSYNC
8
ISET
6
RT
7
SSTCMP
20
DIM
19
LPF
18
LRT
1
R2625
100K
1%
1/20W
MF
201
2
(FREQ=8.4KHZ)
(FREE-RUNNING FREQ)
GND_LED_PWRGND
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=0V
GNDA
13
LED_SW
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 mm
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE
3
PLACEMENT_NOTE=PLACE NEAR U1400
VIN
U2600
QFN
DRV
ISWSEN
APP001
ISEN1
OMIT
ISEN2
ISEN3
ISEN4
ISEN5
ISEN6
VSEN
THRM_PAD
21
2
XW2600
SM
1
REFERENCE DES
PLACEMENT_NOTE=PLACE NEAR Q2602
D2600
SOD-323
LED_GATE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=ANLG
DIDT=TRUE
1
2
LED_ISWSEN
NET_SPACING_TYPE=PWR
DIDT=TRUE
10
LED_IO1_R
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
11
LED_IO2_R
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
12
LED_IO3_R
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
14
LED_IO4_R
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
15
LED_IO5_R
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
16
LED_IO6_R
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
9
LED_VSEN
NET_SPACING_TYPE=ANLG
3
LED_BOOST_SINK
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR
DIDT=TRUE
R2629
100
1%
1/16W
MF-LF
402
12
1
C2600
47PF
5%
50V
2
CERM
402
NOSTUFF
12
1256
D
G
S
PLACEMENT_NOTE=PLACE NEAR C2604
4
PLACEMENT_NOTE=PLACE NEAR C2604 AND Q2602
R2630
0.4
1%
1/6W
MF
402
12
(R2630 AND R2631 PIN 1 SHOULD BE PLACED NEAR C2604 PIN 2)
PMEG4010BEA
CRITICAL
CRITICAL
Q2602
FDC5612
SSOT6
PLACEMENT_NOTE=PLACE NEAR C2604 AND Q2602
R2631
0.4
1%
1/6W
MF
402
12
GND_LED_PWRGND_X
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
DIDT=TRUE
CRITICAL
1
2
PLACEMENT_NOTE=PLACE NEAR J3201
XW2601
C2605
4.7UF
10%
35V
X5R-CERM
0805
SM
12
1
C2620
100PF
5%
50V
2
CERM
402402
R2608
1.00
12
1/20W
MF
201
R2606
1.00
12
1/20W
MF
201
R2605
1.00
12
1/20W
MF
201
R2604
1.00
12
1/20W
MF
201
R2603
1.00
12
1/20W
MF
201
R2617
1.00
12
1/20W
MF
201
1
C2621
100PF
5%
50V
2
CERM
1%
1%
1%
1%
1%
1%
1
C2622
100PF
5%
50V
2
CERM
402
(OVP @ 2.48V)
PPLED_OUT
1
C2623
100PF
5%
50V
2
CERM
402
1
R2610
1M
1%
1/16W
MF-LF
402
2
1
R2611
115K
1%
1/16W
MF-LF
402
2
GND_LED_PWRGND
LED_IO_1
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
LED_IO_2
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
LED_IO_3
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
LED_IO_4
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
LED_IO_5
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
LED_IO_6
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
LAYOUT NOTE:
PLACE U2600 NEAR U1400
SYNC_MASTER=MARK
PAGE TITLE
LED BACKLIGHT CONTROLLER
Apple Inc.
R
U2600
CRITICAL
BOM OPTION
36
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
15
OUT
21
25
OUT
25
OUT
25
OUT
25
OUT
25
OUT
25
OUT
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
26 OF 119
SHEET
21 OF 53
SIZE
D
C
B
A
D
345678
21
DEBUG RESET ACCESS
D
D
C
=VCC_MAIN_AUDIO
15 29
NOSTUFF
1
R2902
1.5K
1%
1/20W
MF
201
FORCE_DFU
6
B
NOSTUFF
1
R2900
300
5%
1/20W
MF
201
2
2
PWR_ON_LED
NOSTUFF
A
LED2900
RED-50MCD-20MA
0603
K
C
B
PMU_SHDWN
19
NOSTUFF
1
R2901
300
5%
1/20W
MF
201
2
A
SYNC_MASTER=MIAMI
PAGE TITLE
DEBUG RESET ACCESS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/21/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
31 OF 119
SHEET
24 OF 53
SIZE
A
D
LVDS CONNECTOR
345678
21
D
SIMILAR TO M97
=PP3V3_LCD
15
NOSTUFF
1
5%
25V25V
CERM
0201
1
G
R3210
10K
1%
1/20W
MF
201
2
D
3
Q3201
2N7002TXG
SOT-523-3
S
2
R3204
21.5K
12
1%
1/20W
MF
201
1
C3240
82PF
13 14 15 25
IN
=PP3V3_MLC
9
NOSTUFF
R3211
13
MLC_PPC_OUT
10K
1/20W
1
1%
MF
201
2
5%
2
CERM
0201
C
1
C3241
82PF
2
LCDVDD_PWREN_L
1
R3205
100K
1%
1/20W
MF
201
2
1
R3203
39K
1%
1/20W
MF
201
2
LCDVDD_PWREN_L_R
SIA413DJ
MOSFET
CHANNEL
RDS(ON)
IMAX
VGS MAX
B
CRITICAL
Q3200
SIA413DJ
SC70-6L
S
3
G
D
C3204
0.015UF
12
47
SIA413DJ
P-TYPE
100MOHM @-1.5V
3 A
+/- 8V
10%
6.3V
X5R
0201
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
1
PP3V3_S0_LCD_FERR
1
C3203
0.1UF
10%
6.3V
2
X5R
201
13
1
C3202
10UF
20%
6.3V
2
X5R
603
1
C3230
82PF
5%
25V
2
CERM
0201
LVDS_DDC_CLK
LVDS_DDC_DATA
13
=PP3V3_MLC
9
13 14 15 25
LVDS_DATA_N<1>
13 45
LVDS_DATA_P<1>
13 45
1
R3201
10K
5%
1/20W
MF
201
2
L3201
FERR-120-OHM-1.5A
12
0402
1
R3200
10K
5%
1/20W
MF
201
2
LVDS_DATA_N<0>
13 45
LVDS_DATA_P<0>
13 45
LVDS_CLK_N
13 45
LVDS_CLK_P
13 45
C3231
82PF
12
5%
25V
CERM
0201
C3200
1000PF
12
10%
16V
X7R
201
L3222
90-OHM-100MA
TCM1005
SYM_VER-1
1
23
4
VOLTAGE=3.3V
L3212
90-OHM-100MA
TCM1005
SYM_VER-1
1
23
LVDS_DATA_N<2>
13 45
LVDS_DATA_P<2>
13 45
4
L3202
90-OHM-100MA
TCM1005
SYM_VER-1
1
23
4
C3206
1000PF
12
10%
16V
1
C3232
82PF
5%
25V
2
CERM
0201
X7R
201
MIN_LINE_WIDTH=0.30 MM
L3232
90-OHM-100MA
TCM1005
SYM_VER-1
1
23
4
LVDS CONNECTOR
PP3V3_LCDVDD_SW_F
MIN_NECK_WIDTH=0.20 MM
45
LVDS_CONN_CLK_N
LVDS_CONN_CLK_P
45
FERR-240-OHM-25%-300MA
=PPLED_REG
15
518S0650
(LVDS DDC POWER)
L3200
12
0402
21
45
45
45
45
45
45
21
21
21
21
21
21
LED_VSYNC
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED
ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
LVDS_DAT_N<0>
LVDS_DAT_P<0>
LVDS_DAT_N<1>
LVDS_DAT_P<1>
LVDS_DAT_N<2>
LVDS_DAT_P<2>
TP_LCD_PGAMMA
PPLED_BACK_REG
LED_IO_6
LED_IO_5
LED_IO_4
LED_IO_3
LED_IO_2
LED_IO_1
1
2
C3233
100PF
5%
50V
CERM
402
1
2
CRITICAL
J3201
20474-030E-11
F-RT-SM
31
32
10
11
12
13
14
15
16
17
18
19
20
21
22
23
NC
24
25
26
27
28
29
30
NC
33
34
C3220
820PF
10%
50V
CERM
402
1
2
3
4
5
6
7
8
9
D
C
B
NOSTUFF RESISTORS ARE THERE TO
INVESTIGATE POSSIBILITY OF REMOVING
THE CHOKE
A
SYNC_MASTER=MIAMI
PAGE TITLE
LVDS CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Apple Inc.
SYNC_DATE=09/16/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
34 OF 119
SHEET
26 OF 53
SIZE
B
A
D
36
USB MUX/BRICK DETECTION
345678
21
SIZE
D
C
B
A
D
D
MAKE SURE RESISTORS ARE ON TOP OF TRACE TO REDUCE STUB
LAND_USB_CHINA_DET
6
VOLTAGE=3.3
CRITICAL
LANDSCAPE_DOCK
U3502
SN74LVC2G66YZPR
BGA
1
C3503
1000PF
10%
16V
2
X7R
201
C
USB_BRICKID
19
6
IF USB DATA LINES GO TO 5V
BRICKID WILL CLIP TO VCC=3V0
B
NOSTUFF
1
C3504
1000PF
10%
16V
2
X7R
201
CRITICAL
LANDSCAPE_DOCK
U3502
SN74LVC2G66YZPR
SN74LVC2G66YZPR
BGA
CRITICAL
PORTRAIT_DOCK
U3504
SN74LVC2G66YZPR
BGA
CRITICAL
PORTRAIT_DOCK
U3504
BGA
A
=PP3V0_HP_DET_BIAS
1
2
D2C2
A2
C1
D1
=PP3V0_HP_DET_BIAS
A1B1
A2
B2
LANDSCAPE_DOCK
D1
R3541
100K
12
1%
1/20W
MF
201
=PP3V0_HP_DET_BIAS
1
2
D2C2
A2
C1
D1
=PP3V0_HP_DET_BIAS
A1B1
A2
B2
PORTRAIT_DOCK
D1
R3543
100K
12
1%
1/20W
MF
201
11 15 27 33 34 36 39
LANDSCAPE_DOCK
C3505
0.1UF
10%
6.3V
X5R
201
USBA_EXT_PR
VOLTAGE=3.3
LAND_BRICK_ID_P
LANDSCAPE_DOCK
R3540
100K
12
1%
1/20W
MF
201
11 15 27 33 34 36 39
USBA_EXT_NR
VOLTAGE=3.3
LAND_BRICK_ID_N
11 15 27 33 34 36 39
PORTRAIT_DOCK
C3506
0.1UF
10%
6.3V
X5R
201
USBB_EXT_PR
VOLTAGE=3.3
PORT_BRICK_ID_P
PORTRAIT_DOCK
R3542
100K
12
1%
1/20W
MF
201
11 15 27 33 34 36 39
USBB_EXT_NR
VOLTAGE=3.3
PORT_BRICK_ID_N
LANDSCAPE_DOCK
R3516
12
8
LANDSCAPE_DOCK
R3512
12
8
PORT_USB_CHINA_DET
6
VOLTAGE=3.3
PORTRAIT_DOCK
R3514
12
8
PORTRAIT_DOCK
R3515
12
8
10K
1/20W
201
10K
1/20W
201
10K
1/20W
201
10K
1/20W
201
1%
MF
1%
MF
1%
MF
1%
MF
875 421
LANDSCAPE_DOCK
1
R3501
100K
1%
1/20W
MF
201
2
USB_LAND_DOCK_P
USB_LAND_DOCK_N
PORTRAIT_DOCK
1
R3502
100K
1%
1/20W
MF
201
2
USB_PORT_DOCK_P
USB_PORT_DOCK_N
27 38 44
27 38 44
27 39 44
27 39 44
=PP3V0_HP_DET_BIAS
11 15 27 33 34 36 39
USB MUX FOR DOCK USB
1
R3521
100K
1/20W
USB_MUX_SEL
6
USB_PWRB_VIN_R
18
PD FOR THIS IS R2031
1%
MF
201
2
36
1
G
USB_DP
44
6
USB_DM
6
44
1
2
USB_PWRB_L
D
3
S
2
R3522
10K
1%
1/20W
MF
201
Q3500
2N7002TXG
SOT-523-3
1
C3507
0.1UF
10%
6.3V
2
X5R
201
8
D+
7
D-
9
S
10
VCC
CRITICAL
U3501
TS3USB221
DRC-QFN
GND
5
1D+
1D-
2D+
2D-
OE*
THRML
PAD
11
SYNC_MASTER=MIAMI
PAGE TITLE
2
3
4
6
USB_PORT_DOCK_N
USB_LAND_DOCK_P
USB_LAND_DOCK_N
USB_MUX_OE_L
1
R3520
100K
1%
1/20W
MF
201
2
6
IF OE IS ENABLED AND 5V IS ON DATA LINE
IT WILL PASS THROUGH TO AP
USB DATA LINES ARE 5V TOLERANT
USB_PORT_DOCK_P
1
USB MUX/BRK DET
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
36 OF 119
SHEET
28 OF 53
36
SIZE
D
C
B
A
D
345678
21
D
D
SPEAKER AMPLIFIER
SSM2319 APN:353S2136
=VCC_MAIN_AUDIO
15 22 29
SPEAKER
R3713
1K
5%
1/20W
MF
201
XW3701
SM
12
SPEAKER
CRITICAL
C3701
0.047UF
10%
6.3V
X5R
201
SPEAKER
R3700
XW3711
SM
12
12
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
12
C3702
0.047UF
100K
5%
1/20W
MF
201
SPEAKER
C3711
0.047UF
SPEAKER
R3703
1K
12
5%
1/20W
MF
201
EAR_OUT_P
28 44
IN
EAR_OUT_N
28 44
IN
AUD_SPKRAMP_MUTE_N
6
29
IN
C
L61 RECEIVER OUTPUT IS CONNECTED TO U3700
L61 SPEAKER OUTPUT IS CONNECTED TO U3710
=VCC_MAIN_AUDIO
15 22 29
B
MONO_OUT_P
28 44
IN
MONO_OUT_N
28 44
IN
AUD_SPKRAMP_MUTE_N
6
29
GAIN = 12DB
80HZ +/- XXX%
CRITICAL
12
SSM2319_L_IN_P
44
10%
6.3V
X5R
201
SPEAKER
1
2
XW3700
SM
12
AUD_SPKR_AMP2_PBUS
CRITICAL
12
CRITICAL
10%
6.3V
C3712
X5R
0.047UF
201
10%
6.3V
X5R
201
SPEAKER
12
AUD_SPKR_AMP1_PBUS
SSM2319_L_IN_N
44
GND_SPKR_AMP1
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.30MM
44
SSM2319_R_IN_N
SSM2319_R_IN_P
44
TURN ON TIME: 28MS
TURN ON DELAY: 50MS
SPEAKER
1
C3703
0.1UF
10%
6.3V
2
X5R
201
A1
B1B3
A2
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
SPEAKER
1
C3713
0.1UF
10%
6.3V
2
X5R
201
A1
B1B3
A2
C2
VDD
U3700
SSM2319CBZ
WLCSP9
IN-
CRITICAL
IN+
SD*
GND
C1
VDD
U3710
SSM2319CBZ
WLCSP9
IN-
CRITICAL
IN+
SD*
GND
C1
SPEAKER
SYNCO
SYNCI
SPEAKER
C2
SYNCI
OUT+
OUT-
B2
SYNCO
B2
OUT+
OUT-
C3
A3
C3
A3
SPEAKER
1
C3704
4.7UF
20%
6.3V
2
X5R
603
SPEAKER
1
C3705
2
SPKRAMP_L_OUT_P
SPKRAMP_L_OUT_N
SSM2319_L_SYNC
SPEAKER
1
2
C3714
4.7UF
20%
6.3V
X5R
1
2
SPKRAMP_R_OUT_P
SPKRAMP_R_OUT_N
SSM2319_R_SYNC
4.7UF
20%
6.3V
X5R
603
SPEAKER
C3715
4.7UF
20%
6.3V
X5R
603603
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
SPKRAMP_L_OUT_P
29 44
SPKRAMP_L_OUT_N
29 44
SPKRAMP_R_OUT_P
29 44
SPKRAMP_R_OUT_N
29 44
29 44
OUT
29 44
OUT
29 44
OUT
29 44
OUT
SPEAKER CONNECTOR
APN 518S0521
SPEAKER
CRITICAL
1
C3750
470PF
10%
16V
2
X5R-X7R
201
SPEAKER
CRITICAL
1
C3751
470PF
10%
16V
2
X5R-X7R
201
SPEAKER
CRITICAL
1
C3752
470PF
10%
16V
2
X5R-X7R
201
SPEAKER
CRITICAL
C3753
470PF
X5R-X7R
10%
16V
201
1
2
J3700
78171-0004
M-RT-SM
5
1
2
3
4
6
C
B
XW3710
SM
12
GND_SPKR_AMP2
A
875 421
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
SIZE
A
D
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: SPEAKER AMP
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
37 OF 119
SHEET
29 OF 53
36
345678
21
HEADPHONE OUTPUT ZOBEL NETWORK
D
28
IN
28
IN
28 34
28 34
HP_L
HP_R
GND_AUDIO_HP_AMP
28 34
HP_REF
OUT
R3850
1/20W
C3850
0.22UF
6.3V
1
1
R3851
2
HP_ZR
1
2
15
1%
1/20W
MF
201
2
HP_ZL
1
C3851
0.22UF
2
20%
6.3V
X5R
201
15
1%
MF
201
20%
X5R
201
C
R3853
12
R3852
0
12
5%
1/20W
MF
201
1/20W
201
0
5%
MF
NOSTUFF
1
C3853
27PF
5%
25V
2
NP0-C0G
201
AUD_HP1_MLBCON_L
AUD_HP1_MLBCON_R
NOSTUFF
1
C3852
27PF
5%
25V
2
NP0-C0G
201
NOSTUFF
R3854
10K
1/20W
34
OUT
34
OUT
1
1
R3855
10K
1%
1%
1/20W
MF
MF
201
201
2
2
IN
=PP3V1_AUDIO
15 28
CODEC_LINE_OUT_REF
28 30
LO_LS_REF_SEL
6
30
IN
GND_AUDIO_CODEC
28 30 33
OUTPUT REF SENSE LINE SHOULD BE SWITCHED TO ACTIVE PORT
LO_LS_REF_SEL = 0: PORTRAIT DOCK SELECTED
LO_LS_REF_SEL = 1: LANDSCAPE DOCK SELECTED
LINE OUTPUT DOCK SELECTOR
LO_LS_REF_SEL = 0: DAC OUTPUT CONNECTED TO PORTRAIT DOCK
LO_LS_REF_SEL = 1: DAC OUTPUT CONNECTED TO LANDSCAPE DOCK
MIN_LINE_WIDTH=0.2MM
CODEC_LINE_OUT_REF
28 30
OUT
ANALOG_SW_VCC
30
1
C3814
0.1UF
B
CODEC_LINE_OUT_L
28
IN
CODEC_LINE_OUT_R
28
IN
LO_LS_REF_SEL
6
30
GND_AUDIO_CODEC
28 30 33
10%
6.3V
2
X5R
201
C1
C3
A1B3
D1
D2
1SEL
2SEL
D2
VCC
U3810
STG5678
CSP
CRITICAL
GND
B2
C2
1S1
1S2
2S1
2S2
B1
D1
D3A3
A2
NC
NOSTUFF
1
C3810
15PF
5%
25V
2
NPO
201
MIN_LINE_WIDTH=0.1MM
MIN_LINE_WIDTH=0.1MM
MIN_LINE_WIDTH=0.1MM
MIN_LINE_WIDTH=0.1MM
NOSTUFF
1
C3811
15PF
5%
25V
2
NPO
201
NOSTUFF
1
C3812
15PF
5%
25V
2
NPO
201
MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM
MIN_NECK_WIDTH=0.07MM
NOSTUFF
1
C3813
15PF
5%
25V
2
NPO
201
MIN_NECK_WIDTH=0.1MM
AUD_LO_LS_L
AUD_LO_PT_L
AUD_LO_LS_R
AUD_LO_PT_R
31
OUT
31
OUT
31
OUT
31
OUT
AUD_LO_LS_REF_FILT
30
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
GND_AUDIO_CODEC
28 30 33
AUD_LO_PT_REF_FILT
30
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
GND_AUDIO_CODEC
28 30 33
LINE OUTPUT REF SENSE DOCK SELECTOR
L3820
80-OHM-0.2A-0.4-OHM
12
0201-1
R3820
10K
1/20W
201
30
ANALOG_SW_VCC
1S1
1S2
2S1
2S2
C3820
NP0-C0G
B1
D1
D3A3
A2
NC
D2
VCC
U3800
STG5678
C1
D1
D2
1SEL
2SEL
CSP
CRITICAL
GND
B2
C2
C3
A1B3
1
5%
MF
2
LINE OUTPUT REF SENSE FILTER
R3822
1.5
12
C3822
0.1UF
6.3V
C3823
0.1UF
6.3V
5%
1/20W
1
10%
2
X5R
201
1
10%
2
X5R
201
MF
201
R3823
1
12
5%
1/20W
MF
201
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
27PF
5%
25V
201
1
1
2
2
AUD_LO_LS_REF
AUD_LO_PT_REF
C3821
1UF
10%
6.3V
TANT
402-1
AUD_LO_LS_REF_FILT
AUD_LO_PT_REF_FILT
31
IN
31
IN
D
30
30
C
B
XW3800
SM
12
XW3801
A
SM
12
875 421
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GND_AUDIO_PT
GND_AUDIO_LS
31
IN
SIZE
A
D
31
IN
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO:HEADPHONE OUT
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
38 OF 119
SHEET
30 OF 53
36
345678
21
D
D
DOCKS OUTPUTS
NOTE:
PORTRAIT DOCK IS PRIMARY DOCK
LANDSCAPE DOCK LINE OUTPUT ESD CIRCUIT
PORTRAIT DOCK LINE OUTPUT
C
LINE_OUT2_L
39
OUT
LINE_OUT2_R
39
OUT
EXTCONB_DIFF_SENSE_CONN
39
IN
GND_AUDIO_DOCKBGND_AUDIO_PT
39
OUT
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.07MM
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
AUD_LO_PT_L
AUD_LO_PT_R
AUD_LO_PT_REF
30
IN
30
IN
30
OUT
30
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.07MM
LINE_OUT1_L
38
OUT
MIN_LINE_WIDTH=0.10MM
MIN_NECK_WIDTH=0.07MM
LINE_OUT1_R
38
OUT
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.10MM
EXTCONA_DIFF_SENSE_CONN
38
IN
GND_AUDIO_DOCKA
38
OUT
LANDSCAPE_DOCK
R3900
1/20W
1%
MF
201
2
1
33
12
LANDSCAPE_DOCK
DZ3906
6.8V-100PF
0201
LANDSCAPE_DOCK
DZ3905
6.8V-100PF
2
0201
LANDSCAPE_DOCK
DZ3901
6.8V-100PF
2
0201
1
LANDSCAPE_DOCK
DZ3900
6.8V-100PF
2
0201
L3900
FERR-120-OHM-1.5A
12
0402
L3901
FERR-120-OHM-1.5A
12
0402
L3905
22-OHM-25%-900MA
12
0201
LANDSCAPE_DOCK
L3906
30-OHM-1.7A
12
0402
LANDSCAPE_DOCK
AUD_LO_LS_L
AUD_LO_LS_R
AUD_LO_LS_REF
GND_AUDIO_LS
30
IN
30
IN
30
OUT
30
C
1
TO LANDSCAPE DOCK MLB CONNECTOR
B
1
GND_CHASSIS_DOCKA
B
TO PORTRAIT DOCK MLB CONNECTOR
A
875 421
36
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: LINE OUT DOCK ESD CIRCUIT
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
39 OF 119
SHEET
31 OF 53
SIZE
A
D
345678
21
D
D
AUDIENCE BYPASS SHUNTS
C
R4000
BB_I2S1_TX
12 41
BB_I2S1_RX
BB_I2S1_WA0
12 41
BB_I2S1_CLK
12 41
1/20W
5%
201
MF
0
R4001
5%01/20W
MF
201
R4002
5%MF1/20W
201
0
R4003
5%
1/20W
201
MF
0
12
12
12
12
BT_I2S_DIN
BT_I2S_DOUT
BT_I2S_LRCLK
BT_I2S_CLK
28 39
28 39 12 41
28 39
28 39
C
SIZE
B
A
D
B
A
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: AUDIENCE
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
40 OF 119
SHEET
32 OF 53
345678
21
INTERNAL(BUILT-IN) ANALOG MIC BIAS & FILTER
D
INTERNAL_MIC
1
C4236
6800PF
10%
10V
2
CERM
201
INTERNAL_MIC
R4233
1.18K
12
INTERNAL_MIC
R4234
1.18K
12
BI MIC LPF FC = ~19.8KHZ
MIC1_P
28
OUT
MIC1_N
28
OUT
INTERNAL_MIC
1
C4237
6800PF
10%
10V
2
CERM
201
GND_AUDIO_CODEC
28 30 33
1/20W
201
1/20W
201
1%
MF
1%
MF
28
IN
MIC1_BIAS
MIC1_P_R
MIC1_N_R
INTERNAL_MIC
C4230
0.47UF
12
20%
4V
CERM-X5R
201
INTERNAL_MIC
C4231
0.47UF
12
20%
4V
CERM-X5R
201
INT_MIC_HI
INTERNAL_MIC
C4233
INT_MIC_LO
100PF
CERM
INTERNAL_MIC
R4230
1
5%
25V
2
201
INTERNAL_MIC
R4232
1
3.3K
1%
1/20W
MF
201
2
INTERNAL_MIC
R4231
1
3.3K
1%
1/20W
MF
201
2
100K
1/20W
1
5%
MF
201
2
INTERNAL_MIC
C4234
27PF
NP0-C0G
INTERNAL_MIC
1
C4232
27PF
5%
25V
2
NP0-C0G
201
INTERNAL_MIC
C4235
27PF
NP0-C0G
1
5%
25V
2
201
1
5%
25V
2
201
L4230
240-OHM-0.2A-0.8-OHM
12
0201
INTERNAL_MIC
L4231
240-OHM-0.2A-0.8-OHM
12
0201
INTERNAL_MIC
INTERNAL_MIC
DZ4230
6.8V-100PF
0201
INT_MIC_CONN_P
INT_MIC_CONN_N
INTERNAL_MIC
DZ4231
6.8V-100PF
2
2
0201
1
1
34
IN
34
IN
C
D
C
EXTERNAL MIC INPUT CIRCUITRY
APN:353S2640
I2C ADD: READ=72H, WRITE=73H
NOTE: INT IS OPEN DRAIN, PULL UP ON MIKEY SIDE
C4211
0.1UF
MIC2_P_R
AUD_HS_MIC1_HI
34
IN
LEFT_HS
27PF
NP0-C0G
R4210
5%
25V
201
LEFT_HS
2.2K
1
2
1/20W
5%
MF
201
C4216
B
AUD_HS_MIC1_LO
34
IN
MIC_BIAS_HP1
OUT
LEFT_HS
C4212
100PF
5%
25V
CERM
201
LEFT_HS
1
1
R4211
1K
1%
1/20W
MF
201
2
2
HP1_SWDET
HP1_BP
CRITICAL
LEFT_HS
1
A
GND_AUDIO_CODEC
28 30 33
C4210
2.2UF
6.3V
TANT
402-1
20%
2
LEFT_HS
1
C4214
0.01UF
10%
10V
2
X5R
201
12
10%
6.3V
X5R
201
1
LEFT_HS
2
C4213
C1
B1
D1
0.1UF
LEFT_HS
U4210
MICBIAS
DETECT
BYPASS
CRITICAL
12
10%
6.3V
X5R
201
A2
AVDD
CD3282A1
WCSP
LEFT_HS
ENABLE
AGND
D2
C2
MIC2_N_R
SCL
SDA
INT*
HDET
CS
DGND
C3
B3
D3
A3
A1
B2
875 421
LEFT_HS
R4213
0
12
5%
1/20W
MF
201
LEFT_HS
R4214
0
12
5%
1/20W
MF
201
=PP3V0_HP_DET_BIAS
LEFT_HS
1
C4215
0.47UF
20%
4V
2
CERM-X5R
201
EXT MIC LPF FC = DISABLED
NOSTUFF
1
C4217
6800PF
10%
10V
2
CERM
201
1
2
11 15 27 34 36 39
LEFT_HS
1
R4212
10K
5%
1/20W
MF
201
2
I2C0_SCL_1V8
I2C0_SDA_1V8
AUD_MIK_HS1_INT_L
AUD_MIKEY_ENA
AUD_JACK_INSERT_HDET
NOSTUFF
C4218
6800PF
10%
10V
CERM
201
MIC2_P
MIC2_N
28
OUT
OUT
GND_AUDIO_CODEC
7
IN
7
BI
19
6
IN
34
IN
28
28 30 33
17 19 26 28 36 44
17 19 26 28 36 44
B
SIZE
A
D
SYNC_MASTER=AUDIO
PAGE TITLE
SYNC_DATE=12/04/2009
AUDIO: DETECT/MIC BIAS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
42 OF 119
SHEET
33 OF 53
36
345678
21
JACK 1 MLB CONNECTOR: HEADPHONE/HS_MIC/INT_MIC
APN: 518S0693
INT_MIC_CONN_P
D
CONN_AUD_HS_MIC1_HI
L4302
240-OHM-0.2A-0.8-OHM
FF18-8A-R11AD-B-3H
PLACE C4300 NEAR CHASSIS SHORT
C
J4300
F-RT-SM
1
2
3
4
5
6
7
8
C4300
LEFT_HS
100PF
CERM
1
5%
25V
2
201
LEFT_HS
DZ4301
6.8V-100PF
0201
2
DZ4303
6.8V-100PF
LEFT_HS
DZ4302
6.8V-100PF
2
0201
LEFT_HS
0201
2
1
LEFT_HS
DZ4304
6.8V-100PF
2
0201
1
CONN_AUD_HS_MIC1_LO
CONN_GND_AUDIO_HP_AMP
CONN_AUD_HP1_DET_H
CONN_AUD_HP1_MLBCON_R
CONN_AUD_HP1_MLBCON_L
2
LEFT_HS
DZ4306
6.8V-100PF
2
0201
LEFT_HS
DZ4305
6.8V-100PF
0201
12
0201
LEFT_HS
L4303
240-OHM-0.2A-0.8-OHM
12
L4306
30-OHM-1.7A
12
L4301
240-OHM-0.2A-0.8-OHM
12
0201
LEFT_HS
L4305
30-OHM-1.7A
12
0402
LEFT_HS
0201
LEFT_HS
LEFT_HS
L4304
30-OHM-1.7A
12
0402
LEFT_HS
0402
INT_MIC_CONN_N
AUD_HS_MIC1_HI
AUD_EXT_MIC_LO
XW4300
SM
12
HP_REF
GND_AUDIO_HP_AMP
AUD_HP1_DET_H
AUD_HP1_MLBCON_R
AUD_HP1_MLBCON_L
33
OUT
33
OUT
33
OUT
34
28 30
OUT
28 30 34
34
OUT
30
IN
30
IN
D
C
1
1
1
1
HEADSET HP/MIC CROSSTALK MITIGATION (NOT USED)
XW4301
SM
LEFT_HS
1
R4323
270K
1%
1/20W
MF
201
2
12
G
1
EXT_MIC_N_SNS
EXT_MIC_D
3
D
LEFT_HS
Q4200
CEDM7001
S
SOT883L
2
B
AUD_EXT_MIC_LO
34
HEADSET JACK INSERTION DETECT
=PP3V0_HP_DET_BIAS
11 15 27 33 36 39
34
IN
AUD_HP1_DET_H
CD3282 DOES NOT REQUIRE PULLUP
NOSTUFF
1
R4311
270K
1%
1/20W
MF
201
2
LEFT_HS
R4312
100K
12
AUD_JACK_INSERT_HDET
1/20W
201
5%
MF
LEFT_HS
1
C4310
0.01UF
10%
10V
2
X5R
201
DIFF_MIC_SEL
9
33
OUT
A
875 421
LEFT_HS
R4320
2.0K
12
5%
1/20W
MF
201
LEFT_HS
R4321
169
12
1%
1/20W
MF
201
36
LEFT_HS
1
R4322
4.7K
1%
1/20W
MF
201
2
GND_AUDIO_HP_AMP
AUD_HS_MIC1_LO
33
OUT
28 30 34
SYNC_MASTER=AUDIO
PAGE TITLE
AUDIO: HP CONN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=12/04/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
43 OF 119
SHEET
34 OF 53
SIZE
B
A
D
ALS CONN.
345678
21
D
D
FPC CONNECTOR
APN: 516S0498
L4510
240-OHM-0.2A-0.8-OHM
CON_ALS_INT_L
L4514
240-OHM-0.2A-0.8-OHM
I2C2_SCL_3V0
7
12 13 17 26
L4513
240-OHM-0.2A-0.8-OHM
I2C2_SDA_3V0
7
C
12 13 17 26 44
12
0201
12
0201
1
C4513
82PF
5%
25V
2
CERM
0201
CON_I2C2_SCL
CON_I2C2_SDA
1
C4514
82PF
5%
25V
2
CERM
0201
CRITICAL
J4501
AA03-S024VA1
F-ST-SM
2526
1
2
34
56
78
10
9
1112
1314
1516
1718
20
19
2122
2324
2728
CON_3V0_ALS
CON_COMP_RST_L
CON_COMP_INT_L
1
C4510
82PF
5%
25V
2
CERM
0201
12
OMIT
1
C4511
82PF
5%
25V
2
CERM
0201
0201
L4507
240-OHM-0.2A-0.8-OHM
12
OMIT
1
C4512
82PF
5%
25V
2
CERM
0201
VOLTAGE=3.0V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 mm
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
0201
NOSTUFF
L4511
240-OHM-0.2A-0.8-OHM
12
0201
NOSTUFF
L4512
240-OHM-0.2A-0.8-OHM
12
0201
ALS_INT_L
=PP3V0_OPTICAL
(ALS POWER)
COMPASS_RST_L
COMPASS_INT_L
6
15
6
26
C
6
26
1
C4507
82PF
5%
25V
2
CERM
0201
B
QTY
PART#
117S0002
DESCRIPTION
0-OHM,5%,1/20W,MF,0201
2
A
875 421
1
C4505
1UF
10%
10V
2
X5R
402
1
C4506
0.1UF
10%
6.3V
2
X5R
201
REFERENCE DESIGNATOR(S)
C4511,C4512
BOM OPTION
B
TABLE_5_HEAD
TABLE_5_ITEM
SIZE
A
D
SYNC_MASTER=MIAMI
PAGE TITLE
ALS CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/16/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
45 OF 119
SHEET
35 OF 53
36
345678
=PP1V8_SDRAM_MISC
11 15 36
NOSTUFF
1
R4800
100K
D
I2C0_SCL_1V8
7
17 19 26 28 33 44
IN
I2C0_SDA_1V8
7
17 19 26 28 33 44
BI
IO_XPNDR_RST_L
6
IN
ADDR DEVICE ADDRESS
0
1
0X40 (DEF)
0X42
1%
1/20W
MF
201
2
THIS IS SAME AS PREVIOUS, BUT CE APPROVED APN NUMBER (SAME PART)
1
R4801
0
5%
1/20W
MF
201
2
1
R4802
0
5%
1/20W
MF
201
2
12
13
1
16
14
U4800
TCA6408A
CRITICAL
SCL
SDA
RESET*
ADDR
GND
VCCIVCCP
QFN
6
1
2
15
2
P0
3
P1
4
P2
5
P3
7
P4
8
P5
9
P6
10
P7
11
INT*
APN: 311S0486
C4800
0.1UF
10%
6.3V
X5R
201
U4800_6
U4800_7
1
2
1
R4808
100K
1%
1/20W
201
2
C4801
0.1UF
10%
6.3V
X5R
201
1
R4809
100K
1%
1/20W
MFMF
2
1
R4803
100K
1%
1/20W
MF
201
2
1
R4805
100K
1%
1/20W
MF
201201
2
1
R4806
100K
1%
1/20W
201
2
(PULL-DOWN ON HWB)
(PULL-DOWN ON HWB)
BB_HOST_WAKE
MAKE_BASE=TRUE
1
R4807
100K
1%
1/20W
MFMF
201
2
BT_RESET_L
WLAN_RESET_L
BT_HOST_WAKE
WLAN_HOST_WAKE
AP_PMU_EXTON
FW_PWR_PRES_L
IO_XPNDR_INT_L
OUT
OUT
IN
IN
IN
IN
OUT
21
39
39
39
39
41
36
6
19
D
C
=PP1V8_SDRAM_MISC
11 15 36
1
R4820
100K
1%
1/20W
MF
201
2
FW_PWR_PRES_L
VIN > VREF: VOUT=LOW
VIN < VREF: VOUT=HIGH
36
FW PWR PRESENT
FW PWR DETECTION IF FW VOLTAGE > 4.5V
NOTE:
ALSO IN THIS CASE, IGNORE H3_DP_HPD
FW_PWR_SNS
38
(VZ=4.84V - 5.37V)
=PP3V0_HP_DET_BIAS
11 15 27 33 34 39
1
C4810
0.1UF
10%
6.3V
2
X5R
201
R4821
60.4K
12
1/20W
201
CRITICAL
U4801
MAX9061
UCSP
B1
REF
A2
INOUT
(5.5V TOL)
U4801_A2
1%
MF
(3.38V - 3.76V)
1
R4822
140K
1%
1/20W
MF
201
2
GND
A1
(OD)
B2
B
C
B
A
875 421
36
PAGE TITLE
I/O EXPANDER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
48 OF 119
SHEET
36 OF 53
SIZE
A
D
345678
D
DisplayPort Mux
=PP3V0_DPMUX
15
1
R4905
100K
1%
1/20W
MF
201
2
DPMUX
1
C4901
0.1UF
10%
6.3V
2
X5R
201
SW_PT_DP_TX_P<0>
SW_PT_DP_TX_N<0>
SW_PT_DP_TX_P<1>
SW_PT_DP_TX_N<1>
SW_PT_DP_AUX_P
SW_PT_DP_AUX_N
SW_PT_DP_HPD
SW_LD_DP_TX_P<0>
SW_LD_DP_TX_N<0>
SW_LD_DP_TX_P<1>
SW_LD_DP_TX_N<1>
SW_LD_DP_AUX_P
SW_LD_DP_AUX_N
SW_LD_DP_HPD
DP_SW_SEL
DP_SW_SHUTDOWN_L
1
R4901
100K
1%
1/20W
MF
201
2
39 45
OUT
39 45
OUT
39 45
OUT
39 45
OUT
37 39 45
BI
37 39 45
BI
38 45
OUT
38 45
OUT
38 45
OUT
38 45
OUT
37 38 45
BI
37 38 45
BI
6
IN
6
IN
R4950
12
NOSTUFF
1
R4951
10K
5%
1/20W
MF
201
2
R4952
12
NOSTUFF
1
R4953
10K
5%
1/20W
MF
201
2
5%
1/20W
MF
201
1/20W
0
0
5%
MF
201
R4950_2
R4952_2
R4910
21.5K
1%
1/20W
MF
201
12
CRITICAL
2
DZ4900
GDZT2R3.9
GDZ-0201
1
R4911
21.5K
1/20W
201
12
CRITICAL
2
DZ4901
GDZT2R3.9
GDZ-0201
1
1%
MF
DPMUX
1
C4900
0.1UF
10%
6.3V
2
X5R
201
A2
J4
VDD
DPMUX
U4900
CBTL06141EE
BGA
CRITICAL
9
45
IN
H3_DP_TX_N<0>
9
45
IN
C
45
45
45
45
9
IN
9
IN
9
BI
9
BI
H3_DP_TX_P<1>
H3_DP_TX_N<1>
H3_DP_AUX_P
H3_DP_AUX_N
C4902
C4903
C4904
C4905
C4906
C4907
37
B
12
0.1UF
12
0.1UF
12
0.1UF
12
0.1UF
12
0.1UF
12
0.1UF
SW_DP_HPD_OUT
6.3V
6.3V
6.3V
6.3V
6.3V
6.3V
1
R4932
100K
1%
1/20W
MF
201
2
X5R10%
X5R10%
X5R10%
X5R10%
X5R10%
X5R10%
SW_DP_TX_P<0>H3_DP_TX_P<0>
45
201
SW_DP_TX_N<0>
45
201
SW_DP_TX_P<1>
45
201
SW_DP_TX_N<1>
45
201
R4903
R4904
45
201
45
201
0
12
0
12
SW_DP_AUX_P
SW_DP_AUX_N
DDC_AUX_SEL
1
R4900
100K
1%
1/20W
MF
201
2
DP_D2
DP_D3
R4902
12
B2
DOUT_0+
B1
DOUT_0-
D2
DOUT_1+
D1
DOUT_1-
E2
DOUT_2+
E1
DOUT_2-
F2
DOUT_3+
F1
DOUT_3-
H2
AUX+
H1
AUX-
J1
HPDIN
C2
DDC_AUX_SEL
G2
TST0
0
5%
1/20W
MF
201
SIGNAL_MODEL=DPMUX
LO=AUX_CH
HI=DDC
GND
DDC_CLK1
DDC_DAT1
DDC_CLK2
DDC_DAT2
DIN1_0+
DIN1_0-
DIN1_1+
DIN1_1-
DIN1_2+
DIN1_2-
DIN1_3+
DIN1_3-
DAUX1+
DAUX1-
HPD_1
DIN2_0+
DIN2_0-
DIN2_1+
DIN2_1-
DIN2_2+
DIN2_2-
DIN2_3+
DIN2_3-
DAUX2+
DAUX2-
HPD_2
LO=PORT1
HI=PORT2
GPU_SEL
XSD*
B3C8G8H4H7
B4
A4
B5
A5
B6
A6
A8
A9
H9
J9
H8
J8
J2
B8
B9
D8
D9
E8
E9
F8
F9
H6
J6
H5
J5
H3
A1
B7
TP_DP_D1_2P
TP_DP_D1_2N
TP_DP_D1_3P
TP_DP_D1_3N
TP_DP_D2_2P
TP_DP_D2_2N
TP_DP_D2_3P
TP_DP_D2_3N
21
=PP3V0_IO_H3
7
11 13 15 37
PORT_FW_PWR_FLT_R
LAND_FW_FTR_PWR
SW_PT_DP_AUX_N
37 39 45
SW_LD_DP_AUX_N
37 38 45
SW_PT_DP_AUX_P
37 39 45
SW_LD_DP_AUX_P
37 38 45
39
38
1
R4920
100K
1%
1/20W
MF
201
2
1
R4922
100K
1%
1/20W
MF
201
2
1
R4921
100K
1%
1/20W
MF
201
2
1
R4923
100K
1%
1/20W
MF
201
2
D
C
B
DISPLAY PORT SWITCH SELECT
=PP3V0_IO_H3
11 13 15 37
7
1
=PP1V8_H3
6 7 9
12 15
SW_DP_HPD_OUT
37
A
1
C4950
0.1UF
10%
6.3V
2
X5R
201
2
1
6
VCC
U4901
74LVC1G07
SOT886
GND
3
CRITICAL
YA
NCNC
4
5
R4931
100K
1%
1/20W
MF
201
2
H3_DP_HPD
9
875 421
0 - PORTRAIT DOCK
1 - LANDSCAPE DOCK
SIZE
A
D
PAGE TITLE
DISPLAY PORT SWITCH
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
49 OF 119
SHEET
37 OF 53
36
345678
40V 200MA
LANDSCAPE_DOCK
36
FW_PWR_SNS
MAKE_BASE=TRUE
DOCK_FW_PWRLAND_FW_PWR
39
2
DZ5095
GDZT2R5.1B
GDZ-0201
1
D5001
BAS40XG
SOT23
13
D
L5060
100-OHM-EMI
12
LAND_USB_PWR
0.6MM
0.3MM
=PP3V3_LAND_ACC
15 38
C
LAND_DOCK_ACC_DET_L
19 38
PMU_ADC_REF
B
19 39
ADC_IN7
19
(INTERNAL 0.5 GAIN)
LAND_DOCK_POD_TO_ACCDEV_TO_ACC_EXTCONA
11 38
A
LAND_DOCK_ACC_TO_PODACC_TO_DEV_EXTCONA
11 38
SM-3
LANDSCAPE_DOCK
1
R5090
100K
5%
1/20W
MF
201
2
15 39
LANDSCAPE_DOCK
2
DZ5050
8V-100PF
0201
1
LANDSCAPE_DOCK
L5014
FERR-120-OHM-1.5A
12
0402
0.095 OHM DCR
=VCC_MAIN_DOCK
LANDSCAPE_DOCK
R5095
10K
12
5%
1/20W
MF
201
LANDSCAPE_DOCK
R5080
100K
1%
1/20W
MF
201
12
LANDSCAPE_DOCK
R5002
10K
12
5%
1/20W
MF
201
LANDSCAPE_DOCK
L5009
240-OHM-0.2A-0.8-OHM
12
LANDSCAPE_DOCK
L5013
240-OHM-0.2A-0.8-OHM
12
ACC_IDENTIFY_DOCKA_R
0201
0201
2
1
LANDSCAPE_DOCK
1
C5000
0.1UF
10%
6.3V
2
X5R
201
0.6MM
0.2MM
LANDSCAPE_DOCK
LANDSCAPE_DOCK
1
R5000
220K
5%
1/20W
MF
201
2
875 421
LANDSCAPE_DOCK
1
C5050
27PF
5%
25V
2
NP0-C0G
201
DZ5090
8V-100PF
0201
LANDSCAPE_DOCK
1
C5054
27PF
5%
25V
2
NP0-C0G
201
LANDSCAPE_DOCK
1
C5055
27PF
5%
25V
2
NP0-C0G
201
LANDSCAPE_DOCK
R5096
21.5K
12
1%
1/20W
MF
201
LANDSCAPE_DOCK
1
2
LANDSCAPE_DOCK
1
C5051
27PF
5%
25V
2
NP0-C0G
201
LANDSCAPE_DOCK
R5031
0
12
5%
1/20W
MF
201
LANDSCAPE_DOCK
R5030
0
12
5%
1/20W
MF
201
LAND_FW_FTR_PWR
37
C5020
12PF
5%
25V
NP0-C0G
201
1
2
LANDSCAPE_DOCK
R5032
10K
12
5%
1/20W
MF
201
NOSTUFF
1
C5081
0.01UF
10%
10V
2
X5R
201
LANDSCAPE_DOCK
1
C5082
0.01UF
10%
10V
2
X5R
201
EXTCONA_ACC_DETECT_L
LANDSCAPE_DOCK
C5052
27PF
5%
25V
NP0-C0G
201
ACC_IDENTIFY_DOCKA
LANDSCAPE_DOCK
1
C5053
27PF
5%
25V
2
NP0-C0G
201
NOSTUFF
1
C5090
22PF
5%
50V
2
CERM
201
LANDSCAPE_DOCK
1
C5083
0.01UF
10%
25V
2
X7R
402
EXTCONA_3_3V
38
EXTCONA_FW_PWR
LANDSCAPE_DOCK
1
C5080
0.01UF
10%
50V
2
X7R
402
EXTCONA_USB_PWR
SW_LD_DP_TX_P<0>
37 45
SW_LD_DP_TX_N<0>
37 45
SW_LD_DP_TX_P<1>
37 45
SW_LD_DP_TX_N<1>
37 45
SW_LD_DP_AUX_P
37 45
SW_LD_DP_AUX_N
37 45
0.6MM
0.30MM
38
38 12
L0560
12-OHM-100MA
TCM1210-4SM
1
23
12-OHM-100MA
TCM1210-4SM
1
23
12-OHM-100MA
TCM1210-4SM
1
23
EXTCONA_CVBS_PB_1
EXTCONA_C_Y_1
EXTCONA_Y_PR_1
0201
0201
0201
LAND_DP_TX0_P
LAND_DP_TX0_N
TP_D0560_6
AUD_VID_RET_EXTCONNA
EXTCONA_CVBS_PB_1
EXTCONA_C_Y_1
EXTCONA_Y_PR_1
38 45
38 45
LANDSCAPE_DOCK
U5000
NUP412VP5XXG
SOT953
1
2
34
GND_AUDIO_DOCKA
31
DOCK1_CVBS_PB
10 45 38 45
DOCK1_C_Y
10 45
DOCK1_Y_PR
10 45
SYM_VER-1
4
VBUS
5
IO
2
NC
D0560
RCLAMP0502N
SLP1210N6
1
5
XW5000
SHORT-0201
12
LANDSCAPE_DOCK
FL5011
80-OHM-0.2A-0.4-OHM
12
LANDSCAPE_DOCK
FL5007
80-OHM-0.2A-0.4-OHM
12
LANDSCAPE_DOCK
FL5008
80-OHM-0.2A-0.4-OHM
12
6
4
IO
3
NC
GND
L0561
SYM_VER-1
4
D0561
RCLAMP0502N
SLP1210N6
6
VBUS
5
IO
2
NC
IO
NC
GND
1
4
3
LAND_DP_TX1_P
LAND_DP_TX1_N
TP_D0561_6
38 45
38 45
L0562
SYM_VER-1
4
D0562
RCLAMP0502N
SLP1210N6
6
VBUS
5
IO
2
NC
IO
NC
GND
1
4
3
LAND_DP_AUX_P
LAND_DP_AUX_N
TP_D0562_6
38 45
38 45
38
38 45
38 45
38 45
38 45
38 45
38 41
38 41
SIMCRD_RST
SIMCRD_CLK
USB_LAND_DOCK_N
27 44
USB_LAND_DOCK_P
27 44 38 44
38 45
38 45
31
31
31 38 41
38
38
38 45
38 45
38 45
38
38
38
3G_CONFIG
2
DZ5070
6.8V-100PF
0201
1
APN: 377S0045
U5070
NUP412VP5XXG
SOT953
1
2
34
3G_CONFIG
5
SIM_DETECT
36
LANDSCAPE_DOCK
90-OHM-100MA
1
23
LAND_DP_AUX_N
LAND_DP_AUX_P
LINE_OUT1_R
LINE_OUT1_L
EXTCONA_DIFF_SENSE_CONN
AUD_VID_RET_EXTCONNA
EXTCONA_USB_PWR
EXTCONA_CVBS_PB_1
EXTCONA_C_Y_1
EXTCONA_Y_PR_1
EXTCONA_ACC_DETECT_L
DEV_TO_ACC_EXTCONA
ACC_TO_DEV_EXTCONA
VSIM
38 41
38 41
SIMCRD_IO
38 41
L5016
TCM1005
LANDSCAPE_DOCK
NUP412VP5XXG
1
2
34
21
SYM_VER-1
4
LANDSCAPE_DOCK
D5000
RCLAMP0502N
SLP1210N6
5
2
IO
NC
6
VBUS
IO
NC
GND
1
ACC_TO_DEV_EXTCONA
ACC_IDENTIFY_DOCKA
EXTCONA_ACC_DETECT_L
U5050
SOT953
5
DEV_TO_ACC_EXTCONA
APN 516S0818
CRITICAL
LANDSCAPE_DOCK
J5001
AXK744137G
F-ST-SM
1
2
3
4
56
78
9
10
1112
1314
1516
1718
20
19
2122
2324
2526
2728
30
29
3132
3334
3536
3738
40
39
4142
4344
PAGE TITLE
ACC_IDENTIFY_DOCKA
3G_CONFIG
1
C5070
0.1UF
10%
6.3V
2
X5R
201
44-PIN LANDSCAPE DOCK CONN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
EXTCONA_USB_D_N
EXTCONA_USB_D_P
4
3
SIM_DETECT
SIMCRD_RST
SIMCRD_CLK
SIMCRD_IO
LAND_DP_TX0_P
LAND_DP_TX0_N
EXTCONA_USB_D_P
EXTCONA_USB_D_N
LAND_DP_TX1_P
LAND_DP_TX1_N
LAND_DOCK_P17
LAND_DOCK_P14
EXTCONA_3_3V
EXTCONA_FW_PWR
TP_D5000_6
38
38
38
38
VSIM
38 41
38 41
38 41
38 41
38 45
38 45
38 44
38 44
38 45
38 45
11
11
38
38
38
38 44
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
50 OF 119
SHEET
38 OF 53
SIZE
D
C
B
A
D
345678
DEVELOPMENT
R5054
AP_TCK
6
44
AP_TMS
6
44
R5055
12
12
DEVELOPMENT
0
0
DOCK_TCK
DOCK_TMS
39
39
DEVELOPMENT
U5100
40V 200MA
D
DOCK_FW_PWR
38
15 38
PORT_DOCK_ACC_DET_L
19
PORTRAIT_DOCK
D5100
BAS40XG
=VCC_MAIN_DOCK
PORT_FW_PWR_R
13
SOT23
PORTRAIT_DOCK
R5103
10K
12
5%
1/20W
MF
201
PORTRAIT_DOCK
C
PMU_ADC_REF
19 38
PORT_DOCK_ACCID
19
PORT_DOCK_ACC_TO_PODACC_TO_POD_CONN
12 39
B
PORT_DOCK_POD_TO_ACC
12
R5157
100K
12
PORTRAIT_DOCK
R5102
10K
12
5%
1/20W
MF
201
PORTRAIT_DOCK
L5150
240-OHM-0.2A-0.8-OHM
12
PORTRAIT_DOCK
L5151
240-OHM-0.2A-0.8-OHM
12
PORTRAIT_DOCK
R5110
21.5K
12
PORTRAIT_DOCK
1
R5100
220K
5%
1/20W
MF
201
2
PORT_CONN_ACC_DET_R_L
1%
1/20W
201
MF
ACC_IDENTIFY_B_R
PORTRAIT_DOCK
1
C5100
0.1UF
10%
6.3V
2
X5R
201
0201
0201
1%
1/20W
MF
201
PORTRAIT_DOCK
1
C5152
27PF
5%
25V
2
NP0-C0G
201
POD_TO_ACC_CONN
PORTRAIT_DOCK
1
C5153
27PF
5%
25V
2
NP0-C0G
201
37
PORT_FW_PWR_FLT_R
PORTRAIT_DOCK
PORTRAIT_DOCK
R5133
12
PORTRAIT_DOCK
R5134
0
12
5%
1/20W
MF
201
0
5%
1/20W
MF
201
1
R5190
1M
1%
1/20W
MF
201
2
39
R5135
10K
12
5%
1/20W
MF
201
PORT_CONN_ACC_DET_L
PORTRAIT_DOCK
1
C5150
27PF
5%
25V
2
NP0-C0G
201
ACC_IDENTIFY_B
PORTRAIT_DOCK
1
C5151
27PF
5%
25V
2
NP0-C0G
201
NOSTUFF
1
C5130
22PF
5%
50V
2
CERM
201
39
PORT_FW_PWR_FLT
39
39
PORTRAIT_DOCK
R5132
0
HOME_L
6
19 39
12
5%
1/20W
MF
201
PORTRAIT_DOCK
R5150
0
=PP1V8_SDRAM_WL
15
12
5%
1/20W
MF
201
=PP3V0_HP_DET_BIAS
11 15 27 33 34 36
HOME_CONN_L
PORTRAIT_DOCK
1
C5156
27PF
5%
25V
2
NP0-C0G
201
1
R5151
0
5%
1/20W
MF
201
2
1
2
NOSTUFF
DEVELOPMENT
C5140
0.1UF
10%
6.3V
X5R
201
PP1V8_X17
39
PORTRAIT_DOCK
C5157
82PF
CERM
0201
39
0.6MM
0.2MM
CONN_VCC_MAIN_WL
1
5%
25V
2
MAX9061
B1
REF
A2
INOUT
UCSP
GND
B2
CONN_CLK_32K_X17
39
CONN_AP_UART3_RTS_L
12
CONN_AP_UART3_CTS_L
12
CONN_AP_UART3_RXD
12
CONN_AP_UART3_TXD
12
CONN_BT_WAKE
39
CONN_BT_HOST_WAKE
39
CONN_BT_RESET_L
39
CONN_WLAN_HOST_WAKE
39
CONN_WLAN_RESET_L
39
PP1V8_X17
39
GND_AUDIO_DOCKB
31
LINE_OUT2_R
31
LINE_OUT2_L
31
EXTCONB_DIFF_SENSE_CONN
31
A1
RESET_L
USB_PORT_CONN_P
39
USB_PORT_CONN_N
39
SW_PT_DP_TX_P<1>
37 45
SW_PT_DP_TX_N<1>
37 45
SW_PT_DP_TX_N<0>
37 45
SW_PT_DP_TX_P<0>
37 45
SW_PT_DP_AUX_P
37 45
SW_PT_DP_AUX_N
37 45
PORT_CONN_ACC_DET_L
39
ACC_IDENTIFY_B
39
6
19
PN 516S0820 (RCPT - FEMALE)
CRITICAL
PORTRAIT_DOCK
J5100
AXK770137G
F-ST-SM
1
3
5
7
9
1112
1314
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
5152
5354
5556
5758
59
6162
6364
6566
6768
69
2
4
6
CONN_WLAN_SDIO_DATA<2>
8
CONN_WLAN_SDIO_DATA<1>
10
CONN_WLAN_SDIO_DATA<3>
CONN_WLAN_SDIO_DATA<0>
20
30
0.6 mm
0.2 mm
40
50
60
70
CONN_WLAN_SDIO_CMD
CONN_WLAN_SDIO_CLK
0.6MM
0.3MM
USB_PWR_B_CONN
PP3V3_PORT_ACC_CONN
PORT_FW_PWR_FLT
HOME_CONN_L
CONN_BT_I2S_DOUT
CONN_BT_I2S_LRCLK
CONN_BT_I2S_DIN
CONN_BT_I2S_CLK
POD_TO_ACC_CONN
DOCK_TCK
ACC_TO_POD_CONN
DOCK_TMS
DOCK2_Y_PR
DOCK2_C_Y
DOCK2_CVBS_PB
39
39
39
39
10 12 45
10 12 45
10 12 45
39
39
39
39
39
39
39
39
39
39
39
39
39
39
PORTRAIT_DOCK
R5140
0
12
5%
1/20W
MF
201
=PP3V3_PORT_ACC
15 39
NOSTUFF
L5152
90-OHM-100MA
TCM1005
SYM_VER-1
USB_PORT_DOCK_N
27 44
A
USB_PORT_DOCK_PUSB_PORT_CONN_P
27 44 39
1
23
PORTRAIT_DOCK
R5141
4
0
12
5%
1/20W
MF
201
USB_PORT_CONN_N
39
PORTRAIT_DOCK
R5130
USB_PWR_B
16
0.6MM
0.3MM
12
1/10W
MF-LF
603
875 421
5%
0
PORTRAIT_DOCK
R5131
0
12
5%
1/20W
MF
201
PORTRAIT_DOCK
1
C5154
27PF
5%
25V
2
NP0-C0G
201
PP3V3_PORT_ACC_CONN
PORTRAIT_DOCK
1
C5155
27PF
5%
25V
2
NP0-C0G
201
USB_PWR_B_CONN
PORTRAIT_DOCK
1
C5120
12PF
5%
25V
2
NP0-C0G
201
39
36
CONN_WLAN_SDIO_DATA<0>
CONN_WLAN_SDIO_DATA<1>
CONN_WLAN_SDIO_DATA<2>
CONN_WLAN_SDIO_DATA<3>
CONN_WLAN_SDIO_CMD
CONN_WLAN_SDIO_CLK
39
CONN_WLAN_HOST_WAKE
CONN_WLAN_RESET_L
39
CONN_BT_I2S_CLK
39
CONN_BT_I2S_DIN
39
CONN_BT_I2S_DOUT
39
CONN_BT_I2S_LRCLK
39
CONN_BT_WAKE
CONN_BT_HOST_WAKE
39
CONN_BT_RESET_L
CONN_VCC_MAIN_WL
19 39
CLK_32K_X17
21
7
7
7
7
7
7
36
36 39
28 32
28 32
28 32
28 32
6
36 39
36
15 39
45 39
45 39
45 39
45 39
45 39
45 39
D
C
WLAN_SDIO_DATA<0>
MAKE_BASE=TRUE
WLAN_SDIO_DATA<1>
MAKE_BASE=TRUE
WLAN_SDIO_DATA<2>
MAKE_BASE=TRUE
WLAN_SDIO_DATA<3>
MAKE_BASE=TRUE
WLAN_SDIO_CMD
MAKE_BASE=TRUE
WLAN_SDIO_CLK
MAKE_BASE=TRUE
WLAN_HOST_WAKE
MAKE_BASE=TRUE
WLAN_RESET_L
MAKE_BASE=TRUE
BT_I2S_CLK
MAKE_BASE=TRUE
BT_I2S_DIN
MAKE_BASE=TRUE
BT_I2S_DOUT
MAKE_BASE=TRUE
BT_I2S_LRCLK
MAKE_BASE=TRUE
BT_WAKE
MAKE_BASE=TRUE
BT_HOST_WAKE
MAKE_BASE=TRUE
BT_RESET_L
MAKE_BASE=TRUE
=VCC_MAIN_WL
B
CONN_CLK_32K_X17
SIZE
A
D
PAGE TITLE
60-PIN PORTRAIT DOCK CONN
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
51 OF 119
SHEET
39 OF 53
345678
21
BUTTON CONNECTOR
D
CRITICAL
APN: 518S0672
J5400
78171-6006
M-RT-SM
L5400
240-OHM-0.2A-0.8-OHM
AUD_VOL_DOWN_L
6
C
12
0201
AUD_VOL_UP_L
6
12
0201
240-OHM-0.2A-0.8-OHM
L5401
19
RINGER_A
6
12
0201
240-OHM-0.2A-0.8-OHM
L5402
2
DZ5400
201-1
12.8V-100PF12.8V-100PF
1
C5400
82PF
5%
25V
2
CERM
0201
1
DZ5401
12.8V-100PF
201-1
2
1
C5401
82PF
5%
25V
2
CERM
0201
1
DZ5402
201-1
ONOFF_L
6
19
2
1
C5402
82PF
5%
25V
2
CERM
0201
1
12
0201
240-OHM-0.2A-0.8-OHM
L5403
DZ5403
201-1
12.8V-100PF
ONOFF_L_R
2
1
1
C5403
82PF
5%
25V
2
CERM
0201
VOL_DN_L_R
VOL_UP_L_R
RINGER_A_R
7
1
2
3
4
5
6
8
D
C
SIZE
B
A
D
B
A
SYNC_MASTER=MIAMI
PAGE TITLE
BUTTONS CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=09/16/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
54 OF 119
SHEET
40 OF 53
345678
21
D
=PP1V8_SDRAM_GPS
15
=BATT_POS_F_3G
15 41
C
3G_CONFIG
R5500
IN
BB_PMU_ON_R_L
19
12
1/20W
B
3G_CONFIG
L5500
240-OHM-0.2A-0.8-OHM
12
0201
3G_CONFIG
1
R5501
91K
1%
1/20W
MF
201
0
5%
MF
201
2
PP1V8_SDRAM_GPS_CONN
3G_CONFIG
1
C5500
82PF
5%
25V
2
CERM
0201
MAKE_BASE=TRUE
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
12
OUT
12
IN
6
OUT
12
IN
6
IN
12
IN
12
OUT
12
OUT
12
IN
6
IN
7
OUT
7
OUT
12 32
IN
12 32
OUT
12 32
OUT
6
OUT
7
IN
38
IN
6
IN
38
OUT
38
OUT
GPS_UART_TX
GPS_UART_RX
RESET_DET_N
BB_RST_RADIO
RADIO_ON
BB_PMU_ON_L
BB_USART0_CTS_L_CONN
BB_USART0_RTS_L_CONN
UMTS_TXD_CONN
UMTS_RXD_CONN
GPS_RESET_L
BB_I2S2_WA0
BB_I2S2_CLK
BB_I2S1_RX
BB_I2S1_WA0
BB_I2S1_CLK
IPC_SRDY
IPC_MRDY
SIM_DETECT
GPS_SYNC
SIMCRD_CLK
SIMCRD_RST
APN: 516-0223
MATES WITH 998-2489
CARD-EDGE-K48
5152
1112
1314
BB_USB_VBUS
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
5354
CRITICAL
J5500
F-RT-TH
1
3
5
78
9
KEY
3G_CONFIG
2
4
6
10
20
30
40
50
BB_FLASH_ACTIVE
AP_PMU_EXTON
BB_USB_DATA_N
BB_USB_DATA_P
BB_USART0_RXD_CONN
BB_USART0_TXD_CONN
BB_I2S2_RX
BB_I2S2_TX
GPS_UARTS_RTS_L
BB_I2S1_TX
GPS_UARTS_CTS_L
IPC_SCLK_CONN
IPC_MISO
IPC_MOSI_CONN
SIMCRD_IO
GPS_STANDBY_L
=BATT_POS_F_3G
38
BI
6
IN
VSIM
MAKE_BASE=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
15 41
12
OUT
36
OUT
12
IN
12
OUT
7
IN
7
OUT
12
OUT
12 32
OUT
12
IN
7
OUT
APN: 155S0373
U5500
800MHZ-100MA-27PF
0603
5
CRITICAL
OUT1
6
OUT2
7
OUT3
8
OUT4
IN1
IN2
IN3
IN4
1
2
3
4
IPC_SCLK
IPC_MOSI
7
IN
7
IN
GND
9
3G_CONFIG
38
OUT
10
D
C
B
A
SYNC_MASTER=MIAMI
PAGE TITLE
3G CONNECTOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=09/16/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
55 OF 119
SHEET
41 OF 53
SIZE
A
D
D
CIN9 AND CIN11 GO TO ACTUAL SENSOR
(ONE TOP SENSOR LAYER, ONE BOTTOM SHIELD LAYER).
CIN7 AND CIN12 GO UP FLEX
BUT DO NOT CONNECT TO SENSOR.
USED FOR DIFFERENTIAL MEASUREMENT TECHNIQUE.
C
NET_SPACING_TYPE=ANLG
CRITICAL
3G_CONFIG
J5700
FF18-6A-R11AD-B-3H
F-RT-SM
1
2
3
4
5
6
518S0692
PCB: ACSHIELD NEEDS TO BE
A PLANE UNDER PROX_CIN NETS
AND ALSO TIE TO CONNECTOR.
ON DEV BOARD: CIN11/ACSHIELD GOES TO COAX CONNECTOR.
ON MIAMI, CIN7/CIN9/CIN11/CIN12/ACSHIELD GOES TO 6-PIN ZIF.
CHOSE CIN NUMBERS FOR LAYOUT EASE
NET_SPACING_TYPE=ANLG
NET_SPACING_TYPE=ANLG
PINOUT: EVT2 IS REVERSED FROM EARLIER VERSIONS
PROX_ACSHIELD_CONN
PROX_CIN12
PROX_CIN11
PROX_CIN9
PROX_CIN7
PROX_ACSHIELD_CONN
NET_SPACING_TYPE=ANLG
NET_SPACING_TYPE=ANLG
ALIAS TO PROX_ACSHIELD_CONN
NET_SPACING_TYPE=ANLG
12 42
12 42
PROX_ACSHIELD
12
NET_SPACING_TYPE=ANLG
0.5 PF
JUST IN CASE
NEED EXTERNAL
REF CAP TO MEASURE
TP_PROX_CIN2
PROX_CIN5
1
C5703
0.5PF
+/-0.05PF
25V
2
CERM
201
NOSTUFF
345678
VDRIVE IS 3.0V TO DRIVE I2C, AND GPIO. INT WILL BE PULLED UP TO 1.8V
=PP3V0_IO_SMS
1
C5704
0.1UF
10%
6.3V
=PP1V8_SMS
R5700
10K
1%
1/20W
MF
201
3G_CONFIG
2
X5R
201
3G_CONFIG
15 26
1.8 MA MAX
1
C5701
0.1UF
10%
6.3V
2
X5R
201
3G_CONFIG
D2
C2
VDRIVE
VCC
U5700
AD7147A-1
NC
CIN0
NC
A3
CIN1
B3
CIN2
A4
NC
CIN3
C3
CIN4
NC
A5
CIN5
B4
CIN6
NC
B5
CIN7
C4
CIN8
NC
C5
CIN9
D4
CIN10
NC
D5
CIN11
E5
CIN12
WLCSP
353S2681
I2C ADDR:
0X54
CRITICAL
GND
E4
E2
ACSHIELD
3G_CONFIG
BIAS
SDA
ADD0
SCLK
ADD1
INT*
VDRIVE RAIL
GPIO
TP
1
2
3G_CONFIG
E3D3
E1
D1
C1
B1
A1
A2
B2
NC
=PP3V0_IO_SMS
C5700
2.2UF
10%
6.3V
X5R
402
PROX_BIAS
1
C5702
0.01UF
10%
10V
2
X5R
201
3G_CONFIG
15 26 42
1
R5701
100K
1%
1/20W
MF
201
2
3G_CONFIG
1
2
PROX_GPIO
15 26 42
PROX_SDA_3V0
PROX_SCL_3V0
PROX_INT_L
BI
BI
IN
OUT
7
PROX_GPIO IS 3.0V LEVEL.
INT IS 1.8V LEVEL.
12
ALIASED TO I2C2 NETS
12
6
P.U. REQUIRED
TO H3
21
D
C
PCB: ENSURE ACSHIELD PLANE UNDER
U5700, NO GND PLANE NEAR PROX_CIN NETS..
SIZE
B
A
D
B
A
SYNC_MASTER=MARKSIN
PAGE TITLE
PROX SENSOR
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
875 421
36
SYNC_DATE=10/14/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
57 OF 119
SHEET
42 OF 53
345678
21
16GB FLASH CONFIGURATIONS
PART#
335S0648
PART NUMBER
335S0683
QTY
DESCRIPTION
2
TOSHIBA 43NM 8GB
ALTERNATE FOR
PART NUMBER
BOM OPTION
16GB_PROD
REFERENCE DESIGNATOR(S)
U6700,U6710
REF DES
COMMENTS:
U6700,U6710
SAMSUNG 35NM 8GB
BOM OPTION
16GB_PROD
TABLE_ALT_HEAD
TABLE_ALT_ITEMTABLE_ALT_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
D
1
C6703
82PF
5%
25V
2
CERM
0201
1
C6700
0.1UF
10%
6.3V
2
X5R
201
1
C6701
0.1UF
10%
6.3V
2
X5R
201
=PP3V3_NAND
1
2
C6702
2.2UF
20%
4V
X5R
402
8
43 15
7
C
F2
G5
OB0
OB8
OC0
OC8
OD0
OD8
OE0
OF0
OF8
1
R6702
100K
1%
1/20W
MF
201
2
F0WP_N
44 43
TP6700
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
NOSTUFF
P4MM
SM
PP
44 43
44 43
44 43
44 43
44 43
44 43
44 43
44 43
F0AD<0>
8
F1AD<0>
8
F0AD<1>
8
F1AD<1>
8
F0AD<2>
8
F1AD<2>
8
F0AD<3>
8
F1AD<3>
8
F0AD<4>
8
F1AD<4>
8
F0AD<5>
8
F1AD<5>
8
F0AD<6>
8
F1AD<6>
8
F0AD<7>
8
F1AD<7>
8
R6701
100K
1
F0RE_N
8
F1RE_N
8
F0WE_N
8
F1WE_N
8
F0CE2_N
44
8
F1CE2_N
44
8
F0CE3_N
44
8
F1CE3_N
44
8
F0CLE
8
F1CLE
8
F0ALE
8
F1ALE
8
12
1/20W
NAND1_RB
1%
MF
201
B6
M6N1N7
VCC
OMIT
(2 OF 2)
IO1_1
IO1_2
IO2_1
IO2_2
IO3_1
IO3_2
IO4_1
IO4_2
IO5_1
IO5_2
IO6_1
IO6_2
IO7_1
IO7_2
IO8_1
IO8_2
RY/BY-1*
RY/BY-2*
RY/BY-3*
RY/BY-4*
RE_1*
RE_2*
WE_1*
WE_2*
CE_1*
CE_2*
CE_3*
CE_4*
CLE_1
CLE_2
ALE_1
ALE_2
U6700
LGA
WP_1*
WP_2*
NC
TH58NVG7D1DLA87
NAND-56NM-16GX8-MLC-3.3V-ODP-LGA52
OA8
OA0
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
E5
E7
A7
C7
D6
E3
E1
A5
C5
A1
A3
C3
C1
D2
F0AD<0>
44 43
8
F1AD<0>
44 43
8
F0AD<1>
44 43
8
F1AD<1>
44 43
8
F0AD<2>
44 43
8
F1AD<2>
44 43
8
F0AD<3>
44 43
8
F1AD<3>
44 43
8
F0AD<4>
44 43
8
F1AD<4>
44 43
8
F0AD<5>
44 43
8
F1AD<5>
44 43
8
F0AD<6>
44 43
8
F1AD<6>
44 43
8
F0AD<7>
44 43
8
F1AD<7>
44 43
8
R6700
100K
B
F0RE_N
44 43
8
F1RE_N
44 43
8
F0WE_N
44 43
8
F1WE_N
44 43
8
F0CE0_N
44
8
F1CE0_N
44
8
F0CE1_N
44
8
F1CE1_N
44
8
F0CLE
44 43
8
F1CLE
44 43
8
F0ALE
44 43
8
F1ALE
44 43
8
12
1/20W
NAND0_RB
1%
MF
201
VSS
B2
L3
M2
F6
OE8
32GB FLASH CONFIGURATIONS
PART#
335S0649
PART NUMBER
335S0682335S0648
QTY
DESCRIPTION
TOSHIBA 43NM 16GB
2
ALTERNATE FOR
PART NUMBER
335S0649
BOM OPTION
32GB_PROD
REFERENCE DESIGNATOR(S)
U6700,U6710
REF DES
COMMENTS:
U6700,U6710
SAMSUNG 35NM 16GB
64GB FLASH CONFIGURATIONS
C6713
82PF
5%
25V
CERM
0201
F2
G5
OB0
OB8
OC0
OC8
OD0
NC
OD8
OE0
OF0
OF8
REF DES
U6700,U6710
REFERENCE DESIGNATOR(S)
U6700,U6710
COMMENTS:
SAMSUNG 35NM 32GB
1
C6710
0.1UF
10%
6.3V
2
X5R
201
PART#
335S0650
PART NUMBER
E5
E7
A7
OA8
C7
D6
E3
E1
A5
C5
A1
OA0
A3
C3
C1
D2
QTY
G3
G1
H2
J1
J3
L1
K2
N3
L5
N5
K6
L7
J5
J7
H6
G7
DESCRIPTION
TOSHIBA 43NM 32GB
2
ALTERNATE FOR
PART NUMBER
335S0650335S0665
IO1_1
IO1_2
IO2_1
IO2_2
IO3_1
IO3_2
IO4_1
IO4_2
IO5_1
IO5_2
IO6_1
IO6_2
IO7_1
IO7_2
IO8_1
IO8_2
RY/BY-1*
RY/BY-2*
RY/BY-3*
RY/BY-4*
RE_1*
RE_2*
WE_1*
WE_2*
CE_1*
CE_2*
CE_3*
CE_4*
CLE_1
CLE_2
ALE_1
ALE_2
BOM OPTION
64GB_PROD
1
2
B6
M6N1N7
VCC
OMIT
(2 OF 2)
U6710
LGA
WP_1*
WP_2*
TH58NVG7D1DLA87
NAND-56NM-16GX8-MLC-3.3V-ODP-LGA52
VSS
B2
L3
M2
F6
OE8
1
C6711
0.1UF
10%
6.3V
2
X5R
201
F0WP_N
BOM OPTION
32GB_PROD
TABLE_ALT_HEAD
BOM OPTION
64GB_PROD
TABLE_ALT_HEAD
TABLE_ALT_ITEM
1
C6712
2.2UF
20%
4V
2
X5R
402
44 43
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
=PP3V3_NAND
D
43 15
8 7
C
B
A
SYNC_MASTER=MIAMI
PAGE TITLE
FLASH
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SYNC_DATE=09/16/2009
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
100 OF 119
SHEET
44 OF 53
36
345678
21
Video Signal Constraints
LAYER
VID_50S
NET_PHYSICAL_TYPE
AREA_TYPE
LVDS_100D
D
MIPI_100D
SMIA_100D
DP_100D
NET_SPACING_TYPE1 NET_SPACING_TYPE2
ANALOG_VIDEO
LVDS
MIPI
SMIA
DP
ALLOW ROUTE
ON LAYER?
PHYSICAL_RULE_SET
*
90_OHM_DIFF
*
90_OHM_DIFF
*
90_OHM_DIFF
*
90_OHM_DIFF
*
**
**
**
**
SDIO SIGNAL CONSTRAINTS
NET_PHYSICAL_TYPE
AREA_TYPE
SDIO_50S
NET_SPACING_TYPE1 NET_SPACING_TYPE2
C
SDIO
PHYSICAL_RULE_SET
*
50_OHM_SE
**
Y*
AREA_TYPE
AREA_TYPE
MINIMUM LINE WIDTH
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
SPACING_RULE_SET
*
TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM
SPACING_RULE_SET
2.5:1_SPACING
4:1_SPACING
4:1_SPACING
4:1_SPACING
4:1_SPACING
1.5:1_SPACING
MINIMUM NECK WIDTH
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
=50_OHM_SE
MAXIMUM NECK LENGTH
=50_OHM_SE=50_OHM_SE
DIFFPAIR PRIMARY GAP
=STANDARD
MIPI,SMIA AND DISPLAYPORT BUS CONSTRAINTS
ELECTRICAL_CONSTRAINT_SET
I91
I92
I93
I94
I95
I96
I271
I270
I97
I98
I99
I100
I170
I171
I279
I278
DIFFPAIR NECK GAPPHYSICAL_RULE_SET
MIPI_ECS
MIPI_ECS
MIPI_ECS
MIPI_ECS
MIPI_ECS
SMIA_ECS
SMIA_ECS
=STANDARD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
MIPI_100D
SMIA_100D
SMIA_100D
SMIA_100D
SMIA_100D
SMIA_100D
SMIA_100D
NET_TYPE
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
MIPI
SMIA
SMIA
SMIA
SMIA
SMIA
SMIA
SPACING
H3_MIPID_DATA_P<0>
H3_MIPID_DATA_N<0>
H3_MIPID_DATA_P<1>
H3_MIPID_DATA_N<1>
H3_MIPID_DATA_P<2>
H3_MIPID_DATA_N<2>
H3_MIPID_DATA_P<3>
H3_MIPID_DATA_N<3>
H3_MIPID_CLK_P
H3_MIPID_CLK_N
CAM_SMIA_DATA_P
CAM_SMIA_DATA_N
CAM_SMIA_CLK_P
CAM_SMIA_CLK_N
CONN_SMIA_CLK_P
CONN_SMIA_CLK_N
D
LVDS CONSTRAINTS
NET_TYPE
NET_TYPE
SPACING
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
SPACING
SDIO
SDIO
SDIO
LVDS_DATA_P<2..0>
LVDS_DATA_N<2..0>
LVDS_CLK_P
LVDS_CLK_N
LVDS_CONN_CLK_P
LVDS_CONN_CLK_N
LVDS_DAT_P<2..0>
LVDS_DAT_N<2..0>
WLAN_SDIO_CLK
WLAN_SDIO_CMD
WLAN_SDIO_DATA<3..0>
13 25
13 25
13 25
13 25
25
25
25
25
7
7
7
C
39
39
39
ELECTRICAL_CONSTRAINT_SET
LVDS_ECS
I175
I174
LVDS_ECSLVDS
I176
I178
I234
I235
I245
9
14
9
14
9
14
9
14
9
14
9
14
9
14
9
14
9
14
9
14
I244
HX SDIO CONSTRAINTS
ELECTRICAL_CONSTRAINT_SET
WLAN_SDIO_ECS
I200
WLAN_SDIO_CMD_ECS
I201
WLAN_SDIO_ECS
I202
PHYSICAL
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
PHYSICAL
SDIO_50S
SDIO_50S
SDIO_50S
DP_H3_ECS
I247
I249
DP_H3_ECS
I248
I250
DP_H3_ECS
I251
I252
I253
ANALOG VIDEO CONSTRAINTS
B
A
ELECTRICAL_CONSTRAINT_SET
I213
I214
I215
I216
I217
I218
I232
I231
I233
I219
I220
I221
I222
I224
I223
I225
I226
I227
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
VID_50S
PHYSICAL
NET_TYPE
SPACING
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
ANALOG_VIDEO
DAC_OUT1
DAC_OUT2
DAC_OUT3
LAND_YOUT
LAND_CVBS_OUT
LAND_COUT
PORT_YOUT
PORT_CVBS_OUT
PORT_COUT
DOCK1_CVBS_PB
DOCK1_C_Y
DOCK1_Y_PR
EXTCONA_CVBS_PB_1
EXTCONA_C_Y_1
EXTCONA_Y_PR_1
DOCK2_CVBS_PB
DOCK2_C_Y
DOCK2_Y_PR
10
10
10
10
10
10
10
10
10
10 38
10 38
10 38
38
38
38
10 12 39
10 12 39
10 12 39
I246
I254
I255
I256
I257
I259
I260
I261
I262
I263
I258
I265
I266
I267
I268
I269
I264
I273
I274
I275
I276
I277
I272
DP_PORT_ECS
DP_PORT_ECS
DP_PORT_ECS
DP_LAND_ECS
DP_LAND_ECS
DP_LAND_ECS
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
H3_DP_TX_P<0>
H3_DP_TX_N<0>
H3_DP_TX_P<1>
H3_DP_TX_N<1>
H3_DP_AUX_P
H3_DP_AUX_N
SW_DP_TX_P<0>
SW_DP_TX_N<0>
SW_DP_TX_P<1>
SW_DP_TX_N<1>
SW_DP_AUX_P
SW_DP_AUX_N
SW_PT_DP_TX_P<0>
SW_PT_DP_TX_N<0>
SW_PT_DP_TX_P<1>
SW_PT_DP_TX_N<1>
SW_PT_DP_AUX_P
SW_PT_DP_AUX_N
SW_LD_DP_TX_P<0>
SW_LD_DP_TX_N<0>
SW_LD_DP_TX_P<1>
SW_LD_DP_TX_N<1>
SW_LD_DP_AUX_P
SW_LD_DP_AUX_N
LAND_DP_TX0_P
LAND_DP_TX0_N
LAND_DP_TX1_P
LAND_DP_TX1_N
LAND_DP_AUX_P
LAND_DP_AUX_N
875 421
9
9
9
9
9
9
37
37
37
37
37
37
37 39
37 39
37 39
37 39
37 39
37 39
37 38
37 38
37 38
37 38
37 38
37 38
38
38
38
38
38
38
37
37
37
37
37
37
B
SIZE
A
D
SYNC_MASTER=MIAMI
PAGE TITLE
MORE CONSTRAINTS
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING NUMBER
051-8245
REVISION
B.0.0
BRANCH
PAGE
106 OF 119
SHEET
46 OF 53
36
345678
12
Title: Basenet Report
Design: lost
Date: Feb 19 11:01:06 2008
Base nets and synonyms for lost_lib.LOST(@lost_lib.lost(sch_1))
Base Signal Synonyms Location([Zone][dir])