Datasheet SA18 Datasheet (Apex)

PULSE WIDTH MODULATION AMPLIFIER

TOP

VIEW

CLK IN

CLK OUT

+PWM

FLAG

SIG GND

SHDN

NC
NC

+VS

VCC

*

*

OUT
PWR GND

1
2
3
4
5
6

12
11
10

9
8
7

TOP

VIEW

Case tied to pin 5. Allow no current in case. Bypassing of supplies
is required. Package is Apex MO–127 (STD). See Outline
Dimensions/Packages in Apex data book.

As +PWM goes more positive, out duty cycle increases.
*See text.

MICROTECHNOLOGY

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FEATURES

• HALF BRIDGE IGBT OUTPUT

• WIDE SUPPLY RANGE—16-500V

• 20A TO 100°C CASE

• 3 PROTECTION CIRCUITS

• SYNCHRONIZED OR EXTERNAL OSCILLATOR

• FLEXIBLE FREQUENCY CONTROL

APPLICATIONS

• MOTORS

• REACTIVE LOADS

• LOW FREQUENCY SONAR

• LARGE PIEZO ELEMENTS

• OFF-LINE DRIVERS

• C-D WELD CONTROLLER

DESCRIPTION

The SA18 is a pulse width modulation amplifier that can
supply 10KW to the load. An internal oscillator requires no
external components. The clock input stage divides the oscil­lator frequency by two, which provides the switching fre­quency of 22.5 kHz. External oscillators may also be used to
lower the switching frequency or to synchronize multiple
amplifiers. A shutdown input turns off both drivers of the half
bridge output. A high side current limit protects the amplifier
from shorts to ground in addition to load shorts. The output
IGBTs are protected from thermal overloads by directly sens­ing the temperature of the die. The 12-pin hermetic MO-127
power package occupies only 3 square inches of board space.

SA18

∆

TE949311

EXTERNAL CONNECTIONS

SA18

U

S

A

BeO

BLOCK DIAGRAM AND TYPICAL APPLICATION
VOLTAGE CONTROLLED VOLTAGE SOURCE

Vcc

10

+PWM

3
4

FLAG

CLK OUT

CONTROL

SIGNAL

3/7V

5V

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2

CLK IN

1

5

SIG GND

470pF

OSC

56K

÷2

10V

P-P

CURRENT

LIMIT

PWM

OUTPUT

DRIVERS

SHUTDOWN

CONTROL

9

+V

S

OUT

8

12

NC

NC

11

6

SHDN

7

PWR GND

5V

.01

5K

µF

RSENSE

LOAD

SA18

ABSOLUTE MAXIMUM RATINGS

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

SUPPLY VOLTAGE, +V
SUPPLY VOLTAGE, V
POWER DISSIPATION, internal
TEMPERATURE, pin solder - 10s 300°C
TEMPERATURE, junction

S

CC

1

2

500V
16V
125W

150°C
TEMPERATURE, storage –65 to +150°C
OPERATING TEMPERATURE RANGE, case –55 to +125°C
INPUT VOLTAGE, +PWM 0 TO +11V
INPUT VOLTAGE, SHDN 0 TO +11V

SPECIFICATIONS

PARAMETER TEST CONDITIONS
CLOCK (CLK)

CLK OUT, high level
CLK OUT, low level
CLK IN, low level
CLK IN, high level

4

4

4

4

I

≤ 1mA 4.8 5.3 V

OUT

I

≤ 1mA 0 .4 V

OUT

FREQUENCY 44.10 45.00 45.9 kHz

ANALOG INPUT (+PWM)

center voltage 5V
P-P voltage 0/100% modulation 4 V

FLAG

FLAG, high level 10 V
FLAG, low level 0V

OUTPUT

TOTAL DROP I = 20A 2.7 V
EFFICIENCY, 20A output VS = 380V 98 %
SWITCHING FREQUENCY OSC in ÷ 2 22.05 22.50 22.95 kHz
CURRENT, continuous
CURRENT, peak

4

4

100°C case 20 A

2

MIN TYP MAX UNITS

0.9V

3.7 5.4 V

28 A

POWER SUPPLY

VOLTAGE, V
VOLTAGE, V
CURRENT, V
CURRENT, V
CURRENT, V

I

/SHUTDOWN

LIM

S
CC

CC

shutdown 50 mA

CC,
S

I

= 0 80 mA

OUT

No Load 45 mA

15 240 500 V
14 15 16 V

TRIP POINT 90 110 mV
INPUT CURRENT 100 nA

THERMAL

3

RESISTANCE, junction to case 1 °C/W
RESISTANCE, junction to air 12 °C/W

NOTES: 1. Each of the two output transistors can dissipate 125W, but only one is on at any time.

2. Unless otherwise noted: TC = 25°C, VS, VCC at typical specification.

3. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power
dissipation to achieve high MTTF. For guidance, refer to the heatsink data sheet.

4. Guaranteed but not tested.

CAUTION

The SA18 is constructed from static sensitive components. ESD handling procedures must be observed.
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush,

machine, or subject to temperatures in excess of 850°C to avoid generating toxic fumes.

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TYPICAL PERFORMANCE
GRAPHS

SA18

125

POWER DERATING

100

75

50

25

EACH ACTIVE

OUTPUT TRANSISTOR

0

INTERNAL POWER DISSIPATION, (W)

FORWARD CURRENT, (A)

25 50 125

0 75 100

CASE TEMPERATURE, (°C)

20

16

12

8

4

0

DIODE FORWARD VOLTAGE DROP, (V)

REVERSE DIODE

Tc = 100°C Tc = 25°C

1.0 1.5 2.0 3.02.5

0.5

100

CLOCK LOADING

99

98

97

96

NORMALIZED FREQUENCY, (%)

95

CLOCK LOAD RESISTANCE, (Ω)

3

CASE TEMPERATURE

2.5

2

1.5

1

TOTAL VOLTAGE DROP, (V)

048121620

F NOMINAL = 45kHz

10K

TOTAL VOLTAGE DROP

100°C

OUTPUT CURRENT, I(A)

25°C

CLOCK FREQUENCY OVER TEMP

102.0

101.5

101.0

100.5
100

99.5

99.0

98.5

NORMALIZED FREQUENCY, (%)

98.0
–25 0 25 50 75 100 125

1M100K

–50

CASE TEMPERATURE, (°C)

CONTINUOUS AMPS

20

18

16

14

12

CONTINUOUS AMPS, (A)

10

25 50 75 100 125

CASE TEMPERATURE, (°C)

Vcc QUIESCENT CURRENT

115

Vcc = 15V
F = 22.5 kHz

110
105
100

95
90
85

80

–50 –25 0 25 50 75 100 125

NORMALIZED Vcc QUIESCENT CURRENT, (%)

CASE TEMPERATURE, (°C)

NORMAL
OPERATION

SHUTDOWN
OPERATION

DUTY CYCLE VS ANALOG INPUT

100

80

60

40

DUTY CYCLE, (%)

20

OUT

0

35476

ANALOG INPUT, (V)

Vs QUIESCENT VS VOLTAGE

150

125

100

75

50

0 100 200 300 400 500

NORMALIZED Vs QUIESCENT CURRENT, (%)

Vs, (V)

Vcc QUIESCENT CURRENT

100

96

92

88

84

5

NORMALIZED QUIESCENT CURRENT, (%)

SWITCHING FREQUENCY, F (kHz)

Vs QUIESCENT VS FREQUENCY

100

90

80

70

60

50

NORMALIZED Vs QUIESCENT CURRENT, (%)

10 15 20

525

SWITCHING FREQUENCY, F (kHz)

2510 15 20

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OPERATING
CONSIDERATIONS

GENERAL

Helpful information about power supplies, heatsinking and
mounting can be found in the “General Operating Consider­ations” section of the Apex data book. For information on the
package outline, heatsinks, and mounting hardware see the
“Package Outlines” and “Accessories” section of the data
book. Also see Application Note 30 on “PWM Basics.”

CLOCK CIRCUIT AND RAMP GENERATOR

The clock frequency is internally set to a frequency of
approximately 45kHz. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to an
RC network which produces a ramp signal. An external clock
signal can be applied to the CLK IN pin for synchronization
purposes, but must be 45 kHz +/- 2%.

FLAG OUTPUT

Whenever the SA18 has detected a fault condition, the flag
output is set high (10V). When the programmable low side
current limit is exceeded, the FLAG output will be set high. The
FLAG output will be reset low on the next clock cycle. This
reflects the pulse-by-pulse current limiting feature. When the
internally-set high side current limit is tripped or the thermal
limit is reached, the FLAG output is latched high. See PRO­TECTION CIRCUITS below.

PROTECTION CIRCUITS

A high side current monitor will latch off the output transistors
when the high side current rises to approximately 150% of
rated output. The temperature of the output transistors is also
monitored. When either of the output transistors reaches
approximately 165°C both are latched off. In either case, it will
be necessary to remove the fault condition and recycle power
to Vcc to restart the circuit. A short to +Vs can be protected
against by inserting a sensing resistor into the PWR GND
circuit as shown in Figure A.

PWR GND

SHDN

R

1

C

1

R

SENSE

FIGURE A. PROTECTING AGAINST SHORTS TO +Vs.

In Figure A, the sense resistor inserted into the PWR GND

connection is tied to the SHDN pin. When the current from a
short to +Vs develops 100 mV across the sense resistor the
shutdown circuit will shut off the output transistors for the
remainder of the switching cycle. The SA18 will restart at the
beginning of a new cycle and retest for this condition. This
circuit does not test for shorts to ground. The RC circuit R
filters out any switching spikes and may need to be adjusted to
ignore normal current spikes in the application circuit.

1, C1

SA18

An external shutdown command can be mixed with the
protection circuit of Figure A. In figure B a 10V shutdown
command signal is injected directly into the shutdown pin
(SHDN). As long as the shutdown command remains high both
output transistors will remain off.

PWR GND

SHDN

C

FIGURE B. ADDING SHUTDOWN CONTROL.

BYPASSING

Adequate bypassing of the power supplies is required for
proper operation. Failure to do so can cause erratic and low
efficiency operation as well as excessive ringing at the outputs.
The Vs supply should be bypassed with at least a 1µF ceramic
capacitor in parallel with another low ESR capacitor of at least
10µF per amp of output current. Capacitor types rated for
switching applications are the only types that should be consid­ered. The bypass capacitors must be physically connected
directly to the power supply pins. Even one inch of lead length
will cause excessive ringing at the outputs. This is due to the
very fast switching times and the inductance of the lead
connection. The bypassing requirements of the Vcc supply are
less stringent, but still necessary. A .1µF to .47µF ceramic
capacitor connected directly to the Vcc pin will suffice.

STARTUP CONDITIONS

The high side of the IGBT output bridge circuit is driven by
bootstrap circuit and charge pump arrangement. In order for
the circuit to produce a 100% duty cycle indefinitely the low
side of each half bridge circuit must have previously been in the
ON condition. This means, in turn, that if the input signal to the
SA18 at startup is demanding a 100% duty cycle, the output
may not follow the command and may be in a tri-state condi­tion. The ramp signal must cross the input signal at some point
to correctly determine the output state. After the ramp crosses
the input signal level one time, the output state will be correct
thereafter.

R

2

10V

SHUTDOWN

R

1

IN4148

1

R

SENSE

SIGNAL

This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.

SA18U REV. A JUNE 1999 © 1999 Apex Microtechnology Corp.