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UG-123
Evaluation Board for Fractional-N PLL Frequency Synthesizer
FEATURES
Self-contained board including synthesizer, VCO, 10 MHz
TCXO reference, USB interface, voltage regulators, and
loop filter (5.8 GHz)
Designed for 10 MHz PFD frequency, minimum charge pump
current, and 20 kHz loop bandwidth
Accompanying software allows control of synthesizer
functions from a PC (via USB interface)
Battery operated: choice of 3 V or 5 V supplies
GENERAL DESCRIPTION
The EVAL-ADF4158EB1Z evaluates the performance of the
ADF4158 frequency synthesizer for phase locked loops (PLL).
A digital picture is shown in Figure 1. It contains the ADF4158
synthesizer, a PC connector, SMA connectors for the power
supplies, and an RF output. There is also a low pass loop filter
(20 kHz) and a VCO (Z Communications, Inc., VCO940ME03
5.8 GHz) on board. The evaluation board is set up for a 10 MHz
PFD comparison frequency. An on-board TCXO provides the
10 MHz reference frequency. A USB cable is included with the
board to connect to a PC USB port.
The package also contains Windows® software (2000- and XPcompatible) to allow easy programming of the synthesizer.
EVALUATION KIT CONTENTS
Antistatic bag with USB warning label (free issue by Analog
Devices, Inc.)
Fractional-N synthesizer CD (with USB control) (issue by
Analog Devices)
Evaluation board box (Europaks K-645/1) with EVAL-
ADF4158EB1Z barcode label
Wrapping material (antistatic bubble wrap)
DIGITAL PICTURE OF THE EVALUATION BOARD
Figure 1.
08972-001
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 12
UG-123 Evaluation Board User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Ordering Information .................................................................... 11
Bill of Materials ........................................................................... 11
Rev. 0 | Page 2 of 12
Evaluation Board User Guide UG-123
EVALUATION BOARD HARDWARE
OVERVIEW
The EVAL-ADF4158EB1Z is supplied with a cable for
connecting to the USB port of a PC. The silk screen for the
evaluation board is shown in Figure 2. The board schematic
is shown in Figure 7, Figure 8, and Figure 9.
It is very important to note that the AV
pins of the ADF4158 should never exceed the V
ADF4158. This can cause damage to the device.
If the user wishes, external power supplies can be used. In this
case, insert SMA connectors as shown on the silk screen (see
Figure 2) and the digital picture (see Figure 1) of the evaluation
board.
LOOP FILTER
The loop filter schematic is included in the board schematic
in Figure 7, Figure 8, and Figure 9. The loop filter component
placements are clarified in Figure 3.
, DVDD, and SDVDD
DD
pin of the
P
Figure 2. Evaluation Board Silk Screen
POWER SUPPLIES
The board is powered from a single 9 V battery. The power
supply circuitry allows the user to choose 3 V for the AV
DV
, and SDVDD pins of the ADF4158 and either 3 V or 5 V
DD
for the V
default settings are 3 V for AV
for V
pin of the ADF4158 and for the VCO supply. The
P
, DVDD, and SDVDD and 5 V
DD
.
P
DD
C3 R1
R2 C2 C1
Figure 3. Loop Filter Placement
R2A
R1A
R3
08972-003
LOCAL OSCILLATOR COMPONENTS
The 10 MHz TCXO provides the reference frequency. The
on-chip R divider should be set to 1 so that the PFD frequency
is also 10 MHz. The PLL is made up of the 10 MHz TCXO, the
ADF4158, a passive loop filter (20 kHz bandwidth), and the
VCO V940ME03 VCO from Z Communications. The output is
available at RF
08972-002
The on-board loop filter has been designed for a charge pump
current of 0.3125 mA. ADIsimPLL, a free download available at
www.analog.com/pll, can be used to design other loop filters.
,
through a standard SMA connector.
OUT
Rev. 0 | Page 3 of 12
UG-123 Evaluation Board User Guide
EVALUATION SETUP
SPECTRUM ANALYZER
9V BATTERY
ONOFF
PC
5.8GHz VCO
RF
OUT
TCXO
EVAL-ADF4158EB1Z
REF
IN
MUXOUT
ADF4158
PC CONNECTOR
08972-007
Figure 4. Evaluation Setup
Rev. 0 | Page 4 of 12
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