Analog Devices MAT02FH Datasheet

Low Noise, Matched

a

FEATURES
Low Offset Voltage: 50 ␮V max
Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/√Hz max
High Gain (h

500 min at I

300 min at I
Excellent Log Conformance: r
Low Offset Voltage Drift: 0.1 ␮V/ⴗC max
Improved Direct Replacement for LM194/394

PRODUCT DESCRIPTION

The design of the MAT02 series of NPN dual monolithic tran­sistors is optimized for very low noise, low drift and low r
Precision Monolithics’ exclusive Silicon Nitride “Triple­Passivation” process stabilizes the critical device parameters
over wide ranges of temperature and elapsed time. Also, the high
current gain (h
range of collector current. Exceptional characteristics of the
MAT02 include offset voltage of 50 µV max (A/E grades) and
150 µV max F grade. Device performance is specified over the
full military temperature range as well as at 25°C.

Input protection diodes are provided across the emitter-base
junctions to prevent degradation of the device characteristics
due to reverse-biased emitter current. The substrate is clamped
to the most negative emitter by the parasitic isolation junction
created by the protection diodes. This results in complete isola­tion between the transistors.

):

FE

= 1 mA

C

= 1 ␮A

C

) of the MAT02 is maintained over a wide

FE

⯝ 0.3 ⍀

BE

BE

.

Dual Monolithic Transistor

MAT02

PIN CONNECTION

TO-78

(H Suffix)

NOTE
Substrate is connected to case on TO-78 package.
Substrate is normally connected to the most negative
circuit potential, but can be floated.

The MAT02 should be used in any application where low
noise is a priority. The MAT02 can be used as an input
stage to make an amplifier with noise voltage of less than

1.0 nV/√Hz at 100 Hz. Other applications, such as log/antilog
circuits, may use the excellent logging conformity of the
MAT02. Typical bulk resistance is only 0.3 Ω to 0.4 Ω. The
MAT02 electrical characteristics approach those of an ideal
transistor when operated over a collector current range of 1
µA to 10 mA. For applications requiring multiple devices
see MAT04 Quad Matched Transistor data sheet.

REV. E

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

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Fax: [phone] © Analog Devices, Inc., 2002

MAT02–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VCB = 15 V, IC = 10 ␮A, TA = 25ⴗC, unless otherwise noted.)

MAT02E MAT02F

Parameter Symbol Conditions Min Typ Max Min Typ Max Unit

Current Gain h

Current Gain Match ∆h
Offset Voltage V
Offset Voltage ∆V

Change vs. V

CB

Offset Voltage Change ∆V

FE

FE

OS

/∆VCB0 ≤ VCB ≤ V

OS

/∆I

OS

IC = 1 mA

= 100 µA 500 590 400 590

I

C

I

= 10 µA 400 550 300 550

C

I

= 1 µA 300 485 200 485

C

10 µA ≤ IC ≤ 1 mA
VCB = 0, 1 µA ≤ IC ≤ 1 mA

1 µA ≤ IC ≤ 1 mA
VCB = 0 V 5 25 5 50 µV

C

vs. Collector Current 1 µA ≤ I

1

MAX

≤ 1 mA

C

500 605 400 605

2

3

4

3

3

0.5 2 0.5 4 %
10 50 80 150 µV
10 25 10 50 µV
10 25 10 50 µV

525 5 50µV

Offset Current

Change vs. V

CB

Bulk Resistance r

∆IOS/∆V

BE

0 ≤ VCB ≤ V

CB

10 µA ≤ IC ≤ 10 mA

MAX

5

30 70 30 70 pA/V

0.3 0.5 0.3 0.5 Ω

Collector-Base

Leakage Current I

CBO

Collector-Collector

Leakage Current I

CC

Collector-Emitter V

Leakage Current I

Noise Voltage Density e

CES

n

VCB = V

VCC = V

VBE = 0 35 200 35 400 pA
IC = 1 mA, VCB = 0

CE

= V

MAX

MAX

MAX

5, 6

5, 6

7

25 200 25 400 pA

35 200 35 400 pA

fO = 10 Hz 1.6 2 1.6 3 nV/√Hz
f

= 100 Hz 0.9 1 0.9 2 nV/√Hz

O

= 1 kHz 0.85 1 0.85 2 nV/√Hz

f

O

f

= 10 kHz 0.85 1 0.85 2 nV/√Hz

O

Collector Saturation

Voltage V
Input Bias Current I
Input Offset Current I

B

OS

Breakdown Voltage BV
Gain-Bandwidth Product f

T

Output Capacitance C

CE(SAT)

CEO

OB

IC = 1 mA, IB = 100 µA0.05 0.1 0.05 0.2 V
IC = 10 µA2534nA
IC = 10 µA 0.6 1.3 nA

40 40 V
IC = 10 mA, VCE = 10 V 200 200 MHz
VCB = 15 V, IE = 0 23 23 pF

Collector-Collector

Capacitance C

NOTES

1

Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to V

2

Current gain match (∆hFE) is defined as: ∆h

3

Measured at IC = 10 µA and guaranteed by design over the specified range of IC.

4

This is the maximum change in VOS as VCB is swept from 0 V to 40 V.

5

Guaranteed by design.

6

ICC and I

7

Sample tested.

Specifications subject to change without notice.

are verified by measurement of I

CES

CC

VCC = 0 35 35 pF

at the indicated collector currents.

100 (∆IB) (hFE min)

FE =

.

CBO

I

C

MAX

–2–

REV. E

MAT02

WARNING!

ESD SENSITIVE DEVICE

ELECTRICAL CHARACTERISTICS

(VCB = 15 V, –25ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)

MAT02E MAT02F

Parameter Symbol Conditions Min Typ Max Min Typ Max Unit

Offset Voltage V

Average Offset

Voltage Drift TCV

Input Offset Current I
Input Offset

Current Drift TCI
Input Bias Current I
Current Gain h

Collector-Base I

OS

OS

OS

B

FE

CBO

VCB = 0 70 220 µV
1 µA ≤ I

10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ V

OS

V

≤ 1 mA

C

Trimmed to Zero

OS

1

2

3

MAX

0.08 0.3 0.08 1 µV/°C

0.03 0.1 0.03 0.3

IC = 10 µA813nA

MAX

4

5

40 90 40 150 pA/°C

325 300

23nA

IC = 10 µA
IC = 10 µA4550nA
IC = 1 mA

= 100 µA 275 250

I

C

= 10 µA 225 200

I

C

I

= 1 µA 200 150

C

VCB = V

Leakage Current
Collector-Emitter I

CES

VCE = V

, VBE = 0 3 4 nA

MAX

Leakage Current
Collector-Collector I

CC

VCC = V

MAX

34nA

Leakage Current

NOTES

1

Measured at IC = 10 µA and guaranteed by design over the specified range of IC.

V

2

Guaranteed by VOS test (TCVOS ≅

3

The initial zero offset voltage is established by adjusting the ratio of IC1 to IC2 at TA = 25°C. This ratio must be held to 0.003% over the entire temperature range.

Measurements are taken at the temperature extremes and 25°C.

4

Guaranteed by design.

5

Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 V to V

Specifications subject to change without notice.

OS

for VOS  VBE) T = 298K for TA = 25°C.

T

at the indicated collector current.

MAX

ABSOLUTE MAXIMUM RATINGS

Collector-Base Voltage (BV
Collector-Emitter Voltage (BV
Collector-Collector Voltage (BV
Emitter-Emitter Voltage (BV
Collector Current (I
Emitter Current (I
Total Power Dissipation

Case Temperature ≤ 40°C
Ambient Temperature ≤ 70°C

Operating Temperature Range

MAT02E, F . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT02 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. E

1

) . . . . . . . . . . . . . . . . . . . . 40 V

CBO

) . . . . . . . . . . . . . . . . . . 40 V

CEO

) . . . . . . . . . . . . . . . . . . 40 V

CC

) . . . . . . . . . . . . . . . . . . . . 40 V

EE

) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

C

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

E

2

. . . . . . . . . . . . . . . . . . . . . 1.8 W

3

. . . . . . . . . . . . . . . . 500 mW

ORDERING GUIDE

VOS max Temperature Package

Model (TA = 25ⴗC) Range Option

MAT02EH 50 µV –25°C to +85°C TO-78
MAT02FH 150 µV –25°C to +85°C TO-78

Operating Junction Temperature . . . . . . . . . . –55°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C

Junction Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

NOTES

1

Absolute maximum ratings apply to both DICE and packaged devices.

2

Rating applies to applications using heat sinking to control case temperature.

Derate linearly at 16.4 mW/°C for case temperature above 40°C.

3

Rating applies to applications not using a heat sinking; devices in free air only.

Derate linearly at 6.3 mW/°C for ambient temperature above 70°C.

–3–

MAT02

–Typical Performance Characteristics

TPC 1. Current Gain vs.
Collector Current

TPC 4. Base-Emitter-On
Voltage vs. Collector Current

TPC 2. Current Gain
vs. Temperature

TPC 5. Small Signal Input
Resistance vs. Collector Current

TPC 3. Gain Bandwidth
vs. Collector Current

TPC 6. Small-Signal Output
Conductance vs. Collector Current

TPC 7. Saturation Voltage
vs. Collector Current

TPC 8. Noise Voltage
Density vs. Frequency

–4–

TPC 9. Noise Voltage Density
vs. Collector Current

REV. E

MAT02

TPC 10. Noise Current
Density vs. Frequency

TPC 13. Collector-to-Collector
Leakage vs. Temperature

TPC 11. Total Noise vs.
Collective Current

TPC 14. Collector-to-Collector
Capacitance vs. Collector-to
Substrate Voltage

TPC 12. Collector-to-Base
Leakage vs. Temperature

TPC 15. Collector-Base
Capacitance vs. Reverse Bias Voltage

TPC 16. Collector-to-Collector
Capacitance vs. Reverse Bias
Voltage

REV. E

TPC 17. Emitter-Base Capacitance
vs. Reverse Bias Voltage

–5–

MAT02

Figure 1. Log Conformance Test Circuit

LOG CONFORMANCE TESTING

The log conformance of the MAT02 is tested using the circuit
shown above. The circuit employs a dual transdiode logarithmic
converter operating at a fixed ratio of collector currents that are
swept over a 10:1 range. The output of each transdiode converter
is the V
uct of the collector current and r
The difference of the V

of the transistor plus an error term which is the prod-

BE

is amplified at a gain of ×100 by the

BE

, the bulk emitter resistance.

BE

AMP01 instrumentation amplifier. The differential emitter-base
voltage (∆V

) consists of a temperature-dependent dc level plus

BE

an ac error voltage, which is the deviation from true log confor­mity as the collector currents vary.

The output of the transdiode logarithmic converter comes from
the idealized intrinsic transistor equation (for silicon):

kT

I

V

=

BE

C

In

q

I

S

(1)

where

–19

–23

J/K)

°C)

k = Boltzmann’s Constant (1.38062 × 10
q = Unit Electron Charge (1.60219 × 10
T = Absolute Temperature, K (= °C + 273.2)

= Extrapolated Current for VBE→0

I

S

I

= Collector Current

C

An error term must be added to this equation to allow for the
bulk resistance (r

) of the transistor. Error due to the op amp

BE

input current is limited by use of the OP15 BiFET-input op
amp. The resulting AMP01 input is:

I

kT

C1

∆

VBE =

In

I

C2

+ IC1 r

q

BE1

– IC2 r

BE2

(2)

A ramp function that sweeps from 1 V to 10 V is converted by
the op amps to a collector current ramp through each transistor.
Because I

is made equal to 10 IC2, and assuming TA = 25°C,

C1

the previous equation becomes:

∆

VBE = 59 mV + 0.9 IC1 rBE (∆rBE ~ 0)

As viewed on an oscilloscope, the change in ∆V
change in I

is then displayed as shown in Figure 2 below:

C

for a 10:1

BE

Figure 2.

With the oscilloscope ac coupled, the temperature dependent
term becomes a dc offset and the trace represents the deviation
from true log conformity. The bulk resistance can be calculated
from the voltage deviation ∆V

and the change in collector

O

current (9 mA):

r

BE

This procedure finds r
provide the r

= R2.

R

1

for Side B. Differential rBE is found by making

BE

∆V

=

9 mA

for Side A. Switching R1 and R2 will

BE

1

O

×

100

(3)

–6–

REV. E

Figure 3. One-Quadrant Multiplier/Divider

MAT02

APPLICATIONS: NONLINEAR FUNCTIONS

MULTIPLIER/DIVIDER CIRCUIT

The excellent log conformity of the MAT02 over a very wide
range of collector current makes it ideal for use in log-antilog
circuits. Such nonlinear functions as multiplying, dividing,
squaring and square-rooting are accurately and easily imple­mented with a log antilog circuit using two MAT02 pairs (see
Figure 3). The transistor circuit accepts three input currents (I
I

and I3) and provides an output current IO according to

2

= I1I2/I3. All four currents must be positive in the log antilog

I

O

,

1

circuit, but negative input voltages can be easily accommodated
by various offsetting techniques. Protective diodes across each
base-to-emitter junction would normally be needed, but these
diodes are built into the MAT02. External protection diodes
are, therefore, not needed.

For the circuit shown in Figure 3, the operational amplifiers
make I

= VX/R1, I2 = VY/R2, I3 = VZ/R3, and IO = VO/RO. The

1

output voltage for this one-quadrant, log-antilog multiplier/
divider is ideally:

R3R

VXV

O

=

V

O

R1R

If all the resistors (R

O

V

Y

(VX, VY, VZ > 0) (4)

V

2

Z

, R1, R2, R3) are made equal, then

= VXVY/V

O

Z

Resistor values of 50 kΩ to 100 kΩ are recommended assuming
an input range of 0.1 V to +10 V.

ERROR ANALYSIS

The base-to-emitter voltage of the MAT02 in its forward active
operation is:

these effects can be lumped together as a total effective bulk
resistance r
logarithmic relationship. The r
than 0.5 Ω and ∆r

. The rBEIC term causes departure from the desired

BE

between the two sides is negligible.

BE

term for the MAT02 is less

BE

Returning to the multiplier/divider circuit of Figure 1 and using
Equation (4):

V

BE1A

+ V

BE2A

– V

BE2B

– V

+ (I1 + I2 – IO – I3) rBE = 0

BE1B

If the transistor pairs are held to the same temperature, then:

kT

q

II

12

In

IIkTq

3

=

O

In

II

S ASA

12

II

SB S B

12

+ (I1 + I2 – IO – I3) rBE(6)

If all the terms on the right-hand side were zero, then In
(I

1 I2/I3 IO

) would equal zero, which would lead directly to

the desired result:

I1I

2

=

I

O

, where I1, I2, I3, IO > 0 (7)

I

3

Note that this relationship is temperature independent. The
right-hand side of Equation (6) is near zero and the output
current I

will be approximately I1 I2/I3. To estimate error,

O

define ø as the right-hand side terms of Equation (6):

II

S ASA

12

ø = In

IIqkT

SB S B

For the MAT02, In (I

Ø

ø, ε

~ 1 + ø and therefore:

12

I1I

I3I

+

(I1 + I2 – IO – I3) r

) and ICrBE are very small. For small

SA/ISB

2

= 1 + ø

O

BE

(8)

(9)

=

V

BE

q

+ rBEIC, VCB ~ 0 (5)

I

S

I

kT

C

In

The first term comes from the idealized intrinsic transistor
equation previously discussed (see equation (1)).

Extrinsic resistive terms and the early effect cause departure
from the ideal logarithmic relationship. For small V

, all of

CB

REV. E

I

1I2

(1 – ø)

I

3

The In (I

~

I

O

) terms in ø cause a fixed gain error of less than

SA/ISB

±0.6% from each pair when using the MAT02, and this gain
error is easily trimmed out by varying R

O

. The I

terms are

OUT

–7–

MAT02

more troublesome because they vary with signal levels and are
multiplied by absolute temperature. At 25°C, kT/q is
approximately 26 mV and the error due to an r

/26 mV. Using an rBE of 0.4 Ω for the MAT02 and assum-

r

BEIC

term will be

BEIC

ing a collector current range of up to 200 µA, then a peak error
of 0.3% could be expected for an r

error term when using

BEIC

the MAT02. Total error is dependent on the specific application
configuration (multiply, divide, square, etc.) and the required
dynamic range. An obvious way to reduce I

error is to re-

CrBE

duce the maximum collector current, but then op amp offsets
and leakage currents become a limiting factor at low input lev­els. A design range of no greater than 10 µA to 1 mA is generally
recommended for most nonlinear function circuits.

A powerful technique for reducing error due to I
Figure 4. A small voltage equal to I

is applied to the transis-

CrBE

is shown in

CrBE

tor base. For this circuit:

V

B

The error from r

R

C

=

V1 and ICrBE =

R

2

is cancelled if RC/R2 is made equal to r

BEIC

r

BE

V

1

R

1

(10)

OUT R1

.

Since the MAT02 bulk resistance is approximately 0.39 Ω, an

of 3.9 Ω and R2 of 10 R1 will give good error cancellation.

R

C

In more complex circuits, such as the circuit in Figure 3, it may
be inconvenient to apply a compensation voltage to each indi­vidual base. A better approach is to sum all compensation to the
bases of Q1. The “A” side needs a base voltage of (V
R

) rBE, and the “B” side needs a base voltage of (VX/R1+VY/R2)

3

. Linearity of better than ±0.1% is readily achievable with

r

BE

O/RO

+ VZ/

this compensation technique.

Operational amplifier offsets are another source of error. In
Figure 4, the input offset voltage and input bias current will
cause an error in collector current of (V
offset op amp, such as the OP07 with less than 75 µV of V

) + IB. A low

OS/R1

OS

and IB of less than ± 3 nA, is recommended. The OP193,
micropower op amp, should be considered if low power con-

sumption or single-supply operation is needed. The value of
frequency-compensating capacitor (C

) is dependent on the

O

op amp frequency response and peak collector current. Typi­cal values for C

range from 30 pF to 300 pF.

O

Figure 4. Compensation of Bulk Resistance Error

FOUR-QUADRANT MULTIPLIER

A simplified schematic for a four-quadrant log-antilog multiplier
is shown in Figure 5. Similar to the previously discussed one­quadrant multiplier, the circuit makes I
input currents, I

and I2, are each offset in the positive direction.

1

= I1 I2/I3. The two

O

This positive offset is then subtracted out at the output stage.
Assuming ideal op amps, the currents are:

VRV

XR YR

I

=+ =+,

1

R

12212

I

VRV

R

(11)

VRVRVRV

XY ROOR

I

=+++ =

O

112

R

V

I

,

3

R

2

From IO = I1 I2/I3, the output voltage will be:

ROR

VXV

2

=

V

O

R

1

Y

2

V

R

(12)

Figure 5. Four-Quadrant Multiplier

–8–

REV. E

Figure 6. Multifunction Converter

MAT02

Collector current range is the key design decision. The inher­ently low r

of the MAT02 allows the use of a relatively high

BE

collector current. For input scaling of ±10 V full-scale and using
a 10 V reference, we have a collector-current range for I

and I

1

2

of:



–10 10 1010



RR



Practical values for R
100 kΩ. Choosing an R



+




12 12

and R2 would range from 50 kΩ to

1

of 82 kΩ and R2 of 62 kΩ provides a

1



≤≤ +

I



C

RR








(13)

collector current range of approximately 39 µA to 283 µA. An
R

of 108 kΩ will then make the output scale factor 1/10 and

O

= VXVY/10. The output, as well as both inputs, are scaled for

V

O

±10 V full scale.

Linear error for this circuit is substantially improved by the
small correction voltage applied to the base of Q1 as shown in
Figure 5. Assuming an equal bulk emitter resistance for each
MAT02 transistor, then the error is nulled if:

(I

+ I2 – I3 – IO) rBE + ρVO = 0

1

The currents are known from the previous discussion, and the
relationship needed is simply:

r

BE

V

=

O

The output voltage is attenuated by a factor of r

V

O

R

O

BE/RO

(14)

and ap­plied to the base of Q1 to cancel the summation of voltage drops
due to r
zero which will thereby make I

terms. This will make In (I1 I2/I3 IO) more nearly

BEIC

= I1 I2/I3 a more accurate rela-

O

tionship. Linearity of better than 0.1% is readily achievable with
this circuit if the MAT02 pairs are carefully kept at the same
temperature.

REV. E

–9–

MULTIFUNCTION CONVERTER

The multifunction converter circuit provides an accurate means
of squaring, square rooting, and raising ratios to arbitrary pow­ers. The excellent log conformity of the MAT02 allows a wide
range of exponents. The general transfer function is:

m





V

= VY

V

O

V

, VY, and VZ are input voltages and the exponent “m” has a

X

practical range of approximately 0.2 to 5. Inputs V

Z





V





X

X

(15)

and VY are
often taken from a fixed reference voltage. With a REF01 pro­viding a precision 10 V to both V

and VY, the transfer function

X

would simplify to:

m





V

VO = 10

Z





10





(16)

As with the multiplier/divider circuits, assume that the transistor
pairs have excellent matching and are at the same temperature.
The In I

will then be zero. In the circuit of Figure 6, the

SA/ISB

voltage drops across the base-emitter junctions of Q1 provide:

kT

q

VA=

In

kT

I

Z

I

X

I

O

In

q

I

Y

(17)

(18)

R

B

RB+ KR

is VZ/R1 and IX is VX/R1. Similarly, the relationship for Q2 is:

I

Z

RB+ 1– K

I

is VO/RO and IY is VY/R1. These equations for Q1 and Q2 can

O

VA=

A

R

B

R

()

A

then be combined.

I

RB+ KR

RB+ 1– K

()

A

In

I

R

A

I

Z

O

= In

I

X

Y

(19)

MAT02

Substituting in the voltage relationships and simplifying leads
to:

m



R

O

=

V

R

1

V

O



V

Z

Y

, where





V





X

(20)

m =

RB+ KR

RB+ 1– K

A

R

()

A

The factor “K” is a potentiometer position and varies from zero
to 1.0, so “m” ranges from R
Practical values are 125 Ω for R

/(RA + RB) to (RB + RA)/RB.

B

and 500 Ω for RA; these

B

values will provide an adjustment range of 0.2 to 5.0. A value
of 100 kΩ is recommended for the R

resistors assuming a full-

1

scale input range of 10 V. As with the one-quadrant
multiplier/divider circuit previously discussed, the V

V

inputs must all be positive.

Z

, VY, and

X

The op amps should have the lowest possible input offsets. The
OP07 is recommended for most applications, although such
programmable micropower op amps as the OP193/OP293 offer
advantages in low-power or single-supply circuits. The micro­power op amps also have very low input bias-current drift, an
important advantage in log/antilog circuits. External offset
nulling may be needed, particularly for applications requiring a
wide dynamic range. Frequency compensating capacitors, on
the order of 50 pF, may be required for A
A

is likely to need a larger capacitor, typically 0.0047 µF, to

1

and A3. Amplifier

2

assure stability.

Accuracy is limited at the higher input levels by bulk emitter
resistance, but this is much lower for the MAT02 than for other
transistor pairs. Accuracy at the lower signal levels primarily
depends on the op amp offsets. Accuracies of better than 1%
are readily achievable with this circuit configuration and can be
better than ±0.1% over a limited operating range.

Figure 7. Fast Logarithmic Amplifier

LOW-NOISE ⴛ1000 AMPLIFIER

The MAT02 noise voltage is exceptionally low, only 1 nV/√Hz
at 10 Hz when operated over a collector current range of 1 mA
to 4 mA. A single-ended ×1000 amplifier that takes advantage of
this low MAT02 noise level is shown in Figure 8. In addition to
low noise, the amplifier has very low drift and high CMRR. An
OP184 is used for the second stage to obtain good speed with
minimal power consumption. Small-signal bandwidth is 4.0
MHz, slew rate is 2.4 V/µs, and total supply current is approxi-
mately 2.25 mA.

FAST LOGARITHMIC AMPLIFIER

The circuit of Figure 7 is a modification of a standard logarith­mic amplifier configuration. Running the MAT02 at 2.5 mA
per side (full-scale) allows a fast response with wide dynamic
range. The circuit has a 7 decade current range, a 5 decade
voltage range, and is capable of 2.5 µs settling time to 1% with
a 1 V to 10 V step.

The output follows the equation:

R3+ R

V

=

O

R

2

V

kT

2

REF

In

q

V

IN

(21)

The output is inverted with respect to the input, and is nomi­nally –1 V/decade using the component values indicated.

–10–

Figure 8. Low-Noise, Single-Ended × 1000 Amplifier

REV. E

MAT02

Transistors Q2 and Q3 form a 2 mA current source (0.65 V/
330 Ω ~ 2 mA).
OP184 inputs are 3 V below the positive supply voltage (R
~ 3 V). Input stage gain is gmRL, which is approximately 100
when operating at I
OP184 has a minimum open-loop gain of 500,000, total
open-loop gain for the composite amplifier is over 50 million.
Even at closed-loop gain of 1000, the gain error due to finite
open-loop gain will be negligible. The OP184 features excellent
symmetry of slew-rate and very linear gain. Signal distortion is
minimal.

Dynamic range of this amplifier is excellent; the OP184 has an
output voltage swing of ±14.8 V with a ±15 V supply.

Input characteristics are outstanding. The MAT02F has offset
voltage of less than 150 µV at 25°C and a maximum offset drift
of 1 µV/°C. Nulling the offset will further reduce offset drift.
This can be accomplished by slightly unbalancing the collector
load resistors. This adjustment will reduce the drift to less than

0.1 µV/°C.

Each collector of Q1 operates at 1 mA. The

LIC

of 1 mA with RL of 3 kΩ. Since the

C

Input bias current is relatively low due to the high current gain
of the MAT02. The minimum β of 400 at 1 mA for the
MAT02F implies an input bias current of approximately 2.5 µA.
This circuit should be used with signals having relatively low
source impedance. A high source impedance will degrade offset
and noise performance.

This circuit configuration provides exceptionally low input noise
voltage and low drift. Noise can be reduced even further by
raising the collector currents from 1 mA to 3 mA, but power
consumption is then increased.

REV. E

–11–

MAT02

0.185 (4.70)

0.165 (4.19)

0.370 (9.40)

0.335 (8.51)

0.335 (8.51)

0.305 (7.75)

0.040 (1.02) MAX

0.045 (1.14)

0.010 (0.25)

OUTLINE DIMENSION

Dimensions shown in inches and (mm).

6-Lead Metal Can

(TO-78)

REFERENCE PLANE

0.750 (19.05)

0.500 (12.70)

0.250 (6.35) MIN

0.050 (1.27) MAX

0.019 (0.48)

0.016 (0.41)

0.021 (0.53)

0.016 (0.41)

BASE AND SEATING PLANE

0.200
(5.08)

BSC

0.100

(2.54)

BSC

0.100 (2.54) BSC

4

3

2

1

0.034 (0.86)

0.027 (0.69)

0.160 (4.06)

0.110 (2.79)

5

6

45° BSC

0.045 (1.14)

0.027 (0.69)

C00283–0–4/02(E)

Revision History

Location Page

4/02—Data Sheet changed from REV. D to REV. E.

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1/02—Data Sheet changed from REV. C to REV. D.

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Deleted ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Deleted TYPICAL ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Deleted DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Updated Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PRINTED IN U.S.A.

–12–

REV. E