Analog Devices MAT02FH Datasheet

Low Noise, Matched

a

FEATURES
Low Offset Voltage: 50 ␮V max
Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/√Hz max
High Gain (h

500 min at I

300 min at I
Excellent Log Conformance: r
Low Offset Voltage Drift: 0.1 ␮V/ⴗC max
Improved Direct Replacement for LM194/394

PRODUCT DESCRIPTION

The design of the MAT02 series of NPN dual monolithic tran­sistors is optimized for very low noise, low drift and low r
Precision Monolithics’ exclusive Silicon Nitride “Triple­Passivation” process stabilizes the critical device parameters
over wide ranges of temperature and elapsed time. Also, the high
current gain (h
range of collector current. Exceptional characteristics of the
MAT02 include offset voltage of 50 µV max (A/E grades) and
150 µV max F grade. Device performance is specified over the
full military temperature range as well as at 25°C.

Input protection diodes are provided across the emitter-base
junctions to prevent degradation of the device characteristics
due to reverse-biased emitter current. The substrate is clamped
to the most negative emitter by the parasitic isolation junction
created by the protection diodes. This results in complete isola­tion between the transistors.

):

FE

= 1 mA

C

= 1 ␮A

C

) of the MAT02 is maintained over a wide

FE

⯝ 0.3 ⍀

BE

BE

.

Dual Monolithic Transistor

MAT02

PIN CONNECTION

TO-78

(H Suffix)

NOTE
Substrate is connected to case on TO-78 package.
Substrate is normally connected to the most negative
circuit potential, but can be floated.

The MAT02 should be used in any application where low
noise is a priority. The MAT02 can be used as an input
stage to make an amplifier with noise voltage of less than

1.0 nV/√Hz at 100 Hz. Other applications, such as log/antilog
circuits, may use the excellent logging conformity of the
MAT02. Typical bulk resistance is only 0.3 Ω to 0.4 Ω. The
MAT02 electrical characteristics approach those of an ideal
transistor when operated over a collector current range of 1
µA to 10 mA. For applications requiring multiple devices
see MAT04 Quad Matched Transistor data sheet.

REV. E

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MAT02–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VCB = 15 V, IC = 10 ␮A, TA = 25ⴗC, unless otherwise noted.)

MAT02E MAT02F

Parameter Symbol Conditions Min Typ Max Min Typ Max Unit

Current Gain h

Current Gain Match ∆h
Offset Voltage V
Offset Voltage ∆V

Change vs. V

CB

Offset Voltage Change ∆V

FE

FE

OS

/∆VCB0 ≤ VCB ≤ V

OS

/∆I

OS

IC = 1 mA

= 100 µA 500 590 400 590

I

C

I

= 10 µA 400 550 300 550

C

I

= 1 µA 300 485 200 485

C

10 µA ≤ IC ≤ 1 mA
VCB = 0, 1 µA ≤ IC ≤ 1 mA

1 µA ≤ IC ≤ 1 mA
VCB = 0 V 5 25 5 50 µV

C

vs. Collector Current 1 µA ≤ I

1

MAX

≤ 1 mA

C

500 605 400 605

2

3

4

3

3

0.5 2 0.5 4 %
10 50 80 150 µV
10 25 10 50 µV
10 25 10 50 µV

525 5 50µV

Offset Current

Change vs. V

CB

Bulk Resistance r

∆IOS/∆V

BE

0 ≤ VCB ≤ V

CB

10 µA ≤ IC ≤ 10 mA

MAX

5

30 70 30 70 pA/V

0.3 0.5 0.3 0.5 Ω

Collector-Base

Leakage Current I

CBO

Collector-Collector

Leakage Current I

CC

Collector-Emitter V

Leakage Current I

Noise Voltage Density e

CES

n

VCB = V

VCC = V

VBE = 0 35 200 35 400 pA
IC = 1 mA, VCB = 0

CE

= V

MAX

MAX

MAX

5, 6

5, 6

7

25 200 25 400 pA

35 200 35 400 pA

fO = 10 Hz 1.6 2 1.6 3 nV/√Hz
f

= 100 Hz 0.9 1 0.9 2 nV/√Hz

O

= 1 kHz 0.85 1 0.85 2 nV/√Hz

f

O

f

= 10 kHz 0.85 1 0.85 2 nV/√Hz

O

Collector Saturation

Voltage V
Input Bias Current I
Input Offset Current I

B

OS

Breakdown Voltage BV
Gain-Bandwidth Product f

T

Output Capacitance C

CE(SAT)

CEO

OB

IC = 1 mA, IB = 100 µA0.05 0.1 0.05 0.2 V
IC = 10 µA2534nA
IC = 10 µA 0.6 1.3 nA

40 40 V
IC = 10 mA, VCE = 10 V 200 200 MHz
VCB = 15 V, IE = 0 23 23 pF

Collector-Collector

Capacitance C

NOTES

1

Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to V

2

Current gain match (∆hFE) is defined as: ∆h

3

Measured at IC = 10 µA and guaranteed by design over the specified range of IC.

4

This is the maximum change in VOS as VCB is swept from 0 V to 40 V.

5

Guaranteed by design.

6

ICC and I

7

Sample tested.

Specifications subject to change without notice.

are verified by measurement of I

CES

CC

VCC = 0 35 35 pF

at the indicated collector currents.

100 (∆IB) (hFE min)

FE =

.

CBO

I

C

MAX

–2–

REV. E

MAT02

WARNING!

ESD SENSITIVE DEVICE

ELECTRICAL CHARACTERISTICS

(VCB = 15 V, –25ⴗC ≤ TA ≤ +85ⴗC, unless otherwise noted.)

MAT02E MAT02F

Parameter Symbol Conditions Min Typ Max Min Typ Max Unit

Offset Voltage V

Average Offset

Voltage Drift TCV

Input Offset Current I
Input Offset

Current Drift TCI
Input Bias Current I
Current Gain h

Collector-Base I

OS

OS

OS

B

FE

CBO

VCB = 0 70 220 µV
1 µA ≤ I

10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ V

OS

V

≤ 1 mA

C

Trimmed to Zero

OS

1

2

3

MAX

0.08 0.3 0.08 1 µV/°C

0.03 0.1 0.03 0.3

IC = 10 µA813nA

MAX

4

5

40 90 40 150 pA/°C

325 300

23nA

IC = 10 µA
IC = 10 µA4550nA
IC = 1 mA

= 100 µA 275 250

I

C

= 10 µA 225 200

I

C

I

= 1 µA 200 150

C

VCB = V

Leakage Current
Collector-Emitter I

CES

VCE = V

, VBE = 0 3 4 nA

MAX

Leakage Current
Collector-Collector I

CC

VCC = V

MAX

34nA

Leakage Current

NOTES

1

Measured at IC = 10 µA and guaranteed by design over the specified range of IC.

V

2

Guaranteed by VOS test (TCVOS ≅

3

The initial zero offset voltage is established by adjusting the ratio of IC1 to IC2 at TA = 25°C. This ratio must be held to 0.003% over the entire temperature range.

Measurements are taken at the temperature extremes and 25°C.

4

Guaranteed by design.

5

Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 V to V

Specifications subject to change without notice.

OS

for VOS  VBE) T = 298K for TA = 25°C.

T

at the indicated collector current.

MAX

ABSOLUTE MAXIMUM RATINGS

Collector-Base Voltage (BV
Collector-Emitter Voltage (BV
Collector-Collector Voltage (BV
Emitter-Emitter Voltage (BV
Collector Current (I
Emitter Current (I
Total Power Dissipation

Case Temperature ≤ 40°C
Ambient Temperature ≤ 70°C

Operating Temperature Range

MAT02E, F . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT02 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. E

1

) . . . . . . . . . . . . . . . . . . . . 40 V

CBO

) . . . . . . . . . . . . . . . . . . 40 V

CEO

) . . . . . . . . . . . . . . . . . . 40 V

CC

) . . . . . . . . . . . . . . . . . . . . 40 V

EE

) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

C

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

E

2

. . . . . . . . . . . . . . . . . . . . . 1.8 W

3

. . . . . . . . . . . . . . . . 500 mW

ORDERING GUIDE

VOS max Temperature Package

Model (TA = 25ⴗC) Range Option

MAT02EH 50 µV –25°C to +85°C TO-78
MAT02FH 150 µV –25°C to +85°C TO-78

Operating Junction Temperature . . . . . . . . . . –55°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C

Junction Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

NOTES

1

Absolute maximum ratings apply to both DICE and packaged devices.

2

Rating applies to applications using heat sinking to control case temperature.

Derate linearly at 16.4 mW/°C for case temperature above 40°C.

3

Rating applies to applications not using a heat sinking; devices in free air only.

Derate linearly at 6.3 mW/°C for ambient temperature above 70°C.

–3–

MAT02

–Typical Performance Characteristics

TPC 1. Current Gain vs.
Collector Current

TPC 4. Base-Emitter-On
Voltage vs. Collector Current

TPC 2. Current Gain
vs. Temperature

TPC 5. Small Signal Input
Resistance vs. Collector Current

TPC 3. Gain Bandwidth
vs. Collector Current

TPC 6. Small-Signal Output
Conductance vs. Collector Current

TPC 7. Saturation Voltage
vs. Collector Current

TPC 8. Noise Voltage
Density vs. Frequency

–4–

TPC 9. Noise Voltage Density
vs. Collector Current

REV. E