Pin Compatible Upgrade for LTC1451 12-Bit DAC
Family
U
APPLICATIOS
■
Digital Calibration
■
Industrial Process Control
■
Automatic Test Equipment
■
Cellular Telephones
The LTC®1655/LTC1655L are rail-to-rail voltage output,
16-bit digital-to-analog converters in an SO-8 package.
They include an output buffer and a reference. The 3-wire
serial interface is compatible with SPI/QSPI and
MICROWIRETM protocols. The CLK input has a Schmitt
trigger that allows direct optocoupler interface.
The LTC1655 has an onboard 2.048V reference that can be
overdriven to a higher voltage. The output swings from 0V
to 4.096V when using the internal reference. The typical
power dissipation is 3.0mW on a single 5V supply.
The LTC1655L has an onboard 1.25V reference that can be
overdriven to a higher voltage. The output swings from 0V
to 2.5V when using the internal reference. The typical
power dissipation is 1.8mW on a single 3V supply.
The LTC1655/LTC1655L are pin compatible with Linear
Technology’s 12-bit V
DAC family, allowing an easy
OUT
upgrade path. They are the only buffered 16-bit DACs in
an SO-8 package and they include an onboard reference
for standalone performance.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
UU
W
FUCTIOAL BLOCK DIAGRA
Functional Block Diagram: 16-Bit Rail-to-Rail DAC
µP
TO
OTHER
DACS
LTC1655: 4.5V TO 5.5V
LTC1655L: 2.7V TO 5.5V
V
2
D
IN
CLK1
16-BIT
SHIFT
OUT
REG
AND
DAC
LATCH
POWER-ON
RESET
CS/LD3
4
D
86
CC
16
LTC1655: 2.048V
LTC1655L: 1.25V
REF
16-BIT
DAC
REF
+
–
GND
5
V
OUT
1655/55L TA01
Differential Nonlinearity
vs Input Code
1.0
0.8
0.6
0.4
0.2
7
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0
1638432768
CODE
49152
65535
1655/55L TA02
1
Page 2
LTC1655/LTC1655L
WW
W
U
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND .............................................. – 0.5V to 7.5V
TTL Input Voltage .................................... – 0.5V to 7.5V
V
, REF ....................................... – 0.5V to V
OUT
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LTC1655C/LTC1655LC ........................... 0°C to 70°C
LTC1655I/LTC1655LI ........................ – 40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 4.5V to 5.5V (LTC1655), VCC = 2.7V to 5.5V (LTC1655L); V
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 4.5V to 5.5V (LTC1655), VCC = 2.7V to 5.5V (LTC1655L); V
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
Op Amp DC Performance
Short-Circuit Current LowV
Short-Circuit Current HighV
Output Impedance to GNDInput Code = 0
Output Line RegulationInput Code = 65535, with Internal Reference±3mV/V
AC Performance
Voltage Output Slew Rate(Note 4)●±0.3±0.7V/µs
Voltage Output Settling Time(Note 4) to 0.0015% (16-Bit Settling Time), V
Digital Feedthrough(Note 5)0.3nV-s
Midscale Glitch ImpulseDAC Switched Between 8000H and 7FFF
Output Voltage NoiseLTC1655, At 1kHz280nV√Hz
Spectral DensityLTC1655L, At 1kHz220nV√Hz
Reference Input ResistanceLTC1655, REF Overdriven to 2.2V●8.513kΩ
Reference Short-Circuit Current●40100mA
Reference Output Line Regulation±1.5mV/V
Reference Load RegulationI
Reference Output Voltage NoiseLTC1655, At 1kHz150nV√Hz
Spectral DensityLTC1655L, At 1kHz115nV√Hz
Digital I/O
V
IH
V
IL
V
OH
V
OL
Digital Input High VoltageLTC1655●2.4V
Digital Input Low VoltageLTC1655●0.8V
Digital Output High VoltageLTC1655, I
Digital Output Low VoltageLTC1655, I
Shorted to GND
OUT
LTC1655
LTC1655L
Shorted to V
OUT
LTC1655●80140mA
LTC1655L
LTC1655
LTC1655L
(Note 4) to 0.012% (13-Bit Settling Time), V
LTC1655L
LTC1655L1.3V
LTC1655L10ppm/°C
LTC1655L, REF Overdriven to 1.3V
= 100µA●5mV/A
OUT
LTC1655L
LTC1655L
LTC1655L, I
LTC1655L, I
CC
= –1mA●VCC – 1.0V
OUT
= – 1mA●VCC – 0.7V
OUT
= 1mA●0.4V
OUT
= 1mA●0.4V
OUT
unloaded, REF unloaded, unless otherwise noted.
OUT
●70120mA
●70140mA
●70150mA
●40120Ω
●70160Ω
= 5V20µs
CC
= 5V10µs
CC
H
●1.2401.2501.260V
●7.013kΩ
●2.0V
●0.6V
12nV-s
/2V
CC
3
Page 4
LTC1655/LTC1655L
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 4.5V to 5.5V (LTC1655), VCC = 2.7V to 5.5V (LTC1655L); V
SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS
I
LEAK
C
IN
Switching
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Digital Input LeakageVIN = GND to V
Digital Input Capacitance(Note 7)10pF
DIN Valid to CLK SetupLTC1655●40ns
LTC1655L
DIN Valid to CLK HoldLTC1655●0ns
LTC1655L
CLK High TimeLTC1655●40ns
LTC1655L
CLK Low TimeLTC1655●40ns
LTC1655L
CS/LD Pulse WidthLTC1655●50ns
LTC1655L
LSB CLK to CS/LDLTC1655●40ns
LTC1655L
CS/LD Low to CLKLTC1655●20ns
LTC1655L
D
Output DelayLTC1655, C
OUT
CLK Low to CS/LD LowLTC1655●20ns
LTC1655L, C
LTC1655L
CC
= 15pF●20120ns
LOAD
= 15pF●20300ns
LOAD
unloaded, REF unloaded, unless otherwise noted.
OUT
●±10µA
●60ns
●0ns
●60ns
●60ns
●80ns
●60ns
●30ns
●30ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity is defined from code 128 to code 65535 (full scale).
See Applications Information.
Note 3: DAC switched between all 1s and all 0s. V
Note 4: Digital inputs at 0V or VCC.
= 4.096V.
FS
Note 5: Part is clocked with pin toggling between 1s and 0s, CS/LD is low.
Note 6: Reference can be overdriven (see Applications Information).
Note 7: Guaranteed by design. Not subject to test.
Note 8: Guaranteed by correlation for other reference and supply
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
D
(Pin 2): The TTL Level Input for the Serial Interface
IN
Data. Data on the DIN pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1655/LTC1655L requires a 16-bit word.
CS/LD (Pin 3): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low, the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
D
(Pin 4): Output of the Shift Register. Becomes valid
OUT
on the rising edge of the serial clock and swings from GND
to VCC.
WUW
TI I G DIAGRA
GND (Pin 5): Ground.
REF (Pin 6): Reference. Output of the internal reference is
2.048V (LTC1655), 1.25V (LTC1655L). There is a gain of
two from this pin to the output. The reference can be
overdriven from 2.2V to VCC/2 (LTC1655) and 1.3V to
VCC/2 (LTC1655L). When tied to VCC/2, the output will
swing from GND to VCC. The output can only swing to
within its offset specification of VCC (see Applications
Information).
V
(Pin 7): Deglitched Rail-to-Rail Voltage Output. V
OUT
OUT
clears to 0V on power-up.
V
(Pin 8): Positive Supply Input. 4.5V ≤ VCC ≤ 5.5V
CC
(LTC1655), 2.7V ≤ VCC ≤ 5.5V (LTC1655L). Requires a
0.1µF bypass capacitor to ground.
CLK
D
CS/LD
D
OUT
t
9
t
7
123
D15
D15
MSB
t
8
IN
PREVIOUS WORD
t
1
D14D13D1
D14
PREVIOUS WORD
t
2
PREVIOUS WORD
t
D13
D0
LSB
t
6
CURRENT WORD
D15
t
5
1655/55L TD
t
3
4
1516
D0
PREVIOUS WORD
8
Page 9
UU
DEFI ITIO S
LTC1655/LTC1655L
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆V
Where ∆V
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Gain Error (GE): The difference between the full-scale
output of a DAC from its ideal full-scale value after offset
error has been adjusted.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
OUT
– LSB)/LSB
OUT
is the measured voltage difference between
lowest code that guarantees the output will be greater than
zero. The INL error at a given input code is
follows:
INL = [V
Where V
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = 2V
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
– VOS – (VFS – VOS)(code/65535)]/LSB
OUT
is the output voltage of the DAC measured at
OUT
/65536
REF
calculated as
U
OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The clock is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse. The input
word must be 16 bits wide.
The buffered output of the 16-bit shift register is available
on the D
Multiple LTC1655s/LTC1655Ls may be daisy-chained together by connecting the D
chip while the clock and CS/LD signals remain common to
all chips in the daisy chain. The serial data is clocked to all
pin which swings from GND to VCC.
OUT
pin to the DIN pin of the next
OUT
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously. The shift register and DAC
register are cleared to all 0s on power-up.
Voltage Output
The LTC1655/LTC1655L rail-to-rail buffered output can
source or sink 5mA over the entire operating temperature
range while pulling to within 600mV of the positive supply
voltage or ground. The output stage is equipped with a
deglitcher that gives a midscale glitch of 12nV-s. At powerup, the output clears to 0V.
The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resis-
tance of 40Ω (70Ω for the LTC1655L) when driving a load
to the rails. The output can drive 1000pF without going into
oscillation.
9
Page 10
LTC1655/LTC1655L
U
WUU
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC/2. If V
= VCC/2 and the DAC full-scale
REF
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if V
is less than (VCC – FSE)/2.
REF
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
POSITIVE
FSE
V
CC
V
REF
= VCC/2
OUTPUT
VOLTAGE
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
INPUT CODE
(1c)
V
CC
V
OUTPUT
VOLTAGE
REF
= VCC/2
32768065535
INPUT CODE
(1a)
0V
INPUT CODE
(1b)
1655/55L F01
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
= VCC/2
REF
10
Page 11
U
TYPICAL APPLICATIONS
LTC1655/LTC1655L
This circuit shows how to use an LTC1655 to make an
optoisolated digitally controlled 4mA to 20mA process
controller. The controller circuitry, including the
optoisolation, is powered by the loop voltage that can have
a wide range of 6V to 30V. The 2.048V reference output of
the LTC1655 is used for the 4mA offset current and V
An Isolated 4mA to 20mA Process Controller
®
LT
1121-5
OUTIN
1µF
FROM
OPTOISOLATED
INPUTS
1
2
3
86
V
CC
CLK
LTC1655
D
IN
CS/LD
V
REF
GND
OUT
5
V
OUT
is used for the digitally controlled 0mA to 16mA current.
RS is a sense resistor and the op amp modulates the
transistor Q1 to provide the 4mA to 20mA current through
this resistor. The potentiometers allow for offset and fullscale adjustment. The control circuitry dissipates well
under the 4mA budget at zero scale.
V
LOOP
6V TO 30V
150k
1%
20k
75k
1%
7
5k
3
2
3k
+
LT®1077
–
7
1k
6
4
Q1
2N3440
CLK
D
CS/LD
IN
OPTOISOLATORS
500Ω
4N28
R
5V
10k
CLK
D
IN
CS/LD
S
10Ω
I
OUT
1655/55L TA03
11
Page 12
LTC1655/LTC1655L
TYPICAL APPLICATIONS
U
This circuit shows how to make a bipolar output 16-bit
DAC with a wide output swing using an LTC1655 and an
LT1077. R1 and R2 resistively divide down the LTC1655
output and an offset is summed in using the LTC1655
onboard 2.048V reference and R3 and R4. R5 ensures that
A Wide Swing, Bipolar Output 16-Bit DAC
5V
0.1µF
8
V
IN
LTC1655
GND V
5
D
IN
CC
V
OUT
REF
6
R3
100k
1%
R5
100k
1%
4.096
V
OUT
–4.096
0
µP
TRANSFER CURVE
32768
1
2
3
65535
CLK
D
CS/LD
the onboard reference is always sourcing current and
never has to sink any current even when V
is at full
OUT
scale. The LT1077 output will have a wide bipolar output
swing of –4.096V to 4.096V as shown in the figure below.
With this output swing 1LSB = 125µV.
7
R1
100k
1%
R2
200k
1%
5V
3
2
+
LT1077
–
–5V
7
6
4
R4
200k
1%
V
OUT
1655/55L TA05
(2)(DIN)(4.096)
:
65536
– 4.096V
12
Page 13
U
TYPICAL APPLICATIONS
LTC1655/LTC1655L
This circuit shows a digitally programmable current source
from an external voltage source using an external op amp,
an LT1218 and an NPN transistor (2N3440). Any digital
word from 0 to 65535 is loaded into the LTC1655 and its
output correspondingly swings from 0V to 4.096V. This
voltage will be forced across the resistor RA. If RA is
Digitally Programmable Current Source
5V
8
V
1
CLK
µP
2
D
IN
3
CS/LD
CC
LTC1655
GND
5
7
V
OUT
chosen to be 412Ω, the output current will range from
0mA at zero scale to 10mA at full scale. The minimum
voltage for VS is determined by the load resistor RL and
Q1’s V
voltage. With a load resistor of 50Ω, the
CESAT
voltage source can be 5V.
< 100V
5V < V
S
FOR R
≤ 50Ω
0.1µF
3
2
+
LT1218
–
7
4
L
R
L
6
Q1
2N3440
R
A
412Ω
1%
(DIN)(4.096)
I
=
OUT
(65536)(R
≈ 0mA TO 10mA
1655/55L TA04
)
A
13
Page 14
LTC1655/LTC1655L
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
87 6
0.255 ± 0.015*
(6.477 ± 0.381)
5
12
0.300 – 0.325
(7.620 – 8.255)
0.065
(1.651)
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.325
–0.015
+0.889
8.255
()
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
TYP
0.045 – 0.065
(1.143 – 1.651)
0.100
(2.54)
BSC
3
4
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.020
(0.508)
MIN
N8 1098
14
Page 15
PACKAGE DESCRIPTION
LTC1655/LTC1655L
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
8
5
6
0.228 – 0.244
(5.791 – 6.197)
0.010 – 0.020
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
×
°
45
0.016 – 0.050
(0.406 – 1.270)
(1.346 – 1.752)
0°– 8° TYP
0.053 – 0.069
0.014 – 0.019
(0.355 – 0.483)
TYP
0.150 – 0.157**
(3.810 – 3.988)
1
3
2
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
SO8 1298
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
Page 16
LTC1655/LTC1655L
TYPICAL APPLICATION
U
This circuit shows how to measure negative offset. Since
LTC1655/LTC1655L operate on a single supply, if its
offset is negative, the output for code 0 limits to 0V. To
measure this negative offset, a negative supply is needed.
Connect resistor R1 as shown in the figure below. The
output voltage is the offset when code 0 is loaded in.
Negative Offset Measurement
5V
0.1µF
8
V
1
CLK
µP
2
D
IN
3
CS/LD
CC
LTC1655/
LTC1655L
GND
5
7
V
OUT
R1
100k
–5V
1655/55L TA06
RELATED PARTS
PART
NUMBERDESCRIPTIONCOMMENTS
LTC1257Single 12-Bit V
in Reference Can Be Overdriven Up to 12V, i.e., FS
LTC1446/Dual 12-Bit V
LTC1446LLTC1446L: V
LTC1448Dual 12-Bit V
LTC1450/Single 12-Bit V
LTC1450LLTC1450L: V
LTC1451Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V,5V, Low Power Complete V
Internal 2.048V Reference Brought Out to Pin
LTC1452Single Rail-to-Rail 12-Bit V
LTC1453Single Rail-to-Rail 12-Bit V
LTC1454/Dual 12-Bit V
LTC1454LLTC1454L: V
LTC1456Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,Low Power, Complete V
Full Scale: 4.095V, V
LTC1458/Quad 12 Bit Rail-to-Rail Output DACs with Added FunctionalityLTC1458: VCC = 4.5V to 5.5V, V
LTC1458LLTC1458L: V
LTC1650Single 16-Bit V
LTC1654Dual 14-Bit DAC1LSB DNL, 2 DACs in SO-8 Footprint
LTC1657/Single 16-Bit V
LTC1657LLTC1657L: V
LTC1658Single Rail-to-Rail 14-Bit V
V
= 2.7V to 5.5VSwings from GND to REF. REF Input Can Be Tied to V
CC
LTC1659Single Rail-to-Rail 12-Bit V
= 2.7V to 5.5VSwings from GND to REF. REF Input Can Be Tied to V
V
CC
DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V,5V to 15V Single Supply, Complete V
OUT
DACs in SO-8 PackageLTC1446: VCC = 4.5V to 5.5V, V
OUT
DAC, VCC: 2.7V to 5.5VOutput Swings from GND to REF. REF Input Can Be Tied to V
OUT
DACs with Parallel InterfaceLTC1450: VCC = 4.5V to 5.5V, V
OUT
Multiplying DAC, VCC: 2.7V to 5.5VLow Power, Multiplying V
OUT
MAX
= 12V
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
OUT
= 0V to 4.095V
OUT
OUT
= 0V to 4.095V
OUT
OUT
DAC in SO-8 Package
OUT
DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V 3V, Low Power, Complete V
OUT
DACs in SO-16 Package with Added FunctionalityLTC1454: VCC = 4.5V to 5.5V, V
OUT
: 4.5V to 5.5VPackage with Clear Pin
CC
Industrial DAC in 16-Pin SO, V
OUT
= ±5VLow Power, Deglitched, 4-Quadrant Mulitplying V
CC
= 2.7V to 5.5V, V
CC
= 2.7V to 5.5V, V
CC
DAC in SO-8 Package
OUT
= 0V to 4.095V
OUT
OUT
DAC in SO-8
OUT
= 0V to 4.095V
OUT
OUT
Output Swing ±4.5V
DAC with Parallel InterfaceLTC1657: VCC = 5V, Low Power, Deglitched, V
OUT
DAC in 8-Pin MSOP,Low Power, Multiplying V
OUT
DAC in 8-Pin MSOP,Low Power, Multiplying V
OUT
= 3V, Low Power, Deglitched, V
CC
DAC in MS8 Package. Output
OUT
DAC in MS8 Package. Output
OUT
DAC SO-8 Package
OUT
= 0V to 2.5V
= 0V to 2.5V
= 0V to 2.5V
= 0V to 2.5V
OUT
= 0V to 4.096V
OUT
OUT
CC
DAC,
= 0V to 2.5V
CC
CC
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear-tech.com
16555lf LT/TP 0800 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.