Analog Devices ee-98 Application Notes

Engineer To Engineer Note EE-98

Technical Notes on using Analog Devices’ DSP components and development tools from the DSP division

Phone: (800) ANALOG-D, FAX: [phone], FTP: ftp.analog.com, EMAIL: [e-mail]

Using external bus arbitration to

group more than two ADSP-21065L

into a multiprocessing cluster

contributed by hs

Introduction:

The new ADSP-21065L allows by its system design
to face high speed real words digital signal
processing applications. To acquire the data or to
provide external mass storage, peripherals have to
be interfaced to the external port of the SHARC
processor. If the complexity of the task rises and
more than two ADSP-21065L are required to meet
the real time specification, an external bus arbiter is
necessary to keep the external bus free of conflicts.
This application note will show how easily more than
two ADSP-21065L can be arbitrated using a small
external programmable logic device.

Multiprocessing capabilities:

The ADSP-21065L is already equipped with
configuration pins and bus arbitration logic for up-to
two processors. These dedicated pins are:

:Definition of processor ID within a cluster

ID

1-0

:Bus arbitration lines between two processors

BR

1-0

So in a cluster of two, it is totally sufficient to assign
one processor to ID1 and the other to ID2. Finally,
the BR
together, as they are used for the handshaking
between the processors. This allows to connect both
external ports together and to log onto a common
external address and data bus which can be
mastered by a host processor, too.

Bus arbitration protocol:

and BR2 lines have to be connected

1

As soon as more than two processors have to share
the external resources, further external arbitration
logic is necessary to prevent bus conflicts.

This external logic has to take care that after reset
all ADSP-21065L will be synchronized and update
their internal record of who the current master is (in
the current bus master field, CRBM, of the SYSTAT
register). The synchronization after reset performs
according to the following rules:

• All ADSP-21065L except the one with ID=1 will
deassert their BR
keep their BR

line during reset. They will

x

deasserted for at least two cycles

x

after reset and until their bus arbitration logic is
synchronized.

• Afterwards an ADSP-21065L will consider itself
synchronized when it sees a cycle in which only
one BR

line is asserted. The ADSP-21065L will

x

identify the bus master by recognizing which BR
is asserted, and will update its internal record of
who the current master is.

• The bus master will drive all memory strobes
directly after reset to prevent them from floating.

Realization in external logic:

To emulate this protocol, every processor must be
configured to ID=2 to remove multiple bus masters
driving memory strobes after reset. This is done by
the external logic asserting the BR

pin of each

1

processor forming the cluster during reset. Further­more it will keep BR

pin low after reset to prevent

1

the bus slaves from glitching into the target. An
ADSP-21065L with ID=2 will drive its BR
reset. If it sees the BR
will deassert its BR

line asserted after reset, it

1

and check BR1 within the next

2

low after

2

two cycles. As this is held low by the programmable
logic device, it will consider itself as a bus slave with
ID=2 and normal processor arbitration can start.

x

When a multiprocessing system is reset by the
RESET pin, the bus arbitration logic on each
processor must synchronize to insure that only one
ADSP-21065L will drive the external bus. There
must be one bus master, and the other processors
must recognize which one it is before actively
arbitrating for the bus. The bus synchronization
scheme also allows the system to safely bring two
ADSP-21065L into and out of reset.

The external logic will give bus mastership to the
attached processors by monitoring their BR

pins.

2

Every ADSP-21065L requiring external access for
peripheral operations will indicate this with driving it

output pin low. If no other ADSP-21065L is

BR

2

currently requiring the external bus, the BR

line of

1

the requesting ADSP-21065L will be deasserted
(e.g. driven high) so that a bus transition cycle
(BTC) can occur. All other BR

lines connected to

1

the other processor will still be kept low. After this

a

BTC the ADSP-21065L has gained bus mastership
and will perform the external operation. The end of
this access is indicated by driving its BR

pin high

2

again. Nevertheless the current ADSP-21065L will
maintain the bus token (BR

high) until a different

1

ADSP-21065L wants to perform an external access.
This insures that the started SDRAM controller will
supply proper signals to possibly available SDRAM
memory bank connected to the external port.

Priority assignments:

Of course, it now may happen that several ADSP­21065L requiring external access at the same time.
Therefore there must be some provisions that the
bus in only granted to one processor. Basically this
gives two possible arbitration schemes with either
fixed or rotating priority.

For example the bus mastership token would be
granted in a cluster of four ADSP-21065L with fixed
priority according to table1

Processor Number

Cycle # P #1 P #2 P #3 P #4

1 M - - -
2 M - BR BR
3 - BR M BR
4 - M - BR
5 - - - M

table1: fixed priority

where (M) = bus mastership, (BR) = external bus
required and (-) = no external request and for
rotating priority like in table2:

Processor Number

Cycle # P #1 P #2 P #3 P #4

1 M - - -
2 M - BR BR
3 - BR M BR
4 - BR - M
5 - M - -

table2: rotating priority

To improve the real time character of the bus usage
it is advisable to check what arbitration scheme
would be best suitable and to use the BMAX register
to determine the maximum amount of time for bus
masterhip.

The programmable logic device:

The following example of an bus arbiter for four
ADSP-21065L explains the requirements for the
logic device and the implemented schemes.

To monitor all BR

pins of all the connected ADSP-

2

21065L, a certain number of input pins (4) is
needed. Additionally, the reset signal (1) and the
processor clock signal (1) is required. Finally a
RPBA pin (1) will allow to switch the arbitration
schemes. For the output the chip needs the BR
pins (4), an init flip- flop for the delay after reset (1)
and a number of flip-flops for the implemented state
machine (3).

Over all, the design requires 7 inputs and 8 outputs
in a device with register capability. Due to the
complexity of the state equations, the design can
not be fitted into 20V8, instead a 22V10 has to used.
This device offers furthermore two unused
registered output pins, so that the device could
easily handle the bus arbitration for a cluster of six
ADSP-21065L. Figure 1 shows one of the possible
pin assignments for the device.

PALL22V10
+----++----+
CLK_IN --| 1 ++ 24 |-- VCC
RESET --| 2 23 |-- INIT REG
RPBA --| 3 22 |-- BR1_4 REG
BR2_4 --| 4 21 |-- BR1_3 REG
BR2_3 --| 5 20 |-- BR1_2 REG
BR2_2 --| 6 19 |-- BR1_1 REG
BR2_1 --| 7 18 |-- B3 REG
NC --| 8 17 |-- B2 REG
NC --| 9 16 |-- B1 REG
NC --| 10 15 |-- NC
NC --| 11 14 |-- NC
GND --| 12 13 |-- NC
+----------+

figure1: pinout of the PLD

The equations for the state machine can be found
attached to this document.

References:

• ADSP-2106x user’s manual chapter 7

• ADSP-21065L preliminary user’s manual

• ADSP-21065L preliminary data sheet

• AMD PALASM software

• http://www.analog.com/sharc/attack

1

EE-98 Page 2
Technical Notes on using Analog Devices’ DSP components and development tools from the DSP division

Phone: (800) ANALOG-D, FAX: [phone], FTP: ftp.analog.com EMAIL: [e-mail]