Analog Devices ee-82 Application Notes

Enginner To Engineer Note EE-82

Technical Notes on using Analog Devices’ DSP components and development tools from the DSP Division
Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com

is automatically incremented after every IDMA
word transfer. As the IDMA port has a 16 bit bus,

Using an ADSP-2181 DSP’s IO
Space to IDMA boot another
ADSP-2181.

Contributed by J. O.
Last Modified 10/28/97

24 bit transfers require two host accesses. The
first access transfers the most significant 16 bits,
the second access transfers the least significant 8
bits, right justified, with a zero filled upper byte.
IDMA address increments occur after the entire 24
bit word has been transferred for a PM transfer, or
after the entire 16 bit data word has been
transferred for a DM transfer

This application note describes an
example hardware and software interface
between the Internal DAM (IDMA) port of the
ADSP-2181. Additionally, this application note
shows how a host DSP can boot a target DSP
using the IDMA port. As each specific system
design has it’s own requirements and
challenges, this application note does not
presume to provide the only possible solution.
Rather, it is meant to provide the system
designer a flexible framework of ideas that can
be tailored to meet individual system
requirement .

IDMA Operation

The host DSP can gain access of the
target ADSP-2181’s internal memory through the
target’s IDMA port. Any host processors
accessing the target ADSP-2181 through IDMA
can treat the target DSP as a memory mapped
slave peripheral, and can have access to all of the
target’s internal Data Memory (DM) and Program
memory (PM), excluding control registers. The
adsp-2181’s IDMA port consists of a 16 bit
multiplexed address/data bus (IAD15:0), a select
line (/IS), IDMA address latch (IAL), read (/IRD),
write (/IWR), and acknowledge (/IACK) signals.
The host DSP is responsible for initiating all data
transfers. The target DSP memory address is
loaded into the IDMA Address register (IDMAA).
This register contains the 14 bit internal memory
address, along with a bit to specify the type of
transfer: 24 bit Program Memory opcodes, or 16
bit Data memory data. The IDMAA register can be
initialized by either the target DSP or by the host
DSP. The host can initialized this register by
performing an address latch cycle. An address
latch cycle is defined by the host asserting the IAL
signal, and then transferring a 15 bit (14 address
bits plus 1 destination memory type bit) value on
the IAD pins. To streamline the transfer of large
segments of opcodes or data, an Address Latch
Cycle does not need to be performed for each
IDMA access. Instead, once latched, the address

Booting the DSP

The IDMA Port on the DSP can be
used to boot load the DSP on power up. This
eliminates the need for a separate EPROM for
the DSP. On the ADSP-2181, booting is
controlled through the use of the MMAP and
BMODE pins. Booting through the IDMA port
is enabled by holding the MMAP pin low, and
the BMODE pin high. With this signal
combination, on RESET, the DSP does not
activate its external address bus to access an
EPROM. Instead, the DSP expects a host to
begin IDMA transfers to fill its internal Data
and Program memories. This process consists of
the host performing standard IDMA instruction
and data transfers. Booting is terminated when
the DSP restart vector at DSP Address
PM(0x0000) is written. An efficient boot
loading sequence would consist of the host
filling the DSP’s internal Program Memory
starting at location PM(0x0001), and using the
automatic address increment feature on the
IDMA port to speed the transfer of code block in
ascending address order. The host can then
initialize data memory. When all initialization is
complete, the host should then initialize the
DSP’s restart vector and DSP program execution
will commence.

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Enginner To Engineer Note EE-82

Technical Notes on using Analog Devices’ DSP components and development tools from the DSP Division
Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com

Interface Hardware Design

The IDMA port of the target DSP is
mapped into two locations in the host ADSP­2181’s IO space. On location is used by the host
to latch the address that an IDMA write would
target. The other location is used when
transferring data an instruction information. The
target DSP has been configured for IDMA boot,
the MMAP=0 and the BMODE=1.

Minimal logic is required to connect
the external bus of the host ADSP-2181 to the
target’s IDMA port. The only external logic
that is required is a singular or gate, which is
used to ensure that IAL and /IWR are never
asserted at the same time. This is achieved by
using the A) and /WR lines from the host as
inputs to an OR gate, whose output is then
connected to /IWR on the target DSP. A0, from
the host, is connected to the address latch signal,
IAL, on the target. This connection allows the
host to commence an address latch sequence by
writing to an address that contains bit 0 in the
host memory. The write strobe, /IOMS, is
connected to /IS, so that any write to the IO
space of the host will trigger the write strobe of
the target DSP’s IDMA port. The 16 data lines
form the host’s IO space (D8-D23) are directly
connected to the IAD data bus on the target
ADSP-2181. The host will use this bus to
transmit the DSP memory addresses, as well as
transfer data to the DSP.

Generating “Boot” Code

The ADSP-21xx family operates on 24­bit instruction opcodes. The IDMA port can only
accept 16-bit values. To transfer instruction
opcodes through the IDMA port, the most
significant 16 bits transferred first, followed by
the least significant 8 bits, right justified.

of the ADSP-2100 Family Assembler Tools &
Simulator Manual.

Since the executable file contains 24 bit
DSP opcodes, the file needs to be re-formatted to
adhere to the IDMA port’s 16 bit data
requirement. First, it is necessary to remove the
place holders and formatting headers from the
opcodes from the .exe file.

The ADSP-2100-Family .EXE format
separates Program Memory and Data Memory
segments on a module-by-module basis. The
executable format has the following elements:

@PA <---- Start of PM RAM
Module
0000 <---- Starting address
123456 <---- First Opcode
789abc <---- Second Opcode
def012 <---- Third Opcode
: :
#12345678 <---- End-of-module specifier
@DA <---- Start of DM RAM
segment
0000 <---- Starting address
1234 <---- First data word
5679 <---- Second data word
: :
: :
#12345678 <---- End-of-module specifier

After the place holders have been
removed, the 24 bit opcodes need to be
reformatted into 2 16 bit words. The first the 16
MSBs and the second with the 8 LSBs with
leading zeroes. Note, the usage of the PX
register is greatly helpful for implementing this
procedure, as seen in the attached code.

DSP Executable files are produced by
the ADSP-21xx Family Linker. The Linker
takes object files generated by the Assembler
and C Compiler, places them within the memory
architecture defined by the system architecture
file, and generates a DSP executable (.EXE). A
detailed description is available in Appendix B

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