Analog Devices ee-77 Application Notes

Engineer-To-Engineer's Note EE-77

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Technical Notes on using Analog Devices’ DSP components and development tools

SHARC Booting Process

Bits

SHARC Link Port Booting

Last Modified: 8/21/97

OVERVIEW:

This Engineer’s Note will discuss the link boot
process from both the perspective of the master
device and the slave SHARC. One characteristic
which makes link port booting different from
EPROM and host booting is the handling of the
link control register, LCTL, during the booting
mode. Unlike the other booting processes where
the control registers are initialized to meaningful
values, the link port control register is initialized
to zero but it is ignored during the initial booting
process. This process results in complications
which must be accounted for during the booting
process. Details of the complications along with
methods of handling them will be presented.

A link port boot example is provided with this
engineers note. The example consists of code for
the master SHARC which will transfer the boot
code to a slave SHARC through the link ports.
The link port boot kernel executed on the booting
SHARC along with a simple test program is also
provided.

The term booting refers to the initial downloading
of data and code into the SHARC processor so it
may then begin instruction execution. There are
three possible booting modes for the SHARC. The
SHARC can be booted by reading data from an
EPROM through its external port. The SHARC
can be booted by a host processor writing data to
the SHARC through its external port, or the
SHARC can be booted by another processor
writing data to the SHARC through its link ports.
The SHARC can also be placed in a no boot mode
after reset. In the no boot mode the SHARC
begins executing instructions form external
memory.

The booting mode of the SHARC is configured in
hardware by three pins: EBOOT, LBOOT and
BMS. Upon power up, the SHARC will enter the
appropriate boot mode based on the setting of the
EBOOT, LBOOT and BMS pins. Table 1
describes the pin configurations for each boot
mode (EPROM boot, Host boot, Link boot and No
boot):

EBOOT LBOOT BMS

Booting Mode
1 0 Output EPROM
0 0 1 Host
0 1 1 Link Port
0 0 0 No Boot

Table 1. Boot mode pin configuration

The first section of the engineers note describes
the general booting process of the SHARC.
Section 2 discusses the details of booting through
the link port. Section 3 discusses the hardware
issues associated with link port booting and how
to accommodate for these issues in software.
Section 4 provides a step by step example of link
port booting including documented code.

On power up the SHARC will be configured for a
256 word Direct Memory Access (DMA) transfer
through either the external port, for EPROM or
Host boot, or through the Link Port for Link boot.
(No boot begins executing code in external
memory no DMA is required.) The registers
associated with DMA Channel 6 are initialized to
perform the 256 word DMA through the
appropriate port to internal memory starting at
location 0x20000 and ending at location 0x200FF.

a

THE DMAC6 register is also initialized at power
up based on the boot mode selected. Table 2
matches the DMAC6 initial setting to the
corresponding boot mode:

Booting Mode DMAC6
EPROM 0x02A1
Host 0x00A1
Link Port 0x00A0

Table 2. Control Register DMAC6 Initial value

All three booting modes initialize DMAC6 for
instruction word transfers and 16-48 bit packing.
(The packing mode is ignored during EPROM
booting which performed 8-48 bit packing and link
port booting which packs nibbles into 48 bit
words.) In Host and EPROM boot mode DMAC6
is set to enable a DMA through the external port.
In the EPROM boot mode DMAC6 is also
configured for a master mode DMA (see chapter 6
of the SHARC User’s Manual for an explanation
of master mode DMA).

After reset the program counter (PC) will be
pointing to location 0x20004 where it will be
executing an idle instruction. Upon completion of
the 256 word DMA the DMA channel 6 interrupt,
EPB0I, will be latched and the PC will jump to
location 0x20040. At this point the SHARC will
begin executing instruction starting with the
instruction at location 0x20040. If the instruction
at location 0x20040 is an RTI, which it will be if
the boot loader kernels provided are used, the PC
will jump to location 0x20005 and begin executing
code in a linear flow.

If the program and data to be booted into the
SHARC is greater than 256 words, the remaining
code and data must be loaded in by the SHARC
and using the first 256 words. For each booting
mode Analog Devices provides what is called a
boot kernel. The boot kernel is 256 words in
length and is prepended to the user code when the
loader utility is run (see link port boot example for
operation of the loader utility). The purpose of the
256 word loader kernel is to complete the booting
process by loading in the user code and data then
writing over itself. Each booting mode requires a
unique loader kernel, however the purpose of each
kernel is the same; load in the user data and code.

The booting kernels provided by Analog devices
create a three phase booting process. the first
phase is the loading in of the first 256 words as
described above. The first 256 words will be the

boot kernel. The second phase is the execution of
the boot loader kernel which will perform single
word DMA transfers through the appropriate port
based on the boot mode. In the third and final
phase the boot kernel performs a 256 word DMA
that will load the code located at addresses
0x20000 through 0x200FF. This results in the
loader kernel overwriting itself. The PC will then
jump to location 0x20005 and begin executing
code. WARNING: a residual instruction will be
left at location 0x20004 (please refer to the boot
kernel code for explanation).

Link Port Booting Process

The link port booting process has an additional
feature unique to the other booting modes. The
DMAC6 register is used to configure the external
port and DMA channel 6. The link port requires
an addition control register, LCTL, in order to
configure link port 4 for a DMA transfer. Unlike
DMAC6, LCTL is initialized to 0x0000 at power
up. LCTL is ignored by the processor during the
initial 256 word DMA.

The SHARC ignores the LCTL register setting
until some time shortly after the first 256 word
DMA is complete. A transition period elapses
from the time the SHARC ignores the LCTL
setting to the time the SHARC adheres to the
LCTL setting. The LCTL is set to 0x0000,
therefore link port 4 will be disabled. The
disabling of link port 4 discontinues LACK from
being driven high. LACK is internally pulled
down by a 50 kΩ resistor thus resulting in an RC
decay of LACK. The actual decay rate of LACK
will depend on the connector type and length
connecting the booting device to the link port of
the SHARC. The decay time of LACK must be
taken into account when transmitting the
remaining data to complete the booting process.

Hardware Issues with Link Port
Booting

The hardware dependent decay time for LACK
must be taken into account when creating the
code to boot the SHARC. LACK is used by the
link port to hold off a transfer if the link port is
not ready to receive data. The transmitting device
must sample LACK to determine if the SHARC is
ready to receive. If LACK is high the SHARC is

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ready to receive, if LACK is low the transfer is
held off. (See chapter 9 of the SHARC User’s
Manual for a detailed explanation of link port
operation.) If LACK is sampled before it decays to
a 0 logic level the transmitter may attempt to
transmit data while the link port is disabled. This
will result in a loss of data.

The actual RC decay time of LACK is hardware
dependent. The decay time will depend on the
length of the cable or trace connecting the link
port with the transmitting device and the type of
material used. Since the decay time will be
variable across platforms, a constant time delay to
wait for LACK to decay after the first 256 words
are transferred is not always possible. The
transmitter must dynamically determine what a
sufficient decay time is for LACK.

Upon completion of the first 256 word DMA, the
transmitter should drive LCLK low and
continually sample LACK until it sees LACK is
low. Once LACK is low, the transmitter can drive
LCLK high and once again sample LACK. When
LACK is now high the transmitter knows the
receiver is ready to receive and can begin
transmitting the remaining data.

A potential race condition is created by the polling
of LACK by the transmitter. If LACK does not
decay to a logic level of 0 before the receiver
enables its link port, LACK will be driven high by
the receiver and the transmitter will be stuck in
an infinite loop. This is avoided by a polling
(handshaking) process within the loader kernel as
described below.

The linker loader kernel executed by the booting
SHARC enables a handshaking process which can
insure the decay of LACK will not result in a loss
of data. Link port 4 will be initially disable when
the SHARC begins executing the loader kernel.
Before the loader kernel enables the link port to
receive the remaining code it polls it’s LSRQ
register. Once it sees a receive data request in the
LSRQ register for link port 4, it enables the link
port to receive.

An LSRQ link port 4 receive request will occur
when the link port 4 LCLK signal is driven high
by another device. (See Chapter 9 of the SHARC
User’s Manual for a detailed description of LSRQ.)
In order for the handshaking to work, the
transmitter must drive LCLK high after it has
sample LACK low.

Link Port Booting Example

The following example demonstrates a link port
boot of one SHARC from another SHARC. The
link boot loader kernel, the transmitter (master)
SHARC code and the secondary (slave) SHARCs
link booted routine are included and documented.

The master SHARC will boot the slave SHARC
over the link ports by transferring a buffer of data
to the booting SHARC. The data will be
transferred by the core in two sections. The first
section will transfer the first 256 48 bit words to
the booting SHARC. After the first transfer the
SHARC will disable its link port and wait for
LACK to go low. Once LACK goes low the
SHARC will re-enable its link port and transmit
the remaining 48 bit words.

The code to be booted into the slave SHARC is
stored in a buffer named ldata within the master
SHARC. This data is stored in 48 bit memory,
however, the data is actually 16 bit words. Loader
data was created using the following call to the
loader:

ldr21k lsrq -blink -fascii -o lsrq.ldr

where lsrq is the name of the program to be
executed by the slave SHARC, -blink indicates the
program will be loaded via a link boot, -fascii
indicates the format of the loader file is to be 16
bit ascii and -o forces the name of the output of
the loader to be lsrq.ldr.

The 16 bit per word loader data is stored in 48 bit
memory. Before transferring the data through
the link port to the slave SHARC the data must be
packed into 48 bit words. The following code in
the master SHARC packs the 16 bit words into 48
bit words and transfers the 48 bit word through
link port 4:

lcntr = 0x100, do link until lce;

px1=dm(i0,m0); /*Read 16 LSBs from

memory to PX1*/
r0=dm(i0,m0); /*Read middle word*/
r1=dm(i0,m0); /*Read 16 MSBs */
r0=r0 OR LSHIFT r1 by 16;
px2=r0; /*load 32 MSBs in PX*/

link: pm(LBUF4)=px; /*Transfer 48 bit word

over link port 4*/

The least significant bits are store in the lowest
location in memory and the most significant 16
bits are stored in the highest location in memory.
Three memory accesses are required to retrieve
the entire 48 bit word. The PX register is used to
pack the 3 16 bit words into one 48 bit word.

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Technical Notes on using Analog Devices’ DSP components and development tools

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