Analog Devices ee-74 Application Notes

Engineer-To-Engineer Note EE-74

Technical Notes on using Analog Devices’ DSP components and development tools

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Analog Devices Serial Port Development and Troubleshooting Guide

Compiled by the Analog Devices DSP Applications group

Introduction

The purpose of this document is to assist engineers in the design and debugging of serial port communications in
systems using Analog Devices’ DSPs. First, it will cover general system design strategies to help ensure low
noise levels and valid signals throughout the system. Next, it will focus on common serial port problems and
their respective solutions. This section is processor nonspecific. The following section deals with processor
specific issues, these being the ADSP21xx family and the ADSP2106x family of DSPs. Finally, there is a
section containing example serial-port initialization code for both families of DSPs.

General ADSP-21xx / 2106x DSP SPORT Design Issues

(Note: because the serial ports on both the ADSP21xx and ADSP2106x families
of DSPs are very similar in architecture and functionality, the issues presented in
the section apply to both)

Perhaps one of the largest cause of serial port problems is poor board design. The serial ports are essentially
edge-triggered state machines - this means that every time a valid edge occurs on a serial clock line, the state
machine is stimulated. A valid edge occurs when the voltage level on a serial port line passes across
approximately 2.5 Volts in 5 Volt parts and 1.3 Volts in 3.3V parts - we will refer to this as the critical
voltage. If the serial clock is set to ‘positive edge’ polarity (configurable in serial port control register), a valid
edge occurs when the voltage on the serial clock line passes from below the critical voltage to above the critical
voltage. On the other hand, if the serial clock is set to ‘falling edge’ polarity, a valid edge occurs when the
voltage passes from above the critical voltage to below the critical voltage.

a

Positive Edge Polarity Negative Edge Polarity

d

d

vali

Vcc

vali

Critical

point

Vdd

Vcc

Critical

point

Vdd

Figure 1 : Positive and Negative Edge Polarity

There are many design related problems that can cause noisy serial clock lines which can potentially cross the
critical voltage multiple times per one clock pulse. The example below presents two variations of the same
serial clock signal - one has a large signal reflection which causes each period of the serial clock to cross the
critical point multiple times. This will cause the state machine within the serial port to sample the serial data lines
twice per clock period causing the serial data to become corrupted. The other signal is properly compensated
so no reflections occur and the data is sampled once per period.

This signal does not contain reflections

This signal contains reflections

Figure 2: Signals with reflections

The following sections present specific design strategies to avoid problems like this one.

Decoupling the DSP’s Vcc and GND Pins

The DSP should have a .1µF capacitor connected between each of its Vcc and Gnd (Vdd) pins. This helps
keep the power supply to the DSP clean of voltage spikes and dips on the Vcc and Gnd lines. Large spikes
and dips in the Vcc and Gnd lines can cause the processor to jump into an unknown state potentially causing the
processor to crash. These capacitors should be placed as close as possible to the actual Vcc and Gnd pins of
the chip for maximum effectiveness.

Hardware Construction (PCB vs. Wirewrap)

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Signal Trace Length

Serial Clock

Serial Data

Frame Sync

Serial lines greater than about 3” will require some sort of reflection compensation. Details about this are
covered in the solutions section.

Common Serial Port Problems

This section is a troubleshooting guide. Each problem listed below contains a description of why it exists and
some techniques to isolate a specific cause. Once the cause is determined, a reference is provided for the
solutions table where conveniently enough, solutions can be found.

DSP is Receiving and/or Transmitting Corrupt Data

First ensure that the device communicating with the DSP is operating correctly. If the DSP is receiving corrupt
data, it may be because the device it is communicating with is transmitting corrupt data. If it is, make sure that
the signals that it is generating are clean, meet required timing specs and have good levels.

Below is an example of communications system where data is being corrupted:

DSP 1 DSP 2

Shifted Data:

When serial data received by DSP 2 is a shifted version of the data transmitted by DSP 1, this usually means
there is a data synchronization problem. This is often common when transmitting unframed data and can be
caused by a noisy serial clock or system noise. Below are a few examples of 8-bit data words which have been
shifted during the transmission from DSP 1 to DSP 2.

Data Sent from DSP 1: Data Received by DSP 2:

10101010 01010101
11110000 01111000
00001111 00011111

See items:

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Incorrect Bits:

When serial data received by DSP 2 contains corrupted bits, there is usually a system noise problem. Below
are a few examples where 8-bit data words transmitted from DSP 1 to DSP 2 have become corrupted.

Data Sent from DSP 1: Data Received by DSP 2:

10101010 10101110
11110000 10110010
00001111 01001111

No activity on serial port lines

When the serials ports are not enabled, the serial port signals are tristated.

Invalid line levels on serial port lines

Invalid line levels will occur when two devices are trying to drive the serial port. If one part is driving a serial
port line high and another is driving it low at the same time the resulting voltage on that line while be somewhere
between Vcc and Gnd. This can also damage one of the

Noise on serial port lines

Solutions Table

Proper termination of long SPORT traces

SPORT_Tech_Note.pd

f

The serial port on the DSP is very sensitive to any external noise in the system. This includes noise due to
reflections on the lines, signal degradation due to long trace lengths, and signal interference. Any trace that is
equal to or longer than 3--4 inches has to be treated as a transmission line at the high frequencies that the
SPORT generally operates at, and must be properly terminated to reduce noise and glitches on the lines. Failure
to do so may result in the SPORT locking up, or the SPORT transmitting or receiving incorrect data. In addition

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to good board layout and design considerations (refer High Speed Digital design book), a popular method to
reduce noise is to provide series termination resistors on the SPORT control lines, as close to the DSP
generating the signals as possible(preferably right next to the DSP).The value of the resistor typically ranges
between 20-100 ohms, but an exact value depends on the trace lengths and the characteristic impedance of the
line. Values can be determined by using an equation described in the book “High-Speed Digital Design-A
Handbook of Black Magic” by Howard W. Johnson and Martin Graham, and published by Prentice-Hall.

If the total electrical delay of the signal net in questions is greater than six times the rise or fall time of the source,
you should terminate the signal. Rough calculations of the total line length delay of the net should be calculated
with 0.180ns per inch and 2 pF per inch.

Example 1:

A driver is connected to 6 loads, each load is 8pf, the connection is a star connection, where the longest path
from the driver is 15 inches, the output impedance of the driver is 10 ohms, and the rise / fall time of the driving
signal is 2.0 ns max.

The max. rise and fall times of the Driving Signal is 2 ns.
The Total Signal trace delay is (15 * .180 ns) this is 2.7 ns.
The Total RC load delay is ((8 pF * 6) + (15 * 2 pF) * 10 ohms = 0.780 ns

Then the ratio of signal delay to rise time is signal delay / rise time equals 3.48 ns / 2.0 ns = 3.48 The ratio is
less than 6, so this signal should be OK, and Terminations would not be required.

Example 2:

A driver is connected to 6 loads, each load is 8pf, the connection is a star connection, where the longest path
from the driver is 30 inches, the output impedance of the driver is 15 ohms, and the rise / fall time of the driving
signal is 1.0 ns max.

The max. rise and fall times of the Driving Signal is 1 ns.
The Total Signal trace delay is (24 * .180 ns) this is 5.4 ns.
The Total RC load delay is ((8 pF * 6) + (30 * 2 pF) * 10 ohms = 1.00 ns

Then the ratio of signal delay to rise time is signal delay / rise time equals 6.4 ns / 1.0 ns = 6.4 The ratio is
greater than 6, this signal would cause reflection problems, and terminations should be used.

For a series termination: The termination value should be the PWB characteristic impedance minus the driver
output impedance. Example: Assuming a PWB Z of 50 ohms, and Driver Z of 10 ohms, then the series
termination located as close to the driver as possible would be 40 ohms.

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For a end termination (parallel split termination): The parallel equivalent termination value should be the PWB
characteristic impedance. Example: Assuming a PWB Z of 50 ohms, then the parallel equivalent split termination
values located as close to the end of the line as possible would be 50 ohms. You should not exceed IOH Max
and I

Max of the Driver. After establishing the 2 resistor values for the termination (for most CMOS logic the

OL

ratio should be the ratio of IOH and IOL), calculate the current through the two resistors based on the VOH
and VOL, if the current in either case exceeds I

Max or IOL Max, you should not use a end termination

OH

arrangement.

Processor Specific Issues

21xx

The questions and answers provided in this Tech-note are based on commonly asked questions from
customers, or information that is not documented extensively in the ADSP-2100 Family User’s manual, and is
intended to supplement the information provided therein.
The serial ports have the capability of transmitting and receiving serial data in the form of bits, with the MSB
first. Bits are clocked in at the rate of the serial port clock (which can either be internally generated by the DSP
as a fraction of the processor clock (CLKOUT), or externally generated by another device, and supplied to the
DSP). Bits are transmitted on the rising edge of an SCLK pulse, and received on the falling edge of an SCLK
pulse. The frame sync signal is used to signify the start of a serial data word or stream of serial words.

Continuous mode of operation of Serial Port

The ADSP-2100 Family User’s manual (third edition) describes the operation of the SPORTs in continuous
mode (for example, refer section 5.9 on timing examples on page 5-16). The serial port is said to operate in
the continuous mode while either transmitting or receiving, if a bit is shifted out or in with every SCLK pulse,
without a pause. This is not a special mode of operating the serial port, and hence there is no register or bit
associated with it. The value in the RFSDIV register determines the operation. For example, to set the serial
port up in this mode, with an internal RFS and alternate framing, set RFSDIV to be equal to the SLEN-1.

Internal generation of transmit and receive frame syncs with frame syncs NOT required

If a serial port is set for internal frame sync(transmit or receive) and the SPORT x Control register is configured
for “frame-sync-not-required”, (in other words, bits 11 and/or 13--the RFSR and the TFSR set to 0), the
serial port continues to generate a frame sync for every transmitted or received word. In other words,
operation of the SPORT is identical for either mode. The main difference is seen at the receiving end where if
the SPORT is set up for external frame sync, the DSP ignores the frame sync after the initial pulse.

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Technical Notes on using Analog Devices’ DSP components and development tools

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