Analog Devices EE229v01 Application Notes

Engineer-to-Engineer Note EE-229

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Technical notes on using Analog Devices DSPs, processors and development tools

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Estimating Power for ADSP-BF533 Blackfin® Processors

Contributed by Joe B. Rev 1 – February 20, 2004

Introduction

This EE-Note discusses the methodology for
estimating total average power consumption on
the ADSP-BF533 Blackfin® family of
processors (including the ADSP-BF531 and
ADSP-BF532 derivatives). The following
documentation will detail how to interpret power
measurements published in the processor data
sheet and how to extrapolate data for individual
sets of operating conditions based on measured
data at specific operating conditions. A “worst­case” scenario is also made available as an
example for board designers to consider when
designing their power supplies.

Average Power Consumption

Total average power consumption (P
sum of the average power dissipated in each of
the three power domains in a Blackfin
application: internal supply (
supply (
supply (V

V

), and, optionally, Real-Time Clock

DDEXT

). There are different supply

DDRTC

V

DDINT

voltages because the core does not operate at the
same voltage as the I/O. The core operates within
the range of 0.8-1.32V with a nominal rating of

1.2V (

V

). The I/O circuitry supports a range

DDINT

of 2.25-3.6V with a nominal rating of 2.5V or

3.3V (

V

), depending on the system. The Real-

DDEXT

Time Clock can be powered by the I/O supply
but, if the user wanted to absolutely maximize
power savings, it could be the case that both

V

DDINT

and V

are powered off. The Hibernate

DDEXT

power mode on the ADSP-BF533 processor

) is the

DDTOT

), external

allows power to be removed from the core and,
optionally, removed from the I/O. To allow a
Real-Time Clock event to restore power to the
core after exiting Hibernate mode, the Real-Time
Clock must remain powered by a separate
supply, such as a battery. A third power domain
(

V

) satisfies this need.

DDRTC

Since power is defined as the product of the
supply voltage and the current drawn, the power
domains are described by the equations:

P = V * I

DDINT DDINT DDINT

P = V * I

DDEXT DDEXT DDEXT

P = V * I

DDRTC DDRTC DDRTC

For the purposes of this document, current and
power values are treated as average values and
voltages are assumed to be constant. The total
average power dissipated by the processor is the
sum of three components:

P = P + P + P

DDTOT DDINT DDEXT DDRTC

The following sections describe how to estimate
each of the three components.

Average Internal Power Consumption

There are a few things to consider when
estimating the average internal power dissipation
of a processor. The first consideration is the fact
that internal power is composed of two
components, one static and one dynamic.

The static component, as the name implies, is
independent of transistor switching frequency. It

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is a reflection of “leakage” current, which is a
phenomenon that causes transistors to dissipate
power even when they are not switching.
Leakage is a factor in high-performance CMOS
circuit design and is a function of both the supply
voltage and the ambient operating temperature at

some die to conduct faster than others, which
results in three process-related groupings. Figure
1 shows a process curve, which is a graphical
representation of this categorization based upon
transistor threshold voltage (
current (

I

DDSAT

).

V

) and saturation

T

which the part is expected to run. Leakage
current increases as temperature and/or voltage
increases.

The dynamic power component is largely
independent of temperature and is a function of
supply voltage and switching frequency. The
faster the transistors can switch, the more voltage
swings occur. The higher the supply voltage, the
larger the voltage swing between the on and off
transistor states. Thus, the dynamic component
will increase with voltage and/or frequency.

The second major consideration in estimating
average internal power is the type of application
code expected to run on the processor.
Specifications in the data sheet were obtained
while the processor ran a 75% Dual-MAC and
25% Dual-ALU algorithm, which was fetching
slowly changing data from L1 data memory. All
peripherals were disabled, but the core and L1
memory were running. To help the board
designer “size” the voltage regulators, power
numbers under full stress conditions are provided
in this document. These conditions include the
core running an algorithm consisting of 100%
Dual-MACs and more strenuous data-switching

Figure 1. Process Curve (I

DDSAT

vs VT)

The process contains three “corners”: fast,
typical, and slow. A “fast corner” part results
when the threshold voltage is minimized and the
saturation current is highest. Conversely, a “slow
corner” part has high threshold voltage and low
saturation current. Although “fast corner” parts
allow for higher operating frequencies, the trade­off is higher leakage current and higher
dissipated power in general.

characteristics. This is discussed in more detail
in the “Estimating Average Static Power” section
of this document.

Finally, the actual power numbers can fluctuate
within a defined range based on the processor
fabrication process at the transistor geometries
required for such high speeds. This is largely due
to the semiconductor doping process (i.e., ion
implantation), which does not result in uniform
connectivity among the transistors, yielding
slight variations of the die in any given wafer of
silicon. Other physical phenomena related to the
fabrication process also contribute to this non-

Estimating Average Static Power

The static component for average internal power
is a result of the leakage current that occurs even
when the transistors are not changing state.
When the clocks (core and system) are off and
voltage is applied to the core and L1 memory,
Blackfin processors are in “Deep Sleep” mode.
The data sheet shows the

I

DDDEEPSLEEP

measurement
to indicate the static current component that
contributes to the internal static power
consumption (

P

P = V * I

DDINT_ST DDINT DDDEEPSLEEP

DDINT_ST

):

uniformity. These physical differences cause

Estimating Power for ADSP-BF533 Blackfin® Processors (EE-229) Page 2 of 10

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Table 1 shows the “Internal Power Dissipation”
table from the ADSP-BF531/BF532/BF533
Blackfin Embedded Processor Data Sheet [1].
This table contains average internal current draw
measurements, which were taken from a
representative sample of typical parts. In terms of
the static current component,

I

DDDEEPSLEEP

, the
ambient temperature that yielded these numbers
was 25

°C, denoted by footnote 2. The table

shows that the drawn current increases when the
voltage rises from 0.8V to 1.2V. Although no
direct correlation between voltage increases and
leakage can be made, the table sufficiently
details the leakage that can be expected within
the acceptable voltage range at 25

°C for “typical

corner” parts.

internal power dissipated when the core is
running a 100% Dual-MAC algorithm, which
maximizes the workload on the core but is not
typical application code.

Table 2. Average I

on Faster Part (1.2V)

DDINT

The average internal power

!

consumption data is an average
measurement of the representative
sample of faster, higher leakage parts.
Therefore, some parts from within this
sample yielded power measurements
that slightly exceed the estimations
presented in this document as “worst­case”.

As can be extrapolated in the comparison
between Table 1 and Table 2, leakage current
can increase in magnitude by a factor of four due
to normal semiconductor processing variations.
Note that the current draw in Table 2 is labeled

I

to differentiate between the current draw

DDFAST

from typical parts (I

) and the current draw

DDTYP

obtained on faster, higher leakage parts.
Another important factor relative to leakage

Table 1. Internal Power Dissipation (Typical)

To help size the power supply, a set of faster,
higher leakage parts were measured. Table 2 is
similar to Table 1, except that it focuses on parts
that have higher leakage current, which are very
close to a worst-case average internal power
dissipation scenario in terms of silicon type with
no DMA and no peripherals enabled.

The ambient temperature is still 25
maximum 85

°C example is addressed in the

°C, as the

“Worst-Case Model” section of this note.

current is ambient temperature. Static power
consumption increases exponentially with
ambient temperature, as detailed by the equation:

P = P * e

DDINT_ST@T DDINT_ST@T0

where P

DDINT_ST@T0

is the power dissipated due to

leakage current at the known temperature (

P

and

DDINT_ST@T

temperature (

is the unknown number at the target

T). Using Table 2, the static

component of 120mA, given at

(0.015 * (T – T0))

T0)

T0 = 25°C, can be

multiplied by the supply voltage (1.2V) to obtain
the

P

DDINT_ST@T0

value of 144mW. Since the goal is

Additionally, these numbers reflect average

Estimating Power for ADSP-BF533 Blackfin® Processors (EE-229) Page 3 of 10