Analog Devices EE228v01 Application Notes
Engineer-to-Engineer Note EE-228
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Technical notes on using Analog Devices DSPs, processors and development tools
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Switching Regulator Design Considerations for ADSP-BF533 Blackfin®
Processors
Contributed by Bob Libert, Brian Erisman, and Joe Beauchemin Rev 1 – February 2, 2005
Introduction
The Blackfin® embedded processor’s on-chip
voltage regulator is a switching buck regulator
that requires external components to function
properly. This application note describes how
buck converters work and provides guidelines for
choosing the external components for the control
circuit to work with ADSP-BF531 / ADSPBF532 / ADSP-BF533 Blackfin processors.
Since the design of the internal voltage regulator
is similar to other Blackfin processors, this note
applies to the ADSP-BF534 / ADSP-BF536 /
ADSP-BF537 and the ADSP-BF561 processors
as well.
A buck converter consists of a switch, an
inductor, a diode, a capacitor, and a pulse-width
modulator (PWM), as shown in Figure 1.
The PWM controller is internal to Blackfin
processors, and the rest of the components are
external.
A control loop senses the regulator voltage and
sets the duty ratio (D) of the PWM to generate
the programmed voltage, where D is
approximately:
As can be seen in this equation, the forward
Internal Voltage Regulator
The internal voltage regulator on Blackfin
processors is a buck converter that reduces the
input voltage, which can range from 2.25 V to
voltage of the diode (Vd) contributes to both
terms. Variations in the diode’s forward voltage
and input and output voltages cause D to range
from approximately 30% to 63%.
3.6 V, to the voltage applied to the core, which is
programmable from 0.8 V to 1.2 V.
Figure 1. Basic Buck Converter
Figure 2. Internal Voltage Regulator Circuit
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The internal voltage regulator circuit (Figure 2)
consists of a voltage reference, an error
amplifier, a ramp generator, a comparator, and a
driver.
There are two states for the switch, closed (Ton)
and open (T
), where D is defined as:
off
During T
, the switch connects the supply
on
voltage (Vin) to the inductor (L), causing the
current in the inductor to ramp up.
Figure 3. Switch Behavior During Ton
During T
, the switch is off and the diode turns
off
on, which results in a negative voltage across the
inductor. This, in turn, causes the current to
decrease.
Another parameter introduced in Figure 5 is the
inductor ripple current (∆I
). This is the peak-
Lpp
to-peak measurement of current values that can
be expected to flow through the inductor.
The real circuit will also contain a number of
parasitic elements associated with the external
components. The PMOS FET has two parasitic
elements which reduce its efficiency. The first is
R
, the resistance between the drain and the
DS(on)
source. The power lost between the drain and the
source (P
) is the power dissipated within the
RDS
channel of the FET itself, which is present only
during the T
period, and is simply:
on
P
RDS
= I
load
2
* R
DS(on)
* D
The second parameter affecting the FET's
efficiency is its gate charge (QG). The loss due to
QG (PQG) occurs during both switching periods,
when the gate driver charges and discharges the
gate (Vgs). The value of PQG depends on the
switching frequency (fSW) and the turn on (Tr)
and turn off (Tf) times of the gate, and is defined
as:
PQG = f
* ((Vin/2)*(I
SW
*(Tr+Tf)) + (QG*Vgs))
load
The inductor has a DC resistance (RL). The loss
due to RL (PRL) is defined as:
Figure 4. Switch Behavior During T
The average current is load current (I
waveforms for the inductor current (I
off
). The
load
) and
inductor
the voltage at the input to the inductor (Vin)
should resemble Figure 5.
= I
P
RL
The largest contributor to overall loss is within
the diode. The diode limits its efficiency (PD)
because it has a forward voltage (V
during the T
time and is dependent on I
off
load
2
* RL
) that is on
d
. The
load
efficiency degradation caused by the diode is
implicit in the equation:
P
= I
D
* Vd * (1 – D)
load
The output filter capacitor has a parasitic
inductance (L
) and resistance (R
ESL
). Parasitic
ESR
inductance has no first-order effect on efficiency,
Figure 5. Inductor Wave Forms
Switching Regulator Design Considerations for ADSP-BF533 Blackfin® Processors (EE-228) Page 2 of 8
but degrades the filter performance by increasing
the output ripple and raising the burden on other
load bypass capacitors. Parasitic resistance
degrades efficiency and directly translates
inductor ripple current into what is usually the
dominant component of output ripple voltage.
The power loss due to R
P
= (∆I
ESR
Lpp
ESR
2
* R
is given by:
) / 12
ESR
Analyzing the loss models for the two switchstates yields two simple observations. Figure 6
shows the equivalent circuit diagram with the
switch on, which eliminates the diode.
Figure 6. On-State Loss Model
Figure 6 shows that the switch’s on-state loss is
in series with the input source Vin, therefore, an
equivalent voltage loss term, Vds, can be
subtracted from the input voltage in the D
equation:
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Buck converters usually work in what is called
the continuous mode. In the continuous mode of
operation, the current through the inductor rises
during the T
and the switching frequency (f
state and falls during the T
on
) spans the two
SW
states:
fSW = 1 / (Ton + T
off
)
The voltage regulator runs in continuous mode
during normal Blackfin processor operation (i.e.,
in Full On mode and Active mode).
The other mode of operation, discontinuous
mode, is the mode in which there is a period of
time after T
when there is no current flowing in
off
the inductor. This occurs when the Blackfin
processor is in a low-power state with a low
voltage on the core supply. Usually, this is a
mode to be avoided because it changes the loop
characteristics. Figure 8 shows the impact on
inductor current for the two modes of operation:
state,
off
Similarly, Figure 7 depicts the equivalent circuit
diagram with the switch open:
Figure 7. Off-State Loss Model
Here, the observation can be made that the
output inductance loss is in series with the
output, so an equivalent voltage loss term can be
added to the output, and is simply the inductor’s
equivalent resistance (R
current (I
Switching Regulator Design Considerations for ADSP-BF533 Blackfin® Processors (EE-228) Page 3 of 8
). Thus, the D equation becomes:
load
) multiplied by the load
L
Figure 8. Continuous IL vs Discontinuous IL
In the discontinuous plot above, the space
between T
and the subsequent Ton is referred to
off
as “dead time”.
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