Analog Devices EE226v01 Application Notes

Engineer-to-Engineer Note EE-226

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Technical notes on using Analog Devices DSPs, processors and development tools

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ADSP-2191 DSP Host Port Booting

Contributed by Michael Kuegler Rev 1 – January 23, 2004

1. Introduction

The Analog Devices ADSP-2191 DSP provides a
Host Port Interface (HPI) that can be used by a
Host to access the internal and external memory
and I/O space of the DSP via an 8- or 16-bit bus.
It is also possible to boot the DSP via the HPI
from the Host. The ADSP-2191 DSP is always
passive during Host Port accesses; therefore it is
called "Target" in this context. This application
note:

• Demonstrates how to access the Host Port

from an FPGA or PLD, using VHDL as the
design language.

• Provides an example of a software boot

loader, written in C, for booting the DSP via
the Host Port from a microcontroller or any
other processor.

and accesses the PLD using a set of low-level
interface functions (which have to be adapted to
the underlying hardware).

Screenshots from a logic analyzer, showing Host
Port transfers during the boot process, are found
in Chapter 7.

Chapter 2 outlines the HPI features and
configuration used in this design.

This document does not provide an

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introduction to the Host Port, and it does
not explain all possible configuration
parameters.

A complete description of the HPI and
the Host Port I/O configuration registers
can be found in [1]. For detailed
information about pin-out and timing
requirements, refer to [2].

To achieve this, a test system has been designed
using another ADSP-2191 DSP as Host
processor and an Altera MAX7000 PLD between
the two DSPs.

The designed hardware is described in chapter 3.
Chapter 4 covers one of the two main objectives:

the VHDL design.
Chapter 5 describes the boot process and the boot

loader file, and Chapter 6 provides details about
the software boot loader.

Chapters 4 and 6 are independent of each other;
it is not necessary to know the internal function
of the PLD to use/understand the software boot
loader. The boot loader is written in generic C

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2. Overview of Host Port

2.1. Pins

Table 1 lists the pins that make up the Host Port.
16 multiplexed address and data lines are

available for the HPI:

The source code for software boot
loader and VHDL design are not
included in this document; they may be
downloaded from the Analog Devices
Web site.

HAD[15..0].

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The default setting for the bus width after reset is
8 bits for data cycles, but the design described in
this note uses all 16 lines.

Address cycles always use the full bus

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Two memory select lines provide the Host access
to internal and external memory (
I/O space (

The
Address Latch Enable (ALE) mode or Address
Cycle Control (ACC) mode. For ACC mode (as
used in this application), it must be driven high
during reset.

width (and
configured for 8 bits.

~HCIOMS).

HALE pin can be configured to function in

Pin Name Input/Output Pin Function

HAD[15..0] I/O/T Host Port Multiplexed Address and Data Bus
HA16 I Host Port Most Significant Address Line

~HCIOMS I Host Port I/O Space Select
~HCMS I Host Port Memory Select
HALE I Host Port Address Latch Strobe
~HWR I Host Port Write Strobe
~HRD I Host Port Read Strobe
HACK I/O Host Port Acknowledge
HACK_P I Host Port Acknowledge Polarity

HA16), even if the bus is

~HCMS) and

The polarity of the strobe signals

~HRD must also be configured. They are driven

high during reset, setting their active state low.

HACK and HACK_P determine the functionality

and polarity of the acknowledge signal during
reset.
Acknowledge mode (ACK) or Ready mode
(READY).
driven low during reset, setting up
ACK mode, active high.

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HACK can be configured to act either in

HACK_P is driven high, and HACK is

HALE, ~HWR, ~HRD, HACK, and
HACK_P have to be driven during, and

for 10 peripheral clock cycles (HCLK)
after reset.

~HWR and

HACK in

Table 1. Host Port pins

2.2. Access Modes

Two modes provide the Host access to memory
and I/O space of the ADSP-2191 DSP: Direct
mode and DMA mode.

The Host boot loader (described in Chapter 6)
uses DMA transfers to write the content of the
loader file into the Target memory. Host Port
DMA behaves like any other DMA channel on
the ADSP-2191 DSP: the transfer direction can
be configured, Autobuffer and Descriptor mode
are available, and an interrupt can be generated
after completion of the data transfer. The
software boot loader uses Autobuffer DMA for
the boot process because it is suitable for
transferring large blocks of data without having

ADSP-2191 DSP Host Port Booting (EE-226) Page 2 of 25

to transmit the address for every word. The
disadvantage of DMA mode is that it has to be
configured, which requires several cycles. For
example, it takes five write accesses in Direct
mode from the Host to set up one Autobuffer
DMA transfer. If only one or two memory
locations need to be written to or read from,
Direct mode is more suitable. The Host boot
loader includes examples of read and write
accesses to internal memory and I/O space in
Direct mode, for which logic analyzer
screenshots are shown in Chapter 7.

Host Port DMA mode is available only

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for accesses to memory, not I/O space.

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2.3. Host Port Registers

Several I/O configuration registers, as listed in
Table 2, are dedicated to the Host Port.

The Host Port Configuration Register, HPCR,
must be set up before any other access. It
contains configuration bits for various access
parameters, and some status bits, reflecting the
functionality of
signals sensed during reset.

For the chosen configuration (modes ACK and
ACC, low active strobe signals), the reset value
of HPCR is 0x0F00. To enable 16-bit bus width,
the value 0x0F01 is written into this register by
the Host after the Target has come out of reset.

Register Name

HACK and the polarity of control

DSP Address

Host Address

Before a read or write is done in Direct mode, the
data type (16- or 24-bit) and the memory page
should be set to the correct values by accessing
the Host Port Direct Page Register, HPPR.

Registers starting with HOSTD_ are used to
configure Host Port DMA transfers. Every DMA
transfer starts with the configuration of the
appropriate I/O registers (HOSTD_XXX); after
that, only data are transmitted or received – no
addresses need be written.

The access to I/O space registers is not

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affected by the setting of HPPR.

Register Function

IOPG:Address

HPCR 0x07:0x001 0x1C01 Host Port Configuration
HPPR 0x07:0x002 0x1C02 Host Port Direct Page
HPDER 0x07:0x003 0x1C03 Host Port DMA Error
HPSMPHA 0x07:0x0FC 0x1CFC Host Port Semaphore A
HPSMPHB 0x07:0x0FD 0x1CFD Host Port Semaphore B
HPSMPHC 0x07:0x0FE 0x1CFE Host Port Semaphore C
HPSMPHD 0x07:0x0FF 0x1CFF Host Port Semaphore D
HOSTD_PTR 0x07:0x100 0x1D00 Host Port DMA Pointer
HOSTD_CFG 0x07:0x101 0x1D01 Host Port DMA Configuration
HOSTD_SRP 0x07:0x102 0x1D02 Host Port DMA Start Page
HOSTD_SRA 0x07:0x103 0x1D03 Host Port DMA Start Address
HOSTD_CNT 0x07:0x104 0x1D04 Host Port DMA Word Count
HOSTD_CP 0x07:0x105 0x1D05 Host Port DMA Chain Pointer
HOSTD_CPR 0x07:0x106 0x1D06 Host Port DMA Chain Pointer
HOSTD_IRQ 0x07:0x107 0x1D07 Host Port DMA Interrupt

Table 2. Host Port configuration registers

1

These addresses are not identical to the values listed in Appendix B, Table B-1, in [1], since the required address generation

is done in the PLD (left shift of actual address by 1 bit for I/O access).

ADSP-2191 DSP Host Port Booting (EE-226) Page 3 of 25

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3. Hardware

The hardware used as the test platform consists
of a Host (ADSP-2191 DSP), a Target (ADSP­2191 DSP), and an Altera PLD (see Figure 1).
The Host can be any kind of processor,
microcontroller, or other programmable device.
An ADSP-2191 DSP was chosen because it is
assumed that the reader is familiar with the
architecture of this DSP, so that there should be
no difficulty understanding the system on the
Host side.

Two ADSP-2191 EZ-KIT Lite™ boards serve as
platforms for the Host and Target. The PLD

Host

(ADSP-2191)

External

Port

PLD

(Altera)

resides on a customized PCB. Figure 2 shows the
connection of the three boards; the schematic
diagram can be found in Appendix A.

The External Port on the Host is connected to the
Host Port on the Target through a PLD. Besides
the two interfaces, two additional signals are
required: an error signal from the PLD to the
Host, and a reset signal controlled by the Host.
This reset signal is connected to the voltage
supervisor circuit on the Target board and the
PLD. It allows the simultaneous reset of Target
DSP and PLD.

Host

Port

Target

(ADSP-2191)

Figure 1. System overview

The loader file, which is transferred to the Target
by the software boot loader, is stored in the on­board Flash on the Host EZ-KIT Lite.

Two sets of jumpers, which are not shown in
Figure 2, configure the system:

Jumper Position Function

J1 1-2* Mode for HACK; default is ACK

2-3 (see ADSP-2191 HRM for details)

J2 1-2* ~HRD is low active

2-3 ~HRD is high active

J3 1-2* ~HWR is low active

2-3 ~HWR is high active

J4 1-2 HACK is low active

2-3* HACK is high active

J5 1-2* HALE acts in ACC mode

2-3 HALE acts in HALE mode

* default setting

On the Target EZ-KIT Lite board, Pins

OPMODE, BMODE0 and BMODE1 have to be

set to Host booting, as described in [4].

Table 3. Jumper settings for Host Port configuration

ADSP-2191 DSP Host Port Booting (EE-226) Page 4 of 25

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Five jumpers on the customized PCB configure
the Host Port, overriding the settings on the
Target board (smaller resistor values). Do not
change the default values as shown in Table 3,

ADSP-2191 EZ-KIT Lite

PF1

Host

ADSP-2191

PF0

Flash

AT49BV040

Error

Address

Data

Control

Reset

1

4

16

4 7

since the PLD is designed to interact with the
Host Port in modes ACK and ACC, with low
active strobe signals.

PLD

EPM7256AETC

Clock

50 MHz

1

17

1

HAD

Control

Reset

Reset

ADSP-2191 EZ-KIT LiteCustom PCB

Target

ADSP-2191

µP

Supervisor

Figure 2. Hardware block diagram

4. VHDL Design

4.1. Overview

Since the External Port on the Host and Host
Port on the Target are not completely compatible
with each other, additional logic is required. This
logic is implemented in an Altera MAX7000
PLD, which resides between Host and Target on
a customized PCB.

The design generates timing for Host Port modes
ACC and ACK.

The main building blocks of the VHDL design is
shown in Figure 3. A graphical representation of
the top-level design together with the pin
assignment is found in Appendix B.

All control signals of External Port and Host Port
are completely separated in the PLD. An access
from the Host is detected in block “External Port
interface logic”. This block will then signal to
the “Host Port interface logic” block that an
access to the Host Port has been requested.

No information is stored inside the PLD, so the
Host is held off until the access to the Target is
finished (flow-through system). This requires the
Host to wait for the PLD to acknowledge that the
access can be finished.

The data are transferred through block “Data
Path”, in which drivers are enabled/disabled
according to the direction of the data flow (read
or write).

The “Watchdog” block contains logic for error
detection.

ADSP-2191 DSP Host Port Booting (EE-226) Page 5 of 25

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To External

Port on Host

Data

16

4Address

Control

Reset

Error

Clock

Figure 3. PLD block diagram

4.2. Interface between Host Software and PLD

External Port

interface logic

Data Path

Watchdog

Data between the Host and the Target are
transmitted via a bi-directional, multiplexed
address and data bus. On the Host side, the data
bus of the External Port is used for this purpose.

All accesses to the Host Port can be considered
to be a (sequential) combination of address
cycles and/or data cycles. Information that
specifies whether an access is an address cycle or
data cycle, plus additional parameters are
encoded in four External Port address lines. This
method creates a “virtual address space”, which
means that there are no physical memory
locations implemented in the PLD. Rather, these
four address lines select the appropriate type of
access.

In summary, the virtual address space on the
Host side transfers information to help the PLD:

• Determine whether an address cycle or data

cycle is to be performed (addresses need to
be shifted on multiplexed address and data
bus due to byte addressing on Host Port)

• Select correct memory type for address

shifting (DM addresses need to be shifted left

To Host Port

on Target

Address

17

& Data

Control

Host Port

interface logic

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by 1 bit; PM addresses need to be shifted left
by 2 bits)

• Assert appropriate chip select (

~HCIOMS)

~HCMS or

Table 4 shows the types of accesses that can be
performed through the PLD, and the addresses
that have to be used to trigger the access.

For example, a write to location 4 in the PLD
triggers a Host Port Address cycle, with the data
on the External Port data bus transferred to bus

HAD, shifted left by 1 bit, and with ~HCIOMS

asserted.
A read from location 1, on the other hand, starts

a Host Port Data read cycle, with

~HCMS

asserted, and no shifting of data on the
multiplexed bus.

One address location inside the PLD is dedicated
to a special purpose: A read from address 8
returns the revision number of the VHDL design.

Some addresses in the PLD are reserved, and
some combinations of access type and data
direction are invalid. A read from address 0, for
example, is not a valid Host Port access, since an

ADSP-2191 DSP Host Port Booting (EE-226) Page 6 of 25

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address read cycle is not specified for the Host
Port. When the Host performs an invalid access,
the PLD does not signal an error, but simply

PLD Address Access type Write / Read

0 DM Address W / ­1 DM Data W / R

2 PM Address W / ­3 PM Data W / R
4 IO Address W / ­5 IO Data W / R

6 - 7 Reserved - / -

8 PLD Version - / R

9 - 15 Reserved - / -

Table 4. Virtual address space for performing different HPI accesses through the PLD

The External Port address lines are not

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4.3. External Port Interface Logic

When the Host starts a read or write access to the
PLD, the External Port interface logic detects
this, and signals to the Host Port interface logic
to start a Host Port access. Some logic gates are
used to assert a signal when the Host begins an
access. This signal, in turn, starts a state machine
(Figure 4) that simply waits until one of the
following conditions is met:

• Host Port state machine finishes cycle

• Error signalled from Watchdog

• Invalid access signalled from Data Path

After that,
the end of the access.

used to transmit addresses to the PLD,
but carry additional information required
for the Host Port access.

ACK is asserted to the Host, marking

acknowledges the access. The data on the
External Port are not valid in such a case (PLD
bus drivers are tri-stated).

4.4. Host Port Interface Logic

This section describes the “core” of the VHDL
design: The logic required for driving the Host
Port control signals. It consists mainly of a state
machine used to generate the timing, as given in
[2]. The state diagram is given in Figure 5 on the
following page.

Access to the Host Port in Direct mode consists
of an address cycle and one or more data cycles.
In DMA mode, only data cycles are performed.
One complete execution of the state machine in
Figure 5 triggers one address cycle or one data
cycle, depending on the input values.

A complete Host Port access can be “assembled”
by executing the Host Port state machine several
times with the appropriate parameters.

For example, access to 24-bit Program Memory
with a 16-bit bus width in Direct Mode requires
one address cycle followed by two data cycles.
The state machine would be started three times in
this case: the first time configured for address
cycle, then two times with the input parameters
set to data cycle.

ADSP-2191 DSP Host Port Booting (EE-226) Page 7 of 25

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Reset

ACK_ASSERTED

ACK = 1

Figure 4. External Port state machine

i_start = 0

IDLE

ACK = 0

i_start

0: Start signal deas serted
1: Start signal as serted

i_finish_ep_access

0: Signal deasserted
1: Signal asserted

i_start = 1

WAIT_HP_ACCESS

_

i_finish_ep_access = 0i_finish_ep_access = 1

ADSP-2191 DSP Host Port Booting (EE-226) Page 8 of 25