Analog Devices EE220v01 Application Notes

Engineer-to-Engineer Note EE-220

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Technical notes on using Analog Devices DSPs, processors and development tools

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Using External Memory with ADSP-2126x SHARC® DSPs

Contributed by Brian M. and Matt W. Rev 1 – January 12, 2004

Introduction

The addressing functionality of the Parallel Port
on the ADSP-2126x SHARC® family of DSPs
has changed greatly when compared to the other
SHARC family DSPs that have an External Port.
This EE-Note describes external memory
addressing and how to use the VisualDSP++®
development tools to handle address translation
and data reorganization via the LDF PACKING
command (for VisualDSP++ 3.0 with Service
Pack 1). A macro that helps the Symbol Manager
convert logical and physical addresses is also
explained.

device, the core only needs to specify the single
32-bit logical address; then, the External Port
automatically calculates the four physical
addresses and performs the four fetches needed
to acquire the entire 32-bit word.

In contrast, the ADSP-2126x family of DSPs
uses a Parallel Port that does not have the
address translation built-in, although it will sill
perform the data packing (e.g., building a 32-bit
word from four 8-bit words). The Parallel Port
operates on physical addresses only. Note that
each external address in the memory map does
not

External Memory Addressing

One significant difference between the Parallel
Port and the previous External Port is that the
Parallel Port no longer accepts logical addresses
from the core, instead requiring the physical
word address to be supplied to the DMA engine.
This change requires special considerations by
software developers wishing to use external
memory on the ADSP-2126x family.

Previous SHARC DSPs have always accessed
the external memory using logical (32-bit)
addressing (i.e., each external address in the
memory map corresponds to exactly one
complete word of data). The translation of each

Logical Address

0x200000 0x200000 Word0 Byte1

0x200001 Word0 Byte2

0x200002 Word0 Byte3

0x200003 Word0 Byte4

0x200001 0x200004 Word1 Byte1

0x200005 Word1 Byte2

0x200006 Word1 Byte3

0x200007 Word1 Byte4

0x200100 0x200400 Word256 Byte1

0x200401 Word256 Byte2

Physical (Byte)

Address

...

...

Data

logical address into the four corresponding
physical addresses is handled transparently by
the hardware of the port. For example, if a 32-bit

Table 1. ADSP-21161 logical-to-physical address
translation by the external port.

word is fetched from an external byte-wide

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correspond to a complete word of data. Instead,
each logical (32-bit) word of data consumes
multiple address in the external range of the
memory map.

To illustrate this fact, compare the handling of
two consecutive 32-bit fetches on a ADSP-21161
SHARC DSP versus the same transaction on a
ADSP-21262 SHARC DSP. Table 1 shows the
corresponding physical addresses generated by
the External Port based on the logical addresses
from the which data is fetched. (Again, this
assumes 32/8 bit packing). Note that consecutive
logical addresses correspond to separate words
externally.

Table 2 highlights the difference in operation on
the ADSP-2126x family Parallel Port and
illustrates the lack of address translation between
the logical (32-bit) address and the physical (8­bit in this case) address.

Logical Address

0x200000 0x200000 Word0 Byte1

0x200001 Word0 Byte2

0x200002 Word0 Byte3

0x200003 Word0 Byte4

0x200001 0x200001 Word0 Byte2

0x200002 Word0 Byte3

0x200003 Word0 Byte4

0x200004 Word1 Byte1

0x200100 0x200100 Word32 Byte1

0x200101 Word32 Byte2

Table 2. ADSP-2126x Logical to Physical address
mapping (not compatible with previous SHARC
addressing schemes).

Physical (Byte)

Address

...

...

Data

Fetching from consecutive logical addresses does
not properly access unique data in external
memory. The rest of this EE-note describes how
to deal with this new functionality in software.

The second change from previous SHARC DSPs
is that, in the ADSP-2126x family, it is necessary
to always use the External Index register (EIPP)
to access external memory; there is no direct core
access to external memory via the Data Address
Generators. The address in the EIPP register is
supplied directly to the AD pins in the address
cycle. (This ‘buffered-access’ architecture
effectively decouples the core from the Parallel
Port, enabling the core clock speed to be
doubled. It also allows the ADSP-2126x family
of DSPs to use fewer pins, significantly reducing
both DSP and system cost.)

Organizing Data for placement in
External Memory using the LDF

The first problem that the new Parallel Port
introduces is that it uses a physical word address,
rather than a logical word address. Because of
this, it is necessary to perform address translation
and data reorganization in software. In
VisualDSP++ 3.0 SP1, the LDF must include the
PACKING() command, enabling the linker to
generate addresses that the Parallel Port can use.
Listings 1 and 2 provide example packing
commands for a variety of possible cases when
packing into 8-bit memory and 16-bit memory,
respectively. The only case where a
PACKING() command would not be required is
when initializing 16-bit external memory with
16-bit data. In this one case, it so happens that
the logical addresses directly match the physical
addresses, so no translation/packing is needed.

The PACKING() command directs the linker to
reformat the data as it is placed into the DXE.
For a memory section of TYPE(DM RAM), each
memory address holds five bytes in the DXE
(regardless of whether the data is 40-, 32-, or 16­bit logical data). For a TYPE(PM RAM) section,
each address corresponds to six bytes (regardless
of whether the data is 48-, 40-, 32-, or 16-bit
logical data). Before each word of data is
assigned an address by the linker, the
PACKING() command reorganizes the order of

Using External Memory with ADSP-2126x SHARC® DSPs (EE-220) Page 2 of 10

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the bytes in the DXE, and can add null bytes to
the DXE, if needed.

The loader and debugging tools (simulator and
emulator) expect the external memory sections
DXE to be in a certain format to initialize
external memory correctly.

For example, when a DM (5-byte) word is
mapped into an address in a memory segment
that is WIDTH(8), only the data in the fourth
most significant byte is placed at that external
address.

Similarly, for DM (5-byte) words mapped to a
memory segment that is WIDTH(16), only the
data in the third and fourth most significant bytes
are placed into the external address. (See Listings
1 and 2 for examples.)

This means that if 32-bit data is mapped into
external 8-bit memory, 3 bytes of data are
uninitialized. To remedy this, translate the 32-bit
word into four words, placing the valid data into

th

the 4

most significant byte of each new word, as
shown in Table 3. (Refer to the Parallel Port
chapter of [1] ADSP-2126x SHARC DSP
Peripherals Manual for information about how
data is packed in external memory.)

The DSP’s internal memory is organized as four
16-bit-wide by 64K-deep columns which are
addressable as a variety of word sizes:

• 64-bit long word data (four columns)

• 48-bit instruction words or 40-bit extended-

precision normal word data (3 columns)

• 32-bit normal word data (2 columns)

• 16-bit short word data (1 column)

The four-columned memory architecture of the
ADSP-2126x family allows each location in
internal memory to be accessed in any of the
above formats, depending on the address used.
However, every access to the Parallel Port is 32­bits (accesses are to 32-bit normal word space,
and counted in number of 32-bit words).

When transferring words that are not 32-bits
long, the External Count register must contain a
whole number of 32-bit words (i.e. it must be a
multiple of four). If it is not, the remainder bytes
are not transferred as expected. It is also
necessary to translate the internal address to 32­bit word space.

External Width

WIDTH(8)

WIDTH(16)

Table 3. Packing in the DXE file for external memory.

Using External Memory with ADSP-2126x SHARC® DSPs (EE-220) Page 3 of 10

Corresponding
Address

0x01000000 0x0000001100 0x000000110000 0x44332211
0x01000001 0x0000002200 0x000000220000
0x01000002 0x0000003300 0x000000330000
0x01000003 0x0000004400 0x000000440000

0x02000000 0x0000112200 0x000011220000 0x33441122
0x02000001 0x0000334400 0x000033440000

DM Packed for
External Memory

PM Packed for
External Memory

32-bit Word
Transferred by
the DSP