Analog Devices ee165 Application Notes
Engineer To Engineer Note EE-165
Technical Notes on using Analog Devices' DSP components and development tools
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The ADSP-2116x On-chip Sync Burst Controller
Contributed by R.Hoffmann April 30, 2002
When using a DSP to address SBSRAM, additional hardware will be needed to handle the synchronous
addressing mode. The ADSP-2116x family members ADSP-21160 and ADSP-21161 use a hardware
intensive solution, an on-chip Sync Burst Controller.
Contact our technical support by phone: (800) ANALOG-D or e-mail: dsp.support@analog.com
Or visit ou r online resources http://www.analog.com/dsp
and http://www.analog.com/dsp/EZAnswers
Introduction
The signal chain is shown for external memories and multiprocessing. Furthermore, different SBSRAM
architectures are introduced. Next, the controller’s characteristics are explored. Finally, different access
modes demonstrate the performance for SISD and SIMD. Refer also to “EE-148: Introduction to
Multiprocessor Systems using VisualDSP++.”
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furnished by Analog Devices Applications and Development Tools Engineers is believed to be accurate and reliable, however no responsibility is assumed by Ana log Devices
regarding the technical accuracy and topicality of the content provided in all Analog Devices’ Engineer-to-Engineer Notes.
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1 – ADSP-2116X MULTIPROCESSING SIGNAL CHAIN................................................................. 5
2 – ADSP-2116X SBSRAM SIGNAL CHAIN........................................................................................ 6
3 – EXTERNAL PORT INTERFACE.................................................................................................... 6
3.1 – P
IN DESCRIPTION ADSP-21160........................................................................................................ 6
3.2 – PIN DESCRIPTION ADSP-21161........................................................................................................ 7
3.3 – COMMAND TRUTH TABLES............................................................................................................... 8
ADSP-21160............................................................................................................................................... 8
ADSP-21161............................................................................................................................................... 8
ETUP AND HOLD TIMES.............................................................................................................................. 9
S
3.4 – CLOCK DERIVATION .........................................................................................................................9
ADSP-21160............................................................................................................................................... 9
ADSP-21161............................................................................................................................................. 10
4 – SBSRAM TECHNOLOGY.............................................................................................................. 10
4.1 – SBSRAM A
RCHITECTURES............................................................................................................ 11
COMMAND UNIT ........................................................................................................................................ 11
URST UNIT............................................................................................................................................... 11
B
REGISTER UNITS ........................................................................................................................................ 11
4.2 – S
TANDARD SBSRAM...................................................................................................................... 11
FLOW THROUGH ........................................................................................................................................ 11
IPELINED .................................................................................................................................................. 11
P
4.3 – Z
ERO BUS TURNAROUND SBSRAM............................................................................................... 13
FLOW THROUGH ........................................................................................................................................ 13
IPELINED .................................................................................................................................................. 13
P
4.4 – PIN DESCRIPTION SBSRAM........................................................................................................... 14
4.5 – M
4.6 - SRAM
EMORY ORGANIZATIONS............................................................................................................. 15
VS. SBSRAM....................................................................................................................... 15
5 – SYNC BURST CONTROLLER CHARACTERISTICS.............................................................. 15
5.1 – MULTIPROCESSING MEMORY SPACE............................................................................................. 15
5.2 – C
5.3 – DMA T
B
B
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 2 of 43
ORE TRANSFERS............................................................................................................................ 16
RANSFERS............................................................................................................................ 16
URST ENABLE......................................................................................................................................... 16
URST LENGTH......................................................................................................................................... 17
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5.4 – DESELECT CYCLE............................................................................................................................ 17
5.5 – ADSP-21160 EXTERNAL PORT ADDRESS MAPPING...................................................................... 17
32-BIT DATA TRANSFERS........................................................................................................................... 17
40-BIT DATA TRANSFERS........................................................................................................................... 17
48-BIT OPCODE FETCHES ........................................................................................................................... 18
8-
BIT PROM/FLASH TRANSFERS............................................................................................................. 18
64-BIT MEMORY ........................................................................................................................................ 18
BIT MEMORY ..................................................................................................................................... 18
8/32-
5.6 – ADSP-21161 EXTERNAL PORT ADDRESS MAPPING...................................................................... 18
32-BIT DATA TRANSFERS........................................................................................................................... 19
40-BIT DATA TRANSFERS........................................................................................................................... 19
48-BIT OPCODE FETCHES ........................................................................................................................... 19
8-BIT PROM/FLASH TRANSFERS............................................................................................................. 19
6 – PROGRAMMING THE SYNC BURST CONTROLLER........................................................... 19
6.1 – A
CCESS MODE................................................................................................................................. 19
6.2 – WAIT STATE MODE......................................................................................................................... 20
6.3 – BURST MODE................................................................................................................................... 20
6.4 – BURST SETTING OVERVIEW............................................................................................................20
6.5 – EXAMPLE ......................................................................................................................................... 20
7 – SYNC BURST INTERFACE AFTER RESET.............................................................................. 21
8 – SINGLE WORD TRANSFERS.......................................................................................................21
8.1 – HOST TO DSP ..................................................................................................................................22
8.2 – HOST TO SBSRAM......................................................................................................................... 22
9 – DMA TRANSFERS.......................................................................................................................... 22
9.1 – DSP
TO SBSRAM........................................................................................................................... 22
MASTER MODE.......................................................................................................................................... 22
ACED MASTER MODE............................................................................................................................... 23
P
9.2 – HOST TO DSP ..................................................................................................................................23
HANDSHAKE MODE ................................................................................................................................... 23
SLAVE MODE............................................................................................................................................. 23
9.3 – HOST TO SBSRAM......................................................................................................................... 24
EXTERNAL HANDSHAKE MODE.................................................................................................................. 24
10 –ADSP-2106X VS. ADSP-2116X MMS TIMING........................................................................... 24
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 3 of 43
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10.1 – WAIT STATES ................................................................................................................................24
10.2 – READS ............................................................................................................................................ 24
10.3 – WRITES.......................................................................................................................................... 24
11 – ADSP-21160 CODE EXECUTION FROM SBSRAM................................................................ 25
12 – MEMORY ACCESS TYPES......................................................................................................... 26
12.1 – I
NTERNAL MEMORY OF ADSP-2116X.......................................................................................... 26
NORMAL WORD SIMD, EXPLICIT EVEN ADDRESS...................................................................................... 26
ORMAL WORD SIMD, EXPLICIT ODD ADDRESS........................................................................................ 26
N
LONG WORD, EXPLICIT EVEN ADDRESS...................................................................................................... 26
LONG WORD , EXPLICIT ODD ADDRESS....................................................................................................... 27
FORCED LONG WORD, EXPLICIT EVEN ADDRESS........................................................................................ 27
FORCED LONG WORD , EXPLICIT ODD ADDRESS......................................................................................... 27
12.2 – EXTERNAL MEMORY OF ADSP-21160......................................................................................... 27
NORMAL WORD SIMD, EXPLICIT EVEN ADDRESS...................................................................................... 27
N
ORMAL WORD SIMD, EXPLICIT ODD ADDRESS........................................................................................ 27
FORCED LONG WORD, EXPLICIT EVEN ADDRESS........................................................................................ 28
FORCED LONG WORD, EXPLICIT ODD ADDRESS.......................................................................................... 28
12.3 – EXTERNAL MEMORY OF ADSP-21161......................................................................................... 28
12.4 – M
EMORY ACCESS TYPES SUMMARY ............................................................................................ 28
13 – OPTIMIZING THE PERFORMANCE....................................................................................... 29
13.1 – T
HROUGHPUT FOR READS............................................................................................................. 29
13.2 – THROUGHPUT FOR WRITES .......................................................................................................... 29
13.3 – RULES FOR BETTER PERFORMANCE.............................................................................................. 29
14 – EXAMPLES FOR CORE/IOP TRANSFERS TO MMS/SBSRAM.......................................... 29
14.1 – SISD C
14.2 – SISD IOP R
14.3 – SIMD C
14.4 – SIMD IOP B
14.5 – SIMD C
ORE READS WITHOUT INTERRUPTION ............................................................................. 30
EADS WITHOUT INTERRUPTION................................................................................ 31
ORE/IOP READS WITHOUT INTERRUPTION....................................................................32
URST READS............................................................................................................. 33
ORE READS WITH MINIMUM INTERRUPTION.................................................................. 34
14.6 – SISD CORE WRITES WITHOUT INTERRUPTION ...........................................................................35
14.7 – SIMD C
14.8 – SIMD C
14.9 – SIMD C
ORE/IOP WRITES WITHOUT INTERRUPTION .................................................................36
ORE WRITES WITH MINIMUM INTERRUPTION................................................................ 37
ORE MINIMUM WRITE TO READ INTERVAL................................................................... 38
14.10 – SIMD CORE MINIMUM READ TO WRITE INTERVAL................................................................. 39
14.11 – 40
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 4 of 43
BIT TRANSFERS....................................................................................................................... 40
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14.12 – DMA CHAINING.......................................................................................................................... 41
14.13 – HOST ACCESS DURING BURST READS ......................................................................................... 42
LINKS AND REFERENCES................................................................................................................. 42
1 – ADSP-2116x Multiprocessing Signal Chain
Figure 1 illustrates the signal chain between two ADSP-21160s.
The 4 blocks for the signal flow are considered:
• Master (core, IOP, address buffer)
• Sync burst controller as encoder (master)
• Sync burst controller as decoder (slave)
• Memory (slave)
The controller works bi-directionally generating and decoding commands. CLKIN is the reference signal
and it is used for the synchronous operation. The Master’s internal strobes are converted to the sync burst
protocol. On the slave side, the commands are registered, decoded and transferred to the slave’s memory.
In the multiprocessor memory space (MMS), the slave’s ACK pin is used to control these transfers.
Moreover, the burst improves the DMA throughput for reads.
Figure 1: Signal chain: Interprocessor Transfer
AD SP-21160 M aster
int. R D
int. W R
int. A CK
core
~RDH
~RDL
d
n
e
~W RH
a
c
a
~W R L
m
f
r
m
e
t
o
n
I
C
BRST
ACK
~RDH
~RDL
~W RH
AD SP-21160 Slave
~W RL
BRST
ACK
t
s
c
i
r
g
u
o
B
L
int. RD
int. W R
IO P
Address
bu ffer
D63:0
A19:0
Address
Map/
Latch
A22:0
A31:0 D63:0
Address
Map/
Latch
A1:0
(Bu rst)
memory
D63:0
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 5 of 43
2 – ADSP-2116x SBSRAM Signal Chain
Figure 2: Signal chain: ADSP-21160 to SBSRAM
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ADS P-21160 Master
int. RD
int. WR
int. A CK
core
A19:0
Address
buffer
IO P
D63:0
d
n
e
c
a
ma
f
r
m
e
t
o
n
I
C
~MS x
Address
Map/
Latch
~RDH
~RDL
~W RH
~W RL
BRST
A17:1
CLKIN
A31:0 D63:0
CLK
~OEL
~OEH
~GW H
~GW L
~ADSC1
~CE
A17:0
DQ63:0
SBSRAM
256k x 64
Figure 2 illustrates the signal chain between the ADSP-2116x, and an external SBSRAM.
The 3 parts for the signal flow to be considered are:
• Master (core, IOP, address buffer)
• Sync burst controller as encoder (master)
• SBSRAM
The signal chain is basically the same as for MMS. The main difference is that SBSRAM is a passive
device and never will be a bus master. The ADSP-2116x bus master writing to MMS or external memory
uses the same synchronous timing.
3 – External Port Interface
3.1 – Pin Description ADSP-21160
Pin State Description
CLKIN (I) clock input
~MSx (O/T) bank memory select line, chip enable
~RDL (I/O/T) initiates a read from an even address
~RDH (I/O/T) initiates a read from an odd address
~WRL (I/O/T) initiates a write to an even address
~WRH (I/O/T) initiates a read to an odd address
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 6 of 43
BRST (I/O/T) starts the burst counter
ACK (I/O/S) acknowledge, slave control
D[31:0] (I/O/T) data for even address lines
D[63:32] (I/O/T) data for odd address lines
A[31:0] (I/O/T) address lines
I=input, O=output, T=Hi-Z, S=synchronous
3.2 – Pin Description ADSP-21161
Pin State Description
XTAL (O) output for crystal
CLKIN (I) clock input
~MSx (I/O/T) bank memory select line, chip enable
~RD (I/O/T) initiates a read
~WR (I/O/T) initiates a write
BRST (I/O/T) starts the burst counter
ACK (I/O/S) acknowledge, slave control
D[47:16] (I/O/T) data
A[23:0] (I/O/T) address lines
I=input, O=output, T=Hi-Z, S=synchronous
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XTAL
On ADSP-21161, a crystal used in conjunction with the CLKIN pin can also generate the clock signal.
CLKIN
This pin is used to guarantee the SBSRAM’s synchronous operation. All addresses and commands are
latched on the positive edge of clock.
Bank Select (~MSx)
This pin is used to access the external device. It is used to sample the external address and command.
Provides address decoding and act as a chip selects for external memory mapped devices. For ADSP21160, the MSIZE bit in SYSCON defines the size for the 4 banks. For ADSP-21161, the bank sizes are
fixed, unbanked memory is not available.
ADSP-21160 Strobes (~RDx, ~WRx)
These pins are sampled to execute read or write operations. Since the ADSP-21160 is a full SIMD
machine, it uses two pairs of strobes for the external 2x32 bit data bus. The ~WRH and ~RDH are
decoded for odd addresses while ~RDL and ~WRL are decoded for even addresses.
ADSP-21161 Strobes (~RD, ~WR)
The ADSP-21161 uses the conventional ~WR and ~RD for the external 32 bit data. It’s internally a full
SIMD machine, but not externally.
Burst (BRST)
Burst feature is implemented to improve read performance. This line is asserted to start a bursting
operation. Burst operations are valid for DMA transfers only. If the burst feature is not needed, tie the pin
low. Partial data bus width transfers are not supported
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 7 of 43
.
Note: ADSP-21160 supports burst for 64bit data only.
Note: ADSP-21161 supports burst for 32bit data only.
Acknowledge (ACK)
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The ACK pin is used to extend external asynchronous and synchronous accesses
completion of an external access. In asynchronous mode, ACK is not sampled until the programmed
numbers of wait states have been counted. SBSRAM requires no slave control; ACK is tied high with an
internal pull-up resistance.
Following for synchronous mode:
2 cycles read: slave must assert ACK at least twice for each access (addresses/commands and data must be
acknowledged by the salve)
1 cycle write: ACK deasserted to extend the access by one cycle.
Used to extend the wait states by external devices.
Note: The ACK timing in MMS has changed between ADSP-2106x and ADSP-2116x family.
3.3 – Command Truth Tables
This section provides a table to get an overview of all commands provided by the Sync Burst controller.
These commands are handled automatically by the interface.
ADSP-21160
. It is used to hold off
Command Data Address ~MSx BRST ~RDH ~RDL ~WRH ~WRL
Read SISD 32-bit
Read SISD 32-bit
Read SIMD 64-bit All 0 0
Read Burst 64-bit All 0
Write SISD 32-bit
Write SISD 32-bit
Write SIMD 64-bit All 0 0 1 1
Write Burst 64-bit All 0
Deselect x x 1 x x x x x
ADSP-21161
Command Data Address ~MSx BRST ~RD ~WR
Read 32-bit All 0 0
Read Burst 32-bit All 0
Write 32-bit All 0 0 1
Write Burst 32-bit All 0
Even
Odd
Even
Odd
0 0 1
0 0
1 0 0
0 0 1 1 1
0 0 1 1
1
1 0
1
0
0 0
1 1
0
1
0
1 1 1
1
1
0
0
1 1
1 1
1 1
0
0 0
0 0
0
1
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 8 of 43
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Deselect x x 1 x x x
Setup and Hold Times
The synchronous operation uses the CLKIN as reference. Commands, addresses and data are latched at the
rising edge of CLKIN. The valid time margin around the rising edge is defined as setup time (time before
rising edge) and hold time (time after rising edge) to guarantee that both the controller encoder and
decoder are working reliably together. Signal’s- slew rates, propagation delays (PCB) and capacitive loads
(devices) influence these parameters and should be taken into consideration. The controller’s timing
characteristics are available in the ADSP-2116x datasheet.
3.4 – Clock Derivation
ADSP-21160
Figure 2a: External Port Clock Derivation ADSP-21160
External Port
Host
M u lt iproces s ing
SRAM, SBSRAM
PLL
core
clock
CLKIN
input
clock
Bus
master
CLKOUT
PLL
x2, x3, x4
CLK_CFG3:0
The clock source must be derived from an external oscillator for the ADSP-21160. The external port
interface (figure 2a) is internally connected with the CLKIN signal. The maximum speed for the external
port is 40 MHz for ADSP-21160M and 47,5 MHz for ADSP-21160N. The CORE:CLKIN ratio depends
only on the hardware pin settings CLK_CFG[3:0]. This ratio cannot be changed dynamically. The
CLKOUT pin is only driven during busmasterchip.
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 9 of 43
ADSP-21161
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Figure 2b: External Port Clock Derivation ADSP-21161
External Port
CLKIN
XTAL
Clock
Doubler
x1, x2
~CLKDBL
PLL
input
clock
Bus
master
CLKOUT
Host
M u lt iproces s ing
SRAM, SBSRAM
PLL
x2, x3, x4
CLK_CFG1:0
core
clock
SDRAM
x1, x1/2
SDCLK1:0
The clock source can be derived from an external oscillator or a crystal for the ADSP-21161. The external
port interface (figure 2b) is internally connected with the output of the clock double unit. The maximum
speed for the external port is 50 MHz for ADSP-21161N. The CORE:CLKIN ratio depends only on the
hardware pin settings CLK_CFG[1:0] and the ~CLKDBL pin. This ratio cannot be changed dynamically.
The maximum crystal speed is 25 MHz. With ~CLKDBL tied low, the external port speed is also 50 MHz.
Using a crystal does not allow the access to an SBSRAM. The CLKOUT pin is only driven during
busmasterchip. Additional, the SDRAM interface’s speed is depending on the core clock speed only.
4 – SBSRAM Technology
When synchronous memories use a pipelined architecture (registers for in- and output signals) they
produce additional performance gains. In a pipelined device, the internal memory array needs only to
present its data to an internal register to be latched rather than pushing the data off the chip to the rest of
the system. Because the array only sees the internal delays, it presents data to the latch faster than it would
if it had to drive it off chip. Further, once the latch captures the array’s data, the array can start preparing
for the next memory cycle while the latch drives the rest of the system.
The SBSRAM is basically an advanced architecture from the classical asynchronous SRAM. (like the
SDRAM from the DRAM) The design is static and requires typically 6 transistors to store 1 bit of
information. The interface’s control lines are sampled synchronously on the positive edge of the system
clock. Therefore, timing is self-timed internally. The memory vendors offer standard- and zero bus
turnaround architectures.
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 10 of 43
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4.1 – SBSRAM Architectures
The architecture can be described in 3 parts (figure 3):
Note: The partial (byte) writes capability, sleep- and suspend modes are not discussed; since they are not
supported by the ADSP-2116x DSPs.
Command Unit
Most of the control pins are registered with the rising edge of clock. These pins are grouped to device
select pins (~CE1, CE2, ~CE3). Another group is responsible for the burst logic (~ADSC, ~ADSP,
~ADV). The ~GW pin, sampled during CLK, controls the read and write operations.
Note: The ~OE pin is fully asynchronous and just used to enable the read output buffers.
Burst Unit
The input address latch plays an important role to support the burst counter. Firstly, the address is latched.
The Deassertion of ~ADSP or ~ADSC on the burst logic freezes the buffer’s input address clock (BCLK)
and clears the burst counter (CLR). The next addresses (linear or interleaved) are now internally
incremented. At the end of burst, ~ADSP or ~ADSC are asserted. Then, the input address is latched again.
Note: The ~ADV pin must be low during burst; otherwise the 2 bit counter does not count.
Note: The Mode (LBO) pin selects between linear and interleaved burst counting.
Register Units
The input- and output registers latch data on the rising edge of clock. The flow-through does not use an
output register like the pipelined architecture.
Note: The registers for address and data make the burst efficient.
4.2 – Standard SBSRAM
Micron Technology originally offered the Standard SBSRAM in 1996 for L2 cache applications. The
synchronous operation, which simplifies the design by shorter setup- and hold times, incorporates a burst
feature (2 bit burst counter) allowing a higher throughput during read operations. To offer these devices
over a large frequency bandwidth, subgroups are available like Pipelined- and Flow-through types (figure
4).
Flow Through
This partial pipelined architecture enables the read buffers and the data just flow through the output. Here
is a good compromise between speed and throughput < 66 MHz. The flow through type gives a
performance of 2-1-1-1 for a burst read.
Pipelined
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 11 of 43
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This architecture registers and enables the read buffers and the data flow through the output. This is used
to improve the performance for high-speed applications. Above 66 MHz, the pipelined devices offer a
clear advantage in terms of performance. For instance, at 100 MHz the pipelined version results in 3-1-1-1
in comparison to a flow through of 3-2-2-2. The pipeline technique helps to fetch, deliver, and capture
subsequent data.
Figure 3: Simplified SBSRAM Arc hit ec t ure 512k x 32 bit
CLK
~CE1
CE2
~CE3
~ADV
~ADSP
~ADSC
~GW
Command
and
Burst
Logic
GW,
CLR,
CLK,
BCLK
(byte write logic ignored)
flow-through version
does not use
registered output buffer
CLK, OE
Output
Buffer
DQ31:0
~OE
Mode
A18:2
A1:0
BCLK
Input
Address
Buffer
A16:0
CLK, GW
Input
Buffer
Address
Latch
Burst
Counter
A18:0
CLK,
Mode,
CLR
A1:0
Memory Core
(512k x 32bit)
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 12 of 43
CLK
~OE
~GW
ADDR
Data
Figure 4: Standard SBSRAM s, pipelined vs. flow through for random reads
e
p
i
P
Read operation requires 3
cycles between latching the
A1
A2A4 A5
Q1
Q2Q4 Q5
address and driving data
BL=4, performance 3-1-1-1
=
d
e
n
i
l
CLK
~OE
~GW
ADDR
Data
A1
2 cycles
3 cycles
Q1
A2A4 A5
Q2Q4 Q5
t
Read operation requires 2
cycles between latching the
address and driving data
BL=4, performance 2-1-1-1
F
h
w
o
l
o
r
u
g
h
Note: For lower frequency, the flow through is best choice, for higher frequency, the pipelined version is
dominant.
4.3 – Zero Bus Turnaround SBSRAM
The ZBT- or No Bus Latency (NoBL) SBSRAM was originally offered by Integrated Device Technology
in 1999. The basic difference between the standard- and ZBT types resides in the access mode. For
network applications, typically where back-to-back read to write are used. The ZBT was created in
response to applications, which require frequent bus turnarounds but could not afford the stall cycles
needed by standard types. The trick is that all read and write accesses have the same fixed offset between
address and data. So, no dead cycles between write ands reads (figure 5).
Flow Through
Just like standard SBSRAM (section 4.2)
Pipelined
Just like standard SBSRAM (section 4.2)
EE-165: The ADSP-2116x On-chip Sync Burst Controller Page 13 of 43
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