Analog Devices EE156 Application Notes

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a Engineer To Engineer Note EE-156

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Technical Notes on using Analog Devices’ DSP components and development tools

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The reverse happens for the receive direction.

Support for the H.100 protocol on the ADSP-2191

Data is accepted on the SPORT’s DR pin, and
serially transmitted to the Receive Shift register.
After a word is received and optional de­companding, the data is transferred to the

DSP Applications Group, March 2002 - Rev 0.1

The serial ports of the ADSP-2191 provide
support for the H.100 standard protocol. It is
also the International Telecommunication
Union’s recommendation for visual telephone
systems. This application note describes the
configurations necessary to be compatible with
the H.100 standard protocol.

The hardware used to test the support for this
protocol was the ADSP-2191 EZ-KIT Lite. The
software used was VisualDSP++ 2.0 with SP1.
The example code is included at the end of this
application note.

Receive Data register.

By writing to different control registers, the
serial clock frequency, data format and length,
multi-channel mode select, and other parameters
can be programmed on the SPORTs.

Direct Memory Access (DMA) is also supported
on each SPORT. The transmit channel enables
DMA transfers from memory to SPORT, while
the receive channel enables DMA transfers from
SPORT to memory.

Hardware Connections

Introduction

The ADSP-2191 has three independent,
synchronous serial ports (SPORT0, SPORT1,
and SPORT2). Each one of the serial ports
supports H.100. In this example, SPORT1 is
used. On each SPORT, data can be
simultaneously transferred in both transmit and
receive directions.

For each SPORT, data is transmitted from the
IO bus to the Transmit Data register. After
optional companding, data is transferred to the
Transmit Shift register. Here the bits are shifted
out serially on the SPORT’s DT pin.

On the ADSP-2191 EZ-KIT Lite, the SPORT0
and SPORT1 pins are brought out via the P6
and P7 SPORT connectors, respectively.

Using SPORT1 in this application, the DT1 and
DR1 pins are connected together to create a
loopback of the data transmitted and received.

Because H.100 applications always runs in
multi-channel mode, the TCLK1 and RCLK1
pins must be wired together. In multi-channel
mode, the TCLK pin is always an input. In this
application, RCLK1 is generated internally.

Copyright 2001, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ prod ucts or
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regarding the technical accuracy of the content provided in all Analog Devices’ Engineer-to-Engineer Notes.

Figure 1: SPORT pins on the EZ-KIT Lite

Software Configurations

The assembly program consists of 4 main
sections. These sections perform the tasks of
initializing SPORT1, configuring SPORT1 for
multi-channel mode operation, setting up
autobuffer-based DMA, and enabling SPORT1.

To be compatible with the H.100 standard
protocol, certain parameters must be set
accordingly to meet the H.100 specification.
The following is a list of these parameters:

• multi-channel mode enabled

• 8-bit words

• 1024 clock cycles per frame, 122 ns

wide, 125 us period frame sync

• transmit/receive frame sync required

• active low transmit/receive frame sync

• 8.192 MHz (+/- 2% bit clock)

• no frame delay between frame sync and

first data bit

• half clock cycle early frame sync

Initializing SPORT1

The transmit configuration register is initialized
to the Hex value of 0x1CF0. This value
configures SPORT1 to transmit 8-bit words,
generate a transmit frame sync for every data
word, and selects an active low transmit frame
sync. Note that the SPORT1 Transmit Enable
bit is not set here. This bit will be set last, after
all other configurations have been programmed.

SP1_TCR (0x03:0x000)

00011 1 0 0 1 1 1 1 00 0 0

Figure 2: Transmit Configuration Register

The receive configuration register is initialized
to the Hex value of 0x1EF2. This value
configures SPORT1 to receive 8-bit words,
generate a receive frame sync for every data
word, and selects an active low receive frame
sync. Note that the SPORT1 Receive Enable bit
is not set here. This bit will be set last, after all
other configurations have been programmed.

SP1_RCR (0x03:0x001)

00011 1 1 0 1 1 1 1 00 1 0

Figure 3: Receive Configuration Register

The SP1_TFSDIV and SP1_RFSDIV registers
hold the number of transmit and receive clock
cycles to count before generating a transmit or
receive frame sync. Both of these registers are
set to a Hex value of 0x03FF. This gives a
value of 1024 clock cycles per frame.

The serial clock frequency is calculated
according to the following equation:

SP1_CLK = HCLK________
2 * (SP1_SCKDIV +1)

EE-156 Page 2

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp