Analog Devices EE154 Application Notes

a Engineer To Engineer Note EE-154

R

O

Technical Notes on using Analog Devices’ DSP components and development tools

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ADSP-2191 Host Port Interface

LH/GO: Revised 2002-10-09

Introduction

This application note introduces the
reader to the ADSP-2191 Host Port Interface
(HPI). This port is an 8- or 16-Bit parallel,
address & data multiplexed, asynchronous slave
that gives a host processor read/write access to all
of the ADSP-2191 internal and external memory
and IO (except IO page 0) space. In addition to
memory access, the ADSP-2191 can be ‘booted’
by the host processor.

An application will be described showing
how to set up the bus for use with a host such as a
second ADSP-2191 EMI port.

Overview of HPI

The ADSP-2191 has 24 pins dedicated to the
HPI.

Pin Name I/O Function
HAD[15..0] I/O MUX’ed Address & Data
HA16 I MSB Address
HACKP I Acknowledge Polarity
HALE I Address Latch Enable
HRD I Read Strobe
HWR I Write Strobe
HACK I/O Access Ready Acknowledge
HCMS I Memory Space Chip Select
HCIOS I IO Space Chip Select

The HPI 16-bit address bus, HAD[15..0],
is multiplexed with the data bus. The data bus
width defaults to 8-bits using HAD[7..0] and is

configurable by the DSP after
Host, to 16-bits.

RESET , or by the

modes called Address Cycle Control (ACC) and
Address Latch Enable (ALE). These two address
modes are shown in the timing diagrams in
Appendix B. This offers flexibility with a
number of different host processors.

Figure 1 shows the HPI connections to a host
processor.

asynchronous and has two handshake modes;
ACKnowledge mode (ACK) and ReaDY mode
(RDY). This is also intended to facilitate
interconnection to alternative hosts.

ADSP-2191 memory and IO locations either by
directly specifying an address and then the data
(Direct Mode) or by Direct Memory Access
(DMA). In Direct Mode, a single HPI transaction
will consist of an ‘Address Phase’ followed by a
‘Data Phase’. Depending upon the size of the
data word, the data phase will consist of one, two,
three or four words being sent over the HPI bus.

The HPI offers two hardware address

ACK ACK

HOST

ADSP-2191

MS3

IOMS

D[15..0]

EXTERNAL MEM INTERFACE

Figure 1: HPI Bus Connections

A9

RD

W

A16

HI

LO

PF

8/16-BIT DATA BUS

ADDRESS MODE

PTION

ACC

ALE

ACK
RDY

ADSP-2191

HACK_P

HACK

HCMS
HCIOS
HALE

HRD

HWR

HAD[15..0]

HA16

RESET

The bus communication protocol is

The Host may write to, or read from,

SLAVE

HOST PORT INTERFACE

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In the case of DMA transfers, the internal
HPI DMA configuration registers will specify the
destination address and number of words so only
the data will need to be passed over the HPI bus.

HPI Configuration

1. Read/Write Strobe Pin Polarity

Several of the interface pins may be
programmed, at reset time, to be active high, or
low. This gives the user more flexibility when
interfacing to different host processors.

The active state of the
strobes is set to active low by holding the

respective pin high, when the
high, and holding the state high for a minimum of
10 clock periods following the leading edge of
Reset. This is the most common mode for most
host processors.

2. Acknowledge Signal Mode & Polarity

Because the internal buses of the ADSP­2191 are shared between internal memories, the
core and other peripherals, it is necessary for the
HPI to access these components using an
asynchronous protocol to signal, to the host,
when the selected location is available for a
transaction to proceed. There are two
asynchronous handshake protocols provided, a
direct acknowledge (ACK) and a continuous
ready acknowledge (RDY).

The following table records the different
modes.

Ext Pin State at RESET Acknowledge Handshake

HACK HACK_P Mode Active State

0 0 Ready Low
0 1 Ack High
1 0 Ack Low
1 1 Ready High

HWR and HRD

RESET pin goes

Selecting the mode of the host port
acknowledge (HACK) signal is done by
externally programming the logic level on the
HACK pin and the HACK_P pin when the

RESET pin goes inactive.

Note that the active state of the
acknowledge handshake signal (HACK) is set by

the state of the HACK_P pin at

RESET . If the

level on the HACK_P is high during RESET , the
HACK pin is active high and if the level is low,
HACK is active low. It is important that the
correct ‘active’ state for this pin is established
otherwise the host processor could ‘hang’ waiting
for an ACK signal that is never returned.

A typical method of programming these
pins is shown in figure 1. Notice that if the host

processor has control of the RESET pin, it can
program the state of the HPI protocol under
software control.

3. HPI Address Modes (ACC vs. ALE)

Selecting Address Cycle Control (ACC)
or Address Latch Enable (ALE), address modes,
is set by the logic level on the HALE pin, at

RESET . Please refer to the timing diagrams in

Appendix B to study the differences in the two
modes.

If the HALE pin is held low, by an off­chip pull-down resistor, or the host, during

RESET , the HALE pin will function in the ALE

mode. In this mode, the HPI latches the address
from the HAD[16..0] bus on the falling edge of
the HALE signal.

If the HALE pin is held high during reset,
it will function in the ACC. In this mode, a logic
zero on the HALE pin will cause a trailing edge
transition of the HWR write strobe to latch an
address into the HPI.

EE-154 Page 2

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp