Analog Devices EE148 Application Notes

Engineer To Engineer Note EE-148

Technical Notes on using Analog Devices' DSP components and development tools

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Introduction to SHARC® Multiprocessor Systems Using VisualDSP++™

Contributed by Maikel Kokaly-Bannourah April 01, 2003

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Introduction

The following Engineer-to-Engineer note
is intended to give an introduction to
Multiprocessor (MP) systems using
VisualDSP++™ The explanation will be based
on code example written for an MP system,
which consists of two ADSP-21160s (2 x ADSP­21160 EZ-Kit Boards) using VisualDSP++™

3.0.
SHARC® DSP Multiprocessor systems can be

configured in different ways:

• Several DSPs sharing the external bus

• Link Port point-to-point communication

• Use of the DSP’s serial ports in multi-channel
mode.

This note will discuss the implementation of an
MP system with the DSPs sharing the external
bus. For more details on other implementations
please refer to the ADSP-21160 SHARC® DSP
Hardware Reference Manual.

• MPMEMORY{}, it defines each processor’s
offset within multi-processor memory space
(MMS). The linker uses the offsets during
multiprocessor linking.

• MEMORY{}, it defines memory for all
processors present in the system.

• PROCESSOR{} and SECTIONS{} commands
define each processor and place program sections
for each processor’s output file, using the
memory definitions.

• SHARED MEMORY{}, it is needed when
external shared memory is used in the system.
This command identifies the output for the
shared memory items and generates Shared
Memory executable files (.SM) that reside in the
shared memory of the MP system.

The .SM file is generated from a source code file
(.ASM, .C or .CPP), which must be included
with the project files. This file contains the
variable definitions for the data that will be
placed in the external shared memory.

• LINK_AGAINST(), it resolves symbols within

Linker Description File (LDF) for MP Systems

The very first step in setting up an MP
system is to create a multiprocessor project using
the multiprocessing capabilities of the linker, and
an LDF file to describe the system.

The LDF describes the multiprocessor memory
offsets, shared memory, and each processor’s
memory. The following LDF commands must be
considered when writing an MP LDF:

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multiprocessor memory and directs the linker to
check specified executables (.DXEs and .SMs) to
resolve variables and labels that have not been
resolved locally. Whenever expressions or
variables are defined in the MMS (i.e. internal
memory of another processor in the system) the
LINK_AGAINST() command must be used in
the LDF.

Note: if .SM files and DXE files are included in
the command line, the .SM file must be placed

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first, followed by all other DXE’s, for the linker
to be able to resolve the variables correctly.

The maximum number of processors that can be
declared in one LDF is architecture-specific (i.e.
maximum of 6 ADSP-21160’s or 2 ADSP­21065L’s). Also note that a combination of
different DSPs with different architectures (i.e.
ADSP-21062 and ADSP-21160) in the same
LDF is not supported by VisualDSP++™.
However, a combination of DSPs from the same
architecture family (i.e. ADSP-2106x members
such as ADSP-21060, ADSP-21061 and ADSP-

21062) is supported although some memory

segments definitions considerations must be
made.

An MP LDF example where all the above
commands are used is shown in Figure 1. The
remainder of the LDF file is basically the same
as the default one provided with the tools (please
refer to the Linker and Utilities Manual for

ADSP-21xxx Family of DSPs or to EE-69
“Understanding and Using Linker Description
Files (LDFs)” for a general description on LDF

files). In the following example, a 2 ADSP­21160 and external shared memory system is
defined.

Figure 1 Excerpt from an MP LDF example

Introduction to SHARC® Multiprocessor Systems Using VisualDSP++™ (EE-148) Page 2 of 13

Now that the different sections of the LDF have
been discussed, we can examine the example
code that explores some of the MP capabilities of
the DSP.

For MP system hardware configuration please
refer to chapter 7 of ADSP-21160 SHARC®
DSP Hardware Reference. Also for information
on how to configure a cluster system using two
ADSP-21160 evaluation boards refer to the
ADSP-21160 EZ-KIT Lite User’s Guide.

Multiprocessor Memory Space (MMS)

The multiprocessor memory space is
divided into a number of address regions (this
number is processor specific) that correspond to
the internal memory of the DSPs in an MP
system. The ADSP-21160’s multiprocessor
memory space appears in Figure 2.

Note: programs may only use Normal word
addressing in multiprocessor memory space.
Other addressing schemes may corrupt valid
data.

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Figure 2 ADSP-21160 Multiprocessor Memory Space

Depending on the address range used, the
internal memory of a particular DSP in the
multiprocessor system will be accessed as a
source or destination. Writes to the Broadcast
region access the memory of all DSPs in the
multiprocessing system.

For instance, accessing a memory location within
the address range 0x300000 – 0x3FFFFF, is
equivalent to accessing the internal memory of
the DSP in the MP system with ID 3.

A DSP can also use the MMS to access its own
internal memory by accessing the corresponding
memory region. Note that in this case, the DSP
reads/writes from/to its own internal memory and
does not make an access on the external system
bus.

The following is an example from the code
where the MMS is used to access a memory
location of another DSP in the system. In this
case DSP with ID1 accesses the external port
buffer 1 (EPB1) of DSP with ID2:

Example 1:

r0=0x200006; dm(EI11)=r0;

In example 1, the MMS address for ID2 is
0x200000, which is then added to the address
corresponding to the EPB1 (0x6). Therefore, this
will result in a write access to ID2’s EPB1 by an
external device (DSP or host).

Note: In DSP multiprocessor systems a DSP with
ID=001 must be present, since this is the DSP
responsible for driving the external bus control
lines stable during reset.

Introduction to SHARC® Multiprocessor Systems Using VisualDSP++™ (EE-148) Page 3 of 13

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External Memory

External memory is widely used in MP
systems. An important point to keep in mind is
that all DSPs in the system must initialize their
own control registers before trying to access the
external memory (i.e. WAIT register in case of
SBSRAM).

The ADSP-21160 can be gluelessly interfaced to
synchronous and asynchronous SRAM devices,
however the use of DRAM requires an external
controller.

It is very important to set up the proper access
mode for the type of memory used in the
hardware system. The access mode is
programmed via the WAIT register. Default
power up/reset settings for the System Control
(SYSCON) and WAIT registers are detailed in
the ADSP-21160 Hardware Reference Manual.
User defined settings must support the external
memory address ranges that the user intends to
use in their code and hardware systems as well as
the access mode appropriate to the memory
device(s) in use (i.e. synchronous or
asynchronous accesses). The MSIZE setting
must also not exceed the size of the actual
physical memory connected in the user’s system.

Note that SDRAM is gluelessly supported by
certain devices like the ADSP-21065L and the
ADSP-21161. For these cases, specific registers
must be initialized prior to accessing the external
memory. The SDRDIV and IOCTL, for the
ADSP-21065L, and the SDRDIV and SDCTL,
for the ADSP-21161, registers of all processors
in the system must be initialized to the same
value. Once the DSP’s internal memory
controller has been configured, the external
memory can be accessed by the DSP via the
external bus.

In the example project, the shared.asm file
contains the variable definitions for the data that
will be placed in the external shared memory.

Note: the DSP with the lowest ID number (and
therefore highest external bus arbitration

priority in the system) is responsible for
initializing the external data defined in the .ASM
shared memory file during the booting-up
sequence.

Inter Processor Messages and Vector Interrupts

The Message Passing registers (MSGRx)
are general-purpose memory mapped registers
that can be used for message passing between the
host and a DSP or between two DSPs. Similarly,
Vector Interrupts are used for inter-processor
communication between the host and a DSP or
between DSPs.

The MSGRx and VIRPT registers can be used
for message passing in the following ways:

• Message Passing. The host (or master DSP) can
use any of the 8 message registers, MSGR0
through MSGR7, to communicate with the DSP.

• Vector Interrupts. The host (or master DSP) can
issue a vector interrupt to the DSP by writing the
address of an interrupt service routine to the
VIRPT register. When serviced, this high priority
interrupt causes the DSP to branch to the service
routine at that address.

Example 2:

// Excerpt from ID2: VIRPT Generation
I0=0x100001; // VIRPT reg. address in ID1

R0=0x40080; // ISR at SFT0I address in ID1
will be executed

DM(I0,M0)=R0;// write to VIRPT reg.in ID1
[...]

// Excerpt from ID1: VIRPT Service Routine
// in SFT0I user software interrupt vector
// address

BIT SET IMASK VIRPTI; // VIRPT enabled [...]
// In vector interrupt table
R0=0x2f2f2f2f; // Value for msg. Passing RTI

(DB);// Serve VIRPTI generated by ID2
I0=MSGR0;// Load address of MSGR0 and write
value in ID2

DM(MMS_ID2,I0)=R0;
[...]

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