Analog Devices EE144 Application Notes

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Creating A Master-Slave SPI Interface

Engineer To Engineer Note EE-144

Technical Notes on using Analog Devices’ DSP components and development tools

configured as the master-driven output device­select signal.

Between Two ADSP-2191 DSPs

Last modified: 6/26/01

Contributed By: JWB.

This Engineer-to-Engineer note will discuss
how to set-up a Serial Peripheral Interface (SPI)
between two ADSP-2191 devices in both the
hardware and the software. The master and
slave code included in the associated archive
can be used as a template for any ADSP-2191
SPI interface.

The hardware for this system was verified using
two ADSP-2191-EZ-KITs, and the software was
built using the VisualDSP++ 2.0 Tools Suite.

On the slave side of the interface, PF0 is the
multiplexed flag pin assigned to be the SPI0
Slave Select (~SPISS0) signal. Figure 2 depicts
the hardware connection for a typical master­slave SPI interface. Remember that we are
utilizing SPI0 in this interface (SPI1 would use
different PFx pins and the SPI1 signals).

1. Hardware Interface

The SPI is a full-duplex, 4-wire, synchronous
interface consisting of two data lines, a clock,
and a device-select signal.

The data is transmitted over the MOSI (Master
Out Slave In) and MISO (Master In Slave Out)
data I/O signals and the clock is the SPI Clock
(SCK) signal. These 3 signals are shared
between the master and slave devices.

The 4th wire in the interface is the device-select
signal. The Programmable Flag pins on the
ADSP-2191 can be configured to function as
SPI device-selects. Please refer to the data sheet
for more information regarding the functional
use of these programmable flag pins. On a
master ADSP-2191 device, up to seven slave­select signals are available for each SPI port. In
this example, programmable flag pin 4 (PF4) is

Figure 1: SPI Hardware Connection For 2 ADSP-2191s

2. How The ADSP-2191 SPI Works

The ADSP-2191 features two SPI-compatible
ports. An SPI Interface essentially consists of
two shift registers that simultaneously transmit
and receive one bit of data to and from each
other at a fixed bit rate. The following diagram
is a general overview of the SPI data buffers and
how they relate to each other in an SPI system:

Figure 2: SPI Data Exchange (16-Bit Registers)

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The behavior of the SPI depends on how the SPI
ports are configured. In this example, transfers
are initiated on reads of the receive data buffer
register (RDBRx) and interrupts are generated
when RDBRx is full. Due to this configuration,
the following describes the behavior of the SPI:

Before the SPI transfer takes place, the master
and slave devices each places the data to be
transmitted in its respective transmit data
register (TDBRx).

The master then drives the device-select signal
of the slave and supplies the gated SPI Clock
(SCK). When the master initiates the transfer,
the master’s data moves from its TDBRx
register to its shift data register (SDBR), where
it is shifted out one bit at a time on the MOSI
pin on active SCK edges. The master is also
sampling the MISO pin on inactive SCK edges.

Meanwhile, the slave waits for its device-select
input to go active, meaning that the master is
about to transmit. When that happens, the slave
moves its data from its TDBRx to its SDBR and
starts shifting out on the MISO pin on active
SCK edges and sampling the MOSI pin on
inactive SCK edges.

So, both devices are transmitting and sampling
on each SCK pulse simultaneously. This data­shifting scheme continues until one full word
has been transmitted and received (i.e., the two
devices have essentially exchanged SDBR data).

The received data in SDBR then moves to the
respective receive data register (RDBRx), which
is when the interrupt is generated, informing the
DSP that the data can now be read *. When the
RDBRx register is read, it is cleared and
becomes ready to get the next word from the
shift register when it arrives.

*Note: The ADSP-2191 core cannot directly access the
Shift Data Buffer Register (SBDR).

3. Programming The SPI Devices

Once the hardware is properly connected, it is
time to generate the software to control the two
SPI ports so that they will talk to each other.
For this to work, software is required to
initialize both the master and the slave devices.

Please refer to chapter 10 of the “ADSP-
219x/2191 Hardware Reference” for the various
SPI register descriptions and for the “SPI
General Operation” section, which describes
the steps required by both the master and the
slave to get an SPI interface running properly.

The code contained in the ZIP archive
associated with this Engineer-to-Engineer note
will be referenced throughout this section of the
text.

3.1. Master Code

The assembly code for the master has been
broken into two files, the source code
(SPI_Master.asm) and the interrupt handler
(SPI_MISR.asm). The numeric super-scripts
indicate the corresponding source code line
numbers being referenced in the text.

3.1.1. SPI_Master.asm

The very first thing that is always required when
initializing an SPI interface is the setting of the
OPMODE bit (bit 0) in the System
Configuration Register
this bit instructs the DSP to disable SPORT2
and to enable SPI0/1 on those pins. It is also
good practice to set bit 4 while you are
manipulating SYSCR to ensure that the
Interrupt Vector Table (IVT) resides with the
rest of your code. There are 3 possible default
locations for the IVT depending on the boot
mode and whether or not an emulator is present

54-56

(SYSCR). Setting

EE-144 Page 2

Technical Notes on using Analog Devices’ DSP components and development tools

Phone: (800) ANALOG-D, FAX: [phone], EMAIL: [e-mail], FTP: ftp.analog.com, WEB: www.analog.com/dsp