Analog Devices EE131 Application Notes

Engineer To Engineer Note EE-131

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Technical Notes on using Analog Devices' DSP components and development tools

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Booting the ADSP-2191/95/96 DSPs

Contributed by Ramdas C. - Glen O. - Benno K. April 14, 2003

Overview

The purpose of this application note is to
describe how to boot an Analog Device’s ADSP­2191/95/96 DSP processors. The ADSP-2191
has a booting scheme that is different from other
existing ADI DSP’s such as the ADSP-218x and
the SHARC families. When the ADSP-218x or
SHARC come out of
to automatically boot in a

/RESET, they are configured

Loader Kernel via DMA.

218x) or set up additional DMA’s to transfer the
rest of user code and data into internal and
external memory (as in the SHARC).

In case of the ADSP-2191, the

Boot Kernel is

located on-chip and stored in a 24-bit wide, 1K
ROM - Figure 1. The starting address of this
boot ROM begins at 0xFF0000 (i.e., the first
location of page 255).

Hardware Reset

s

There are three input pins on the ADSP-2191
whose termination state upon hard

/RESET

determines the booting mode – Figure 2. The
state of these three pins (

BMODE1) are sampled on the rising edge of
/RESET and are captured into the corresponding

bits (0,1,and 2) of the

(SYSCR –IO:0x204)

.

OPMODE, BMODE0 and

System Configuration Register

Figure 2 SYSCR Register

Figure 1 Loader Kernel BOOT ROM at Page 255

This Loader Kernel would then either load in
corresponding

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Page Loaders (as in the ADSP-

Note that for pinout requirements, the OPMODE
pin has a dual role (boot-mode-select during a
hard

/RESET and also in determining whether the

third SPORT on the DSP functions as SPORT2
or SPI1). Hence it is possible that an application

a

might require the OPMODE to be different at
runtime than it is at hard
the

Boot Kernel has the ability to set it accordingly

/RESET. In such cases,

at the end of the boot process.

Figure 3 Selectable Boot Modes

The OPMODE bit can be changed in

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software at anytime during run-time
provided the corresponding peripherals
are disabled at that time.

Software Reset

When the ADSP-2191 comes out of /RESET,
program control jumps to 0xFF0000 and begins
execution of the internal boot ROM code. In the
case of a software

/RESET, program control will

either jump to 0xFF0000 or to 0x000000,
depending on the state of bit 4 of the

Configuration Register (NXTSCR - IO:0x203)

Next System

. If this bit
is a 0, program flow jumps to 0xFF0000. If it is a
1, program flow jumps to 0x000000, which is
equivalent to doing

Software /RESET without a Boot.

Boot Modes

Following a /RESET, the first operation performed
by the

Configuration Register (SYSCR, IO 0x00204) and

determine the means from which the DSP is set
up to boot (

Boot Kernel is to read the SYSTEM

BMODE 0/1 and OPMODE).

In the event that the DSP is configured to boot,
the first operation performed by the
to read in the first word of the

Boot Kernel is

Boot Stream. This

“control” word will contain information on the
rest of the boot. This transfer will be done in the
default modes that the DSP comes up with (e.g.,
8-bit external to 16-bit internal packing mode in
case of the EMI, with maximum wait states and
base clock divisor).

If it is determined that the DSP is not going to
boot in a program, but instead run a users
program from 8-bit or 16-bit external memory,
the boot ROM routine will set up the

Memory Interface

and the External Access Bridge

External

register for the desired packing mode (8-bit
external to 24-bit internal or 16-bit-external-to­24-bit internal), and then jump to the first
location of external memory (0x10000), where
the user program will be executed.

SPI Booting

If SPI booting is selected, the Boot Kernel will set
up SPI0 as master. It is set to receive 8-bit words,
MS-Bit first, SCLK = HCLK/60, with an active­low serial clock to be compatible with commonly
available serial EEPROMS.

The DMA engine is not used at all, but rather all
the data is read in through core reads a byte at a
time and packed internally by the

Boot Kernel.

Please note, that there is a dedicated application
note available. EE-145 describes SPI booting in
detail [4].

UART Booting

In the case of UART boot, the Boot Kernel begins
by first running an
to determine the baud-rate of the external UART
device. Once the baud-rate has been determined,
the

Boot Kernel will proceed with the rest of boot.

For

auto-baud detection the ADSP-2191 expects

the character 0xAA to be transmitted by an
external device. The

auto-baud routine using a timer

Boot Kernel initializes Timer

Booting the ADSP-2191/95/96 DSPs (EE-131) Page 2 of 9

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0 in order to capture an active high pulse at the
RX pin. Therefore Bit 1 of the
evaluated in order to determine the UART bit
rate.

Please be aware that just the width of

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Once Bit 1 has been captured and the bit rate has
been determined, the UART loader kernel replies
immediately the bytes
corresponding to “OK” in ASCII. Due to a chip
anomaly the
transmitted [3]. This depends on the bit rate and
DSP clock.

Bit 1 is captured, it is not sampled like
during normal UART operation. It is
obvious that missing signal integrity
and unsymmetrical raising/falling edges
may force the auto-baud detection to
fail. Especially at higher bit rates this
can become a serious issue. In practice
bit rates above 9600bps are not
recommended for booting if the UART
signal passes standard EIA-232 cables
and level shifters.

0x4F (“O”) may or may not be

0xAA character is

0x4F and 0x4B

Users of VisualDSP++™ 2.0 without

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There also exists a rare case that requires this
first wait-state byte again in order to correct the
alignment of the entire boot stream. This is the
case when the bit rate used during booting gets
close to the default bit rate of the DSP
(HCLK/16). While listening to the auto-baud
character
buffer normally captures two bytes.

Service Pack 1 need to remove this first
byte manually from the loader file.

0xAA, the two-depth UART receive

The resulting UART bit rate will always

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The external device can now begin transmitting
the boot file, byte by byte without caring about
any protocol. The DSP is fast enough to process
the data in time in any usual configuration. The

Boot Kernel does not transmit any further

characters by itself. Therefore, it is very common
that the loaded application finalizes the boot
procedure by transmitting any acknowledge as
soon as it has been started. Note that the loader
kernel does not alter the UART settings (neither
the
booting.

UART boot files have basically the same format
like others. Only the first byte of the boot stream,
that normally holds the wait-state information, is
removed in case of UART booting.

be a fraction of the peripheral clock
HCLK. With low HCLK frequencies
(bypass mode) and high bit rates the
likelihood of bit errors may increase.

LCR register nor the divisor latch) after

Figure 4 UART Load Property Page

In unusual applications where in either the DSP
clock is very low or the UART bit rate is very
high, the receive buffer may hold only one byte
after auto-baud detection. Therefore new
versions of the VisualDSP++ loader utility
remove the wait-state byte by default in case of
UART booting but provide a new command line
switch
the boot stream alignment in the special case
described above. Within the Load property page
of the
switch in the
Figure 4.

-forcefirstbyte. This switch corrects

Projects Options menu you can specify this

Additional options field like shown in

Booting the ADSP-2191/95/96 DSPs (EE-131) Page 3 of 9