Analog Devices ee-115 Application Notes

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Engineer To Engineer Note EE-115

Technical Notes on using Analog Devices’ DSP components and development tools

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ADSP-2189 IDMA Interface to Motorola MC68300

Family of Microprocessors

Note: This is the modified AN-415 Application Note for the ADSP-2189 and the new tools

INTRODUCTION

The speed and mathematical capabilities of DSP
processors, combined with their low cost and
expanded integration, make them a natural choice
for use as signal co-processors in embedded
environments. When paired with a host
microprocessor, a DSP processor allows for a very
powerful and flexible system at a reasonable price.
The ADSP-2189 is an ideal candidate for use in a
co-processing system. The 192K Bytes on chip
RAM, configured as 32K words of on-chip Program
Memory RAM and 48 K words on chip Data Memory
RAM and extensive DMA and peripheral interface
features allow the ADSP-2189 to function with
minimal external support circuitry. In order to realize
the highest possible performance in a co-processor
system, efficient host-DSP communication is vital.
The popular Motorola M68300 Family of
microcontrollers provides a powerful and flexible
bus interface that is easily adaptable to a co­processing system. This application note describes
an example hardware and software interface
between the Internal DMA (IDMA) Port of the ADSP­2189 and the Motorola M68300 Family of
microcontrollers. As each specific system design
has its own requirements and challenges, this
application note does not presume to provide the
only possible solution. Rather it is meant to provide
the system designer a flexible framework of ideas
that can be tailored to meet individual system
requirements.

IDMA Operation

External devices can gain access of the ADSP­2189’s internal memory through the DSP’s IDMA
Port. Host processors accessing the ADSP-2189
through IDMA can treat the DSP as a memory­mapped slave peripheral, and can have access to
all of the DSP’s internal Data Memory (DM) and
Program Memory (PM).

The DSP memory address is loaded into the IDMA
Address register (IDMAA) shown in Figure 2. This
register contains the 14-bit internal memory
address, along with a bit to specify the type of
transfer: 24-bit Program Memory opcodes, or 16-bit
Data Memory data. The IDMAA register can be
initialized by either the DSP or by a host processor.
The host can initialize this register by performing an
address latch cycle. An address latch cycle is
defined by the host asserting the ALE signal, and
then transferring a 15-bit (14 address bits plus 1
destination memory type bit) value on the IAD pins.
If Bit 15 is set to 0, IDMA latches the address. If Bit
15 is set to 1, IDMA latches into the OVERLAY
register. This register, as shown in Figure 2, is
memory mapped at address DM (0x3FE0). Note
that the host cannot read the latched address
(IDMAA) back

Host uses IS and IAL c ontrol lines to latch either th e D M A

sta rting a d dre ss (IDMAA) or th e P M /DM OVLAY selection

into th e D S P ’s IDM A control registers. If B it 15 = 1, the

va lue of b its 7 :0 represent the ID M A overlay: Bits 14:8 m ust

be se t to 0. If Bit 15 = 0, th e v a lue of bits 1 3 :0 rep resent the

sta rting a d dre ss o f interna l memory to be accessed and Bit 14

.

Host starts IDM A tra n s fer.

Host checks IAC K control line

to s e e if the D SP is busy.

reflects PM or DM for access.

Host uses IS and IRD (o r IWR )

to read (or write ) DSP inte rnal

m e m o ry (PM or DM ).

Done ?

Host ends IDMA transfer.

Continue

More ?

Host checks IAC K line to se e if

the D SP ha s c om pleted the

previous IDM A operation.

Figure1. IDMA Transfer Sequence

The ADSP-2189’s IDMA Port consists of a 16-bit
multiplexed address/data bus (IAD16:0), a select
line ( /IS ), address latch enable (ALE), read ( /IRD ),
write ( /IWR ), and acknowledge ( /IACK ) signals.
The host processor is responsible for initiating all
data transfers. A typical transfer sequence is shown
in Figure 1.

To streamline the transfer of large segments of
opcodes or data, an Address Latch Cycle does not
need to be performed for each IDMA access.
Instead, once latched, the address is automatically
incremented after every IDMA word transfer. As the
IDMA Port has a 16-bit bus, 24-bit transfers require
two host accesses. The first access transfers the

1

Copyright 2000, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are
property of their respective holders. Information furnished by Analog Devices Applications and Development Tools Engineers is believed to be accurate and
reliable, however no responsibility is assumed by Analog Devices regarding the technical accuracy of the content provided in all Analog Devices’ Engineer-to­Engineer Notes.

Figure 2. IDMA Control Registers

most significant 16 bits, the second access transfers
the least significant 8 bits, right justified, with a zero­filled upper byte. IDMA address increments occur
after the entire 24-bit word has been transferred.

The 6833x will use this bus to transmit the DSP
memory address, as well as transfer data to and
from the DSP processor. The /IACK signal from the
DSP is routed to both the DSACK1 pin and a
programmable flag pin on the MC6833x. The

For more information about the IDMA Port see the
ADSP-21xx Family User’s Manual (Third Edition)
and the ADSP-2189 Data Sheet.

DSACK1 pin signals the end of a memory transfer
cycle for the MC6833x, while the programmable flag
pin is used by the MC6833x to check /IACK status
prior to initiating a transfer. The microcontroller
downloader code, presented in the Code Listing

INTERFACE HARDWARE DESIGN

The IDMA Port of the ADSP-2189 is mapped into
two locations in the microcontroller’s external
memory space. One location is used by the
microcontroller to set the DSP memory address it
wishes to access, and the other location is used
when transferring data and instruction information.

section of this EE note, checks for a low level of the
flag prior to any transfer. The microcontroller’s
address pin A1 is connected directly to the ALE pin
of the IDMA port. To begin a transfer, the
microcontroller must first initialize the DSP’s IDMAA
register through an Address Latch cycle. This is
accomplished by writing the DSP memory address
that the microcontroller wants to access to address
0xbbb2 in the microcontroller’s memory space. The

MC6833x Overview

The Motorola MC6833x Family of microprocessors
use a System Integration Module (SIM) to
communicate to parallel peripherals. The SIM

setting of the base address is described in the next
paragraph. Address pin A1 was used because it is
the lease significant address pin used by the
microcontroller during 16-bit word transfers.

incorporates separate address and data busses,
along with multiple memory select lines and strobe
lines. The SIM is common (with minor changes) to
all MC6833x processors, and material presented in
this application note should apply to all processors
in the family.

Assigning the base address that the ADSP-2189
IDMA port resides at is accomplished through the
use of the MC68332’s address lines A12 and A13,
in conjunction with the microcontroller’s DS signal.
Or in using one of the MC6833x Chip Select pins. (
see glue logic at the end of this note) These signals

Schematic Explanation

Minimal logic is required to connect the external bus
of the MC6833x to the IDMA Port. All logic
necessary for this interface was programmed into a
single GAL20V8B programmable logic device. The
16 data lines from the MC6833x are connected via a
logic level translator to the ADSP-2189’s IAD pins.

are combined such that the IDMA Port’s /IS signal is
asserted (low) when DS is asserted (low), A12 is
low, and A13 is high. With this combination, the
IDMA Port can be accessed in the microcontroller’s
memory space at addresses 0x2xxx, 0x6xxx,
0xaxxx, and so on. In this application example we
use address 0x2000 for data transfers and 0x2002

2

Copyright 2000, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are
property of their respective holders. Information furnished by Analog Devices Applications and Development Tools Engineers is believed to be accurate and
reliable, however no responsibility is assumed by Analog Devices regarding the technical accuracy of the content provided in all Analog Devices’ Engineer-to­Engineer Notes.

for IDMA address transfers. Tighter assignment of
addresses can be accomplished through the use of
additional address lines in the /IS logic. The final
IDMA control lines that need to be driven by the
68332 are /IRD (IDMA Read) and /IWR (IDMA
Write). Since the microcontroller only has a single,
multiplexed R/W (Read/Write ) line, the R/W line is
inverted and then routed to /IRD to generate the
IDMA read signal. The IDMA Write signal, /IWR , is
the OR’ed combination of the microcontroller’s R/W
line, and address line 2. This logic is necessary to
insure that /IWR stays high during n IDMA Address
Latch cycle.

SYSTEM DESIGN ISSUES

The physical hardware interface between the
microcontroller and DSP is just the enabling step in
a DSP-based co-processing system. System start­up and host-DSP communication issues must be
planned for ahead of time and adequate provisions
for these issues should be included into both the
microcontroller’s and the DSP’s firmware.

Booting The DSP

The IDMA Port on the DSP can be used to boot
load the DSP on power up. This eliminates the need
for a separate EPROM for the DSP. On the ADSP­2189, booting is controlled through the use of the
MODE[A,B,C,D] pins. Booting through the IDMA
port is enabled by holding the MODE B,D pin low,
and the MODE A,C pin high. With this signal
combination, on RESET, the DSP does not activate
its external address bus to access an EPROM.
Instead, the DSP expects a host to begin IDMA
transfers to fill its internal Data and Program
memories. This process consists of the host
performing standard IDMA instruction and data
transfers. Booting is terminated when the DSP
restart vector at DSP Address PM(0x0000) is
written. An efficient boot loading sequence would
consist of the host filling the DSP’s internal Program
Memory starting at location PM(0x0001), and using
the automatic address increment feature on the
IDMA port to speed the transfer of code block in
ascending address order. The host can then
initialize data memory. When all initialization is
complete, the host should then initialize the DSP’s
restart vector and DSP program execution will
commence. This process is shown in Figure 3.

Generating “Boot” Code

The ADSP-21xx Family operates on 24-bit
instruction opcodes. The IDMA port can only
accept 16-bit values. To transfer instruction
opcodes through the IDMA port, the most
significant 16 bits transferred first, followed by the
least significant 8 bits, right justified with leading
zeros. The DSP IDMA boot files are produced by
the ADSP-21xx Family PROM Splitter (elfspl21).
Use the PROM Splitter Switch “-idma” to generate
a text file suitable for booting an ADSP-2181 or
218x (additional “-218x”) through the IDMA port.
The file will contain a series of IDMA transfer
records, each starting with a count (of 16 bit.

Latch Address

PM(0x0001)

Downl oad First

PM Seg ment

Download Additional

PM Seg ments*

Downl oad D M

Segme nts**

Latch Address

PM(0x0000)

Dow nload

RESAR T Vecto r

*Each segment download requires its own address
latch cycle.
**DM segments can be downloaded first, or
intermixed with PM segments.

Figure 3. IDMA Booting Process

words), an address (consisting of the 14 bit internal
address (IDMAA) and the 1 bit IDMAD), to be
written to the IDMA control register. For 218x, there
will be an additional address word, for the overlay
page, after the IDMA control word. Each word will
be represented as four characters encoding a 16-bit
value in hexadecimal format. The data appears one
word per line.

00A8 <—— count value
0001 <—— IDMA control word
8000 <—— IDMA OVERLAY control word (218x)
0001 <—— First Opcode (16 bit MSB), (count -2)
0002 <—— First Opcode ( 8 bit LSB), (count -3)
0001 <—— Second Opcode (16 bit MSB), (count -4)
0002 <—— Second Opcode (8 bit LSB), (count -5)
: :
: :
: :
: :
5678 <—— Last Opcode (16 bit MSB), (count =1)
0090 <—— Last Opcode (8 bit LSB), (count =0)
: :
: : <—— additional PM or DM Segments

: :

End-of-module specifier

FFFF

<——

Host Code Generation - Downloading Issues

In order to utilize the data file produced by the
PROM Splitter program, the microcontroller needs

Copyright 2000, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of

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customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are
property of their respective holders. Information furnished by Analog Devices Applications and Development Tools Engineers is believed to be accurate and
reliable, however no responsibility is assumed by Analog Devices regarding the technical accuracy of the content provided in all Analog Devices’ Engineer-to­Engineer Notes.