Analog Devices EE056v02 Application Notes

Engineer-to-Engineer Note EE-56

a

Technical notes on using Analog Devices DSPs, processors and development tools

Contact our technical support at [e-mail] and at [e-mail]
Or vi sit our o n-li ne r esou rces htt p:/ /www.analog.com/ee-notes and http://www.analog.com/processors

Tips & Tricks on the ADSP-2106x SHARC® EPROM and Host Bootloader

Contributed by Stefan Hacker Rev 2 – March 24, 2004

Introduction

After creating ADSP-2106x SHARC® processor
application code and verifying it in simulation or
emulation, one of final tasks is creating a boot
image for an EPROM or host processor. Though
this is an easy task using the VisualDSP++®
tools set, some users want to add specific
functionality to the boot loader or created their
own. This document discusses the output of the
elfloader tool and the arrangement of the data in
the boot image. It shows you where to add
changes to modify the boot loaders to adapt to
different host processor widths or types.

Boot Loader Names

060_prom.asm and 065l_prom.asm are the source

files for the ADSP-2106x PROM-based loaders.

060_host.asm and 065l_host.asm are the source files

for the ADSP-2106x host-based boot loader.

21060/ 61/ 62 21065L

Boot Space 4M x 8-bit 8M x 8-bit

DMAC Register DMAC6=0x2A1 DMAC0=0x2A1

II6 IIEP0 0x20000 0x8000

IM6 IMEP0 0x1 0x1

C6 CEP0 0x100 0x100
EI6* EIEP0* 0x40 0000 0x80 0000
EM6 EMEP0 0x1 0x1
EC6 ECEP0 0x600 0x600

IRQ Vector 0x20040 0x8040

Boot Loading

By default, the ADSP-2106x SHARC processor
is configured to load 256 words of 48-bit width
(instruction size) after reset by DMA. DMA
channel 6 is initialized for the ADSP-21060/ 61/
62 and DMA channel 8 is initialized for the
ADSP-21065L. Both DMA channels have in
common the 0x40 offset in the interrupt vector
table of the ADSP-2106x. The DMA settings for

Table1: EPROM boot setting with BSO bit set

* BMS space

Depending on the selected processor and the
boot loading type, one of the four kernels is
loaded into
architecture file is either named

065l_ldr.ldf. These source files are located in the
\21K\LDR subdirectory within the VisualDSP++

seg_ldr at reset. The corresponding

060_ldr.ldf or

tools set.

EPROM booting are shown in Table 1.
Numbers printed in italics are not initialized but

are assumed by the DMA engine.
Since user application code is far larger than

words, a boot kernel ensures that the complete
user application code and data is loaded into the
internal memory spaces of the SHARC.
Additionally, external memories and data ports
are initialized by the kernel.

Copyright 2004, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property
of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however
no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.

Boot Kernel Structure

Each kernel begins by defining macros for the
various IOP registers used in the code, followed
by a table containing the interrupt vectors, up to
and including the DMA interrupt aligned to the
external port buffer 0 (
priority interrupts are not necessary for the
operation of the boot loader and are filled with

EP0I). Most of these high-

a

NOP or RTI instructions. The only interrupts used

by the kernel are the reset interrupt
(offset 0x04-0x07) and the

___lib_EP0I (offset 0x40-0x43).

___lib_RSTI

EP0I interrupt

Beginning from the start_loader label the kernel
code can be divided into four main sections:

Start_loader Initializes some required registers

and determines for EPROM booting the
processor ID of the SHARC in a
multiprocessor environment.

Load_memory Starts to parse the information

from the boot source and copies it into the
required memory location or clears not
preplaced memory segments.

Final_init Swaps out the boot kernel and replaces

it with the user application code.

read_PROM_word Sets up the new DMA

transfer to collect a new 48-bit word.

the

SYSCON register. Three copies of SYSCON are

used in the program one that contains the original
value of

SYSCON, one that contains SYSCON with

the BSO-bit set so that an ADSP-2106x can gain
access to the boot EPROM, and a third with the

BSO bit cleared. When BSO=1, the EPROM

packing mode -bits in the

DMACx control register

are ignored and 8-to-48-bit packing is forced. For
the ADSP-21065L a 32-bit-wide system bus is
assumed. (Note that 8-to-48-bit packing is
available only on the ADSP-2106x during DMA
reads from

/BMS space with the BSO bit set).

When one of the external port DMA channels is
being used in conjunction with the

BSO bit, none

of the other three channels may be used. When

BSO=1, /BMS is not asserted by a core processor

access, only during a DMA transfer. This allows
your bootstrap program (run by the ADSP-2106x
core) to perform other external accesses to non­boot memory.

The

IMASK register is set finally to allow the EP0I

EPROM Boot Kernel Operation

After reset, the core processor is held in an IDLE
mode until the first 256 words, each 48-bits
wide, have been loaded by DMA into the internal
memory. The External Port DMA interrupt for
EP0I is activated upon the completion of the
DMA transfer. The core processor will start
execution of the just-loaded boot kernel by
branching to the vector interrupt location for
EP0I.

In

___lib_EP0I the DMA control register setting is

stored in R2 for later restoration and the DMA
channel is disabled temporarily by clearing the
DMA enable bit in the control register. Having
completed the IRQ service, the core processor
starts up the loader program.

Beginning from
registers are initialized. This is be a good place to
start up external memories like SDRAM on the
ADSP-21065L or to set wait states and wait
modes.

/BMS is deactivated and normal external memory

Start_Loader some required

interrupt and the

MODE1 register is set to enable

interrupts and nesting.
Having completed the setup, the DMA engine on

the ADSP-2106x processors is used to collect
48-bit words from the EPROM. As an external
boot EPROM allows starting a complete
multiprocessor cluster, the proper section in the
EPROM must be determined by checking the
processor ID in the

SYSTAT register. The code

beginning from get_addr label will parses a seven
entry 48-bit table stored in the EPROM (hex
offset 0x600 = 6*0x100 = 256 instruction words)
to find start address of boot section for this
processor. Every entry of the table is formatted
as:

address(32 -bit) processor ID (16 -bit)

As an example the readback 0x8002062A0001 for
an ADSP-21065L translates into an EPROM
offset of

Having determined the offset, the

0x8002062A and processor ID 0001.

DMAC6/DMAC0

control register is set to 0x2A1 and DMA
parameters are set up to read data word-by-word

selects are activated by clearing the BSO -bit in

Tips & Tricks on the ADSP-2106x SHARC® EPROM and Host Bootloader (EE-56) Page 2 of 8

a

beginning from the starting address of the boot
section corresponding to the processor ID in the
boot EPROM. Each 48-bit word is transferred
into address

0x20004 / 0x8004 for dispatching.

Because the image in the EPROM contains
program memory code sections and data memory
sections with different sizes, a preamble is stored
before each boot block. The preamble with the
attached boot block is formatted as shown in
Table 2.

0x0000 0000 DDDD
0xAAAA AAAA LLLL
0xBOOT BOOT BOOT
:
0xBOOT BOOT BOOT

Table 2. Boot Section Header

D (data type tag)
A (address), L (length)

Boot data
:
Boot data

Each initialization block is identified by a 16-bit
tag placed before the block. Each type of
initialization has a unique tag number.

Tag Number Initialization Type

0 0x0 FINAL INIT
1 0x1 ZERO DM16
2 0x2 ZERO DM32
3 0x3 ZERO DM40
4 0x4 INIT DM16
5 0x5 INIT DM32
6 0x6 INIT DM40
7 0x7 ZERO PM16
8 0x8 ZERO PM32

9 0x9 ZERO PM40
10 0xA ZERO PM48
11 0xB INIT PM16
12 0xC INIT PM32
13 0xD INIT PM40
14 0xE INIT PM48

Table 3. Section Header Types

The boot kernel initializes internal and external
memories by reading the data from EPROM
using a routine called

Read_Prom_Word and

writing it to a specific location of memory
(

0x20004 / 0x8004). For a zero-valued format data

block whose tag is 1, 2, 3, 7, 8, 9, or 10, an
initialization of 16- or 32-bit memory is done in
a loop, which writes a zero value to memory,
reducing the required space in the EPROM.

Any initialization of 40- or 48-bit PM memory
uses a write with the PX register set to zero. For
a non-zero format data block whose tag is 4, 5, 6,
11, 12, 13, or 14 the kernel enters a loop which
reads one 48-bit word from EPROM and writes
the appropriate width value to memory. This
loop is repeated once for each word being
initialized.

When the boot loader has completed parsing a
boot block, it continues with the next tag and
executes the appropriate initialization routine
until the kernel reaches the

FINAL_INIT (0x0) boot

tag.
In the final initialization stage, the kernel loads

the first 256 words of the target executable file
and will overwrites itself. When the loader
detects the tag, it reads the next 48-bit word. This
word indicates the instruction to be located at

0x20040 / 0x8004 when the loading is close to

being completed. This instruction is saved into
the 48-bit PX register so that the boot loader can
now finish initializing internal memory. The
kernel requires an

0x020040 / 0x8040 which is temporarily placed,

because an

EP0 interrupt is generated when the

initialization is completed. The
loaded with
instruction

0xbdb0000 containing the encoded

PM(0,I8)=PX. This writes the desired

customer instruction over the
boot kernel with

RTI instruction at address

R9 register is

RTI used by the

I8 pointing to 0x20040 / 0x8040.

Before the DMA sequence is initiated, the core
processor is trapped in a pseudo loop by issuing

Tips & Tricks on the ADSP-2106x SHARC® EPROM and Host Bootloader (EE-56) Page 3 of 8