ANALOG DEVICES CN-0187 Service Manual

Circuit Note

150 mA, Low Quiescent Current, CMOS Linear

engineers. Standard engineering practices have been employed in the design and construction of

room temperature. However, you are solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices

U3-A

U3-D

U1

COMM

ENBL

VA1

VA2

VB1

VB2

D

CAP

B

D

CAP

A

0.47µF

27Ω

27Ω

27Ω

AGND DGND

10kΩ

10kΩ

0.47µF

220Ω

220Ω

220Ω

442Ω

75Ω

+3.3V

C

FLTR

*

+3.3V

0.01µF 0.01µF

RFIN

0.01µF

0.1µF1000pF

+3.3V+3.3V

AVDD

DVDD

VDRIVE

CS

DOUTA

SCLK

ADP121

ADL5502

AD7266

+5.5V

+3.3V

1µF

VIN

FLTR

VPOS

RFIN

VRMS

PEAK

CNTL

VOUT

EN

GND

1µF

SDP

BOARD

AND
SUPPORT
CIRCUITS

NOTE: U2 AND U3 ARE ADA4891- 4

CONTROL
(HIGH RESET;
LOW PE AK HOLD)

U5

U6

+1.25V

+1.25V

+2.5V

* *

* *

*SEE TEXT

8

4

1

2

3

7

6

5

U2-B

U3-B

27Ω

U2-D

10kΩ

10kΩ

0.47µF

220Ω

220Ω

220Ω

442Ω

+3.3V

U3-D

U3-A

0.47µF

+2.5V

U2-A

U2-C

U3-C

09569-001

Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0187.

Crest Factor, Peak, and RMS RF Power Measurement Circuit Optimized for

High Speed, Low Power, and Single 3.3 V Supply

EVALUATION AND DESIGN SUPPORT

Circuit Evaluation Boards

CN-0187 Circuit Evaluation Board (EVAL-CN0187-SDPZ)
System Demonstration Platform (EVAL-SDP-CB1Z)

Design and Integration Files
Schematics, Layout Files, Bill of Materials

CN-0187

Devices Connected/Referenced

ADL5502 450 MHz to 6 GHz Crest Factor Detector

Differential/Single-Ended Input, Dual,

AD7266

ADA4891-4

ADP121

CIRCUIT FUNCTION AND BENEFITS

The circuit shown in Figure 1 measures peak and rms power
at any RF frequency from 450 MHz to 6 GHz over a range of
approximately 45 dB. The measurement results are converted
to differential signals in order to eliminate noise and are
provided as digital codes at the output of a 12-bit SAR ADC
with serial interface and integrated reference. A simple two­point calibration is performed in the digital domain.

Simultaneous Sampling, 2 MSPS, 12-Bit,
3-Channel SAR Analog-to-Digital Converter

Low Cost, Quad, CMOS, High Speed, Rail-to­Rail Amplifier

Regulator in 5-Lead TSOT or 4-Ball WLCSP

Figure 1. High Speed, Low Power, Crest Factor, Peak, and RMS Power Measurement System (Simplified Schematic: All connections and Decoupling Not Shown)

Rev.0

Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices

each circuit, and their function and performance have been tested and verified in a lab environment at

be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause
whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)

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Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

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CN-0187 Circuit Note

The ADL5502 is a mean-responding (true rms) power detector
in combination with an envelope detector to accurately
determine the crest factor (CF) of a modulated signal. It can be
used in high frequency receiver and transmitter signal chains
from 450 MHz to 6 GHz with envelope bandwidths over 10 MHz.
The peak-hold function allows the capture of short peaks in the
envelope with lower sampling rate ADCs. Total current
consumption is only 3 mA @ 3 V.

The ADA4891-4 is a high speed, quad, CMOS amplifier that
offers high performance at a low cost. Current consumption is
only 4.4 mA/amplifier at 3 V. The amplifier features true single­supply capability, with an input voltage range that extends 300 mV
below the negative rail. The rail-to-rail output stage enables
the output to swing to within 50 mV of each rail, ensuring
maximum dynamic range. Low distortion and fast settling time
makes it ideal for this application.

The AD7266

is a dual, 12-bit, high speed, low power, successive

approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features sampling rates up to 2 MSPS. The
device contains two ADCs, each preceded by a 3-channel
multiplexer, and a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz.
Current consumption is only 3 mA at 3 V. It also contains an
internal 2.5 V reference.

The circuit operates on a single +3.3 V supply from the

ADP121, a low quiescent current, low dropout, linear regulator

that operates from 2.3 V to 5.5 V and provides up to 150 mA
of output current. The low 135 mV dropout voltage at 150 mA
load improves efficiency and allows operation over a wide input
voltage range. The low 30 μA of quiescent current at full load
makes the ADP121 ideal for battery-operated portable equipment.

The ADP121 is available in output voltages ranging from 1.2 V
to 3.3 V. The parts are optimized for stable operation with small
1 μF ceramic output capacitors. The ADP121 delivers good
transient performance with minimal board area.

Short-circuit protection and thermal overload protection
circuits prevent damage in adverse conditions. The ADP121 is
available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch halide­free WLCSP packages and utilizes the smallest footprint
solution to meet a variety of portable applications.

CIRCUIT DESCRIPTION

The RF signal being measured is applied to the ADL5502.
A single 75 Ω termination resistor at the RF input in parallel
with the input impedance of the ADL5502 provides a
broadband match of 50 Ω. More precise resistive or reactive
matches can be applied for narrow frequency band use (see
the RF Input Interfacing section of the ADL5502 data sheet).

The internal filter capacitor of the ADL5502 provides averaging
in the square domain but leaves some residual ac on the output.
Signals with high peak-to-average ratios, such as W-CDMA or
CDMA2000, can produce ac residual levels on the ADL5502
VRMS dc output. To reduce the effects of these low frequency
components in the waveforms, some additional filtering is
required. The internal square-domain filter capacitance of the
ADL5502 can be augmented by connecting a C

capacitor

FLTR

between Pin 1 (FLTR) and Pin 2 (VPOS). The ac residual can be
reduced further by adding capacitance to the VRMS output.
The combination of the internal 100 Ω output resistance and
the added output capacitance

produces a low-pass filter to

reduce output ripple of the VRMS output (see the Selecting the
Square-Domain Filter and Output Low-Pass Filter section of the
ADL5502 data sheet for more details).

To measure the peak of a waveform, the control line (CNTL)
must be temporally set to a logic high (reset mode for >1 µs)
and then set back to a logic low (peak-hold mode). This allows
the ADL5502 to be initialized to a known state. When setting
the device to measure peak, peak-hold mode should be toggled
for a period in which the input rms power and crest factor (CF)
is not likely to change.

If the ADL5502 is in peak-hold mode and the CF changes from
high to low or the input power changes from high to low, a
faulty peak measurement is reported. The ADL5502 simply
keeps reporting the highest peak that occurred when the peak­hold mode was activated and the input power or the CF was
high. Unless CNTL is reset, the PEAK output does not reflect
the new peak in the signal.

The ADL5502 is capable of sourcing a VRMS output current of
approximately 3 mA. The output current is sourced through the
on-chip, 100 Ω series resistor; therefore, any load resistor forms
a voltage divider with this on-chip resistance. It is
recommended that the ADL5502 VRMS output drive high
resistive loads to preserve output swing. If an application
requires driving a low resistance load (as well as in cases where
increasing the nominal conversion gain is desired), a buffering
circuit is necessary.

The PEAK output is designed to drive 2 pF loads. It is
recommended that the ADL5502 PEAK output drive low
capacitive loads to achieve a full output response time. The
effects of larger capacitive loads are particularly visible when
tracking envelopes during the falling transitions. When the
envelope is in a fall transition, the load capacitor discharges
through the on-chip load resistance of 1.9 kΩ. If the larger
capacitive load is unavoidable, the additional capacitance can be
counteracted by putting a shunt resistor to ground on the PEAK
output to allow for fast discharge. Such a shunt resistor also
makes the ADL5502 run higher current, and it should not be
lower than 500 Ω.

Rev. 0| Page 2 of 7

Circuit Note CN-0187

0.01

0.1

1

10

–25 –20 –15 –10 –5 0 5 10 15

OUTPUT (V)

INPUT (d Bm)

450MHz
900MHz
1900MHz
2350MHz
2600MHz

09569-002

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 0.2 0.4 0.6 0.8 1.0

OUTPUT (V)

INPUT (V rms)

450MHz
900MHz
1900MHz
2350MHz
2600MHz

09569-003

0.01

0.1

1

10

–25 –20 –15 –10 –5 0 5 10 15

OUTPUT (V)

INPUT (d Bm)

450MHz
900MHz
1900MHz
2350MHz
2600MHz

09569-004

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 0.2 0.4 0.6 0.8 1.0

OUTPUT (V)

INPUT (V rms)

450MHz
900MHz
1900MHz
2350MHz
2600MHz

09569-005

VRMS (250mV/DIV)

1ms/DIV

70mV rms

160mV rms

250mV rms

400mV rms RF INPUT

VRMS

PULSED RFIN

09569-053

Typ ical measured performance characteristics of the circuit are
presented in Figure 2 through Figure 5.

Figure 2. Measured VRMS Output vs. Input Level (Log Scale), 450 MHz,

900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V

Figure 5. Measured PEAK Output vs. Input Level (Linear Scale), 450 MHz,

900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V

The turn-on time and pulse response is strongly influenced by
the size of the square-domain filter (C

) and output shunt

FLTR

capacitor connected to the VRMS output. Figure 6 (taken from
the ADL5502 data sheet) shows a plot of the output response to
an RF pulse on the RFIN pin, with a 0.1 μF output filter
capacitor and no square-domain filter capacitor (C

FLTR

). The
falling edge is particularly dependent on the output shunt
capacitance.

Figure 3. Measured VRMS Output vs. Input Level (Linear Scale), 450 MHz,

900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V

Figure 4. Measured PEAK Output vs. Input Level (Log Scale), 450 MHz,

900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V

Figure 6. Output Response to Various RF Input Pulse Levels, Supply3 V,

900 MHz Frequency, Square-Domain Filter Open, Output Filter 0.1 μF

To improve the falling edge of the enable and pulse responses,
a resistor can be placed in parallel with the output shunt
capacitor. The added resistance helps to discharge the output
filter capacitor. Although this method reduces the power-off
time, the added load resistor also attenuates the output (see the
Output Drive Capability and Buffering section of the ADL5502
data sheet). Figure 7 (taken from the ADL5502 data sheet)

Rev. 0| Page 3 of 7

shows the improvement obtained by adding a parallel 1 kΩ
resistor.