Closed-Loop
a
FEATURES
Bandwidth – 110 MHz
Slew Rate – 3000 V/ms
Low Offset Voltage – <1 mV
Very Low Noise – < 4 nV/√
Low Supply Current – 8.5 mA Mux
Wide Supply Range – 65 V to 615 V
Drives Capacitive Loads
Pin Compatible with BUF03
APPLICATIONS
Instrumentation Buffer
RF Buffer
Line Driver
High Speed Current Source
Op Amp Output Current Booster
High Performance Audio
High Speed AD/DA
GENERAL DESCRIPTION
The BUF04 is a wideband, closed-loop buffer that combines
state of the art dynamic performance with excellent dc
performance. This combination enables designers to maximize
system performance without any speed versus dc accuracy
compromises.
Built on a high speed Complementary Bipolar (CB) process for
better power performance ratio, the BUF04 consumes less than
8.5 mA operating from ±5 V or ±15 V supplies. With a 2000 V/µs
min slew rate, and 100 MHz gain bandwidth product, the
BUF04 is ideally suited for use in high speed applications where
low power dissipation is critical.
Full ±10 V output swing over the extended temperature range
along with outstanding ac performance and high loop gain
accuracy makes the device useful in high speed data acquisition
systems.
Hz
High Speed Buffer
BUF04*
FUNCTIONAL BLOCK DIAGRAMS
Plastic DIP
8-Lead Narrow-Body SO
(S Suffix)
1
BUF04
High slew rate and very low noise and THD, coupled with wide
input and output dynamic range, make the BUF04 an excellent
choice for video and high performance audio circuits.
The BUF04’s inherent ability to drive capacitive loads over a
wide voltage and temperature range makes it extremely useful
for a wide variety of applications in military, industrial, and
commercial equipment.
The BUF04 is specified over the extended industrial (–40°C to
+85°C) and military (–55°C to +125°C) temperature range.
BUF04s are available in plastic and ceramic DIP plus SO-8
surface mount packages.
Contact your local sales office for MIL-STD-883 data sheet and
availability.
*Patent pending.
8-Lead and Cerdip
(P, Z Suffix)
1
1
NULL
NC
IN
V–
BUF04
Top View
2
3
4
NC = NO CONNECT
8
NULL
7
V+
6
OUT
5
NC
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
BUF04–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = 615.0 V, TA = +258C unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS
Offset Voltage V
Input Bias Current I
B
Input Voltage Range V
Offset Voltage Drift ∆V
OS
CM
/∆T30µV/°C
OS
–40°C ≤ T
V
CM
–40°C ≤ T
≤ +85°C 1.3 4 mV
A
= 0 0.7 5 µA
≤ +85°C 2.2 10 µA
A
0.3 1 mV
±13 V
Offset Null Range ±25 mV
OUTPUT CHARACTERISTICS
Output Voltage Swing V
Output Current – Continuous I
Peak Output Current I
O
OUT
OUTP
R
= 150 Ω, ±10.5 ±11.1 V
L
–40°C ≤ T
R
= 2 kΩ, ±13 ±13.5 V
L
–40°C ≤ T
≤ +85°C ±10 ±11 V
A
≤ +85°C ±13 ±13.15 V
A
±50 ±65 mA
Note 2 ±80 mA
TRANSFER CHARACTERISTICS
Gain A
VCL
Gain Linearity NL R
R
= 2 kΩ 0.995 0.9985 1.005 V/V
L
–40°C ≤ T
= 1 kΩ, VO = ±10 V 0.005 %
L
R
= 150 kΩ 0.008 %
L
≤ +85°C 0.995 0.9980 1.005 V/V
A
POWER SUPPLY
Power Supply Rejection Ratio PSRR V
Supply Current I
SY
= ±4.5 V to ± 18 V 76 93 dB
S
–40°C ≤ T
VO = 0 V, R
≤ +85°C7693 dB
A
= ∞ 6.9 8.5 mA
L
–40°C ≤ TA ≤ +85°C 6.9 8.5 mA
DYNAMIC PERFORMANCE
Slew Rate SR R
Bandwidth BW –3 dB, C
Bandwidth BW –3 dB, C
Bandwidth BW –3 dB, C
Settling Time V
Differential Phase f = 3.58 MHz, R
Differential Gain f = 3.58 MHz, R
= 2 kΩ, CL = 70 pF 2000 3000 V/µs
L
IN
f = 4.43 MHz, R
f = 4.43 MHz, R
= 20 pF, R
L
= 20 pF, R
L
= 20 pF, R
L
= ∞ 110 MHz
L
= 1 kΩ 110 MHz
L
= 150 Ω 110 MHz
L
= ±10 V Step to 0.1% 60 ns
= 150 Ω 0.02 Degrees
L
= 150 Ω 0.03 Degrees
L
= 150 Ω 0.014 %
L
= 150 Ω 0.008 %
L
Input Capacitance 3pF
NOISE PERFORMANCE
Voltage Noise Density e
Current Noise Density i
NOTE
1
Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C with an LTPD of 1.3.
Specifications subject to change without notice.
n
n
f = 1 kHz 4 nV/√Hz
f = 1 kHz 2 pA/√Hz
–2–
REV. 0
BUF04
ELECTRICAL CHARACTERISTICS
(@ VS = 65.0 V, TA = +258C unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS
Offset Voltage V
Input Bias Current I
B
Input Voltage Range V
Offset Voltage Drift ∆V
OS
CM
/∆T30µV/°C
OS
–40°C ≤ T
V
CM
–40°C ≤ T
≤ +85°C 1.0 4 mV
A
= 0 V 0.15 5 µA
≤ +85°C 1.6 10 µA
A
0.8 2.0 mV
±3.0 V
Offset Null Range ±25 mV
OUTPUT CHARACTERISTICS
Output Voltage Swing V
Output Current - Continuous I
Peak Output Current I
O
OUT
OUTP
R
= 150 Ω, ±3.0 V
L
–40°C ≤ T
R
= 2 kΩ, ±3.0 ±3.6 V
L
–40°C ≤ T
≤ +85°C ±2.75 ±3.00 V
A
≤ +85°C ±3.0 ±3.35 V
A
±40 mA
Note 2 ±75 mA
TRANSFER CHARACTERISTICS
Gain A
VCL
Gain Linearity NL R
R
= 2 kΩ, 0.995 0.9977 1.005 V/V
L
–40°C ≤ T
= 1 kΩ 0.005 %
L
≤ +85°C 0.995 1.005 V/V
A
POWER SUPPLY
Power Supply Rejection Ratio PSRR V
Supply Current I
SY
= ±4.5 V to ± 18 V 76 93 dB
S
–40°C ≤ T
VO = 0 V, R
≤ +85°C7693 dB
A
= ∞ 6.60 8 mA
L
–40°C ≤ TA ≤ +85°C 6.70 8 mA
DYNAMIC PERFORMANCE
Slew Rate SR R
Bandwidth BW –3 dB, C
Bandwidth BW –3 dB, C
Bandwidth BW –3 dB, C
Differential Phase f = 3.58 MHz, R
Differential Gain f = 3.58 MHz, R
= 2 kΩ, CL = 70 pF 2000 V/µs
L
f = 4.43 MHz, R
f = 4.43 MHz, R
= 20 pF, R
L
= 20 pF, R
L
= 20 pF, R
L
= 150 Ω 0.13 Degrees
L
= 150 Ω 0.15 Degrees
L
= 150 Ω 0.04 %
L
= 150 Ω 0.06 %
L
= ∞ 100 MHz
L
= 1 kΩ 100 MHz
L
= 150 Ω 100 MHz
L
NOISE PERFORMANCE
Voltage Noise Density e
Current Noise Density i
NOTE
1
Long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 °C, with an LTPD of 1.3.
Specifications subject to change without notice.
n
n
f = 1 kHz 4 nV/√Hz
f = 1 kHz 2 pA/√Hz
REV. 0
–3–
BUF04
WAFER TEST LIMITS
(@ VS = 615.0 V, TA = +258C unless otherwise noted)
Parameter Symbol Conditions Limit Units
Offset Voltage V
Input Bias Current I
OS
V
OS
B
V
= ±15 V 1 mV max
S
V
= ±5 V 2 mV max
S
V
= 0 V 5 µA max
CM
Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 76 dB
Output Voltage Range V
Supply Current I
Gain A
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
O
SY
VCL
1
R
= 150 Ω±10.5 V min
L
VO = 0 V, R
V
= ±10 V, RL = 2 kΩ 1 ± 0.005 V/V
O
= 2 kΩ 8.5 mA max
L
DICE CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Maximum Power Dissipation . . . . . . . . . . . . . . . See Figure 16
Storage Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
BUF04Z . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
BUF04S, P . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Package Type θ
2
JA
θ
JC
Units
8-Pin Cerdip (Z) 148 16 °C/W
8-Pin Plastic DIP (P) 103 43 °C/W
8-Pin SOIC (S) 158 43 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket
for cerdip, P-DIP, and LCC packages; θJA is specified for device soldered in circuit
board for SOIC package.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
BUF04AZ/883 –55°C to +125°C Cerdip Q-8
BUF04GP –40°C to +85°C Plastic DIP N-8
BUF04GS –40°C to +85°C SO SO-8
BUF04GBC +25°C DICE DICE
BUF04 Die Size 0.075 x 0.064 inch, 5,280 Sq. Mils
Substrate (Die Backside) Is Connected to V+
Transistor Count 45.
–4–
REV. 0
Typical Performance Characteristics–
125–50–75 1007550250–25
TEMPERATURE – °C
–1.0
–5.0
–6.0
–3.0
–4.0
–2.0
0
INPUT BIAS CURRENT – µA
VS = ±5V
VS = ±15V
BUF04
150
VS = ±15V
120
90
UNITS
60
30
30
0
0
OFFSET – mV
315 PLASTIC DIPS
T
= +25°C
A
0.60.0–0.1 0.50.40.30.20.1
Figure 1. Input Offset Voltage (VOS) Distribution @
±
15 V, P-DIP
125
VS = ±5V
100
75
UNITS
50
315 PLASTIC DIPS
T
= +25°C
A
200
VS = ±15V
160
120
UNITS
80
40
0
–0.15
–0.1
OFFSET – mV
315 CERDIPS
T
= +25°C
A
0.150.10.50–0.5
0.2
Figure 4. Input Offset Voltage (VOS) Distribution @
±
15 V, Cerdip
125
VS = ±5V
100
75
UNITS
50
315 CERDIPS
T
= +25°C
A
25
0
OFFSET – mV
1.40.20 1.21.00.80.60.4
Figure 2. Input Offset Voltage (VOS) Distribution @
±
5 V, P-DIP
2.0
1.0
0
–1.0
–2.0
OFFSET – mV
–3.0
–4.0
–5.0
–6.0
Figure 3. Input Offset Voltage (VOS) vs. Temperature
±15V
TEMPERATURE – °C
±5V
125–50–75 1007550250–25
25
0
0.2
0
OFFSET – mV
1.4
1.21.00.80.60.4
Figure 5. Input Offset Voltage (VOS) Distribution @
±
5 V, Cerdip
Figure 6. Input Bias Current vs. Temperature
REV. 0
–5–
BUF04
8.0
7.5
VS = ±18V
7.0
6.5
SUPPLY CURRENT – mA
6.0
5.5
VS = ±5V
TEMPERATURE – °C
VS = ±15V
125–50–75 1007550250–25
Figure 7. Supply Current vs. Temperature
15
VS = ±15V
14
13
12
11
–11
–12
OUTPUT SWING – Volts
–13
–14
–15
–25
0
TEMPERATURE – °C
RL = 2k
RL = 1k
RL = 150
RL = 150
RL = 1k
RL = 2k
Ω
Ω
Ω
Ω
Ω
Ω
125–50–75 100755025
Figure 8. Output Voltage Swing vs. Temperature @ ±15 V
50
TA = +25°C
45
40
35
30
25
20
15
OUTPUT IMPEDANCE – Ω
10
5
0
1k 10k 100M10M1M100k
FREQUENCY – Hz
VS = ±5V
VS = ±15V
Figure 10. Output Impedance vs. Frequency
5.0
4.5
4.0
3.5
3.0
–3.0
–3.5
OUTPUT SWING – Volts
–4.0
–4.5
–5.0
VS = ±5V
–25
Ω
RL = 2k , 1k
RL = 150
RL = 150
RL = 2k , 1k Ω
0
TEMPERATURE – °C
Ω
Ω
Ω
Ω
125–50–75 100755025
Figure 11. Output Voltage Swing vs. Temperature @ ±5 V
5
4
POSITIVE
SWING
3
ABS NEGATIVE
2
OUTPUT SWING – Volts
1
0
10 100 1M100k10k1k
SWING
LOAD RESISTANCE – Ω
Figure 9. Maximum V
VS = ±5V
T
= +25°C
A
Swing vs. Load @ ±5 V
OUT
16
14
12
POSITIVE
10
OUTPUT SWING – Volts
SWING
8
6
4
2
0
10 100 10k1k
ABS NEGATIVE
SWING
LOAD RESISTANCE – Ω
Figure 12. Maximum V
VS = ±15V
T
= +25°C
A
Swing vs. Load @ ±15 V
OUT
–6–
REV. 0
BUF04
10
0
100
110 1M100k10k1k100
FREQUENCY – Hz
INPUT NOISE VOLTAGE
SPECTRAL DENSITY – nV/ Hz
0.5
0
–0.5
–1.0
INPUT BIAS CURRENT – µA
–1.5
–2.0
TA = +25°C
10–8–10 86420–2–4–6
COMMON MODE VOLTAGE – Volts
Figure 13. Bias Current vs. Input Voltage
100
90
80
70
60
50
40
30
20
POWER SUPPLY REJECTION – dB
10
0
1k 10k 100M10M1M100k
FREQUENCY – Hz
– PSRR
+PSRR
TA = +25°C
V
= ±5, ±15V
S
Figure 14. Power Supply Rejection vs. Frequency
1.5
P DIP
ΘJA = 103°C/W
CERDIP
1.0
ΘJA = 148°C/W
SOIC
ΘJA = 158°C/W
0.5
POWER DISSIPATION – W
0
0
TEMPERATURE –
TJ MAX = 150°C
FREE AIR
NO HEAT SINK
°
C
Figure 16. Maximum Power Dissipation vs.
Ambient Temperature
Figure 17. Input Noise Voltage vs. Frequency
12525 1007550 85
6000
5000
+EDGE
4000
3000
2000
SLEW RATE – V/µs
1000
0
–EDGE
0
TEMPERATURE – °C
Figure 15. Slew Rate vs. Temperature
VS = ±15V
75–25
6000
5000
4000
3000
0
NEGATIVE
SLEW RATE
2000
SLEW RATE – V/µs
1000
125–50–75 1005025
POSITIVE
SLEW RATE
CAPACITIVE LOAD – pF
VS = ±15V
SWING = ±10V
= +25°C
T
A
250500 200150100
Figure 18. Slew Rate vs. Capacitive Loads
REV. 0
–7–
BUF04
150
125
100
75
50
BANDWIDTH – MHz
25
0
PHASE @
R
= 150
L
PHASE @
R
= 2k
L
BANDWIDTH
CAPACITANCE – pF
Figure 19. Bandwidth and Phase vs.
Capacitive Loads @
140
RL= 2kΩ
130
120
110
±
5 V
Ω
Ω
TA = +25°C
V
= ±5V
S
–55°C
+25°C
250500 200150100
–45
–67.5
–90
–112.5
–135
–157.5
–180
PHASE – Deg
150
125
100
75
50
BANDWIDTH – MHz
25
0
Figure 22. Bandwidth & Phase vs.
Capacitive Loads @
200
150
100
BANDWIDTH
PHASE
CAPACITANCE – pF
±
15 V
TA = +25°C
V
= ±15V
S
RL = 150
RL = 2k
TA = +25°C
Ω
V
Ω
S
= ±15V
250500 200150100
–45
–67.5
–90
–112.5
–135
–157.5
–180
PHASE – Deg
100
BANDWIDTH – MHz
90
80
SUPPLY VOLTAGE –Volts
+125°C
Figure 20. Bandwidth vs. Supply Voltage and
Temperature
1.5
1.0
0.5
0
–0.5
GAIN DEVIATION – dB
–1.0
–1.5
VS = ±15V
V
= 0.1V
IN
FREQUENCY = 10MHz
R
= 150
L
RMS
Ω
GAIN
OUTPUT VOLTAGE – Volts
0
PHASE
6–2–4–6
Figure 21. Gain and Phase Deviation, RL = 150
±15±10±5
6
4
2
0
–2
PHASE DEVIATION – Degrees
–4
–6
10–8–10 842
Ω
BANDWIDTH – MHz
50
0
100 1k 10k
RESISTIVE LOAD – Ω
Figure 23. Bandwidth vs. Loads
0.075
0.050
0.025
–0.025
GAIN DEVIATION – dB
–0.050
–0.075
VS = ±15V
V
= 0.1V
IN
FREQUENCY = 10MHz
R
= 2k
L
GAIN
0
RMS
Ω
OUTPUT VOLTAGE – Volts
PHASE
0
6–2–4–6
Figure 24. Gain and Phase Deviation, RL = 2 k
1.5
1.0
0.5
0
–0.5
PHASE DEVIATION – Degrees
–1.0
–1.5
10–8–10 842
Ω
–8–
REV. 0
BUF04
10
100
0%
90
2V
50ns
2V
INPUT
(2V/DIV)
OUTPUT
(2V/DIV)
V
S
= ±15V, RL = 2kΩ, CL = 15pF
DLY 375.0ns
INPUT
(50mV/DIV)
OUTPUT
(50mV/DIV)
100
90
10
0%
50mV
50mV
V
= ±15V, RL = 2kΩ, CL = 15pF
S
10ns
Figure 25. Small-Signal Transient Response
AUDIO PRECISION BUF04 THD+N (%) vs FREQ (Hz)
0.1
A
VS= ±15V
LPF=80kHz
A
0.010
B
C
0.001
D
0.0001
T
20 100 1k 10k 20k
A : VIN = 7.75V
B : VIN = 7.75V
B
C
D
rms, RL
rms, RL
= 150W
= 600W
: VIN = 0.775V
C
C
: VIN = 0.775V
D
07 MAR 93 21:31:53
rms, RL
rms, RL
Figure 27. THD + Noise vs. Amplitude
= 150W
= 600W
Figure 26. Large-Signal Transient Response
12
VS = ±15V
9
= +25°C
T
A
Ω
= 150
R
L
6
3
0
GAIN – dB
–3
–6
–9
–12
10k 100k 1000M100M10M1M
BUF04
C
L
Ω
150
Ω
10
FREQUENCY – Hz
CL = 100pF
CL = 50pF
CL = 0pF
Figure 28. Bandwidth vs. Frequency
FUNCTIONAL DESCRIPTION
The BUF04 is a closed-loop voltage buffer based on a current
feedback architecture. Its high open-loop transimpedance, high
output current drive capability, and its low input offset voltage
makes it useful in a variety of applications, such as buffering the
inputs of sampling and flash A/D converters, audio and video
line drivers, active filters, and precision op amp hoosters.
A transistor-level equivalent circuit for the BUF04 is illustrated
in Figure 29. The input stage consists of a pair of emitter
follower transistors, Q1 and Q2, whose outputs drive a second
set of transistors, Q3 and Q4. The emitters of Q3 and Q4 are
connected together through diodes, D1 and D2, to form a low
impedance input for the feedback signal (in current mode) from
the output stage. The outputs of Q3 and Q4 are then
“mirrored” to Q5 and Q6 which form the gain stage of the
BUF04. The signal is taken from the collectors of Q5 and Q6
which drive a “Darlington-connected” output stage made up of
transistors Q7-Q10. Three R-C networks (R1–C1, R2–C2, and
R3–C3) form feed-forward paths which bypass certain sections
of the BUF04 for improved high frequency performance and
capacitive load drive capability. Since the signal conveyed
internally in the BUF04 is a current, the frequency response
and slew rate of the BUF04 are insensitive to supply voltage
variations.
REV. 0
Q11
V
IN V
Q1
Q12
Q2
Q13
D1
D2
Q14
Q3
Q4
100Ω
R2
Q5
Q7
C1
R
FB
C3
R3
C2
Q6
Q8
Q9
Q10
Ω
20
Ω
20
Figure 29. Transistor-Level Equivalent Circuit
An interesting feature of the BUF04 architecture is the use of
“slew-enhancement” transistors, Q11–Q14. Under normal small
signal (V
< 2 Vbes) conditions, these transistors are normally
IN
“OFF.” In large signals, high speed transient applications where
the input signal is > 2 V
s, these transistors turn on and literally
be
“brute-force” the output to follow the input. When the input
signal drops below 2 V
s, the transistors return to their
be
normally “OFF” state.
–9–
OUT
BUF04
V+
BUF04
7
6
10µF
0.1µF
0.1µF
V–
10µF
4
3
V
IN
10k
1
V
OUT
TRIM RANGE
±30mV
8
A two-terminal equivalent circuit of the BUF04 is shown in
Figure 30 where the transistor-level equivalent circuit is reduced
to its essential elements. The input stage develops a signal
current, I
as to flow through R
voltage developed across R
voltage follower. With an open-loop R
30 Ω, the voltage gain of the BUF04, given by the ratio R
, that is replicated by an internal current conveyor so
IN
, the transimpedance of the BUF04. The
t
is buffered by a unity-gain output
t
of 400 kΩ and an R
t
IN
t/RIN
of
is
approximately 13,000—accurate to approximately 13.5 bits.
The BUF04’s open-loop ac transimpedance response is
determined by the open-loop pole formed by R
C
is typically 8 pF, the open-loop pole occurs at approximately
t
and Ct. Since
t
50 kHz.
V
X1
IN
R
I
IN
R
FB
RIN = 30
R
= 400 k
t
C
= 8pF
t
RFB = 100
t
C
Ω
XI
t
Ω
Ω
I
IN
R
IN
V
OUT
Figure 30. Current-Feedback Functional Equivalent
Circuit of the BUF04
Grounding and Bypassing Considerations
To take full advantage of the BUF04’s very wide bandwidth,
high slew rates, and dynamic range capabilities requires due
diligence with regard to supply bypassing. In high speed circuits,
the supply bypassing network must provide a very low impedance
return path for currents flowing to and from the load network.
As with any high speed application, multiple bypassing is always
recommended. A 10 µF tantalum electrolytic in parallel with a
0.1 µF ceramic capacitor is sufficient for most applications. For
those high speed applications where output load currents
approach 50 mA, small valued resistors (1.1 Ω to 4.7 Ω) in
series with the tantalum capacitors may improve circuit
transient response by damping out the capacitor’s selfinductance. Figure 31 illustrates bypassing recommendations.
V+
10µF
R1
0.1µF
KELVIN RETURN
7
BUF04
4
V–
6
0.1µF
10µF
V
IN
Figure 31. Recommended Power-Supply Bypassing
3
R
S
NOTE
USE SHORT LEAD LENGTHS (<5mm)
FOR LOAD CURRENT
R2
KELVIN RETURN
FOR LOAD CURRENT
V
OUT
R
L
To minimize the effects of high-frequency coupling, circuits
must be built with short interconnect leads, and large ground
planes should he used whenever possible to provide a low
resistance, low-inductance circuit path. Sockets should be
avoided because the increased interlead capacitance can degrade
bandwidth and stability. If sockets are necessary, individual pin
sockets (oftentimes called “cage jacks,” AMP Part No.
5-330808-3 or 5-330808-6) should be used. They contribute far
less stray reactance than molded socket assemblies.
Offset Voltage Nulling
Although the offset voltage of the BUF04 is very low (1 mV,
maximum) for such a high speed buffer, the circuit shown in
Figure 32 can be used if additional offset voltage nulling is
required. A potentiometer ranging from 1 k to 10 k can be used
for V
nulling; with a 10 kΩ potentiometer, the trim range is
OS
±30 mV.
Figure 32. Optional Offset Voltage Nulling Scheme
APPLICATIONS
Output Short-Circuit Protection
To optimize the transient response and output voltage swing of
the BUF04, internal output short-circuit current limiting was
omitted. Although the BUF04 can provide continuous output
currents of 50 mA without protection, direct connection of the
BUF04’s output to ground or to the supplies will destroy the
device. An active current limit technique, illustrated in Figure
33, provides the necessary short-circuit protection while
retaining full dc output voltage swing to the load.
+15V
RSC1
≥10Ω
2N2905
0.1µF
7
3
V
IN
BUF04
0.1µF
4
2N2219
RSC2
≥10Ω
–15V
10µF
2N2905
SET ISC +(ISC–) <60mA,
CONTINUOUS
RSC1 (RSC2) =
6
Ω
6.2k
2N2219
10µF
V
OUT
0.01µF
0.6V
ISC + (ISC–)
Figure 33. Short-Circuit Current Limiting Using
Current Sources
–10–
REV. 0
BUF04
6
3
V
IN
6'
COAX
R
L
BUF04
R
S
R
X
C
T
C
X
Z
O
50Ω
75Ω
COAX
RG-58
RG-59
R
S
, R
L
50Ω
75Ω
R
X
50
75
C
X
91pF
62pF
C
T
3–15pF
3–15pF
Output Current Transient Recovery
Settling characteristics of high speed buffers also include the
buffer’s ability to recover, i.e., settle, from a transient output
current load condition. When driving the input of an A/D
converter, especially the successive-approximation converter
types, the buffer must maintain a constant output voltage under
dynamically changing load current conditions. In these types of
converters, the comparison point is usually diode-clamped, but
it may deviate several hundred millivolts resulting in high
frequency modulation of the A/D input current. Open-loop and
closed-loop buffers (also, op amps configured as followers) that
exhibit high closed-loop output impedances and/or low unity
gain crossover frequencies recover very slowly from output load
current transients. This slow recovery leads to linearity errors or
missing codes because of errors in the instantaneous input voltage. Therefore, the buffer (or op amp) chosen for this type of
application should exhibit low output impedance and high unity
gain bandwidth so that its output has had a chance to settle to
its nominal value before the converter makes its comparison.
The circuit in Figure 34 illustrates a settling measurement
circuit for evaluating the recovery time of high speed buffers
from an output load current transient. The input to the buffer is
grounded for ease of measuring the recovery time, and two
resistors are used to sum steady-state and transient load currents
at the output. As a worst-case condition, R1, was chosen such
that the BUF04 would source (or sink) a steady-state current of
25 mA. R2 was then chosen to add a 10 mA transient current
upon the steady-state value. To set accurately the nodal voltages
internal to the BUF04, the supply voltages were offset by the
voltage applied to R1. Because of its high transimpedance, wide
bandwidth, and low output impedance, the BUF04 exhibits an
extremely fast recovery time of 60 ns to 0.01%, as shown in
Figure 34. Results were identical regardless whether the BUF04
was sourcing or sinking current.
V+
10µF
0.1µF
7
3
BUF04
6
0.1µF
4
V–
10µF
V
TP1
LOAD
R1
200Ω
TP2
R2
250Ω
SOURCE: 0➔ –2.5 V
SINK: 0➔ +2.5V
SOURCE: –5V
SINK: +5V
V
IN
Figure 34. Transient Output Load Current Test Circuit
t
59.00ns
I
SOURCE
(4mA/DIV)
V
OUT
(5mV/DIV)
∆
100
90
10
0%
100mV
5mV
20ns
25mA
35mA
Figure 35. BUF04’s Output Load Current Recovery Time
Terminated Line Drivers
The BUF04’s high output current, large slew rate, and wide
bandwidth all combine to make it an ideal device for high speed
line driver applications. As shown in Figure 36, the BUF04 can
be configured for driving doubly terminated 50 Ω and 75 Ω
cables. To optimize the circuit’s pulse response, a capacitor, C
(CX + C
), is connected across the series back termination.
TRIM
T
The BUF04 can drive a 50 Ω line to ±2.5 V and a 75 Ω line to
±3.75 V when operating on ±15 V supplies.
Figure 36. Line Driver Configuration
Low-Pass Active Filter
In many signal-conditioning applications, filters are required to
band-limit noise or altogether eliminate other unwanted signals
prior to conversion. Often, high frequency filters are needed for
these applications; however, there are few op amps that exhibit
the high open-loop gain and wide unity-gain crossover
frequency required for these applications. As illustrated in
Figure 37, the BUF04 and a handful of passive components can
be configured as a high frequency, low-pass active filter. Since
the filter configuration is a unity-gain Sallen-Key topology, the
BUF04 is particularly well suited for this application. In this
circuit, an additional resistor, R3, was added to prevent
interaction between C2 and the BUF04’s input capacitance.
C1*
44pF (22pF x 2)
R1
499Ω
V
IN
REV. 0
–11–
W
Figure 37. A 10 MHz Low-Pass Active Filter
R2
499Ω
C2*
22pF
= R1 · R2 · C1 · C2
O
1
R3
47Ω
3
BUF04
* SILVERED MICA OR
DIPPED CERAMIC
; Q = 4 · C2
6
C1
V
OUT
BUF04
V
IN
±10V
R
L
50Ω
V
OUT
3
R3
100Ω
R1
47Ω
6
BUF04
R
S
50Ω
3
R2
47Ω
6
BUF04
±5V
R4
100Ω
Operation Within an Op Amp Feedback Loop
The BUF04 is well suited as a current booster or isolation
buffer within the closed loop of precision op amps such as the
OP177, the OP97, the OP27, or the OP77. Since the BUF04 is
a closed loop voltage buffer, no interstage coupling resistor
between the op amp and the buffer’s input is required for circuit
stability. The wide bandwidth and high slew rate of the BUF04
assure that the loop has the characteristics of the op amp; hence,
no additional rolloff is required.
R1
100
2
OP177
V
IN
3
GAIN
10
100
1000
R2
6
R2 (kΩ)
1
10
100
3
BUF04
6
R
L
500Ω
C
L
1000pF
V
OUT
Figure 38. BUF04 as Booster Stage for a Precision Op Amp
Paralleling BUF04s for Increased Load Drive Capability
In applications where continuous output currents greater than
50 mA are required or where heat management is an issue, a
number of BUF04s can be connected in parallel to reduce the
drive requirement of any one buffer. An example of one such
application is illustrated in Figure 39. In this circuit, the
BUF04s are required to drive a doubly terminated 50 Ω line to
±5 V. This type of a load for a single BUF04 would certainly
cause a power dissipation problem. Parallel operation results in
lower input and output impedances and increased bias currents;
on the other hand, input equivalent noise voltage is reduced and
input offset voltage remains unchanged.
Figure 39. Paralleling BUF04s for High Output Currents
Overdrive Recovery and Phase Reversal
In applications where the inputs could be driven to the supply
rails, the BUF04 recovers in 10 ns from positive or negative
overdrive. The BUF04 does not exhibit any output voltage
phase reversal when the input signal exceeds its input voltage
range.
–12–
REV. 0
BUF04
* BUF04 SPICE Macro-model 7/93, Rev. A
* JCB / PMI
*
* Copyright 1993 by Analog Devices, Inc.
*
*
* Node assignments
* noninverting input
* positive supply
* negative supply
* output
*
*
.SUBCKT BUF04 1 99 50 6
*
* INPUT STAGE
*
R1 99 8 200
R2 10 50 200
V1 99 9 4.4
D198DX
V2 11 50 4.4
D2 10 11 DX
I1 99 5 1.8E-3
I2 4 50 1.8E-3
Q1 50 3 5 QP
Q2 99 3 4 QN
Q3 8 61 30 QN
Q4 10 7 30 QP
R3 5 61 50E3
R4 4 7 50E3
CP1 61 99 14E-15
CP2 7 50 14E-15
RFB 6 2 100
*
* INPUT ERROR SOURCES
*
IB1 99 1 0.7E-6
VOS 3 1 0.7E-6
LS1 30 2 1E-9
CS1 99 2 2.0E-12
CS2 99 1 3.0E-12
*
EREF 97 0 22 0 1
*
* TRANSCONDUCTANCE STAGE
*
R5 12 97 365E3
C3 12 97 8E-12
G1 97 12 99 8 SE-3
G2 12 97 10 50 SE-3
E3 13 97 POLY(1) 99 97 –2.5 1.1
E4 97 14 POLY(1) 97 50 –2.5 1.1
D3 12 13 DX
D4 14 12 DX
R6 12 15 200
C2 15 6 20E-12
*
* POLE AT 200 MHz
*
R11 20 97 1E6
C7 20 97 0.759E-15
G7 97 20 12 22 1E-6
*
* POLE AT 200 MHz
*
R12 21 97 1E6
C8 21 97 0.759E-15
G8 97 21 20 22 1E-6
*
* OUTPU T STAGE
*
FSY 99 50 POLY(2) V7 V8 1.85E-3 1 1
R13 22 99 16.67E3
R14 22 50 16.67E3
R15 27 99 80
R16 27 50 80
L2 27 6 10E-9
G11 27 99 99 21 12.5E-3
G12 50 27 21 50 12.5E-3
V5 23 27 3.3
V6 27 24 3.3
D5 21 23 DX
D6 24 21 DX
G10 97 70 27 21 12.5E-3
D7 70 71 DX
D8 72 70 DX
V7 71 97 DC 0
V8 97 72 DC 0
*
* MODELS USED
*
.MODEL QN NPN(BF= 1000 IS= 1E-15)
.MODEL QP PNP(BF= 1000 IS= 1E-15)
.MODEL DX D(IS= 1E-15)
.ENDS BUF04
REV. 0
–13–
BUF04
BUF04 SPICE
+IN
97
CS2
G7
99
CP1
Q2
50
5
Q1
R4
I2
I1
8
R3
61
30
7
10
CP2
G8 R12
Q3
Q4
IB1
V
OS
1
3
4
C7
R11
V1
R1
9
CS1
D1
12
LS1
2
6
RFB
D2
11
R2
V2
2120
C8
99
G1 G2 R5
97
12
R6
C3
C2
15
D3
13
E3
6
D4
14
E4
R13
R14
FSY
70
22
G10
97
D7
71
V7
21
D8
72
V8
G11
V5
D5
23
V6
D6
24
G12
R15
L2
27
50
6
R16
–14–
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
BUF04
0.005 (0.13) MIN
PIN 1
0.200
(5.08)
MAX
0.200 (5.08)
0.125 (3.18)
8-Lead Cerdip (Q-8)
0.055 (1.4) MAX
8
1
0.405 (10.29) MAX
0.070 (1.78)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.030 (0.76)
5
4
0.310 (7.87)
0.220 (5.59)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.320 (8.13)
0.290 (7.37)
15
8
1
0.015 (0.38)
0.008 (0.20)
°
0
°
0.430 (10.92)
0.348 (8.84)
0.100
(2.54)
BSC
5
4
0.070 (1.77)
0.045 (1.15)
0.280 (7.11)
0.240 (6.10)
0.015
(0.381) TYP
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
0.195 (4.95)
0.115 (2.93)
8-Lead Narrow-Body SO (R-8)
0.1968 (5.00)
0.1890 (4.80)
0.0192 (0.49)
0.0138 (0.35)
5
0.1574 (4.00)
0.1497 (3.80)
4
0.102 (2.59)
0.094 (2.39)
0.2440 (6.20)
0.2284 (5.80)
0.0098 (0.25)
0.0075 (0.19)
8
°
0
°
0.0196 (0.50)
0.0099 (0.25)
8
1
0.0500
(1.27)
BSC
x 45
0.0500 (1.27)
0.0160 (0.41)
°
REV. 0
–15–
BUF04
C1856–10–10/93
–16–
PRINTED IN U.S.A.
REV. 0
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