Analog Devices AN-260 Application Notes
AN-260
a
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com
Using Digitally Programmable Delay Generators
by Allen Hill, IED
The AD9500 and AD9501 digitally programmable delay
generators are versatile parts, useful in numerous applications. The parts are designed for use in automatic test
equipment as a deskew element for digital data lines.
The versatility of the AD9500 and AD9501 for generating
programmable delays allows them to be used in applications that range from ATE to communications, computers, disk drives, lasers and ultrasound systems. This
note describes how best to apply these parts in some of
these applications.
GENERAL DESCRIPTION
A digitally programmable delay generator delays a digital edge by a programmed amount of time. Figure 1
shows the basic function of a programmable delay generator. The delay through the device is controlled by an
N-bit digital word. This is the programmed delay. A trigger pulse is applied to the input, and after a fixed propagation delay (t
), the pulse edge appears a program
PD
delay later at the output.
comparator threshold set by the DAC, the output of the
comparator switches.
This output is delayed from the trigger pulse by an
amount of time that is proportional to the DAC digital
input code and the slope of the ramp. Altering the digital
delay value changes the DAC output voltage, which alters the delay through the circuit. The slope of the ramp
is controlled with external components.
TRIGGER
RESET
DIGITAL
DELAY
VALUE
TRIGGER
DELAYED
OUTPUT
RESET
TIMING
CONTROL
FLIP-FLOP
N N
LATCH
RAMP
GENERATOR
D/A
CONVERTER
DELAYED
OUTPUT
COMPARATOR
DIGITAL
DELAY
VALUE
TRIGGER
TRIGGER
PULSE
OUTPUT
PULSE
N
GENERATOR
t
PD
DELAY
PROGRAM
OUTPUT
DELAY
Figure 1. Programmable Delay Generator
The AD9500 (ECL) and AD9501 (TTL) use a ramp/comparator/DAC architecture as shown in Figure 2. One
input of a high speed comparator is driven by a digitalto-analog converter (DAC). The DAC is used to set a reference voltage at this comparator input. The other input
is connected to a ramp generator. The ramp generator is
started by applying a pulse to the trigger input of the
delay generator. When the ramp voltage crosses the
RAMP
VOLTAGE
DAC
VOLTAGE
(DAC CODE
00 HEX)
(DAC CODE
FF HEX)
Figure 2. Delay Generator Block Diagram and Basic
Timing
Once the comparator has switched, the ramp generator
and comparator must be reset so that the device can be
triggered again. One method of accomplishing the reset
is to connect the output of the delay generator to the
reset pin. This results in an output pulsewidth that is
equal to the reset propagation delay of the device (7 ns
to 15 ns). An alternate, and versatile, method of resetting the device is to use an external signal that meets the
timing requirements of the part. An external reset signal
allows the pulsewidth to be controlled and makes system integration of the delay signal easier.
AN-260
Full-Scale Range Setting
The full-scale range of the generator is the span over
which the delay can be programmed. This range is divided into 256 equal delays by the 8-bit digital delay
value. The full-scale range of the delay generator is configured by connecting R
SET
and C
as shown in Figure
EXT
3. Additional information is available on the AD9500 and
AD9501 data sheets. The range can be adjusted from a
minimum of 2.5 ns out to 10 µs and beyond.
+5V
C
EXT
7
AD9500
18
R
SET
–5.2V
FULL-SCALE RANGE =
3 (C
EXT
+10pF)
R
SET
3.84 3 R
+5V
C
EXT
6
AD9501
7
R
SET
FULL-SCALE RANGE =
3 (C
EXT
+8.5pF)
SET
Figure 3. Setting Full-Scale Range on the AD9500 and
AD9501
The full-scale range can be adjusted by switching different values of resistance into the R
pin. A digitally con-
SET
trolled resistor can also be used to provide this function.
A programmable full-scale circuit is generated by using
a DAC to control the current flow into the R
shown in Figure 5. The R
pin of the AD9500 is biased
SET
SET
pin as
at approximately –4.3 V and requires a current source to
set full scale. The bias on the R
pin of the AD9501 is
SET
about 0.5 V and can be used in a similar manner.
AD9500
DELAY
GENERATOR
R
SET
AD557
DAC
1kV
–2.5V
1kV
AD707
AD9500
DELAY
GENERATOR
R
SET
1N4148
1.7kV
The maximum full-scale range of these devices depends
on the amount of jitter the application can tolerate. Jitter
is the variation of delay through the device with subsequent trigger pulses. An increase in full-scale results in
an increase in jitter of the output delay. As the full-scale
is increased, the slope of the ramp is decreased, resulting in a longer period of time that the ramp is in the comparator transition region. Any noise on the ramp or DAC
during this time can cause the comparator to switch.
Figure 4 illustrates the output jitter with various fullscale delay settings.
200mV 1ns
FULL-SCALE = 100ns
JITTER = 0.4ns
200mV 10ns
FULL-SCALE = 10ms
JITTER = 10ns
DIGITALLY
CONTROLLED
RESISTOR
* X9MME
XICOR
XICOR IS A REGISTERED
–5.2V
*
TRADEMARK OF XICOR
CORPORATION
Figure 5. Programmable Full-Scale Range Using a DAC
or a Digitally Controlled Resistor
C
should not be switched on the AD9500 or AD9501 to
EXT
provide a programmable full-scale range. The noise
pickup on the interconnects can cause false triggering at
the input of the device.
When C
is increased to extend full-scale range, the
EXT
reset propagation delay increases because the larger
capacitance must be discharged to reset the ramp.
The propagation delay is the time required for the ramp
to reach the first DAC threshold. The slope of the ramp is
determined by the full-scale setting, which means the
propagation delay will change with full-scale range. The
propagation delay of the AD9500 and AD9501 can be
calculated from the equations shown below:
AD9500 Prop Delay = 5 ns + 0.18 × (Full-Scale Range);
Offset Pin Open
200mV
FULL-SCALE = 100ms
JITTER = 200ns
100ns
Figure 4. Output Jitter at Various Full-Scale Settings for
the AD9500 and AD9501
–2–
AD9501 Prop Delay = 8 ns + 0.18
Offset Pin Grounded
×
(Full-Scale Range);
Loading...