Analog Devices AN-21065L-I2S Application Notes

Application Note

Interfacing I2S-Compatible Audio Devices

To The ADSP-21065L Serial Ports

SDRAM

Host

Micro

ADSP 21065L

Version 1.0A

2 Channel

D/A

2 Channel

D/A

2 Channel

D/A

2 Channel

D/A

John Tomarakos

ADI DSP Applications

4/2/99

0. Introduction

The ADSP-21065L is the newest first generation SHARC member to be released, enabling 32-bit processing in either fixed or floating point at a cost comparable to lower data word DSPs. This application note will cover the new features of the ADSP21065L Serial Ports, the addition of the I2S mode of operation, which allows a simple glueless interface to a wide range of industry standard audio devices. The I2S format was developed and promoted by Philips Semiconductor, and today many professional and consumer audio manufacturers use this standard interface for interconnection of audio devices, and as a result, it has become the dominant, de-facto standard.

This document will serve as a reference for those who wish to understand the I2S serial protocol and the programming of the ADSP-21065L to enable this mode of operation. First, a short tutorial will be given on the I2S bus, and then 21065L I2S mode functionality will be described in detail. Finally, two I2S loopback examples will be demonstrated. One was written and tested on the ADSP-21065L EZ-LAB with a simple wired loopback on the EMAFE interface, while the other example is an audio loopback on the Bittware Research Systems Spinner Audio OEM Board, which uses 24-bit, 96 kHz I2S ADCs and DACs (AKM semiconductor converters).

Figure 1. ADSP-21065L Serial Port I2S Interconnection Pins

RX0a RX0b RFS0 RCK0

ADSP-

TX0 TX0 TFS TCK0

21065L

RX1a RX1b RFS1 RCK1

• 4 RX Inputs with I2S support

• Supports 8 Input Audio Channels

The ADSP-21065L includes 2 on-chip serial ports –SPORT0 and SPORT1- that contain a new I2S mode of operation. Figure 1 shows the basic serial connections that enable this interface. The ADSP-21065L’s two serial ports provide 4 receive inputs and 4 transmit outputs to allow the processing of 8 I2S input audio channels and playback through 8 I2S output audio channels.

• 4 TX Outputs with I2S support

• Supports 8 Output Audio Channels

TX1 TX1 TFS TCK1

1. Philips I2S Serial Bus Protocol Overview

In consumer and professional audio products of recent years, the analog or digital ‘front-end’ of the DSP uses a digital audio serial protocol known as I2S. Audio interfaces between various ICs in the past was hampered because each manufacturer had dedicated audio interfaces that made it extremely difficult to interface these devices to each other. Standardization of audio interfaces was promoted by Philips with the development of the Inter-IC-Sound (I2S) bus, a serial interface developed for digital audio to enable easy connectivity and ensure successful designs. In short, I2S is a popular 3 wire serial bus standard

protocol developed by Philips for transmission of 2 channel (stereo) Pulse Code Modulation digital data, where each audio sample is sent MSB first. I2S signals, shown in Figures 1 and 2, consist of a bit-clock, Left/Right Clock (also is often referred to

as the Word Select) and alternating left and right channel data. This protocol can be compared to synchronous serial ports in TDM mode with 2 timeslots (or channels) active. This multiplexed protocol requires only 1 data path to send/receive 2 channels of digital audio information.

Figure 1

I2S Digital Audio Serial Bus Interface Examples

Figure 2.

Example I2S Timing Diagram for 16-bit

Stereo PCM Audio Data

Transmitter

SCLK

DSP Audio

Serial Bus Master

LR_Select SDATA

Transmitter Reciever

SCLK

Audio

A/D

LR_Select SDATA

Reciever

D/A

DSP

Serial Bus Master

SCLK

Left/Right FS Clock

Serial Data

Audio data word sizes supported by various audio converter manufacturers range can be either

Left Channel Select Right Channel Select

1 Serial Bit Clock Delay From LRCLK transistion

0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M S

Left Sample Right Sample

16, 18, 20, or 24 bits

As a result, today many analog and digital audio 'front-end' devices support the I2S protocol. Some of these devices include:

• Audio A/D and D/A converters

• PC Multimedia Audio Controllers

• Digital Audio Transmitters and Receivers that support serial digital audio transmission standards such as

AES/EBU, SP/DIF, IEC958, CP-340 and CP-1201.

• Digital Audio Signal Processors

• Dedicated Digital Filter Chips

• Sample Rate Converters

L S B

The ADSP-21065L has 4 transmit and receive data pins (DT0A, DT0B, DT1A, DT1B), providing I2S serial port support for interfacing to up to 8 commercially available I2S stereo devices, yielding 16 channels of audio with only 2 serial ports. The ADSP-21065L's built-in support for the I2S protocol eliminates the need for interface logic with a FPGA and result in a simple, glueless interface.

In addition to the master/slave timing generation of the word select and serial clock signals, it is also possible to generates the clocks with an external controller or another audio device, which in effect makes both I2S devices slaves. An example of this is shown in Figure 3. So for multiple devices, it is possible to synchronize all samples being transmitted or received with both SPORTs through a common clock and word select signal.

Figure 3. I

S Digital Audio Serial Bus Master Controller

Word Select and

Serial Clock

Controller

Transmitter Receiver

SCLK

DSP Audio

LR_Select

SDATA

Controller = Serial Bus

D/A

So this serial format efficiently transfers two-channel audio data for each I2S interconnection, while other control, status, and sub-coding signals (for example, AES/EBU devices used in ADAT equipment and SP/DIF devices found in DVD players) are transferred through a separate interface. As shown in the above figures, the buses three lines are:

• Continuous serial clock - SCK (RCLKx or TCLKx if the 21065L is the master)

• Word Select – WS (RFSx or TFSx if the 21065L is the master)

• Serial Data - SD ( DTx, DRx on the 21065L SPORTs), this is in a 2-channel time-division multiplexed format

The transmitter, receiver or and system clock controller generates the serial clock and word select signals. Thus the I2S device that generates the serial clock and word select is the master I2S device.

The Philips I2S bus defines the following:

Serial Data Pins:

• Serial data is transmitted in two’s complement format, with the MSB transmitted first, because the transmitter and

receiver may have different word lengths.

• The receiver ignores extra bits from the transmitter if greater than it’s capable (or programmed) serial length.

• If the receiver’s word length is greater than the data sent, all missing bits are set to zero internally

• The transmitter always sends the MSB of the next word one clock period after the WS changes.

• Serial data sent by the Transmitter can be sync’ed with either the trailing or leading edge of the SCLK.

• The Receiver (or the device in Slave Mode) always latches data on the leading edge of SCLK.

Word Select Pins:

• When WS = 0 or ‘low’, the data is Channel 1, or Left Channel data in a stereo system.

• When WS = 0 or ‘low’, the data is Channel 2, or Right Channel data in a stereo system.

• WS may change on a trailing or leading edge of the SCLK, but it does not need to be symmetrical.

• WS changes state one SCLK period before the MSB is transmitted.

• In slave mode, the data is latched on the leading edge of the serial clock signal.

• The slave determines synchronous timing of the serial data that will be transmitted, based on the external clock

generated by the master. The WS signal is latched on the leading edge of the clock signal. The slave takes into account the propagation delays between the master clock and the data and/or word select signals. Thus, the total delay is simply the sum of

- The delay between the master clock and the slave’s internal clock

- The delay between the internal clock and the data and/or the word select signals.

Other I2S Specification Notes:

• To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock

signal, always giving the reciever sufficient setup time.

• The data setup and hold time must not be less than the specified reciever set-up and hold time.

• In slave mode, the transmitter and receiver meed a clock signal with minimum HIGH and LOW periods so that

they can detect the signal.

• Any device can act as the serial bus master by providing the necessary clock signals.

2. Usage of I2S Peripherals in 32-bit Audio Applications

The following Figures 4 and 5 show how the ADSP-21065L can be used in certain audio applications to take advantage of it’s I2S mode for processing multiple channels of audio. One example shows a surround sound application, where multiple DACs are required for the playback and placement of 6 channels of audio. Notice that for each I2S link, we have two channels of audio transmission from a stereo ADC or to a stereo DAC. The other example shows how the ADSP-21065L can be used in a prosumer application such as a digital mixer or digital recorder. Inputs and outputs can be either analog or digital.

Figure 4.

Example Consumer Audio DSP System Using the ADSP-21065L

Home Theatre System

Left Front

Laserdisc

Player

Compact

Disk Player

Stereo

ADC

Stereo

ADC

I2S Link

Addr. Data

SRAM /

SDRAM

ADSP-

21065L

I2S Link

8, 6, or 32-

bit Host uP

Stereo

DAC

Stereo

DAC

Stereo

DAC

SP/DIF

X-mitter

RCA

Connector

Figure 5.

Example Prosumer Audio DSP System Using the ADSP-21065L

digital 4-track home studio recording/playback system

I2S Link

AES/EBU

Channel 1 Channel 2

Channel 3 Channel 4

AES/EBU

reciever

Compact

Disk Player

Stereo

ADC

Stereo

ADC

I2S Link

ADSP-

21065L

Stereo

DAC

Stereo

DAC

Recorder

X-mitter

Right Front

Left Rear

Right Rear

Center

Subwoofer

Left

Right

Addr. Data

SRAM /

SDRAM

XLR

Connector

to DAT

machine

8, 6, or 32-

bit Host uP

3. Digital Audio Interface I2S Devices: SPD/IF & AES/EBU Digital Audio Transmitters and Receivers

The ADSP-21065L's I2S interface easily allows transmission and reception of audio data using industry standard digital audio serial protocols. These devices act as a 'digital' front-end for the DSP. There are primarily 2 dominant digital protocols used today. One is used for professional audio and the other for consumer audio applications.

AES/EBU (Audio Engineering Society/European Broadcast Union)

AES/EBU is a standardized digital audio bit serial communications protocol for transmitting and receiving two channels of digital audio information through a transmission line (balanced or unbalanced XRL microphone cables and audio coax cable with RCA connectors). This format of transmission is used to transmit digital audio data over distances of 100 meters. Data can be transmitted up to 24 bit resolution, along with control, status and sample rate information embedded in frame[37]. AES/EBU is considered to be the standard protocol for professional audio applications. It is a common interface that is used in interfacing different professional mixing and DAT recording devices together. The AES3-1992 Standard can be obtained from the Audio Engineering Society.

Figure 6. AES3 Frame Format

0 3

Preamble

Audio Engineering Society Recommended Practice: AES3-1992: Serial Transmission Format for TwoChannel Linearly Represented Digital Audio Data

4 27

Up to 24 bit Audio Sample Word

S B

(16/20/24 Data)

28 29 30 31

M S

V U C P

V = Validity U = User Data C = Channel Status P = Parity Bit

SPD/IF (Sony/Philips Digital Interface Format)

SPD/IF is based on the AES/EBU standard in operating in 'consumer' mode. The physical medium is an unbalanced RCA cable. The consumer mode carries less control/status information. Typical applications where this interface can be found is in home theater equipment (Dolby Digital & DTS Decoders) and CD players.

Digital Audio Receivers typically receive AES/EBU and SP/DIF information and convert the audio information into the I2S (or parallel) format for the ADSP-21065L, as well as provide status information (through flag pins or a parallel interface) that is received along with the audio data. Digital Audio Transmitters can take an I2S audio stream from the ADSP-21065L and transmit the audio data along with control information in AES/EBU and SPD/IF formats. Control and status information contains useful information such as the sampling rate of the data being transmitted or received.

4. Configuring the ADSP-21065L Serial Port Interface In I2S Mode

When interfacing an I2S device to an ADSP-21065L processor, the interconnection between both devices can be through either SPORT0 or SPORT1. In this application note, SPORT0 is used to demonstrate the I2S loopback test since SPORT1 is activated for communications with the AD1819a SoundPort Codec.

Figure 7. ADSP-21065L SPORTs

RX0 RX0 RFS0 RCK0

ADSP-

TX0 TX0 TFS TCK0

21065L

RX1 RX1 RFS1 RCK1

In order to facilitate serial communications with an I2S-compatible device, the DSP designer would simply tie the device to either the SPORT0 and SPORT1 pins as shown in the above diagram. Table 1 below shows the function of all of the serial port pins:

Table 1. ADSP-21065L Serial Port Pins

SPORT0

Function

Transmit data DT0A DT0B DT1A DT1B Transmit clock TCLK0 TCLK1

A Chn

B Chn

TX1 TX1 TFS TCK1

SPORT1

A Chn

B Chn

Transmit frame sync/ TFS0 TFS1 word select

Receive data DR0A DR0B DR1A DR1B Receive cock RCLK0 RCLK1 Receive frame sync RFS0 RFS1

Notice that both SPORTs have 2 channel, or data pins for both the transmit side and the receive side.

• Transmit A Channels - DT0A, DT1A

• Transmit B Channels – DT0B, DT1B

• Receive A Channels – DR0A, DR1A

• Receive B Channels – DR0B, DR1B

Both the transmitter and receiver have their own serial clocks. The TFSx and RFSx pins become word select signals in I2S mode, versus being regular small pulse signals that initiate shifting of data. Both channel A and channel B share both the serial

clock and frame syncs. For example, DR0A and DR0B use the RCLK0 and RFS0 signals to receive data, regardless if they are internally or externally generated.

Since there are 8 data pins (4 transmit and 4 receive channels), then for I2S mode of operation where two channels of data of transmitted or received on each data pin, the actual number of channels is doubled. Therefore, both serial ports combined gives the capability of passing up to 8 input channels of audio to the DSP and 8 output channels of audio, giving 16 audio streams with both SPORTs.

4.1 I2S-related bits in the SPORT Transmit and Receive Control Registers

The ADSP-21065L has two transmit (STCTL0, STCLT1) and two receive (SRCTL0, SRCTL1) control registers for configuring the timing signals, data size and DMA parameters. Figure 8 below highlights the related bits.

Figure 8.

I2S Control bits in the SPORT Control Registers

I2S enable

Sport channel enable (SPEN_x)

Word length (SLEN)

I2S channel transfer order (L_FIRST)

Frame sync (word select) generation

Master mode enable

DMA channel enable (SDEN_x)

DMA chaining enable (SCHEN_x)

OPMODE – Operation Mode (bit 11)

Setting this bit to a 1 will enable I2S mode, versus standard mode when it is 0.

MSTR – Master/Slave Mode Enable (bit 10)

When this bit is set to a 1 in the SPORT transmit control register, then the transmitter is the master. When it is cleared, the transmitter is the slave When this bit is set to a 1 in the SPORT receive control register, then the receiver is the master. When it is cleared, the receiver is the slave For Master Mode, the frame sync/word select and serial clock is internally generated, and values must be specified in the transmit or receive divisor registers. For Slave Mode, the frame sync/word select and serial clock is externally generated, and any values specified in the divisor registers are ignored.

For I2S master mode only in revs 0.2 and prior, otherwise it is applicable for master and slave parts of revision 0.3 and greater. With this bit set, the master transmitter sends the left channel first and the master receiver shifts in the right channel first. The L_FIRST control bit is ignored for slave mode (refer to anomaly list). With these earlier revisions, there is no way to select if the first transmitted or received word at startup will align to the left or right I2S channel, unless the WS pin is connected to a flag input pin for detection at the enabling of the SPORT.

SLEN – Data Word Length (bits 4-8)

This bit sets the serial word length, the value specified in the register is ‘SLEN – 1’. The serial data length can be from 3 to 32 bits in length.

FS_BOTH – Frame Sync Word Generation (bit 22, transmit control registers only)

(This applies for the transmit control register only). This bit select when during transmission to issue the word select (change in the state of WS) If FS_BOTH= 0, the word select state change (high –to-low, or low-to-high) is issued if data is in either the transmit A or transmit B channel. If FS_BOTH= 1, the word select toggles state only if data is in BOTH the transmit A and B channels.

SPL – Sport Loopback Mode (bit 22, receive control registers only)

This internally loops back the transmit side to the receive side of the same channel (TX A to RX A, TX B to RX B). This is useful for running internal SPORT tests and debugging code. SPL = 0, disables loopback mode. SPL = 1, enables loopback mode.

SPEN_A – SPORT Channel A Enable (bit 0)

This enables and disables the SPORT’s A channel. Performs a software reset.

SPEN_B – SPORT Channel B Enable (bit 24)

This enables and disables the SPORT’s B channel. Performs a software reset.

SDEN_A – SPORT Channel A DMA Enable (bit 18)

Enables and disables SPORT DMA operation (versus interrupt driven transfers) SDEN_A = 0, disables DMA transfers for channel A, interrupt generated for every word transmitted or received SDEN_A = 1, enables DMA transfers for channel A

SDEN_B - SPORT Channel B DMA Enable (bit 20)

SDEN_B = 0, disables DMA transfers for channel B, interrupt generated for every word transmitted or received SDEN_B = 1, enables DMA transfers for channel B

SCHEN_A – SPORT DMA Chaining Channel A Enable (bit 19)

0= Disables DMA chaining 1=Enables DMA chaining

SCHEN_B – SPORT DMA Chaining Channel B Enable (bit 21)

0= Disables DMA chaining 1=Enables DMA chaining

DITFS – Data Independent TFS (bit 15, transmit control registers only)

Selects when the processor toggles the TFS word select signal from low-to-high or high-to-low 0 = Data dependent TFS

TFS signal is generated only when nes data is in the SPORT chennel’s transmit data buffer.

1 = Data independent TFS

TFS signal generated regardless of the validity of the data present in SPORT channel’s transmit data buffer. The processor generates the TFS signal at the frequency specified by the value you load in the TDIV register.

TXS_A, RXS_A - Transmit and Receive Status Buffers (bits 30 and 31 in the SPORT transmit and receive control registers)

Read-only registers. Indicates the status of channel A’s transmit buffer contents 00 = empty, 10 = partially full, 11 = full, 01 = reserved. This is useful in detecting if the interrupt generated was because of data transmitted/received in channel A or channel B (for interrupt driven transfers.

4.2 States of SPORT Pins When Operating in Master or Slave Mode

The following tables 2 through 5 show the states of the pins on both SPORT0 and SPORT1 when the 21065L is set up for either master mode or slave mode. The states of the pins are shown for either a transmitter or reciever. The particular pins are matched up with the pins of the connecting I2S device (in the second column), showing generic definitions for the I2S compatible device, which contains a serial clock, word select, and serial data signals. The states of these pins, which are either outputs or inputs, are indicated in the third column in the tables.

Table 2. 21065L I2S Receiver in Master Mode

ADSP-2106x Pin: I2S Device Pin: Driven By:

RCLK0, RCLK1 SCLK 21065L RFS0, RFS1 WS (Word Select) 21065L DR0A, DR0B, DR1A, DR1B SD (Serial Data Out) I2S device

Table 3. 21065L I2S Receiver in Slave Mode

ADSP-2106x Pin: I2S Device Pin: Driven By:

RCLK0, RCLK1 SCLK I2S device RFS0, RFS1 WS (Word Select) I2S device DR0A, DR0B, DR1A, DR1B SD (Serial Data Out) I2S device

Table 4. 21065L I2S Transmitter in Master Mode

ADSP-2106x Pin: I2S Device Pin: Driven By:

TCLK0, TCLK1 SCLK 21065L TFS0, TFS1 WS 21065L DT0A, DT0B, DT1A, DT1B SD (Serial Data In) 21065L

Table 5. 21065L I2S Transmitter in Slave Mode

ADSP-2106x Pin: I2S Device Pin: Driven By:

TCLK0, TCLK1 SCLK I2S device TFS0, TFS1 WS I2S device DT0A, DT0B, DT1A, DT1B SD (Serial Data In) 21065L

4.3 Important Notes from the ADSP-21065L User’s Manual ‘Serial Ports’ Chapter

In I2S Mode, one or both of the transmit channels can transmit, and one or both receive channels can receive. Each channel either transmits or receives Left and Right Channels.

In I2S Mode, when both A and B channels are used, they transmit or receive data simultaneously, sending or receiving bit 0 on the same edge of the serial clock, bit 1 on the next edge of the serial clock, and so on.

The processor always drives, never puts the DT pins in a high impedance state, except when a serial port is in multichannel mode and an inactive time slot occurs.

SPORT interrupts occur on the second system clock (CLKIN) after the serial port latches or drives out the last bit of the serial word.

A serial port configured for external clock and frame sync can start transmitting or receiving data two CLKIN cycles after becoming enabled.

In I2S mode:

• Both SPORTs transmit channels (Tx_A and Tx_B) always transmit simultaneously, each transmitting left and right I2S

channels.

• Both SPORT receive channels (Rx_A and Rx_B) always receive simultaneously, each receiving left and right I2S

channels.

• Data always transmits in MSB format.

• You can select either DMA-driven or interrupt-driven transfers.

• TFS and RFS are the transmit and receive word select signals

• Multichannel operation and companding are not supported.

Both transmitters share a common interrupt vector and both receivers share a common interrupt vector.

To determine the source of an interrupt, applications must check the TXSx or RXSx data buffer status bits, respectively (this applies only for interrupt driven transfers).

When using both transmitters (FS_BOTH=1) and MSTR=1 and DITFS=0, the processor generates a frame sync signal only when both transmit buffers contain data because both transmitters share the same CLKDIV and TFS. So, for continuous transmission, both transmit buffers must contain new data. To enable continuous transmission when only one transmit buffer contains data, set FS_BOTH=0.

When using both transmitters and MSTR=1 and DITFS=1, the processor generates a frame sync signal at the frequency set by FSDIV=x whether or not the transmit buffers contain new data. In this case, the processor ignores the FS_BOTH bit. The DMA controller or the application is responsible for filling the transmit buffers with new data.

The SPORT generates and interrupt when the transmit buffer has a vacancy or whenever the receive buffer has data.

Each transmitter and receiver has it’s own set of DMA registers.

The same DMA channel drives both the left and right I2S channels for the transmitter or for the receiver. The software application must demultiplex the left and right channel data received by the RX buffer (this means that when data is transferred to a receive DMA buffer, the data is interleaved where the left and right data alternate in consecutive locations in memory).

4.4 SPORT DMA Channels and Interrupt Vectors

There are 8 dedicated DMA channels for the I2S channel A and B buffers on both SPORT0 and SPORT1. The IOP addresses for the DMA registers are shown in the table below for each corresponding channel and SPORT data buffer.

Table 6. 8 SPORT DMA channels and data buffers

Chn Data Buffer Address Description 0 Rx0A 0x0060 0x0064 Serial port 0 receive; A data 1 Rx0B 0x0030 0x0034 Serial port 0 receive; B data 2 Rx1A 0x0068 0x006C Serial port 1 receive; A data 3 Rx1B 0x0038 0x003C Serial port 1 receive; B data 4 Tx0A 0x0070 0x0074 Serial port 0 transmit; A data 5 Tx0B 0x0050 0x0054 Serial port 0 transmit; B data 6 Tx1A 0x0078 0x005C Serial port 1 transmit; B data 7 Tx1B 0x0058 0x005C Serial port 1 transmit; B data

Each serial port has a transmit DMA interrupt and a receive DMA interrupt (shown in Table 7 below). With serial port DMA disabled, interrupts occur on a word by word basis, when one word is transmitted or received. Table 7 also shows the interrupt priority, because of their relative location to one another in the interrupt vector table. The lower the interrupt vector address, the higher priority interrupt. Note that channels A and B for the transmit and receive side of each SPORT share the same interrupt location. Thus, data for both DMA buffers is processed at the same time, or on a conditional basis depending on the state of the buffer status bits in the SPORT control registers.

Table 7. ADSP-21065L Serial Port Interrupts

Priority

Interrupt1Function

SPR0I SPORT0 receive DMA channels 0 and 1

SPR1I SPORT1 receive DMA channels 2 and 3

SPT0I SPORT0 transmit DMA channels 4 and 5

SPT1I SPORT1 transmit DMA channels 6 and 7

EP0I Ext. port buffer 0 DMA channel 8

EP1II Ext. port buffer 1 DMA channel 9

Highest

Lowest

Interrupt names are defined in the def21065.h include file supplied

with the ADSP-21000 Family Visual DSP Development Software.

+ 25 hidden pages

Analog Devices AN-21065L-I2S Application Notes

Specifications and Main Features

Frequently Asked Questions

User Manual