ANALOG DEVICES AN-0978 Service Manual

AN-0978

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APPLICATON NOTE

Component Processor Nonstandard Video Formats

by Witold Kaczurba

INTRODUCTION

The purpose of this application note is to assist the user in
configuring the component processor (CP) core to process
the HD, PS, and graphics standards not covered by PRIM_
MODE[3:0] and VID_STD[3:0]. For example, the CP can be
programmed to support other SMPTE HD standards that are
not supported using VID_STD[3:0], such as 720p/50 Hz and
1080i/50 Hz. Graphics standards such as MAC 13 and MAC 16
are examples of RGB nonstandard graphics formats that the CP
can support if configured correctly.

In ADV7401/ADV7403 standard operation, the PRIM_
MODE[3:0] and VID_STD[3:0] controls configure the CP to
process the most common HD, PS, SD, and RGB graphics
formats. (For more information on primary mode and video
standard selection, refer to the ADV7401/ADV7403 hardware
manuals, Integrated Multiformat SDTV/HDTV Video Decoder
and RGB Graphics Digitizer, which list the supported modes.)

This application note describes how to configure the CP to
process nonstandard video formats using the following steps:

1. Choose the appropriate PRIM_MODE[3:0]/VID_STD[3:0].

2. Program the latch clock.

3. Program PLL_DIV_RATIO[11:0].

4. Program FR_LL[10:0].

The PRIM_MODE[3:0]/VID_STD[3:0] Selection for
Nonstandard Formats, Latch Clock, Pixel Clock Generation,
and Free-Run Mode Configuration sections describe each of
these steps, respectively. The Worked Examples section provides
examples.

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AN-0978 Application Note

TABLE OF CONTENTS

Introduction ...................................................................................... 1

CP Core Configuration .................................................................... 3

PRIM_MODE[3:0]/VID_STD[3:0] Selection for

Nonstandard Formats .................................................................. 3

Latch Clock .................................................................................... 3

Pixel Clock Generation ................................................................ 3

Free-Run Mode Configuration ................................................... 4

Worked Examples ............................................................................. 5

Example 1: 720p at 50 Hz .............................................................5

Example 2: MAC 16 ......................................................................6

Example 3: SXGA at 75 Hz

(Subsampled Pixel Clock = 108 MHz) .......................................7

Example 4: VESA 1360 × 768 at 60.015 Hz

(Pixel Clock = 85.5 MHz).............................................................8

Hints ....................................................................................................9

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Application Note AN-0978

HSYNC

PIXELCLOCK

f

f

FREQUENCY

PHASE

DETECTOR

LOW-PASS

FILTER

VOLTAGE-

CONTROLLED

OSCILLATOR

PREDIVIDER

TLLC

OUT

SYNC

IN

FEEDBACK

DIVIDER

CONTROLLED BY

PLL_DIV_RATIO[11:0]

CONTROLLED BY
VCO_RANGE[1:0]

07829-001

CP CORE CONFIGURATION

PRIM_MODE[3:0]/VID_STD[3:0] SELECTION FOR NONSTANDARD FORMATS

The CP can be configured for nonstandard operation by setting
PRIM_MODE[3:0] and VID_STD[3:0] to the nearest available
standard. Ta ble 2 gives examples of PRIM_MODE[3:0] and
VID_STD[3:0] selections for nonstandard formats. A selection
should be based on the best match for resolution and pixel clock
frequency.

LATCH CLOCK

The latch clock is an internal ADC parameter that controls
sampling. The recommended latch clock settings can be set
according to Tabl e 1.

Table 1. Latch Clock Settings

LATCH_CLK[3:0]

0001 13.5 to 54
0010 55 to 100
0101 108
0110 135

Pixel Clock (MHz)

PIXEL CLOCK GENERATION

The ADV7401/ADV7403 use a PLL to synthesize a pixel clock
(TLLC) from the incoming Hsyncs. For nonstandard video
formats, the PLL can be configured manually to derive a pixel
clock of arbitrary frequency. This is achieved by programming
the PLL feedback divider block (refer to Figure 1).

First, the user must set PLL_DIV_MAN_EN to 1 to enable manual
programming of the PLL block. Then, for a nonstandard mode,
PLL_DIV_RATIO[11:0] is set to give the required pixel clock.

Two methods are available to calculate this value of PLL_DIV_
RATIO[11:0]. The user chooses one of these methods depending
on the information available about the nonstandard format.

Method 1 is detailed in Equation 1 where the pixel clock fre­quency is divided by the incoming Hsync frequency. This
equation describes the multiplying process of the PLL to
generate a pixel clock from the incoming Hsyncs.

PLL_DIV_RATIO[11:0] =

Method 2 follows the rule that PLL_DIV_RATIO[11:0] is always
equal to the number of luma sample pixel periods per total line.

(1)

Table 2. Examples of PRIM_MODE[3:0]/VID_STD[3:0] Selections for Nonstandard Formats

Nonstandard Video Format ADV7401/ADV7403 CP Default Configurations

Format Resolution Pixel Clock (MHz) PRIM_MODE[3:0] VID_STD[3:0] Format Resolution Pixel Clock (MHz)

VGA 70 640 × 480 28.561 0010 1001 VGA 72 640 × 480 31.515
WVGA60 852 × 480 34.000 0010 0000 SVGA 56 800 × 600 36.00
MAC 13 640 × 480 30.240 0010 1001 VGA 72 640 × 480 31.515
MAC 21 1152 × 870 100.00 0010 1111 XGA 85 1024 × 768 94.5
1080i/50 Hz 1920 × 1080 74.25 0001 1100 HD 1080/60 1920 × 1080 74.25

Figure 1. PLL Architecture

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AN-0978 Application Note

MHZXTAL

PERIODLINE

t

t

_

VCO_RANGE[1:0] and PLL_QPUMP[2:0] Manual Configuration

VCO_RANGE[1:0] and PLL_QPUMP[2:0] must be set to
configure the PLL to generate a stable TLLC. The recommended
VCO range and PLL charge pump settings can be set according
to Table 3 and Tab le 4.

Table 3. Nonstandard Video Format VCO Range Settings

VCO_RANGE[1:0]

00 13.5 to 29
01 30 to 44
10 45 to 89
11 90 to 140

Pixel Clock (MHz)

Table 4. Nonstandard Video Format PLL Settings

Charge Pump Current, PLL_QPUMP[2:0] Pixel Clock (MHz)

001 <22
011 ≥22
100 ≥31
101 ≥42
011 ≥45
100 ≥48
101 ≥58
100 ≥90
101 ≥95
110 ≥136
111 ≥205

The settings of VCO_RANGE[1:0] become active only if VCO_
RANGE_MAN is set to 1. The appropriate VCO range is selected
automatically for all standards supported by PRIM_MODE[3:0]
and VID_STD[3:0].

Subsampling Input Video

It is also possible to subsample the input video by adjusting the
PLL divider ratio. This allows the CP to process a standard
format at a lower horizontal resolution (luma samples per line)
while keeping the same vertical resolution (lines per frame).
Care should be taken to band limit the incoming video signal to
prevent aliasing distortion.

Using subsampling, the CP can also process a video format with
a resolution and pixel clock that are higher than the specifications

of the ADV7401/ADV7403. For example, UXGA at 60 Hz
(1600 × 1200) has a pixel clock at 162 MHz, which is above the
maximum sample rate of the ADC. By using the PLL to generate a
108 MHz clock from the incoming Hsyncs, the 1200 line resolu­tion can be processed by the CP. The lower pixel clock gives a
lower horizontal resolution with just 1440 luma samples per total
line (S/TL) instead of 1600 S/TL in the full bandwidth signal.

FREE-RUN MODE CONFIGURATION

The free-run function in the ADV7401/ADV7403 enables a
blue screen output to be displayed when the CP core enters the
unlocked state. The CP uses the line length measurement to decide
when to go into the free-run state. The CP uses VID_STD[3:0]
to determine the expected line length. The CP must be manually
programmed to expect a different line length for nonstandard
formats.

The FR_LL (free-run line length) parameter is the number of
crystal clock cycles in the ideal line length of the video format.
CP uses this parameter to detect when the line length has changed,
either when the input format changes or when there is no input
present. This parameter is normally decoded from VID_STD[3:0]
and PRIM_MODE[3:0].

When the measured line length differs from FR_LL[11:0] by
32 clock cycles (this threshold can be set in CP_F_RUN_TH[2:0]),
the CP core goes into the unlocked state and enters into free-run
mode. To configure the CP for nonstandard video, the FR_LL[11:0]
must be set manually. This enables it to ignore the default line
length associated with the corresponding VID_STD[3:0].

To calculate the FR_LL[11:0] manual parameter, the line period
is divided by the 27 MHz clock period (for a 27 MHz crystal) or

28.6363 MHz clock period (for a 28.6363 MHz crystal); refer to
Equation 2. The numerator in this equation can be calculated
directly from the Hysnc period, or by using the total number of
luma pixel periods per line, multiplied by the pixel clock period.

FR_LL[11:0] =

where t

XTA L_M HZ

t

28.6363MHZ

= t

for a 27 MHz crystal or t

27 MHZ

for a 28.6363 MHz crystal.

(2)

=

XTAL _MHZ

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