ANALOG DEVICES ADSP-2191 Service Manual

ADSP-219x/2191 DSP

Hardware Reference

Analog Devices, Inc. Digital Signal Processor Division One Technology Way Norwood, Mass. 02062-9106

Revision 1.1, August 2003

Part Number 82-00390-06

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, VisualDSP, and the VisualDSP logo are registered trademarks of Analog Devices, Inc.

CROSSCORE, the CROSSCORE logo, VisualDSP++ and the VisualDSP++ logo are trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ............................................................... xxix

Intended Audience ....................................................................... xxix

Manual Contents .......................................................................... xxx

Additional Literature .................................................................... xxxi

What’s New in This Manual ........................................................ xxxii

Technical or Customer Support ................................................... xxxii

Processor Family ........................................................................ xxxiii

Product Information ................................................................. xxxiii

DSP Product Information ..................................................... xxxiii

Product Related Documents ................................................. xxxiv

Technical Publications Online or on the Web ......................... xxxv

Printed Manuals .................................................................... xxxv

VisualDSP++ and Tools Manuals ...................................... xxxvi

Hardware Manuals ........................................................... xxxvi

Data Sheets ...................................................................... xxxvi

Recommendations for Improving Our Documents ............... xxxvii

Conventions ............................................................................. xxxvii

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INTRODUCTION

Overview—Why Fixed-Point DSP? ............................................... 1-1

ADSP-219x Design Advantages ..................................................... 1-2

ADSP-219x Architecture .............................................................. 1-6

Overview ................................................................................ 1-6

DSP Core Architecture ............................................................ 1-8

DSP Peripherals Architecture ................................................. 1-10

Memory Architecture ............................................................ 1-13

Internal (On-Chip) Memory ............................................. 1-14

External (Off-Chip) Memory ............................................ 1-16

Interrupts ............................................................................. 1-17

DMA Controller ................................................................... 1-17

Host Port .............................................................................. 1-18

DSP Serial Ports (SPORTs) ................................................... 1-18

Serial Peripheral Interface (SPI) Ports .................................... 1-19

UART Port ........................................................................... 1-20

Programmable Flag (PFx) Pins ............................................... 1-20

Low-Power Operation ........................................................... 1-21

Clock Signals ........................................................................ 1-21

Booting Modes ..................................................................... 1-22

JTAG Port ............................................................................ 1-22

Differences from Previous DSPs .................................................. 1-23

Computational Units and Data Register File .......................... 1-25

Arithmetic Status (ASTAT) Register Latency .......................... 1-25

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NORM and EXP Instruction Execution ................................. 1-25

Shifter Result (SR) Register as Multiplier Dual Accumulator ... 1-25

Shifter Exponent (SE) Register is Not Memory Accessible ....... 1-26

Software Condition (SWCOND) Register and

Condition Code (CCODE) Register ................................... 1-26

Unified Memory Space .......................................................... 1-28

Data Memory Page (DMPG1 and DMPG2) Registers ............ 1-28

Data Address Generator (DAG) Addressing Modes ................. 1-28

Base Registers for Circular Buffers .......................................... 1-29

Program Sequencer, Instruction Pipeline, and Stacks .............. 1-30

Conditional Execution (Difference in Flag Input Support) ...... 1-30

Execution Latencies (Different for JUMP Instructions) ........... 1-31

Development Tools ..................................................................... 1-31

COMPUTATIONAL UNITS

Overview ...................................................................................... 2-1

Data Formats ................................................................................ 2-5

Binary String ........................................................................... 2-6

Unsigned ................................................................................. 2-6

Signed Numbers: Twos Complement ....................................... 2-7

Signed Fractional Representation: 1.15 .................................... 2-7

ALU Data Types ...................................................................... 2-7

Multiplier Data Types .............................................................. 2-8

Shifter Data Types ................................................................... 2-9

Arithmetic Formats Summary .................................................. 2-9

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Setting Computational Modes .................................................... 2-11

Latching ALU Result Overflow Status ................................... 2-12

Saturating ALU Results on Overflow ..................................... 2-12

Using Multiplier Integer and Fractional Formats .................... 2-13

Rounding Multiplier Results ................................................. 2-15

Unbiased Rounding .......................................................... 2-15

Biased Rounding .............................................................. 2-17

Using Computational Status ....................................................... 2-18

Arithmetic Logic Unit (ALU) ...................................................... 2-18

ALU Operation ..................................................................... 2-19

ALU Status Flags ................................................................... 2-19

ALU Instruction Summary .................................................... 2-20

ALU Data Flow Details ......................................................... 2-23

ALU Division Support Features ............................................. 2-25

Multiply/Accumulates (Multiplier) .............................................. 2-30

Multiplier Operation ............................................................. 2-31

Placing Multiplier Results in the MR or SR Registers ........ 2-32

Clearing, Rounding, or Saturating Multiplier Results ......... 2-33

Multiplier Status Flags ........................................................... 2-34

Saturating Multiplier Results on Overflow ............................. 2-34

Multiplier Instruction Summary ............................................ 2-36

Multiplier Data Flow Details ................................................. 2-37

Barrel Shifter (Shifter) ................................................................ 2-39

Shifter Operations ................................................................. 2-40

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Derive Block Exponent ..................................................... 2-42

Immediate Shifts ............................................................... 2-43

Denormalize ..................................................................... 2-45

Normalize, Single-Precision Input ..................................... 2-47

Normalize, ALU Result Overflow ...................................... 2-48

Normalize, Double-Precision Input ................................... 2-51

Shifter Status Flags ................................................................ 2-54

Shifter Instruction Summary .................................................. 2-55

Shifter Data Flow Details ....................................................... 2-56

Data Register File ........................................................................ 2-61

Secondary (Alternate) Data Registers ........................................... 2-63

Multifunction Computations ...................................................... 2-64

PROGRAM SEQUENCER

Overview ...................................................................................... 3-1

Instruction Pipeline ...................................................................... 3-7

Instruction Cache ......................................................................... 3-9

Using the Cache .................................................................... 3-12

Optimizing Cache Usage ....................................................... 3-12

Branches and Sequencing ............................................................ 3-13

Indirect Jump Page (IJPG) Register ........................................ 3-16

Conditional Branches ............................................................ 3-16

Delayed Branches .................................................................. 3-17

Loops and Sequencing ................................................................. 3-20

Managing Loop Stacks ........................................................... 3-24

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Restrictions on Ending Loops ................................................ 3-24

Interrupts and Sequencing .......................................................... 3-25

Overview .............................................................................. 3-25

Sensing Interrupts ................................................................. 3-30

Masking Interrupts ............................................................... 3-31

Latching Interrupts ............................................................... 3-31

Interrupt Vector Table ........................................................... 3-32

Stacking Status During Interrupts .......................................... 3-33

Nesting Interrupts ................................................................. 3-34

Interrupt Latency .................................................................. 3-35

Placing the DSP in Idle Mode ............................................... 3-36

Stacks and Sequencing ................................................................ 3-36

Conditional Sequencing .............................................................. 3-41

Sequencer Instruction Summary .................................................. 3-44

DATA ADDRESS GENERATORS (DAGS)

Overview ...................................................................................... 4-1

Setting DAG Modes ..................................................................... 4-4

Secondary (Alternate) DAG Registers ...................................... 4-4

Bit-Reverse Addressing Mode .................................................. 4-6

Data Memory Page Registers (DMPGx) ................................... 4-7

Using DAG Status ........................................................................ 4-8

DAG Operations .......................................................................... 4-9

Addressing with DAGs ............................................................ 4-9

Addressing Circular Buffers ................................................... 4-12

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Addressing with Bit-Reversed Addresses ................................. 4-16

Modifying DAG Registers ...................................................... 4-20

DAG Register Transfer Restrictions ............................................. 4-21

DAG Instruction Summary ......................................................... 4-23

MEMORY

Overview ...................................................................................... 5-1

Internal Address and Data Buses .............................................. 5-4

External Address and Data Buses .............................................. 5-6

Internal Data Bus Exchange ..................................................... 5-7

ADSP-2191 DSP Memory Map .................................................... 5-9

Overview .............................................................................. 5-11

Internal Memory Space .......................................................... 5-12

External Memory Space ......................................................... 5-13

System Control Registers ....................................................... 5-15

I/O Memory Space ................................................................ 5-16

Boot Memory Space .............................................................. 5-16

Shadow Write FIFO .............................................................. 5-17

Data Move Instruction Summary ................................................. 5-18

I/O PROCESSOR

System Interrupt Controller .......................................................... 6-1

Configuring System Interrupts ................................................. 6-4

Interrupt Setup Examples ........................................................ 6-4

Servicing System Interrupts ..................................................... 6-6

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DMA Controller .......................................................................... 6-7

Descriptor-Based DMA Transfers .......................................... 6-11

Autobuffer-Based DMA Transfers .......................................... 6-14

Interrupts from DMA Transfers ............................................. 6-15

Setting Peripheral DMA Modes .................................................. 6-17

DMA Channels ..................................................................... 6-17

MemDMA DMA Settings ..................................................... 6-21

Host Port DMA Settings ....................................................... 6-22

Serial Port DMA Settings ...................................................... 6-23

SPI Port DMA Settings ......................................................... 6-23

UART Port DMA Settings .................................................... 6-25

Working with Peripheral DMA Modes ........................................ 6-26

Using MemDMA DMA ........................................................ 6-27

Using Host Port DMA .......................................................... 6-28

Using Serial Port (SPORT) DMA .......................................... 6-30

Descriptor-Based SPORT DMA ....................................... 6-30

Autobuffer-Based SPORT DMA ....................................... 6-31

SPORT DMA Data Packed/Unpacked Enable ................... 6-32

Using SPI Port DMA ............................................................ 6-33

SPI DMA in Master Mode ................................................ 6-33

SPI DMA in Slave Mode ................................................... 6-35

SPI DMA Errors ............................................................... 6-37

Using UART Port DMA ........................................................ 6-39

Boot Mode DMA Transfers ......................................................... 6-41

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Code Example: Internal Memory DMA ....................................... 6-42

EXTERNAL PORT

Overview ...................................................................................... 7-1

Setting External Port Modes .......................................................... 7-3

Memory Bank and Memory Space Settings ............................... 7-3

External Bus Settings ............................................................... 7-5

Bus Master Settings ................................................................. 7-7

Boot Memory Space Settings ................................................... 7-7

Working with External Port Modes ................................................ 7-9

Using Memory Bank/Space Waitstates Modes ........................... 7-9

Using Memory Bank/Space Clock Modes ............................... 7-10

Using External Memory Banks and Pages ............................... 7-11

Using Memory Access Status .................................................. 7-12

Using Bus Master Modes ....................................................... 7-13

Using Boot Memory Space ..................................................... 7-14

Reading from Boot Memory .............................................. 7-15

Writing to Boot Memory ................................................... 7-15

Interfacing to External Memory ................................................... 7-15

Data Alignment—Logical vs. Physical Address ....................... 7-16

Memory Interface Pins .......................................................... 7-21

Memory Interface Timing ...................................................... 7-24

Code Example: BMS Run-Time Access ........................................ 7-28

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HOST PORT

Overview ...................................................................................... 8-1

Host Port Setup Parameters ........................................................... 8-5

Overview ................................................................................ 8-5

Data Bus Width and Address Bus ............................................ 8-6

Packing Parameters ................................................................. 8-7

Control Signals ....................................................................... 8-9

Address Latch Enable/Address Cycle Control (HALE) ......... 8-9

HRD and HWR Data Strobes ........................................... 8-10

Read and Write Timing Diagrams ......................................... 8-11

Acknowledge/Ready .......................................................... 8-11

Direct Access Mode Transactions ................................................ 8-18

Direct Access Mode ............................................................... 8-18

Direct Access Read Modes ..................................................... 8-19

Direct Access Mode Timing Diagrams ................................... 8-20

Host Port DMA Mode Transactions ............................................ 8-24

Host Port DMA Mode .......................................................... 8-25

Host Port DMA Controller ................................................... 8-27

Bus Arbitration and Usage Restrictions .................................. 8-28

Using Semaphores ................................................................. 8-30

Host Port DMA Mode Timing Diagrams ............................... 8-30

Interrupt Interface ................................................................ 8-31

Setting Up the Host Port ............................................................ 8-32

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SERIAL PORTS (SPORTS)

Overview ...................................................................................... 9-1

SPORT Operation ................................................................... 9-5

SPORT Disable ....................................................................... 9-7

Setting SPORT Modes .................................................................. 9-9

Overview ................................................................................ 9-9

Transmit Configuration (SPx_TCR) Register and

Receive Configuration (SPx_RCR) Register ......................... 9-12

Transmit (SPx_TX) Data Buffer and

Receive Data Buffer (SPx_RX) ............................................ 9-19

Clock and Frame Sync Frequencies ........................................ 9-20

Maximum Clock Rate Restrictions .................................... 9-22

Frame Sync and Clock Example ......................................... 9-22

Data Word Formats ............................................................... 9-22

Word Length .................................................................... 9-23

Endian Format .................................................................. 9-23

Data Type ......................................................................... 9-23

Companding ..................................................................... 9-24

Clock Signal Options ............................................................ 9-25

Frame Sync Options .............................................................. 9-25

Framed vs. Unframed ........................................................ 9-26

Internal vs. External Frame Syncs ...................................... 9-27

Active Low vs. Active High Frame Syncs ............................ 9-28

Sampling Edge for Data and Frame Syncs .......................... 9-28

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Early vs. Late Frame Syncs (Normal and Alternate Timing) 9-29

Data-Independent Transmit Frame Sync ........................... 9-30

Multichannel Operation ........................................................ 9-32

Overview .......................................................................... 9-32

Frame Syncs in Multichannel Mode .................................. 9-35

Multichannel Frame Delay ................................................ 9-36

Window Size .................................................................... 9-36

Window Offset ................................................................. 9-36

Other Multichannel Fields in SPx_TCR and SPx_RCR ..... 9-37

Channel Selection Registers .............................................. 9-38

Multichannel Enable ......................................................... 9-39

Multichannel DMA Data Packing ..................................... 9-39

Multichannel TX FIFO Prefetch ....................................... 9-40

Multichannel Mode Example ............................................ 9-41

Moving Data Between SPORTs and Memory .............................. 9-42

SPORT DMA Autobuffer Mode Example .............................. 9-42

SPORT Descriptor-Based DMA Example .............................. 9-44

Support for Standard Protocols ................................................... 9-46

2X Clock Recovery Control ................................................... 9-46

SPORT Pin/Line Terminations ................................................... 9-47

Timing Examples ........................................................................ 9-47

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

Overview .................................................................................... 10-2

Interface Signals ......................................................................... 10-6

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Serial Peripheral Interface Clock Signal (SCK) ........................ 10-6

Serial Peripheral Interface Slave Select Input Signal (SPISS) .... 10-6

Master Out Slave In (MOSI) ................................................. 10-7

Master In Slave Out (MISO) ................................................. 10-7

Interrupt Behavior ................................................................. 10-7

SPI Registers ............................................................................... 10-8

SPI Baud Rate (SPIBAUDx) Registers .................................... 10-9

SPI Control (SPICTLx) Registers ......................................... 10-10

SPI Flag (SPIFLGx) Register ................................................ 10-12

Slave-Select Inputs .......................................................... 10-15

Using the SPIFLG Register’s FLS Bits

for Multiple-Slave SPI Systems ..................................... 10-15

SPI Status (SPISTx) Registers .............................................. 10-16

Transmit Data Buffer (TDBRx) Registers ............................. 10-18

Receive Data Buffer (RDBRx) Registers ............................... 10-19

Data Shift (SFDR) Register ................................................. 10-19

SPI Transfer Formats ................................................................. 10-21

SPI General Operation .............................................................. 10-23

Overview ............................................................................ 10-24

Clock Signals ...................................................................... 10-25

Master Mode Operation ...................................................... 10-25

Transfer Initiation from Master (Transfer Modes) ................. 10-26

Slave Mode Operation ..................................................... 10-27

Slave Ready for a Transfer ................................................ 10-28

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Error Signals and Flags ............................................................. 10-29

Mode-Fault Error (MODF) ................................................. 10-29

Transmission Error (TXE) Bit ............................................. 10-30

Reception Error (RBSY) Bit ................................................ 10-30

Transmit Collision Error (TXCOL) Bit ............................... 10-31

Beginning and Ending an SPI Transfer ...................................... 10-31

DMA ....................................................................................... 10-32

SPI Example ............................................................................. 10-33

UART PORT

Overview .................................................................................... 11-1

Serial Communications ............................................................... 11-3

I/O Mode ................................................................................... 11-5

DMA Mode ............................................................................... 11-6

Descriptors ........................................................................... 11-6

Autobuffer Mode .................................................................. 11-8

Mixing Modes ....................................................................... 11-9

Code Examples ........................................................................... 11-9

Initializing the UART ......................................................... 11-10

Polling the TX Channel ...................................................... 11-10

Interrupt Controlled Transmission ....................................... 11-11

Using Descriptor DMA on the UART TX Channel ............. 11-12

Setting Up Autobuffer DMA on the UART TX Channel ...... 11-14

Auto-Baud Rate Detection Using Timer 0 ........................... 11-15

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TIMER

Overview .................................................................................... 12-1

Pulsewidth Modulation (PWMOUT) Mode ........................... 12-6

PWM Waveform Generation ............................................. 12-8

Single-Pulse Generation .................................................. 12-10

Pulsewidth Count and Capture (WDTH_CAP) Mode ......... 12-11

Auto-Baud Mode ............................................................ 12-13

External Event Watchdog (EXT_CLK) Mode ....................... 12-14

Code Examples ......................................................................... 12-14

Timer Example Steps ........................................................... 12-15

Timer0 Initialization Routine .............................................. 12-18

Timer Interrupt Service Routine .......................................... 12-20

JTAG TEST-EMULATION PORT

Overview .................................................................................... 13-2

JTAG Test Access Port ................................................................. 13-2

Instruction Register ..................................................................... 13-3

Bypass Register ........................................................................... 13-4

Boundary Register ....................................................................... 13-5

IDCODE Register ...................................................................... 13-5

References ................................................................................... 13-5

SYSTEM DESIGN

Pin Descriptions ......................................................................... 14-2

Recommendations for Unused Pins ........................................ 14-8

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Pin States at Reset ....................................................................... 14-8

Resetting the Processor (“Hard Reset”) ...................................... 14-12

Resetting the Processor (“Soft Reset”) ........................................ 14-15

Booting the Processor (“Boot Loading”) .................................... 14-16

Boot Modes ........................................................................ 14-16

SPI Port and UART Port Booting ........................................ 14-18

Host Port Booting ............................................................... 14-19

External Memory Interface Booting ..................................... 14-20

Bootstream Format ............................................................. 14-21

Configuring and Servicing Interrupts ........................................ 14-27

User-Mappable Interrupts ................................................... 14-28

Managing DSP Clocks .............................................................. 14-29

Using the PLL Control (PLLCTL) Register .......................... 14-32

Designing for Multiplexed Clock Pins ................................. 14-36

Using Clock Modes ............................................................. 14-37

Using Programmable Flags ........................................................ 14-40

Flag Configuration Registers ............................................... 14-41

Flag Direction (DIR) Register ......................................... 14-42

Flag Control (FLAGC and FLAGS) Registers .................. 14-42

Flag Interrupt Mask Registers

(MASKAC, MASKAS, MASKBC, and MASKBS) ......... 14-43

Flag Interrupt Polarity (FSPR) Register ........................... 14-44

Flag Sensitivity (FSSR) Register and

Flag Sensitivity Both Edges (FSBER) Register ............... 14-45

Power-Down Modes ................................................................. 14-45

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Idle Mode ................................................................................. 14-46

Power-Down Core Mode ........................................................... 14-46

Power-Down Core/Peripherals Mode ......................................... 14-47

Power-Down All Mode .............................................................. 14-48

Working with External Bus Masters ........................................... 14-49

Recommended Reading ............................................................. 14-52

Programmable Flags Example .................................................... 14-53

ADSP-219X DSP CORE REGISTERS

Overview ..................................................................................... A-1

Core Registers Summary ......................................................... A-2

Core Status Registers .................................................................... A-8

Arithmetic Status (ASTAT) Register ........................................ A-8

Mode Status (MSTAT) Register .............................................. A-8

System Status (SSTAT) Register ............................................ A-10

Computational Unit Registers .................................................... A-11

Data Register File (Dreg) Registers ........................................ A-12

ALU X Input (AX0, AX1) Registers and

ALU Y Input (AY0, AY1) Registers ..................................... A-13

ALU Results (AR) Register .................................................... A-13

ALU Feedback (AF) Register ................................................. A-13

Multiplier X Input (MX0, MX1) Registers and

Multiplier Y Input (MY0, MY1) Registers .......................... A-13

Multiplier Results (MR2, MR1, MR0) Registers .................... A-14

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Shifter Input (SI) Register ..................................................... A-14

Shifter Exponent (SE) Register and

Shifter Block Exponent (SB) Register .................................. A-14

Shifter Result (SR2, SR1, SR0) Registers ............................... A-14

Program Sequencer Registers ....................................................... A-15

Interrupt Mask (IMASK) Register and

Interrupt Latch (IRPTL) Register ....................................... A-15

Interrupt Control (ICNTL) Register ...................................... A-15

Indirect Jump Page (IJPG) Register ....................................... A-17

PC Stack Page (STACKP) Register and

PC Stack Address (STACKA) Register ................................. A-17

Loop Stack Page (LPSTACKP) Register and

Loop Stack Address (LPSTACKA) Register ......................... A-17

Counter (CNTR) Register ..................................................... A-18

Condition Code (CCODE) Register ...................................... A-18

Cache Control (CACTL) Register ......................................... A-19

Data Address Generator Registers ................................................ A-20

Index (Ix) Registers ............................................................... A-21

Modify (Mx) Registers .......................................................... A-21

Length (Lx) Registers and Base (Bx) Registers ........................ A-21

Data Memory Page (DMPGx) Registers ................................. A-21

Memory Interface Registers ......................................................... A-22

PM Bus Exchange (PX) Register ............................................ A-22

I/O Memory Page (IOPG) Register ....................................... A-22

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ADSP-2191 DSP I/O REGISTERS

I/O Processor Registers ................................................................. B-2

Clock and System Control Registers ........................................... B-17

PLL Control (PLLCTL) Register .......................................... B-17

PLL Lock Counter (LOCKCNT) Register ............................. B-19

Software Reset (SWRST) Register ........................................ B-19

Next System Configuration (NXTSCR) Register ................... B-19

System Configuration (SYSCR) Register ............................... B-20

System Interrupt Controller Registers ......................................... B-21

Interrupt Priority (IPRx) Registers ........................................ B-22

Interrupt Source (INTRDx) Registers ................................... B-25

DMA Controller Registers .......................................................... B-27

MemDMA Channel Write Pointer

(DMACW_PTR) Register ................................................. B-29

MemDMA Channel Write Configuration

(DMACW_CFG) Register ................................................. B-29

MemDMA Channel Write Start Page

(DMACW_SRP) Register .................................................. B-31

MemDMA Channel Write Start Address

(DMACW_SRA) Register .................................................. B-31

MemDMA Channel Write Count

(DMACW_CNT) Register ................................................ B-31

MemDMA Channel Write Chain Pointer

(DMACW_CP) Register .................................................... B-32

MemDMA Channel Write Chain Pointer Ready

(DMACW_CPR) Register ................................................. B-32

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MemDMA Channel Write Interrupt

(DMACW_IRQ) Register .................................................. B-32

MemDMA Channel Read Pointer

(DMACR_PTR) Register ................................................... B-33

MemDMA Channel Read Configuration

(DMACR_CFG) Register ................................................... B-33

MemDMA Channel Read Start Page

(DMACR_SRP) Register .................................................... B-33

MemDMA Channel Read Start Address

(DMACR_SRA) Register .................................................... B-34

MemDMA Channel Read Count

(DMACR_CNT) Register .................................................. B-34

MemDMA Channel Read Chain Pointer

(DMACR_CP) Register ...................................................... B-34

MemDMA Channel Read Chain Pointer Ready

(DMACR_CPR) Register ................................................... B-35

MemDMA Channel Read Interrupt

(DMACR_IRQ) Register .................................................... B-35

SPORT Registers ........................................................................ B-35

SPORT Transmit Configuration (SPx_TCR) Registers ........... B-38

SPORT Receive Configuration (SPx_RCR) Registers ............. B-38

SPORT Transmit Data (SPx_TX) Registers ........................... B-41

SPORT Receive Data (SPx_RX) Registers .............................. B-41

SPORT Transmit Serial Clock Divisor

(SPx_TSCKDIV) Registers and

SPORT Receive Serial Clock Divisor

(SPx_RSCKDIV) Registers ................................................. B-42

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SPORT Transmit Frame Sync Divisor

(SPx_TFSDIV) Registers and SPORT Receive Frame Sync Divisor

(SPx_RFSDIV) Registers ................................................... B-43

SPORT Status (SPx_STATR) Registers ................................. B-43

SPORT Multichannel Transmit Channel Select

(SPx_MTCSx) Registers ..................................................... B-44

SPORT Multichannel Receive Channel Select

(SPx_MRCSx) Registers ..................................................... B-46

SPORT Multichannel Mode Configuration

(SPx_MCMCx) Registers ................................................... B-47

SPORT DMA Receive Pointer (SPxDR_PTR) Registers ........ B-50

SPORT Receive DMA Configuration

(SPxDR_CFG) Registers .................................................... B-50

SPORT Receive DMA Start Page (SPxDR_SRP) Registers ..... B-52

SPORT Receive DMA Start Address (SPxDR_SRA) Registers B-53

SPORT Receive DMA Count (SPxDR_CNT) Registers ........ B-53

SPORT Receive DMA Chain Pointer

(SPxDR_CP) Register ........................................................ B-53

SPORT Receive DMA Chain Pointer Ready

(SPxDR_CPR) Registers .................................................... B-54

SPORT Receive DMA Interrupt (SPxDR_IRQ) Registers ...... B-54

SPORT Transmit DMA Pointer (SPxDT_PTR) Registers ...... B-55

SPORT Transmit DMA Configuration

(SPxDT_CFG) Registers .................................................... B-56

SPORT Transmit DMA Start Address

(SPxDT_SRA) Registers .................................................... B-56

SPORT Transmit DMA Start Page (SPxDT_SRP) Registers ... B-57

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SPORT Transmit DMA Count (SPxDT_CNT) Registers ....... B-57

SPORT Transmit DMA Chain Pointer

(SPxDT_CP) Registers ....................................................... B-58

SPORT Transmit DMA Chain Pointer Ready

(SPxDT_CPR) Registers ..................................................... B-58

SPORT Transmit DMA Interrupt (SPxDT_IRQ) Registers .... B-59

Serial Peripheral Interface Registers ............................................. B-60

SPI Control (SPICTLx) Registers .......................................... B-61

SPI Flag (SPIFLGx) Registers ................................................ B-63

SPI Status (SPISTx) Registers ................................................ B-65

SPI Transmit Buffer (TDBRx) Registers ................................. B-65

Receive Data Buffer (RDBRx) Registers ................................. B-67

Receive Data Buffer Shadow, SPI (RDBRSx) Registers ........... B-67

SPI Baud Rate (SPIBAUDx) Registers ................................... B-68

SPI DMA Current Pointer (SPIxD_PTR) Registers ................ B-68

SPI DMA Configuration (SPIxD_CFG) Registers .................. B-68

SPI DMA Start Page (SPIxD_SRP) Registers ......................... B-70

SPI DMA Start Address (SPIxD_SRA) Registers .................... B-70

SPI DMA Word Count (SPIxD_CNT) Registers ................... B-70

SPI DMA Next Chain Pointer (SPIxD_CP) Registers ............. B-71

SPI DMA Chain Pointer Ready (SPIxD_CPR) Registers ........ B-71

SPI DMA Interrupt (SPIxD_IRQ) Registers .......................... B-71

UART Registers .......................................................................... B-72

UART Control Registers ....................................................... B-72

Transmit Hold (THR) Register ......................................... B-74

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CONTENTS

Receive Buffer (RBR) Register .......................................... B-74

Interrupt Enable (IER) Register ........................................ B-75

UART Divisor Latch Registers (DLL and DLH) ............... B-76

Interrupt Identification (IIR) Register .............................. B-77

Line Control (LCR) Register ............................................ B-77

Modem Control (MCR) Register ...................................... B-77

Line Status (LSR) Register ................................................ B-78

Modem Status (MSR) Register ......................................... B-78

Scratch (SCR) Register ..................................................... B-80

UART RX DMA Registers .................................................... B-80

UART DMA Receive Pointer (UARDR_PTR) Register ..... B-81

UART Receive DMA Configuration (UARDR_CFG) Register B-81 UART Receive DMA Start Page

(UARDR_SRP) Register ................................................ B-83

UART Receive DMA Start Address

(UARDR_SRA) Register ............................................... B-83

UART Receive DMA Count (UARDR_CNT) Register ..... B-83

UART Receive DMA Chain Pointer

(UARDR_CP) Register ................................................. B-84

UART Receive DMA Chain Pointer Ready

(UARDR_CPR) Register ............................................... B-84

UART Receive DMA Interrupt Register

(UARDR_IRQ) Register ............................................... B-84

UART TX DMA Registers .................................................... B-85

UART Transmit DMA Pointer (UARDT_PTR) Register ... B-85

ADSP-219x/2191 xxv DSP Hardware Reference

CONTENTS

UART Transmit DMA Configuration

(UARDT_CFG) Register ............................................... B-86

UART Transmit DMA Start Page

(UARDT_SRP) Register ................................................ B-86

UART Transmit DMA Start Address

(UARDT_SRA) Register ................................................ B-86

UART Transmit DMA Count (UARDT_CNT) Register ... B-87 UART Transmit DMA Chain Pointer

(UARDT_CP) Register .................................................. B-87

UART Transmit DMA Chain Pointer Ready

(UARDT_CPR) Register ............................................... B-87

UART Transmit DMA Interrupt

(UARDT_IRQ) Register ................................................ B-87

Timer Registers .......................................................................... B-88

Overview .............................................................................. B-88

Timer Global Status and Control (T_GSRx) Registers ........... B-89

Timer Configuration (T_CFGRx) Registers ........................... B-91

Timer Counter Low Word (T_CNTLx) and

Timer Counter High Word (T_CNTHx) Registers ............. B-91

Timer Period Low Word (T_PRDLx) and

Timer Period High Word (T_PRDHx) Registers ................. B-93

Timer Width Low Word (T_WLRx) Register and

TImer Width High Word (T_WHRx) Register ................... B-94

Programmable Flag Registers ....................................................... B-96

Direction for Flags (DIR) Register ......................................... B-96

Flag (PFx) Interrupt Registers:

Flag Clear (FLAGC) and Flag Set (FLAGS) ........................ B-97

xxvi ADSP-219x/2191

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Flag (PFx) Interrupt Mask Registers ...................................... B-97

Flag Source Polarity (FSPR) Register ..................................... B-98

Flag Source Sensitivity (FSSR) Register ................................. B-98

Flag Sensitivity Both Edges (FSBER) Register ....................... B-99

External Memory Interface Registers ........................................... B-99

External Memory Interface Control/Status

(E_STAT) Register ............................................................ B-100

External Memory Interface Control (EMICTL) Register ....... B-100

Boot Memory Select Control (BMSCTL) Register ................ B-101

Memory Select Control (MSxCTL) Registers ....................... B-103

I/O Memory Select Control (IOMSCTL) Registers .............. B-104

External Port Status (EMISTAT) Register ............................. B-105

Memory Page (MEMPGx) Registers ..................................... B-106

Host Port Registers ................................................................... B-107

Host Port Configuration (HPCR) Register ........................... B-108

Host Port Direct Page (HPPR) Register ................................ B-110

Host Port DMA Error (HPDER) Register ............................ B-110

Host Port Semaphore (HPSMPHx) Registers ....................... B-111

Host Port DMA Pointer (HOSTD_PTR) Register ............... B-111

Host Port DMA Configuration (HOSTD_CFG) Register .... B-112

Host Port DMA Start Page (HOSTD_SRP) Register ............ B-112

Host Port DMA Start Address (HOSTD_SRA) Register ....... B-112

Host Port DMA Word Count (HOSTD_CNT) Register ...... B-114

Host Port DMA Chain Pointer (HOSTD_CP) Register ........ B-114

ADSP-219x/2191 xxvii DSP Hardware Reference

Host Port DMA Chain Pointer Ready

(HOSTD_CPR) Register ................................................. B-114

Host Port DMA Interrupt (HOSTD_IRQ) Register ............. B-115

NUMERIC FORMATS

Un/Signed: Twos Complement Format .......................................... C-1

Integer or Fractional ..................................................................... C-2

Binary Multiplication ................................................................... C-5

Fractional Mode and Integer Mode .......................................... C-6

Block Floating-Point Format ......................................................... C-6

INDEX

-xxviii ADSP-219x/2191 DSP Hardware Reference

PREFACE

Thank you for purchasing and developing systems using ADSP-219x DSPs from Analog Devices.

Purpose of This Manual

The ADSP-219x/2191 DSP Hardware Reference provides architectural information on the ADSP-219x modified Harvard architecture Digital Signal Processor (DSP) core and ADSP-2191 DSP products.

Preface

This functional description also describes the ADSP-2191 memory derivatives, the ADSP-2195 and the ADSP-2196. Most of this manual refers to the ADSP-2191 DSP; refer to the chip data sheets for differences.

The architectural descriptions cover functional blocks, buses, and ports, including all the features and processes they support. For programming information, refer to the ADSP-219x DSP Instruction Set Reference.

Intended Audience

This manual is intended for system designers and programmers who are familiar with digital signal processing (DSP) concepts. Users should have a working knowledge of microcomputer technology and DSP related mathematics.

ADSP-219x/2191 DSP Hardware Reference xxix

Manual Contents

This reference presents instruction information organized by the type of the instruction. Instruction types relate to the machine language opcode for the instruction. On this DSP, the opcodes categorize the instructions by the portions of the DSP architecture that execute the instructions. The following chapters cover the different types of instructions:

• “Introduction” on page 1-1—This chapter describes the DSP .

• “Computational Units” on page 2-1—This chapter describes the arithmetic/logic unit (ALU), multiplier/accumulator (multiplier), and shifter.

• “Program Sequencer” on page 3-1—This chapter describes pro- gram flow.

• “Data Address Generators (DAGs)” on page 4-1—This chapter describes the automatic generation of addresses for indirect addressing.

• “Memory” on page 5-1—This chapter describes how to use inter- nal memory.

• “I/O Processor” on page 6-1—This chapter describes Direct Memory Access (DMA) of DSP memory through the external, host, serial, SPI, and UART ports.

• “External Port” on page 7-1—This chapter describes how to configure, connect, and access external memory or memory-mapped peripherals.

• “Host Port” on page 8-1—This chapter describes how to directly access the DSP memory space, boot space, and I/O space.

• “Serial Ports (SPORTs)” on page 9-1—This chapter describes the serial ports (SPORTS) available on the DSP.

xxx ADSP-219x/2191 DSP Hardware Reference

+ 720 hidden pages

ANALOG DEVICES ADSP-2191 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

PREFACE

Purpose of This Manual

Intended Audience

Manual Contents