ANALOG DEVICES ADSP-2191 Service Manual

ADSP-219x/2191 DSP

Hardware Reference

Analog Devices, Inc.
Digital Signal Processor Division
One Technology Way
Norwood, Mass. 02062-9106

Revision 1.1, August 2003

Part Number
82-00390-06

a

Copyright Information

© 2003 Analog Devices, Inc., ALL RIGHTS RESERVED. This docu­ment may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by impli­cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

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CROSSCORE, the CROSSCORE logo, VisualDSP++ and the Visu­alDSP++ logo are trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of
their respective owners.

CONTENTS

PREFACE

Purpose of This Manual ............................................................... xxix

Intended Audience ....................................................................... xxix

Manual Contents .......................................................................... xxx

Additional Literature .................................................................... xxxi

What’s New in This Manual ........................................................ xxxii

Technical or Customer Support ................................................... xxxii

Processor Family ........................................................................ xxxiii

Product Information ................................................................. xxxiii

DSP Product Information ..................................................... xxxiii

Product Related Documents ................................................. xxxiv

Technical Publications Online or on the Web ......................... xxxv

Printed Manuals .................................................................... xxxv

VisualDSP++ and Tools Manuals ...................................... xxxvi

Hardware Manuals ........................................................... xxxvi

Data Sheets ...................................................................... xxxvi

Recommendations for Improving Our Documents ............... xxxvii

Conventions ............................................................................. xxxvii

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INTRODUCTION

Overview—Why Fixed-Point DSP? ............................................... 1-1

ADSP-219x Design Advantages ..................................................... 1-2

ADSP-219x Architecture .............................................................. 1-6

Overview ................................................................................ 1-6

DSP Core Architecture ............................................................ 1-8

DSP Peripherals Architecture ................................................. 1-10

Memory Architecture ............................................................ 1-13

Internal (On-Chip) Memory ............................................. 1-14

External (Off-Chip) Memory ............................................ 1-16

Interrupts ............................................................................. 1-17

DMA Controller ................................................................... 1-17

Host Port .............................................................................. 1-18

DSP Serial Ports (SPORTs) ................................................... 1-18

Serial Peripheral Interface (SPI) Ports .................................... 1-19

UART Port ........................................................................... 1-20

Programmable Flag (PFx) Pins ............................................... 1-20

Low-Power Operation ........................................................... 1-21

Clock Signals ........................................................................ 1-21

Booting Modes ..................................................................... 1-22

JTAG Port ............................................................................ 1-22

Differences from Previous DSPs .................................................. 1-23

Computational Units and Data Register File .......................... 1-25

Arithmetic Status (ASTAT) Register Latency .......................... 1-25

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NORM and EXP Instruction Execution ................................. 1-25

Shifter Result (SR) Register as Multiplier Dual Accumulator ... 1-25

Shifter Exponent (SE) Register is Not Memory Accessible ....... 1-26

Software Condition (SWCOND) Register and

Condition Code (CCODE) Register ................................... 1-26

Unified Memory Space .......................................................... 1-28

Data Memory Page (DMPG1 and DMPG2) Registers ............ 1-28

Data Address Generator (DAG) Addressing Modes ................. 1-28

Base Registers for Circular Buffers .......................................... 1-29

Program Sequencer, Instruction Pipeline, and Stacks .............. 1-30

Conditional Execution (Difference in Flag Input Support) ...... 1-30

Execution Latencies (Different for JUMP Instructions) ........... 1-31

Development Tools ..................................................................... 1-31

COMPUTATIONAL UNITS

Overview ...................................................................................... 2-1

Data Formats ................................................................................ 2-5

Binary String ........................................................................... 2-6

Unsigned ................................................................................. 2-6

Signed Numbers: Twos Complement ....................................... 2-7

Signed Fractional Representation: 1.15 .................................... 2-7

ALU Data Types ...................................................................... 2-7

Multiplier Data Types .............................................................. 2-8

Shifter Data Types ................................................................... 2-9

Arithmetic Formats Summary .................................................. 2-9

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Setting Computational Modes .................................................... 2-11

Latching ALU Result Overflow Status ................................... 2-12

Saturating ALU Results on Overflow ..................................... 2-12

Using Multiplier Integer and Fractional Formats .................... 2-13

Rounding Multiplier Results ................................................. 2-15

Unbiased Rounding .......................................................... 2-15

Biased Rounding .............................................................. 2-17

Using Computational Status ....................................................... 2-18

Arithmetic Logic Unit (ALU) ...................................................... 2-18

ALU Operation ..................................................................... 2-19

ALU Status Flags ................................................................... 2-19

ALU Instruction Summary .................................................... 2-20

ALU Data Flow Details ......................................................... 2-23

ALU Division Support Features ............................................. 2-25

Multiply/Accumulates (Multiplier) .............................................. 2-30

Multiplier Operation ............................................................. 2-31

Placing Multiplier Results in the MR or SR Registers ........ 2-32

Clearing, Rounding, or Saturating Multiplier Results ......... 2-33

Multiplier Status Flags ........................................................... 2-34

Saturating Multiplier Results on Overflow ............................. 2-34

Multiplier Instruction Summary ............................................ 2-36

Multiplier Data Flow Details ................................................. 2-37

Barrel Shifter (Shifter) ................................................................ 2-39

Shifter Operations ................................................................. 2-40

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Derive Block Exponent ..................................................... 2-42

Immediate Shifts ............................................................... 2-43

Denormalize ..................................................................... 2-45

Normalize, Single-Precision Input ..................................... 2-47

Normalize, ALU Result Overflow ...................................... 2-48

Normalize, Double-Precision Input ................................... 2-51

Shifter Status Flags ................................................................ 2-54

Shifter Instruction Summary .................................................. 2-55

Shifter Data Flow Details ....................................................... 2-56

Data Register File ........................................................................ 2-61

Secondary (Alternate) Data Registers ........................................... 2-63

Multifunction Computations ...................................................... 2-64

PROGRAM SEQUENCER

Overview ...................................................................................... 3-1

Instruction Pipeline ...................................................................... 3-7

Instruction Cache ......................................................................... 3-9

Using the Cache .................................................................... 3-12

Optimizing Cache Usage ....................................................... 3-12

Branches and Sequencing ............................................................ 3-13

Indirect Jump Page (IJPG) Register ........................................ 3-16

Conditional Branches ............................................................ 3-16

Delayed Branches .................................................................. 3-17

Loops and Sequencing ................................................................. 3-20

Managing Loop Stacks ........................................................... 3-24

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Restrictions on Ending Loops ................................................ 3-24

Interrupts and Sequencing .......................................................... 3-25

Overview .............................................................................. 3-25

Sensing Interrupts ................................................................. 3-30

Masking Interrupts ............................................................... 3-31

Latching Interrupts ............................................................... 3-31

Interrupt Vector Table ........................................................... 3-32

Stacking Status During Interrupts .......................................... 3-33

Nesting Interrupts ................................................................. 3-34

Interrupt Latency .................................................................. 3-35

Placing the DSP in Idle Mode ............................................... 3-36

Stacks and Sequencing ................................................................ 3-36

Conditional Sequencing .............................................................. 3-41

Sequencer Instruction Summary .................................................. 3-44

DATA ADDRESS GENERATORS (DAGS)

Overview ...................................................................................... 4-1

Setting DAG Modes ..................................................................... 4-4

Secondary (Alternate) DAG Registers ...................................... 4-4

Bit-Reverse Addressing Mode .................................................. 4-6

Data Memory Page Registers (DMPGx) ................................... 4-7

Using DAG Status ........................................................................ 4-8

DAG Operations .......................................................................... 4-9

Addressing with DAGs ............................................................ 4-9

Addressing Circular Buffers ................................................... 4-12

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Addressing with Bit-Reversed Addresses ................................. 4-16

Modifying DAG Registers ...................................................... 4-20

DAG Register Transfer Restrictions ............................................. 4-21

DAG Instruction Summary ......................................................... 4-23

MEMORY

Overview ...................................................................................... 5-1

Internal Address and Data Buses .............................................. 5-4

External Address and Data Buses .............................................. 5-6

Internal Data Bus Exchange ..................................................... 5-7

ADSP-2191 DSP Memory Map .................................................... 5-9

Overview .............................................................................. 5-11

Internal Memory Space .......................................................... 5-12

External Memory Space ......................................................... 5-13

System Control Registers ....................................................... 5-15

I/O Memory Space ................................................................ 5-16

Boot Memory Space .............................................................. 5-16

Shadow Write FIFO .............................................................. 5-17

Data Move Instruction Summary ................................................. 5-18

I/O PROCESSOR

System Interrupt Controller .......................................................... 6-1

Configuring System Interrupts ................................................. 6-4

Interrupt Setup Examples ........................................................ 6-4

Servicing System Interrupts ..................................................... 6-6

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DMA Controller .......................................................................... 6-7

Descriptor-Based DMA Transfers .......................................... 6-11

Autobuffer-Based DMA Transfers .......................................... 6-14

Interrupts from DMA Transfers ............................................. 6-15

Setting Peripheral DMA Modes .................................................. 6-17

DMA Channels ..................................................................... 6-17

MemDMA DMA Settings ..................................................... 6-21

Host Port DMA Settings ....................................................... 6-22

Serial Port DMA Settings ...................................................... 6-23

SPI Port DMA Settings ......................................................... 6-23

UART Port DMA Settings .................................................... 6-25

Working with Peripheral DMA Modes ........................................ 6-26

Using MemDMA DMA ........................................................ 6-27

Using Host Port DMA .......................................................... 6-28

Using Serial Port (SPORT) DMA .......................................... 6-30

Descriptor-Based SPORT DMA ....................................... 6-30

Autobuffer-Based SPORT DMA ....................................... 6-31

SPORT DMA Data Packed/Unpacked Enable ................... 6-32

Using SPI Port DMA ............................................................ 6-33

SPI DMA in Master Mode ................................................ 6-33

SPI DMA in Slave Mode ................................................... 6-35

SPI DMA Errors ............................................................... 6-37

Using UART Port DMA ........................................................ 6-39

Boot Mode DMA Transfers ......................................................... 6-41

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Code Example: Internal Memory DMA ....................................... 6-42

EXTERNAL PORT

Overview ...................................................................................... 7-1

Setting External Port Modes .......................................................... 7-3

Memory Bank and Memory Space Settings ............................... 7-3

External Bus Settings ............................................................... 7-5

Bus Master Settings ................................................................. 7-7

Boot Memory Space Settings ................................................... 7-7

Working with External Port Modes ................................................ 7-9

Using Memory Bank/Space Waitstates Modes ........................... 7-9

Using Memory Bank/Space Clock Modes ............................... 7-10

Using External Memory Banks and Pages ............................... 7-11

Using Memory Access Status .................................................. 7-12

Using Bus Master Modes ....................................................... 7-13

Using Boot Memory Space ..................................................... 7-14

Reading from Boot Memory .............................................. 7-15

Writing to Boot Memory ................................................... 7-15

Interfacing to External Memory ................................................... 7-15

Data Alignment—Logical vs. Physical Address ....................... 7-16

Memory Interface Pins .......................................................... 7-21

Memory Interface Timing ...................................................... 7-24

Code Example: BMS Run-Time Access ........................................ 7-28

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HOST PORT

Overview ...................................................................................... 8-1

Host Port Setup Parameters ........................................................... 8-5

Overview ................................................................................ 8-5

Data Bus Width and Address Bus ............................................ 8-6

Packing Parameters ................................................................. 8-7

Control Signals ....................................................................... 8-9

Address Latch Enable/Address Cycle Control (HALE) ......... 8-9

HRD and HWR Data Strobes ........................................... 8-10

Read and Write Timing Diagrams ......................................... 8-11

Acknowledge/Ready .......................................................... 8-11

Direct Access Mode Transactions ................................................ 8-18

Direct Access Mode ............................................................... 8-18

Direct Access Read Modes ..................................................... 8-19

Direct Access Mode Timing Diagrams ................................... 8-20

Host Port DMA Mode Transactions ............................................ 8-24

Host Port DMA Mode .......................................................... 8-25

Host Port DMA Controller ................................................... 8-27

Bus Arbitration and Usage Restrictions .................................. 8-28

Using Semaphores ................................................................. 8-30

Host Port DMA Mode Timing Diagrams ............................... 8-30

Interrupt Interface ................................................................ 8-31

Setting Up the Host Port ............................................................ 8-32

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SERIAL PORTS (SPORTS)

Overview ...................................................................................... 9-1

SPORT Operation ................................................................... 9-5

SPORT Disable ....................................................................... 9-7

Setting SPORT Modes .................................................................. 9-9

Overview ................................................................................ 9-9

Transmit Configuration (SPx_TCR) Register and

Receive Configuration (SPx_RCR) Register ......................... 9-12

Register Writes and Effect Latency ......................................... 9-18

Transmit (SPx_TX) Data Buffer and

Receive Data Buffer (SPx_RX) ............................................ 9-19

Clock and Frame Sync Frequencies ........................................ 9-20

Maximum Clock Rate Restrictions .................................... 9-22

Frame Sync and Clock Example ......................................... 9-22

Data Word Formats ............................................................... 9-22

Word Length .................................................................... 9-23

Endian Format .................................................................. 9-23

Data Type ......................................................................... 9-23

Companding ..................................................................... 9-24

Clock Signal Options ............................................................ 9-25

Frame Sync Options .............................................................. 9-25

Framed vs. Unframed ........................................................ 9-26

Internal vs. External Frame Syncs ...................................... 9-27

Active Low vs. Active High Frame Syncs ............................ 9-28

Sampling Edge for Data and Frame Syncs .......................... 9-28

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Early vs. Late Frame Syncs (Normal and Alternate Timing) 9-29

Data-Independent Transmit Frame Sync ........................... 9-30

Multichannel Operation ........................................................ 9-32

Overview .......................................................................... 9-32

Frame Syncs in Multichannel Mode .................................. 9-35

Multichannel Frame Delay ................................................ 9-36

Window Size .................................................................... 9-36

Window Offset ................................................................. 9-36

Other Multichannel Fields in SPx_TCR and SPx_RCR ..... 9-37

Channel Selection Registers .............................................. 9-38

Multichannel Enable ......................................................... 9-39

Multichannel DMA Data Packing ..................................... 9-39

Multichannel TX FIFO Prefetch ....................................... 9-40

Multichannel Mode Example ............................................ 9-41

Moving Data Between SPORTs and Memory .............................. 9-42

SPORT DMA Autobuffer Mode Example .............................. 9-42

SPORT Descriptor-Based DMA Example .............................. 9-44

Support for Standard Protocols ................................................... 9-46

2X Clock Recovery Control ................................................... 9-46

SPORT Pin/Line Terminations ................................................... 9-47

Timing Examples ........................................................................ 9-47

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

Overview .................................................................................... 10-2

Interface Signals ......................................................................... 10-6

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Serial Peripheral Interface Clock Signal (SCK) ........................ 10-6

Serial Peripheral Interface Slave Select Input Signal (SPISS) .... 10-6

Master Out Slave In (MOSI) ................................................. 10-7

Master In Slave Out (MISO) ................................................. 10-7

Interrupt Behavior ................................................................. 10-7

SPI Registers ............................................................................... 10-8

SPI Baud Rate (SPIBAUDx) Registers .................................... 10-9

SPI Control (SPICTLx) Registers ......................................... 10-10

SPI Flag (SPIFLGx) Register ................................................ 10-12

Slave-Select Inputs .......................................................... 10-15

Using the SPIFLG Register’s FLS Bits

for Multiple-Slave SPI Systems ..................................... 10-15

SPI Status (SPISTx) Registers .............................................. 10-16

Transmit Data Buffer (TDBRx) Registers ............................. 10-18

Receive Data Buffer (RDBRx) Registers ............................... 10-19

Data Shift (SFDR) Register ................................................. 10-19

Register Mapping ................................................................ 10-19

SPI Transfer Formats ................................................................. 10-21

SPI General Operation .............................................................. 10-23

Overview ............................................................................ 10-24

Clock Signals ...................................................................... 10-25

Master Mode Operation ...................................................... 10-25

Transfer Initiation from Master (Transfer Modes) ................. 10-26

Slave Mode Operation ..................................................... 10-27

Slave Ready for a Transfer ................................................ 10-28

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Error Signals and Flags ............................................................. 10-29

Mode-Fault Error (MODF) ................................................. 10-29

Transmission Error (TXE) Bit ............................................. 10-30

Reception Error (RBSY) Bit ................................................ 10-30

Transmit Collision Error (TXCOL) Bit ............................... 10-31

Beginning and Ending an SPI Transfer ...................................... 10-31

DMA ....................................................................................... 10-32

SPI Example ............................................................................. 10-33

UART PORT

Overview .................................................................................... 11-1

Serial Communications ............................................................... 11-3

I/O Mode ................................................................................... 11-5

DMA Mode ............................................................................... 11-6

Descriptors ........................................................................... 11-6

Autobuffer Mode .................................................................. 11-8

Mixing Modes ....................................................................... 11-9

Code Examples ........................................................................... 11-9

Initializing the UART ......................................................... 11-10

Polling the TX Channel ...................................................... 11-10

Interrupt Controlled Transmission ....................................... 11-11

Using Descriptor DMA on the UART TX Channel ............. 11-12

Setting Up Autobuffer DMA on the UART TX Channel ...... 11-14

Auto-Baud Rate Detection Using Timer 0 ........................... 11-15

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TIMER

Overview .................................................................................... 12-1

Pulsewidth Modulation (PWMOUT) Mode ........................... 12-6

PWM Waveform Generation ............................................. 12-8

Single-Pulse Generation .................................................. 12-10

Pulsewidth Count and Capture (WDTH_CAP) Mode ......... 12-11

Auto-Baud Mode ............................................................ 12-13

External Event Watchdog (EXT_CLK) Mode ....................... 12-14

Code Examples ......................................................................... 12-14

Timer Example Steps ........................................................... 12-15

Timer0 Initialization Routine .............................................. 12-18

Timer Interrupt Service Routine .......................................... 12-20

JTAG TEST-EMULATION PORT

Overview .................................................................................... 13-2

JTAG Test Access Port ................................................................. 13-2

Instruction Register ..................................................................... 13-3

Bypass Register ........................................................................... 13-4

Boundary Register ....................................................................... 13-5

IDCODE Register ...................................................................... 13-5

References ................................................................................... 13-5

SYSTEM DESIGN

Pin Descriptions ......................................................................... 14-2

Recommendations for Unused Pins ........................................ 14-8

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Pin States at Reset ....................................................................... 14-8

Resetting the Processor (“Hard Reset”) ...................................... 14-12

Resetting the Processor (“Soft Reset”) ........................................ 14-15

Booting the Processor (“Boot Loading”) .................................... 14-16

Boot Modes ........................................................................ 14-16

SPI Port and UART Port Booting ........................................ 14-18

Host Port Booting ............................................................... 14-19

External Memory Interface Booting ..................................... 14-20

Bootstream Format ............................................................. 14-21

Configuring and Servicing Interrupts ........................................ 14-27

User-Mappable Interrupts ................................................... 14-28

Managing DSP Clocks .............................................................. 14-29

Using the PLL Control (PLLCTL) Register .......................... 14-32

Designing for Multiplexed Clock Pins ................................. 14-36

Using Clock Modes ............................................................. 14-37

Using Programmable Flags ........................................................ 14-40

Flag Configuration Registers ............................................... 14-41

Flag Direction (DIR) Register ......................................... 14-42

Flag Control (FLAGC and FLAGS) Registers .................. 14-42

Flag Interrupt Mask Registers

(MASKAC, MASKAS, MASKBC, and MASKBS) ......... 14-43

Flag Interrupt Polarity (FSPR) Register ........................... 14-44

Flag Sensitivity (FSSR) Register and

Flag Sensitivity Both Edges (FSBER) Register ............... 14-45

Power-Down Modes ................................................................. 14-45

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Idle Mode ................................................................................. 14-46

Power-Down Core Mode ........................................................... 14-46

Power-Down Core/Peripherals Mode ......................................... 14-47

Power-Down All Mode .............................................................. 14-48

Working with External Bus Masters ........................................... 14-49

Recommended Reading ............................................................. 14-52

Programmable Flags Example .................................................... 14-53

ADSP-219X DSP CORE REGISTERS

Overview ..................................................................................... A-1

Core Registers Summary ......................................................... A-2

Register Load Latencies .......................................................... A-2

Core Status Registers .................................................................... A-8

Arithmetic Status (ASTAT) Register ........................................ A-8

Mode Status (MSTAT) Register .............................................. A-8

System Status (SSTAT) Register ............................................ A-10

Computational Unit Registers .................................................... A-11

Data Register File (Dreg) Registers ........................................ A-12

ALU X Input (AX0, AX1) Registers and

ALU Y Input (AY0, AY1) Registers ..................................... A-13

ALU Results (AR) Register .................................................... A-13

ALU Feedback (AF) Register ................................................. A-13

Multiplier X Input (MX0, MX1) Registers and

Multiplier Y Input (MY0, MY1) Registers .......................... A-13

Multiplier Results (MR2, MR1, MR0) Registers .................... A-14

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Shifter Input (SI) Register ..................................................... A-14

Shifter Exponent (SE) Register and

Shifter Block Exponent (SB) Register .................................. A-14

Shifter Result (SR2, SR1, SR0) Registers ............................... A-14

Program Sequencer Registers ....................................................... A-15

Interrupt Mask (IMASK) Register and

Interrupt Latch (IRPTL) Register ....................................... A-15

Interrupt Control (ICNTL) Register ...................................... A-15

Indirect Jump Page (IJPG) Register ....................................... A-17

PC Stack Page (STACKP) Register and

PC Stack Address (STACKA) Register ................................. A-17

Loop Stack Page (LPSTACKP) Register and

Loop Stack Address (LPSTACKA) Register ......................... A-17

Counter (CNTR) Register ..................................................... A-18

Condition Code (CCODE) Register ...................................... A-18

Cache Control (CACTL) Register ......................................... A-19

Data Address Generator Registers ................................................ A-20

Index (Ix) Registers ............................................................... A-21

Modify (Mx) Registers .......................................................... A-21

Length (Lx) Registers and Base (Bx) Registers ........................ A-21

Data Memory Page (DMPGx) Registers ................................. A-21

Memory Interface Registers ......................................................... A-22

PM Bus Exchange (PX) Register ............................................ A-22

I/O Memory Page (IOPG) Register ....................................... A-22

Register and Bit #Defines File (def219x.h) .................................. A-22

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ADSP-2191 DSP I/O REGISTERS

I/O Processor Registers ................................................................. B-2

Clock and System Control Registers ........................................... B-17

PLL Control (PLLCTL) Register .......................................... B-17

PLL Lock Counter (LOCKCNT) Register ............................. B-19

Software Reset (SWRST) Register ........................................ B-19

Next System Configuration (NXTSCR) Register ................... B-19

System Configuration (SYSCR) Register ............................... B-20

System Interrupt Controller Registers ......................................... B-21

Interrupt Priority (IPRx) Registers ........................................ B-22

Interrupt Source (INTRDx) Registers ................................... B-25

DMA Controller Registers .......................................................... B-27

MemDMA Channel Write Pointer

(DMACW_PTR) Register ................................................. B-29

MemDMA Channel Write Configuration

(DMACW_CFG) Register ................................................. B-29

MemDMA Channel Write Start Page

(DMACW_SRP) Register .................................................. B-31

MemDMA Channel Write Start Address

(DMACW_SRA) Register .................................................. B-31

MemDMA Channel Write Count

(DMACW_CNT) Register ................................................ B-31

MemDMA Channel Write Chain Pointer

(DMACW_CP) Register .................................................... B-32

MemDMA Channel Write Chain Pointer Ready

(DMACW_CPR) Register ................................................. B-32

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MemDMA Channel Write Interrupt

(DMACW_IRQ) Register .................................................. B-32

MemDMA Channel Read Pointer

(DMACR_PTR) Register ................................................... B-33

MemDMA Channel Read Configuration

(DMACR_CFG) Register ................................................... B-33

MemDMA Channel Read Start Page

(DMACR_SRP) Register .................................................... B-33

MemDMA Channel Read Start Address

(DMACR_SRA) Register .................................................... B-34

MemDMA Channel Read Count

(DMACR_CNT) Register .................................................. B-34

MemDMA Channel Read Chain Pointer

(DMACR_CP) Register ...................................................... B-34

MemDMA Channel Read Chain Pointer Ready

(DMACR_CPR) Register ................................................... B-35

MemDMA Channel Read Interrupt

(DMACR_IRQ) Register .................................................... B-35

SPORT Registers ........................................................................ B-35

SPORT Transmit Configuration (SPx_TCR) Registers ........... B-38

SPORT Receive Configuration (SPx_RCR) Registers ............. B-38

SPORT Transmit Data (SPx_TX) Registers ........................... B-41

SPORT Receive Data (SPx_RX) Registers .............................. B-41

SPORT Transmit Serial Clock Divisor

(SPx_TSCKDIV) Registers and

SPORT Receive Serial Clock Divisor

(SPx_RSCKDIV) Registers ................................................. B-42

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SPORT Transmit Frame Sync Divisor

(SPx_TFSDIV) Registers and
SPORT Receive Frame Sync Divisor

(SPx_RFSDIV) Registers ................................................... B-43

SPORT Status (SPx_STATR) Registers ................................. B-43

SPORT Multichannel Transmit Channel Select

(SPx_MTCSx) Registers ..................................................... B-44

SPORT Multichannel Receive Channel Select

(SPx_MRCSx) Registers ..................................................... B-46

SPORT Multichannel Mode Configuration

(SPx_MCMCx) Registers ................................................... B-47

SPORT DMA Receive Pointer (SPxDR_PTR) Registers ........ B-50

SPORT Receive DMA Configuration

(SPxDR_CFG) Registers .................................................... B-50

SPORT Receive DMA Start Page (SPxDR_SRP) Registers ..... B-52

SPORT Receive DMA Start Address (SPxDR_SRA) Registers B-53

SPORT Receive DMA Count (SPxDR_CNT) Registers ........ B-53

SPORT Receive DMA Chain Pointer

(SPxDR_CP) Register ........................................................ B-53

SPORT Receive DMA Chain Pointer Ready

(SPxDR_CPR) Registers .................................................... B-54

SPORT Receive DMA Interrupt (SPxDR_IRQ) Registers ...... B-54

SPORT Transmit DMA Pointer (SPxDT_PTR) Registers ...... B-55

SPORT Transmit DMA Configuration

(SPxDT_CFG) Registers .................................................... B-56

SPORT Transmit DMA Start Address

(SPxDT_SRA) Registers .................................................... B-56

SPORT Transmit DMA Start Page (SPxDT_SRP) Registers ... B-57

ADSP-219x/2191 xxiii
DSP Hardware Reference

CONTENTS

SPORT Transmit DMA Count (SPxDT_CNT) Registers ....... B-57

SPORT Transmit DMA Chain Pointer

(SPxDT_CP) Registers ....................................................... B-58

SPORT Transmit DMA Chain Pointer Ready

(SPxDT_CPR) Registers ..................................................... B-58

SPORT Transmit DMA Interrupt (SPxDT_IRQ) Registers .... B-59

Serial Peripheral Interface Registers ............................................. B-60

SPI Control (SPICTLx) Registers .......................................... B-61

SPI Flag (SPIFLGx) Registers ................................................ B-63

SPI Status (SPISTx) Registers ................................................ B-65

SPI Transmit Buffer (TDBRx) Registers ................................. B-65

Receive Data Buffer (RDBRx) Registers ................................. B-67

Receive Data Buffer Shadow, SPI (RDBRSx) Registers ........... B-67

SPI Baud Rate (SPIBAUDx) Registers ................................... B-68

SPI DMA Current Pointer (SPIxD_PTR) Registers ................ B-68

SPI DMA Configuration (SPIxD_CFG) Registers .................. B-68

SPI DMA Start Page (SPIxD_SRP) Registers ......................... B-70

SPI DMA Start Address (SPIxD_SRA) Registers .................... B-70

SPI DMA Word Count (SPIxD_CNT) Registers ................... B-70

SPI DMA Next Chain Pointer (SPIxD_CP) Registers ............. B-71

SPI DMA Chain Pointer Ready (SPIxD_CPR) Registers ........ B-71

SPI DMA Interrupt (SPIxD_IRQ) Registers .......................... B-71

UART Registers .......................................................................... B-72

UART Control Registers ....................................................... B-72

Transmit Hold (THR) Register ......................................... B-74

xxiv ADSP-219x/2191

DSP Hardware Reference

CONTENTS

Receive Buffer (RBR) Register .......................................... B-74

Interrupt Enable (IER) Register ........................................ B-75

UART Divisor Latch Registers (DLL and DLH) ............... B-76

Interrupt Identification (IIR) Register .............................. B-77

Line Control (LCR) Register ............................................ B-77

Modem Control (MCR) Register ...................................... B-77

Line Status (LSR) Register ................................................ B-78

Modem Status (MSR) Register ......................................... B-78

Scratch (SCR) Register ..................................................... B-80

UART RX DMA Registers .................................................... B-80

UART DMA Receive Pointer (UARDR_PTR) Register ..... B-81

UART Receive DMA Configuration (UARDR_CFG) Register B-81
UART Receive DMA Start Page

(UARDR_SRP) Register ................................................ B-83

UART Receive DMA Start Address

(UARDR_SRA) Register ............................................... B-83

UART Receive DMA Count (UARDR_CNT) Register ..... B-83

UART Receive DMA Chain Pointer

(UARDR_CP) Register ................................................. B-84

UART Receive DMA Chain Pointer Ready

(UARDR_CPR) Register ............................................... B-84

UART Receive DMA Interrupt Register

(UARDR_IRQ) Register ............................................... B-84

UART TX DMA Registers .................................................... B-85

UART Transmit DMA Pointer (UARDT_PTR) Register ... B-85

ADSP-219x/2191 xxv
DSP Hardware Reference

CONTENTS

UART Transmit DMA Configuration

(UARDT_CFG) Register ............................................... B-86

UART Transmit DMA Start Page

(UARDT_SRP) Register ................................................ B-86

UART Transmit DMA Start Address

(UARDT_SRA) Register ................................................ B-86

UART Transmit DMA Count (UARDT_CNT) Register ... B-87
UART Transmit DMA Chain Pointer

(UARDT_CP) Register .................................................. B-87

UART Transmit DMA Chain Pointer Ready

(UARDT_CPR) Register ............................................... B-87

UART Transmit DMA Interrupt

(UARDT_IRQ) Register ................................................ B-87

Timer Registers .......................................................................... B-88

Overview .............................................................................. B-88

Timer Global Status and Control (T_GSRx) Registers ........... B-89

Timer Configuration (T_CFGRx) Registers ........................... B-91

Timer Counter Low Word (T_CNTLx) and

Timer Counter High Word (T_CNTHx) Registers ............. B-91

Timer Period Low Word (T_PRDLx) and

Timer Period High Word (T_PRDHx) Registers ................. B-93

Timer Width Low Word (T_WLRx) Register and

TImer Width High Word (T_WHRx) Register ................... B-94

Programmable Flag Registers ....................................................... B-96

Direction for Flags (DIR) Register ......................................... B-96

Flag (PFx) Interrupt Registers:

Flag Clear (FLAGC) and Flag Set (FLAGS) ........................ B-97

xxvi ADSP-219x/2191

DSP Hardware Reference

CONTENTS

Flag (PFx) Interrupt Mask Registers ...................................... B-97

Flag Source Polarity (FSPR) Register ..................................... B-98

Flag Source Sensitivity (FSSR) Register ................................. B-98

Flag Sensitivity Both Edges (FSBER) Register ....................... B-99

External Memory Interface Registers ........................................... B-99

External Memory Interface Control/Status

(E_STAT) Register ............................................................ B-100

External Memory Interface Control (EMICTL) Register ....... B-100

Boot Memory Select Control (BMSCTL) Register ................ B-101

Memory Select Control (MSxCTL) Registers ....................... B-103

I/O Memory Select Control (IOMSCTL) Registers .............. B-104

External Port Status (EMISTAT) Register ............................. B-105

Memory Page (MEMPGx) Registers ..................................... B-106

Host Port Registers ................................................................... B-107

Host Port Configuration (HPCR) Register ........................... B-108

Host Port Direct Page (HPPR) Register ................................ B-110

Host Port DMA Error (HPDER) Register ............................ B-110

Host Port Semaphore (HPSMPHx) Registers ....................... B-111

Host Port DMA Pointer (HOSTD_PTR) Register ............... B-111

Host Port DMA Configuration (HOSTD_CFG) Register .... B-112

Host Port DMA Start Page (HOSTD_SRP) Register ............ B-112

Host Port DMA Start Address (HOSTD_SRA) Register ....... B-112

Host Port DMA Word Count (HOSTD_CNT) Register ...... B-114

Host Port DMA Chain Pointer (HOSTD_CP) Register ........ B-114

ADSP-219x/2191 xxvii
DSP Hardware Reference

Host Port DMA Chain Pointer Ready

(HOSTD_CPR) Register ................................................. B-114

Host Port DMA Interrupt (HOSTD_IRQ) Register ............. B-115

Register and Bit #define File (def2191.h) .................................. B-115

NUMERIC FORMATS

Un/Signed: Twos Complement Format .......................................... C-1

Integer or Fractional ..................................................................... C-2

Binary Multiplication ................................................................... C-5

Fractional Mode and Integer Mode .......................................... C-6

Block Floating-Point Format ......................................................... C-6

INDEX

-xxviii ADSP-219x/2191
DSP Hardware Reference

PREFACE

Thank you for purchasing and developing systems using ADSP-219x
DSPs from Analog Devices.

Purpose of This Manual

The ADSP-219x/2191 DSP Hardware Reference provides architectural
information on the ADSP-219x modified Harvard architecture Digital
Signal Processor (DSP) core and ADSP-2191 DSP products.

Preface

This functional description also describes the ADSP-2191 memory deriva­tives, the ADSP-2195 and the ADSP-2196. Most of this manual refers to
the ADSP-2191 DSP; refer to the chip data sheets for differences.

The architectural descriptions cover functional blocks, buses, and ports,
including all the features and processes they support. For programming
information, refer to the ADSP-219x DSP Instruction Set Reference.

Intended Audience

This manual is intended for system designers and programmers who are
familiar with digital signal processing (DSP) concepts. Users should have a
working knowledge of microcomputer technology and DSP related
mathematics.

ADSP-219x/2191 DSP Hardware Reference xxix

Manual Contents

Manual Contents

This reference presents instruction information organized by the type of
the instruction. Instruction types relate to the machine language opcode
for the instruction. On this DSP, the opcodes categorize the instructions
by the portions of the DSP architecture that execute the instructions. The
following chapters cover the different types of instructions:

• “Introduction” on page 1-1—This chapter describes the DSP .

• “Computational Units” on page 2-1—This chapter describes the
arithmetic/logic unit (ALU), multiplier/accumulator (multiplier),
and shifter.

• “Program Sequencer” on page 3-1—This chapter describes pro-
gram flow.

• “Data Address Generators (DAGs)” on page 4-1—This chapter
describes the automatic generation of addresses for indirect
addressing.

• “Memory” on page 5-1—This chapter describes how to use inter-
nal memory.

• “I/O Processor” on page 6-1—This chapter describes Direct Mem­ory Access (DMA) of DSP memory through the external, host,
serial, SPI, and UART ports.

• “External Port” on page 7-1—This chapter describes how to con­figure, connect, and access external memory or memory-mapped
peripherals.

• “Host Port” on page 8-1—This chapter describes how to directly
access the DSP memory space, boot space, and I/O space.

• “Serial Ports (SPORTs)” on page 9-1—This chapter describes the
serial ports (SPORTS) available on the DSP.

xxx ADSP-219x/2191 DSP Hardware Reference

Preface

• “Serial Peripheral Interface (SPI) Ports” on page 10-1—This chap­ter describes the use of the DSP’s two SPI ports.

• “UART Port” on page 11-1—This chapter describes how to use its
UART port.

• “Timer” on page 12-1—This chapter describes how to use the
DSP’s three 32-bit timers.

• “JTAG Test-Emulation Port” on page 13-1—This chapter
describes the use of the DSP’s JTAG port.

• “System Design” on page 14-1—This chapter describes basic sys­tem interface features of the ADSP-219x DSP family processors.

• “ADSP-219x DSP Core Registers” on page A-1—This chapter
describes the DSP core’s general-purpose.

• “ADSP-2191 DSP I/O Registers” on page B-1—This chapter
describes the DSP’s I/O processor registers.

• “Numeric Formats” on page C-1—This chapter describes various
aspects of the 16-bit data format and how to implement a block
floating-point format in software.

Additional Literature

For more information about Analog Devices DSPs and development
products, see the following documents:

• ADSP-2191 DSP Microcomputer Data Sheet

• ADSP-219x DSP Instruction Set Reference

All the manuals are available in PDF format from the software distribu­tion CD-ROM. You can also access these manuals via VisualDSP++
online Help.

ADSP-219x/2191 DSP Hardware Reference xxxi

What’s New in This Manual

What’s New in This Manual

This revision of the ADSP-219x/2191 DSP Hardware Reference includes
fixes to defects logged on the Analog Devices Web site under documenta­tion errata. In addition, the following changes were made:

• A preface was added

• Several block diagrams and descriptions of core DSP components
were updated in Chapter 1 “Introduction”, Chapter 2 “Computa­tional Units”, Chapter 3 “Program Sequencer”, Chapter 4
“Memory”, and Chapter 12 “Timer”.

• Appendix C “Interrupts” was moved to Chapter 6 together with
new information.

Technical or Customer Support

You can reach our DSP Tools Customer Support in the following ways:

• E-mail development tools questions to

[e-mail]

• E-mail processor questions to [e-mail]

• Phone questions to 1800-ANALOGD

• Visit our World Wide Web site at http://www.analog.com/dsp

• Telex questions to 924491, TWX:710/394-6577

• Cable questions to ANALOG NORWOODMASS

• Contact your local Analog Devices sales office or an authorized
Analog Devices distributor

xxxii ADSP-219x/2191 DSP Hardware Reference

Processor Family

The name ADSP-219x refers to the family of Analog Devices 16-bit,
fixed-point processors. VisualDSP++™ currently supports these
processors:

• ADSP-2191

• ADSP-2192-12

• ADSP-2195

• ADSP-2196

• Mixed-signal processors (ADSP-21990, ADSP-21991, and
ADSP-21992)

Preface

Product Information

You can obtain product information from the Analog Devices Web site,
from the product CD-ROM, or from printed documents/manuals.

Analog Devices is online at http://www.analog.com. Our Web site pro­vides information about a broad range of products: analog integrated
circuits, amplifiers, converters, and digital signal processors.

DSP Product Information

For information on digital signal processors, visit our Web site at
http://www.analog.com/dsp. It provides access to technical information
and documentation, product overviews, and product announcements.

ADSP-219x/2191 DSP Hardware Reference xxxiii

Product Information

You may also obtain additional information about Analog Devices and its
products by:

• FAXing questions or requests for information:

1(781)461-3010 (North America) or
089/76 903-557 (Europe Headquarters)

• Accessing the FTP site:

ftp ftp.analog.com or ftp 137.71.23.21 or
ftp://ftp.analog.com

Product Related Documents

For information on product related development software and Analog
Devices processors, see these publications:

• VisualDSP++ Getting Started Guide for 16-Bit Processors

• VisualDSP++ User's Guide for 16-Bit Processors

• VisualDSP++ C/C++ Compiler and Library Manual for ADSP-219x

DSPs

• VisualDSP++ Assembler and Preprocessor Manual for ADSP-218x
and ADSP-219x DSPs

• VisualDSP++ Linker and Utilities Manual for 16-Bit Processors

• VisualDSP++ Loader and Utilities Manual for 16-Bit Processors

• VisualDSP++ Kernel (VDK) User’s Guide for 16-Bit Processors

• VisualDSP++ Component Software Engineering User’s Guide for

16-Bit Processors

xxxiv ADSP-219x/2191 DSP Hardware Reference

Preface

Technical Publications Online or on the Web

You can access DSP (or TigerSHARC processor) documentation in these
ways:

• Online Access using VisualDSP++ Installation CD-ROM

Your VisualDSP++™ software distribution CD-ROM includes all
of the listed VisualDSP++ software tool publications.

After you install VisualDSP++ software on your PC, select the

Help Topics command on the VisualDSP++ Help menu, click the
Reference book icon, and select Online Manuals. From this Help

topic, you can open any of the manuals, which are either in HTML
format or in Adobe Acrobat PDF format.

If you are not using VisualDSP++, you can manually access these
PDF files from the CD-ROM using Adobe Acrobat.

• Web Access

Use the Analog Devices technical publications Web site
http://www.analog.com/industry/dsp/tech_doc/
gen_purpose.html to access DSP publications, including data
sheets, hardware reference manuals, instruction set reference manu­als, and VisualDSP++ software documentation. You can view,
download, or print in PDF format. Some publications are also
available in HTML format.

Printed Manuals

For all your general questions regarding literature ordering, call the Litera­ture Center at 1-800-ANALOGD (1-800-262-5643) and follow the
prompts.

ADSP-219x/2191 DSP Hardware Reference -xxxv

Product Information

VisualDSP++ and Tools Manuals

The VisualDSP++ and Tools manuals can be purchased through your
local Analog Devices sales office or an authorized Analog Devices distribu­tor. These manuals can be purchased only as a kit.

Hardware Manuals

Hardware reference and instruction set reference manuals can be ordered
through the Literature Center at 1-800-ANALOGD (1-800-262-5643) or
downloaded from the Analog Devices Web site. The manuals can be
ordered by a title or by product number located on the back cover of each
manual.

Data Sheets

All data sheets (preliminary and production) can be downloaded from the
Analog Devices Web site. As a general rule, only production (not prelimi­nary) data sheets can be obtained from the Literature Center at
1-800-ANALOGD (1-800-262-5643). You can request data sheets using
part numbers.

If you want to have a data sheet faxed to you, use the Analog Devices Fax­back system at 1-800-446-6212. Follow the prompts, and you can either
get a particular data sheet or a list of the data sheet code numbers faxed to
you. If the data sheet you request is not listed on Faxback, check for it on
the Web site.

-xxxvi ADSP-219x/2191 DSP Hardware Reference

Preface

Recommendations for Improving Our Documents

Please send us your comments and recommendation on how to improve
our manuals. Contact us at:

• Software/Development Tools manuals

[e-mail]

• Data sheets, Hardware and Instruction Reference Set manuals

[e-mail]

Conventions

The following table identifies and describes text conventions used in this
manual.

L

Example Description

Close command
(File menu)

{this | that} Alternative items in syntax descriptions appear within curly brackets

[this | that] Optional items in syntax descriptions appear within brackets and sepa-

[this,…] Optional item lists in syntax descriptions appear within brackets

.SECTION Commands, directives, keywords, and feature names are in text with

filename Non-keyword placeholders appear in text with italic style format.

chapters, may appear throughout this document.

Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close
command appears on the File menu).

and separated by vertical bars; read the example as this or that. One
or the other is required.

rated by vertical bars; read the example as an optional

delimited by commas and terminated with an ellipse; read the example
as an optional comma-separated list of

letter gothic font.

this.

this or that.

Note that additional conventions, which apply only to specific

ADSP-219x/2191 DSP Hardware Reference -xxxvii

Conventions

Example Description

AX0, SR, PX Register names appear in UPPERCASE and keyword font

TMR0E, RESET Pin names appear in UPPERCASE and keyword font; active low sig-

nals appear with an

DRx, MS3-0 Register and pin names in the text may refer to groups of registers or

pins. When a lowercase “x” appears in a register name (e.g., DRx), that
indicates a set of registers (e.g., DR0, DR1, and DR2). A range also may
be shown with a hyphen (e.g.,

MS0).

IF, DO/UNTIL Assembler instructions (mnemonics) appear in UPPERCASE and in

keyword font

This symbol indicates a note that provides supplementary information
on a related topic. In the online Help version of this book, the word
Note appears instead of this symbol.

This symbol indicates a warning that advises on an inappropriate usage
of the product that could lead to undesirable results or product dam­age. In the online Help version of this book, the word Wa rn in g appears
instead of this symbol.

OVERBAR.

MS3-0 indicates MS3, MS2, MS1, and

-xxxviii ADSP-219x/2191 DSP Hardware Reference

Introduction

1 INTRODUCTION

This description covers the ADSP-2191 and memory derivatives, the
ADSP-2195 and the ADSP-2196. Most of this manual refers to the
ADSP-2191 DSP; refer to the chip data sheets for differences.

This chapter provides the following sections:

• “Overview—Why Fixed-Point DSP?” on page 1-1

• “ADSP-219x Design Advantages” on page 1-2

• “ADSP-219x Architecture” on page 1-6

• “Differences from Previous DSPs” on page 1-23

• “Development Tools” on page 1-31

Overview—Why Fixed-Point DSP?

A digital signal processor’s (DSP’s) data format determines its ability to
handle signals of differing precision, dynamic range, and signal-to-noise
ratios. Because 16-bit, fixed-point DSP math is required for certain DSP
coding algorithms, using a 16-bit, fixed-point DSP can provide all the fea­tures needed for certain algorithm and software development efforts. Also,
a narrower bus width (16-bit as opposed to 32- or 64-bit wide) leads to
reduced power consumption and other design savings. The extent to
which this is true depends on the fixed-point processor’s architecture.

ADSP-219x/2191 DSP Hardware Reference 1-1

ADSP-219x Design Advantages

High-level language programmability, large address spaces, and wide
dynamic range allow system development time to be spent on algorithms
and signal processing concerns, rather than assembly language coding,
code paging, and error handling. The ADSP-2191 DSP is a highly inte­grated, 16-bit fixed-point DSP that provides many of these design
advantages.

ADSP-219x Design Advantages

The ADSP-219x family DSPs are high-performance 16-bit DSPs for com­munications, instrumentation, industrial/control, voice/speech, medical,
military, and other applications. These DSPs provide a DSP core that is
compatible with previous ADSP-2100 family DSPs, but provides many
additional features. The ADSP-219x core combines with on-chip periph­erals to form a complete system-on-a-chip. The off-core peripherals add
on-chip SRAM, integrated I/O peripherals, timer, and interrupt
controller.

The ADSP-219x architecture balances a high-performance processor core
with high performance buses (PM, DM, DMA). In the core, every compu­tational instruction can execute in a single cycle. The buses and
instruction cache provide rapid, unimpeded data flow to the core to main­tain the execution rate.

Figure 1-1 on page 1-4 shows a detailed block diagram of the processor,

illustrating the following architectural features:

• Computation units—multiplier, ALU, shifter, and data register file

• Program sequencer with related instruction cache, interval timer,
and Data Address Generators (DAG1 and DAG2)

• Dual-blocked SRAM

• External ports for interfacing to off-chip memory, peripherals, and
hosts

1-2 ADSP-219x/2191 DSP Hardware Reference

Introduction

• Input/Output (I/O) processor with integrated DMA controllers,
serial ports (SPORTs), serial peripheral interface (SPI) ports, and a
UART port

• JTAG Test Access Port for board test and emulation

Figure 1-1 on page 1-4 also shows the three on-chip buses of the

ADSP-219x: the PM bus, DM bus, and DMA bus. The PM bus provides
access to either instructions or data. During a single cycle, these buses let
the processor access two data operands (one from PM and one from DM),
and access an instruction (from the cache).

The buses connect to the ADSP-219x’s external port, which provides the
processor’s interface to external memory, I/O memory-mapped, and boot
memory. The external port performs bus arbitration and supplies control
signals to shared, global memory and I/O devices.

Further, the ADSP-219x addresses the five central requirements for DSPs:

• Fast, flexible arithmetic computation units

Fast, Flexible Arithmetic. The ADSP-219x family DSPs execute all
computational instructions in a single cycle. They provide both fast
cycle times and a complete set of arithmetic operations.

• Unconstrained data flow to and from the computation units

Unconstrained Data Flow. The ADSP-219x has a modified Har­vard architecture combined with a data register file. In every cycle,
the DSP can:

• Read two values from memory or write one value to
memory

• Complete one computation

• Write up to three values back to the register file

• Extended precision and dynamic range in the computation units

ADSP-219x/2191 DSP Hardware Reference 1-3

ADSP-219x Design Advantages

INTERNAL MEMORY

DATA

DMA

DATA

0
K
C

1

O

K

L

2

C

B

K

O

C

L

O

B

L
B

PROGRAMMABLE

FLAGS (16)

DAG1

4 ⴛ 4 ⴛ16

REGISTER

MULT

ADSP-219x
DSP CORE

PX

DATA

FILE

DAG2

4 ⴛ 4 ⴛ16

DM ADDRESS BUS

INPUT

REGISTERS

RESULT

REGISTERS

16 ⴛ 16-BIT

PM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BARREL
SHIFTER

CACHE

64 ⴛ 24-BIT

PROGRAM

SEQUENCE R

24

DMA

CONNECT

ALU

FOUR INDEPENDENT BLOCKS

ADDRESS

24

24

DMA ADDRESS

24

16

24

16

24 BIT

24 BIT

ADDRESS

ADDRESS

DMA DATA

I/O DATA

16 BIT

ADDRESS

16 BIT

I/O ADDRESS

I/O REGISTER S

(MEMORY-MAPPED)

CONTROL

STATUS

BUFFERS

SYSTEM INTERRUPT CONTROLLER

DATA

DATA

18

CONTROLLER 6

Figure 1-1. ADSP-219x/ADSP-2191 DSP Block Diagram

40-Bit Extended Precision. The DSP handles 16-bit integer and
fractional formats (twos-complement and unsigned). The proces­sors carry extended precision through result registers in their
computation units, limiting intermediate data truncation errors.

3
K
C
O
L
B

JTAG

TEST &

EMULATION

EXTERNAL PORT

ADDR BUS

MUX

DATA BUS

MUX

I/O PROCESSOR

HOST PORT

SERIAL PORTS

(3)

SPI PORTS

(2)

UART PORT

(1)

TIMERS (3)

6

22

16

24

18

2

3

• Dual address generators with circular buffering support

Dual Address Generators. The DSP has two data address genera­tors (DAGs) that provide immediate or indirect (pre- and
post-modify) addressing. Modulus and bit-reverse operations are
supported with memory page constraints on data buffer placement
only.

1-4 ADSP-219x/2191 DSP Hardware Reference

Introduction

• Efficient program sequencing

Efficient Program Sequencing. In addition to zero-overhead loops,
the DSP supports quick setup and exit for loops. Loops are both
nestable (eight levels in hardware) and interruptable. The proces­sors support both delayed and non-delayed branches.

ADSP-219x/2191 DSP Hardware Reference 1-5

ADSP-219x Architecture

ADSP-219x Architecture

This section provides the following topics:

• “Overview” on page 1-6

• “DSP Core Architecture” on page 1-8

• “DSP Peripherals Architecture” on page 1-10

• “Memory Architecture” on page 1-13

• “Interrupts” on page 1-17

• “DMA Controller” on page 1-17

• “Host Port” on page 1-18

• “DSP Serial Ports (SPORTs)” on page 1-18

• “Serial Peripheral Interface (SPI) Ports” on page 1-19

• “UART Port” on page 1-20

• “Programmable Flag (PFx) Pins” on page 1-20

• “Low-Power Operation” on page 1-21

• “Clock Signals” on page 1-21

• “Booting Modes” on page 1-22

• “JTAG Port” on page 1-22

Overview

An ADSP-219x is a single-chip microcomputer optimized for digital sig­nal processing (DSP) and other high speed numeric processing
applications. These DSPs provide a complete system-on-a-chip, integrat-

1-6 ADSP-219x/2191 DSP Hardware Reference

Introduction

ing a large, high-speed SRAM and I/O peripherals supported by a
dedicated DMA bus. The following sections summarize the features of
each functional block in the ADSP-219x architecture, which appears in

Figure 1-1 on page 1-4.

The ADSP-2191 combines the ADSP-219x family base architecture (three
computational units, two data address generators, and a program
sequencer) with three serial ports, two SPI-compatible ports, one UART
port, a DMA controller, three programmable timers, general-purpose Pro­grammable Flag pins, extensive interrupt capabilities, and on-chip
program and data memory blocks.

The ADSP-2191 architecture is code compatible with ADSP-218x family
DSPs. Though the architectures are compatible, the ADSP-2191 architec­ture has a number of enhancements over the ADSP-218x architecture.
The enhancements to computational units, data address generators, and
program sequencer make the ADSP-2191 more flexible and even easier to
program than the ADSP-218x DSPs.

Indirect addressing options provide addressing flexibility—pre-modify
with no update, pre- and post-modify by an immediate 8-bit, twos-com­plement value and base address registers for easier implementation of
circular buffering.

The ADSP-2191 DSP integrates 64K words of on-chip memory config­ured as 32K words 24-bit SRAM and 32K words of 16-bit SRAM. The
ADSP-2195 DSP features 16K of 24-bit SRAM and 16K words of 16-bit
SRAM, whereas the ADSP-2196 DSP provides 8K words of 24-bit SRAM
and 8K words of 16-bit SRAM.

The ADSP-2191’s flexible architecture and comprehensive instruction set
support multiple operations in parallel. For example, in one processor
cycle, the ADSP-2191 can:

• Generate an address for the next instruction fetch

• Fetch the next instruction

ADSP-219x/2191 DSP Hardware Reference 1-7

ADSP-219x Architecture

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

These operations take place while the processor continues to:

• Receive and transmit data through two serial ports

• Receive and/or transmit data from a host

• Receive or transmit data through the UART

• Receive or transmit data over two SPI ports

• Access external memory through the external memory interface

• Decrement the timers

DSP Core Architecture

The ADSP-219x instruction set provides flexible data moves and multi­function (one or two data moves with a computation) instructions. Every
single-word instruction can be executed in a single processor cycle. The
ADSP-219x assembly language uses an algebraic syntax for ease of coding
and readability. A comprehensive set of development tools supports pro­gram development.

Figure 1-1 on page 1-4 shows the architecture of the ADSP-219x core. It

contains three independent computational units: the ALU, the multi­plier/accumulator, and the shifter. The computational units process 16-bit
data from the register file and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic and logic
operations; division primitives also are supported. The multiplier per­forms single-cycle multiply, multiply/add, and multiply/subtract
operations. The multiplier has two 40-bit accumulators, which help with
overflow. The shifter performs logical and arithmetic shifts, normaliza-

1-8 ADSP-219x/2191 DSP Hardware Reference

Introduction

tion, denormalization, and derive exponent operations. The shifter can
efficiently implement numeric format control, including multiword and
block floating-point representations.

Register-usage rules influence placement of input and results within the
computational units. For most operations, the computational units’ data
registers act as a data register file, permitting any input or result register to
provide input to any unit for a computation. For feedback operations, the
computational units let the output (result) of any unit be input to any
unit on the next cycle. For conditional or multifunction instructions,
there are restrictions limiting which data registers may provide inputs or
receive results from each computational unit. For more information, see

“Multifunction Computations” on page 2-64.

A powerful program sequencer controls the flow of instruction execution.
The sequencer supports conditional jumps, subroutine calls, and low
interrupt overhead. With internal loop counters and loop stacks, the
ADSP-2191 executes looped code with zero overhead; no explicit jump
instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for simultaneous
dual operand fetches (from data memory and program memory). Each
DAG maintains and updates four 16-bit address pointers. Whenever the
pointer is used to access data (indirect addressing), it is pre- or post-modi­fied by the value of one of four possible modify registers. A length value
and base address may be associated with each pointer to implement auto­matic modulo addressing for circular buffers. Page registers in the DAGs
allow circular addressing within 64K word boundaries of each of the 256
memory pages, but these buffers may not cross page boundaries. Second­ary registers duplicate all the primary registers in the DAGs; switching
between primary and secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved by using internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

ADSP-219x/2191 DSP Hardware Reference 1-9

ADSP-219x Architecture

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• DMA Address Bus

• DMA Data Bus

The internal address buses share a single external address bus, allowing
memory to be expanded off-chip, and the data buses share a single external
data bus. Boot memory space and external I/O memory space also share
the external buses.

Program memory can store both instructions and data, permitting the
ADSP-219x to fetch two operands in a single cycle, one from program
memory and one from data memory. The DSP’s dual memory buses also
let the ADSP-219x core fetch an operand from data memory and the next
instruction from program memory in a single cycle.

DSP Peripherals Architecture

Figure 1-1 on page 1-4 shows the DSP’s on-chip peripherals, which

include the external memory interface, host port, serial ports, SPI compat­ible ports, UART port, JTAG test and emulation port, timers, flags, and
interrupt controller. Figure 1-2 on page 1-11 illustrates a typical
ADSP-2191 system with peripheral connections.

The ADSP-2191 has a 16-bit host port with DMA capability that pro­vides external hosts access to on-chip memory. This parallel port consists
of a multiplexed data/address bus and provides a low-service overhead data
move capability. Configurable for 8- or 16-bit data bus widths, this port
provides a glueless interface to a wide variety of 8- and 16-bit microcon­trollers. Two chip-selects provide hosts access to the DSP’s entire memory
map. The DSP is bootable through this port.

1-10 ADSP-219x/2191 DSP Hardware Reference

Introduction

CLOCK

OR

CRYSTAL

TIMER

OUT OR

CAPTURE

CLOCK

MULTIPLY

AND

RANGE

BOOT

AND OP

MODE

SERIAL
DEVICE

(OPTIONA L)

SERIAL
DEVICE

(OPTIONA L)

SERIAL
DEVICE

(OPTIONA L)

UART

DEVICE

(OPTIONA L)

ADSP-2191M

CLKIN
XTAL

TMR2–0

MSEL6–0/PF6–0
DF/PF7
BYPASS
BMODE1–0
OPMODE

SPORT0
TCLK0
TFS0
DT0
RCLK0
RFS0
DR0

SPORT1
TCLK1
TFS1
DT1
RCLK1
RFS1
DR1

SPORT2
TCLK2/SCK0
TFS2/MOSI0
DT2/MISO0
RCLK2/SCK

1
RFS2/MOSI1

DR2/MISO1

UART
RXD
TXD

RESET

6

JTAG

CLKOUT

ADDR21–0

DATA15–8

DATA7–0

MS3–0

RD

WR

ACK

BMS

BR
BG

BGH

IOMS

SPI0

SPI1

HAD15–

HA16

HCMS

HCIOMS

HRD

HWR

HAC

HALE

HACK_

EXTERNAL

MEMORY

(OPTIONA L)

ADDR21–
0

DATA15–
8

DATA7–
0

CS
OE
WE

S
S
E
R
D
D
A

A
T
A
D

ACK

BOOT

MEMORY

(OPTIONA L)

ADDR21–
0

DATA15–
8

DATA7–
0

CS
OE
WE
ACK

EXTERNAL

I/O MEMORY

(OPTIONAL )

ADDR21–
0

DATA15–
8

DATA7–
0

CS
OE
WE
ACK

HOST

PROCESSOR

(OPTIONAL )

ADDR15–0
/
ADDR16

DATA15–0
CS0

CS1
RD
WR
ACK

ALE

L
O
R
T
N
O
C

0

K

P

Figure 1-2. ADSP-219x/ADSP-2191 DSP Block Diagram

The ADSP-2191 also has an external memory interface that is shared by
the DSP’s core, the DMA controller, and DMA capable peripherals,
which include the UART port, serial ports, SPI ports, and the host port.

ADSP-219x/2191 DSP Hardware Reference 1-11

ADSP-219x Architecture

The external port consists of an 8- or 16-bit data bus, a 22-bit address bus,
and control signals. The data bus is configurable to provide an 8- or 16-bit
interface to external memory. Support for word packing lets the DSP
access 16- or 24-bit words from external memory regardless of the external
data bus width. When configured for an 8-bit interface, the unused eight
lines provide eight programmable, bidirectional general purpose Program­mable Flag lines, six of which can be mapped to software condition
signals.

The memory DMA controller lets the ADSP-2191 transfer data to and
from internal and external memory. On-chip peripherals also can use this
port for DMA transfers to and from memory.

The ADSP-2191 can respond to up to 16 interrupt sources at any given
time: three internal (stack, emulator kernel, and power-down), two exter­nal (emulator and reset), and twelve user-defined (peripherals) interrupt
requests. Programmers assign a peripheral to one of the 12 user defined
interrupt requests. These assignments determine the priority of each
peripheral for interrupt service. Several peripherals can be combined on a
single interrupt request line.

There are three serial ports on the ADSP-2191 that provide a complete
synchronous, full-duplex serial interface. This interface includes optional
companding in hardware and a wide variety of framed or frameless data
transmit and receive modes of operation. Each serial port can transmit or
receive an internal or external, programmable serial clock and frame syncs.
Each serial port supports 128-channel time division multiplexing (TDM).

The ADSP-2191 provides up to sixteen general-purpose I/O pins, which
are programmable as either inputs or outputs. Eight of these pins are ded­icated general purpose programmable flag pins. The other eight are
multifunctional pins, acting as general purpose I/O pins when the DSP
connects to an 8-bit external data bus and acting as the upper eight data
pins when the DSP connects to a 16-bit external data bus. These program-

1-12 ADSP-219x/2191 DSP Hardware Reference

Introduction

mable flag pins can implement edge- or level-sensitive interrupts. The
execution of conditional instructions can be based on some of the pro­grammable flag pins.

Three programmable interval timers generate periodic interrupts. Each
timer can be independently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

Each timer has one bi-directional pin and four registers that implement its
mode of operation: a configuration register, a count register, a period reg­ister, and a pulsewidth register. A single status register supports all three
timers. A bit in the mode status register globally enables or disables all
three timers, and a bit in each timer’s configuration register enables or dis­ables the corresponding timer independently of the others.

Memory Architecture

The ADSP-2191 provides 64K words of on-chip memory. This memory
is divided into four 16K blocks located on memory page 0 in the DSP’s
memory map. The ADSP-2195 features only two 16K blocks, and the
ADSP-2196 has two 8K blocks. In addition to the internal and external
memory space, the ADSP-2191 can address two additional and separate
memory spaces: I/O space and boot space.

As shown in Figure 1-3 on page 1-14, the DSP’s two internal memory
blocks populate all of Page 0. The entire DSP memory map consists of
256 pages (pages 0-255), and each page is 64K words long. External mem­ory space consists of four memory banks (banks 3–0) and supports a wide
variety of SRAM memory devices. Each bank is selectable using the mem­ory select pins (
and waitstate modes. The 1K word of on-chip boot-ROM populates the

ADSP-219x/2191 DSP Hardware Reference 1-13

MS3-0) and has configurable page boundaries, waitstates,

ADSP-219x Architecture

lower 1K addresses of page 255. Other than page 0 and page 255, the
remaining 254 pages are addressable off-chip. I/O memory pages differ
from external memory pages in that I/O pages are 1K word long, and the
external I/O pages have their own select pin (

IOMS). Pages 0–7 of I/O

memory space reside on-chip and contain the configuration registers for
the peripherals. Both the DSP core and DMA-capable peripherals can
access the DSP’s entire memory map.

LOGICAL

ADDRESS

0xFF FFFF
0xFF 0400

0xFF 03FF
0xFF 0000

0xC0 0000

0x80 0000

0x40 0000

0x01 0000
0x00 C000
0x00 8000
0x00 4000
0x00 0000

LOWER PAGEBOUNDARIES
ARE CONFIGURABLE FOR
BANKS OF EXTERNAL MEMORY.
BOUNDARIES SHOWNARE
BANK SIZESAT RESET.

BOOT MEMORY

16-BIT

(BMS)

64K WORD

PAGES 1–254

LOGICAL

ADDRESS

0xFE FFFF

0x01 0000

MEMORYSELECTS (MS)
FOR PORTIONS OF THE

MEMORY MAP APPEAR

WITH THESELECTED

I/O MEMORY

16-BIT

1K WORD

PAGES 8–255

1K WORD

PAGES 0–7

EXTERNAL

(IOMS)

INTERNAL

INTERNAL

MEMORY

EXTERNAL

MEMORY

(16-BIT)

INTERNAL

MEMORY

64K WORD

MEMORY

PAGES

PAGE 255

PAGES 192–254

PAGES 128–191

PAGES 64–127

PAGES 1–63

PAGE 0

RESERVED

BOOT ROM, 24-BIT

BANK3

(MS3)

BANK2

(MS2)

BANK1

(MS1)

BANK0

(MS0)

BLOCK3, 16-BIT
BLOCK2, 16-BIT

BLOCK1, 24-BIT
BLOCK0,24-BIT

Figure 1-3. ADSP-2191 Internal/External Memory, Boot Memory, and
I/O Memory Maps

Internal (On-Chip) Memory

MEMORY.

LOGICAL

ADDRESS

0xFF 3FF

0x08 000
0x07 3FF
0x00 000

8-BIT 10-BIT

The ADSP-2191’s unified program and data memory space consists of
16M locations that are accessible through two 24-bit address buses, the
PMA and DMA buses. The DSP uses slightly different mechanisms to
generate a 24-bit address for each bus. The DSP has three functions that
support access to the full memory map.

1-14 ADSP-219x/2191 DSP Hardware Reference

Introduction

The DAGs generate 24-bit addresses for data fetches from the entire DSP
memory address range. Because DAG index (address) registers are 16 bits
wide and hold the lower 16-bits of the address, each of the DAGs has its
own 8-bit page register (

DMPGx) to hold the most significant eight address

bits. Before a DAG generates an address, the program must set the DAG’s

DMPGx register to the appropriate memory page.

• The program sequencer generates the addresses for instruction
fetches. For relative addressing instructions, the program sequencer
bases addresses for relative jumps, calls, and loops on the 24-bit
Program Counter (PC) register. For direct addressing instructions
(two-word instructions), the instruction provides an immediate
24-bit address value. The PC allows linear addressing of the full 24
bit address range.

• The program sequencer relies on an 8-bit Indirect Jump Page
(IJPG) register to supply the most significant eight address bits for
indirect jumps and calls that use a 16-bit DAG address register for
part of the branch address. Before a cross page jump or call, the
program must set the program sequencer’s IJPG register to the
appropriate memory page.

The ADSP-2191 has 1K word of on-chip ROM that holds boot routines.
If peripheral booting is selected, the DSP starts executing instructions
from the on-chip boot ROM, which starts the boot process from the
selected peripheral. For more information, see “Booting Modes” on page

1-22. The on-chip boot ROM is located on Page 255 in the DSP’s mem-

ory map.

The ADSP-2191 has internal I/O memory for peripheral control and sta­tus registers. For more information, see the I/O memory space discussion
on page 1-16.

ADSP-219x/2191 DSP Hardware Reference 1-15

ADSP-219x Architecture

External (Off-Chip) Memory

Each of the ADSP-2191’s off-chip memory spaces has a separate control
register, so applications can configure unique access parameters for each
space. The access parameters include read and write wait counts, waitstate
completion mode, I/O clock divide ratio, write hold time extension,
strobe polarity, and data bus width. The core clock and peripheral clock
ratios influence the external memory access strobe widths. For more infor-

mation, see “Clock Signals” on page 1-21. The off-chip memory spaces

are:

• External memory space (

MS3-0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of these off-chip memory spaces are accessible through the external
port, which can be configured for 8-bit or 16-bit data widths.

External Memory Space.External memory space consists of four memory
banks. These banks can contain a configurable number of 64K word
pages. At reset, the page boundaries for external memory have Bank 0 con­taining pages 1-63, Bank 1 containing pages 64-127, Bank 2 containing
pages 128-191, and Bank 3 containing pages 192-254. The MS3-0 mem­ory bank pins select Bank 3-0, respectively. The external memory interface
decodes the eight MSBs of the DSP program address to select one of the
four banks. Both the DSP core and DMA-capable peripherals can access
the DSP’s external memory space.

I/O Memory Space. The ADSP-2191 supports an additional external
memory called I/O memory space. This space is designed to support sim­ple connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space supports a total
of 256K locations. The first 8K addresses are reserved for on-chip periph­erals. The upper 248K addresses are available for external peripheral
devices and are selected with the IOMS pin. The DSP’s instruction set pro-

1-16 ADSP-219x/2191 DSP Hardware Reference

Introduction

vides instructions for accessing I/O space. These instructions use an 18-bit
address that is assembled from an 8-bit I/O Memory Page (
and a 10-bit immediate value supplied in the instruction. Both the
ADSP-219x core and a host (through the host port) can access I/O mem­ory space.

Boot Memory Space. Boot memory space consists of one off-chip bank
with 253 pages. The BMS pin selects boot memory space. Both the DSP
core and DMA-capable peripherals can access the DSP’s off-chip boot
memory space. If the DSP is configured to boot from boot memory space,
the DSP starts executing instructions from the on-chip boot ROM, which
starts booting the DSP from boot memory. For more information, see

“Booting Modes” on page 1-22.

IOPG) register

Interrupts

The interrupt controller allows the DSP to respond to 17 interrupts with
minimal overhead. The controller implements an interrupt priority
scheme, allowing programs assign interrupt priorities to each peripheral.

For more information, see “System Interrupt Controller” on page 6-1.

DMA Controller

The ADSP-2191 has a DMA controller that supports automated data
transfers with minimal overhead for the DSP core. Cycle stealing DMA
transfers can occur between the ADSP-2191’s internal memory and any of
its DMA capable peripherals. Additionally, DMA transfers also can be
accomplished between any of the DMA capable peripherals and external
devices connected to the external memory interface. DMA capable periph­erals include the host port, serial ports, SPI ports, UART port, and
memory-to-memory (memDMA) DMA channel. Each individual DMA
capable peripheral has one or more dedicated DMA channels. For a
description of each DMA sequence, the DMA controller uses a set of
parameters—called a DMA descriptor. When successive DMA sequences

ADSP-219x/2191 DSP Hardware Reference 1-17

ADSP-219x Architecture

are needed, these descriptors can be linked or chained together. When
chained, the completion of one DMA sequence auto-initiates and starts
the next sequence. DMA sequences do not contend for bus access with the
DSP core, instead DMAs “steal” cycles to access memory.

Host Port

The ADSP-2191’s host port functions as a slave on the external bus of an
external host. The host port interface lets a host read from or write to the
DSP’s memory space, boot space, or internal I/O space. Examples of hosts
include external microcontrollers, microprocessors, or ASICs.

The host port is a multiplexed address and data bus that provides an 8- or
16-bit data path and operates using an asynchronous transmission proto­col. To access the DSP’s internal memory space, a host steals one cycle per
access from the DSP. A host access to the DSP’s external memory uses the
external port interface and does not stall (or steal cycles from) the DSP’s
core. Because a host can access internal I/O memory space, a host can con­trol any of the DSP’s I/O mapped peripherals.

DSP Serial Ports (SPORTs)

The ADSP-2191 incorporates three complete synchronous serial ports
(SPORT0, SPORT1, and SPORT2) for serial and multiprocessor com­munications. The SPORTs support the following features:

• Bidirectional operation—each SPORT has independent transmit
and receive pins.

• Buffered (eight-deep) transmit and receive ports—each port has a
data register for transferring data words to and from other DSP
components and shift registers for shifting data in and out of the
data registers.

1-18 ADSP-219x/2191 DSP Hardware Reference

Introduction

• Clocking—each transmit and receive port either can use an exter­nal serial clock (

ⱕ75 MHz) or generate its own, in frequencies

ranging from 1144 Hz to 75 MHz.

• Word length—each SPORT supports serial data words from 3- to
16-bits in length transferred in big endian (MSB) or little endian
(LSB) format.

• Framing—each transmit and receive port can run with or without
frame sync signals for each data word.

• Companding in hardware—each SPORT can perform A-law or
µ-law companding, according to ITU recommendation G.711.

• DMA operations with single-cycle overhead—each SPORT can
automatically receive and transmit multiple buffers of memory
data, one data word each DSP cycle.

• Interrupts—each transmit and receive port generates an interrupt
upon completing the transfer of a data word or after transferring an
entire data buffer or buffers through DMA.

• Multichannel capability—each SPORT supports the H.100
standard.

Serial Peripheral Interface (SPI) Ports

The DSP has two SPI-compatible ports, which enable the DSP to com­municate with multiple SPI compatible devices. These ports are
multiplexed with SPORT2, so either SPORT2 or the SPI ports are active
depending on the state of the
mode, the pin can be changed during hardware or software reset, or the bit
can be changed at runtime.

The SPI interface uses three pins for transferring data: two data pins (mas­ter output-slave input,
clock pin (serial clock,

MOSIx, and master input-slave output, MISOx) and a

SCKx). Two SPI chip-select input pins (SPISSx) let

ADSP-219x/2191 DSP Hardware Reference 1-19

OPMODE pin or OPMODE bit. To change the

ADSP-219x Architecture

other SPI devices select the DSP, and fourteen SPI chip select output pins

(SPIxSEL7-1) let the DSP select other SPI devices. The SPI select pins are

re-configured programmable flag pins. Using these pins, the SPI ports
provide a full duplex, synchronous serial interface, which supports both
master and slave modes and multiple master environments.

Each SPI port’s baud rate and clock phase/polarities are programmable,
and each has an integrated DMA controller, configurable to support both
transmit and receive data streams. The SPI’s DMA controller can only ser­vice uni-directional accesses at any given time.

During transfers, the SPI ports simultaneously transmit and receive by
serially shifting data in and out on their two serial data lines. The serial
clock line synchronizes the shifting and sampling of data on the two serial
data lines.

UART Port

The UART port provides a simplified UART interface to another periph­eral or host. It performs full duplex, asynchronous transfers of serial data.
The UART port supports two modes of operation:

• PIO (programmed I/O)

• DMA (direct memory access)

Programmable Flag (PFx) Pins

The ADSP-2191 has sixteen bi-directional, general-purpose I/O, pro­grammable flag (PF15-0) pins. The PF7-0 pins are dedicated to
general-purpose I/O. The PF15-8 pins serve either as general-purpose I/O
pins (if the DSP is connected to an 8-bit external data bus) or serve as

DATA15-8 lines (if the DSP is connected to a 16-bit external data bus). The

programmable flag pins have special functions for clock multiplier selec­tion and for SPI port operation.

1-20 ADSP-219x/2191 DSP Hardware Reference

Introduction

Low-Power Operation

The ADSP-2191 has four low-power options that significantly reduce the
power dissipation when the device operates under standby conditions. To
enter any of these modes, the DSP executes an IDLE instruction. The
ADSP-2191 uses configuration of the bits in the PLLCTL register to select
between the low-power modes as the DSP executes the IDLE instruction.
Depending on the mode, an IDLE shuts off clocks to different parts of the
DSP in the different modes. The low-power modes are:

•Idle

• Powerdown core

• Powerdown core/peripherals

• Powerdown all

Clock Signals

The ADSP-2191 can be clocked by a crystal oscillator or a buffered,
shaped clock derived from an external clock oscillator. If a crystal oscilla­tor is used, the crystal should be connected across the CLKIN and XTAL pins,
with two capacitors connected. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A parallel-reso­nant, fundamental frequency, microprocessor-grade crystal should be used
for this configuration.

If a buffered, shaped clock is used, this external clock connects to the
DSP’s
below the specified frequency during normal operation. This clock signal
should be a TTL-compatible signal. When an external clock is used, the

XTAL input must be left unconnected.

ADSP-219x/2191 DSP Hardware Reference 1-21

CLKIN pin. CLKIN input cannot be halted, changed, or operated

ADSP-219x Architecture

The DSP provides a user programmable 1x to 31x multiplication of the
input clock—including some fractional values—to support 128 exter­nal-to-internal (DSP core) clock ratios.

Booting Modes

The ADSP-2191 has seven mechanisms for automatically loading internal
program memory after reset. The
reset, and three bits in the System Configuration (
ment these modes:

• Boot from 16-bit external memory

• Boot from 8-bit EPROM

• Boot from host

• Execute from 8-bit external memory (no boot)

BMODE2-0 pins, sampled during hardware

SYSCR) register imple-

• Boot from UART

• Boot from SPI 4 Kbits

• Boot from SPI 512 Kbits

JTAG Port

The JTAG port on the ADSP-2191 supports the IEEE standard 1149.1
Joint Test Action Group (JTAG) standard for system test. This standard
defines a method for serially scanning the I/O status of each component in
a system. Emulators use the JTAG port to monitor and control the DSP
during emulation. Emulators using this port provide full-speed emulation
with access to inspect and modify memory, registers, and processor stacks.
JTAG-based emulation is non-intrusive and does not affect target system
loading or timing.

1-22 ADSP-219x/2191 DSP Hardware Reference

Introduction

Differences from Previous DSPs

This section identifies differences between the ADSP-219x DSPs and pre­vious ADSP-2100 family DSPs: ADSP-210x, ADSP-211x, ADSP-217x,
and ADSP-218x. The ADSP-219x preserves much of the core ADSP-2100
family architecture, while extending performance and functionality. For
background information on previous ADSP-2100 family DSPs, see the
ADSP-2100 Family User’s Manual.

Chip enhancements also lead to some differences in the instruction sets
between these DSPs. For more information, see the ADSP-219x DSP
Instruction Set Reference.

ADSP-219x/2191 DSP Hardware Reference 1-23

Differences from Previous DSPs

This section describes the following differences:

• “Computational Units and Data Register File” on page 1-25

• “Arithmetic Status (ASTAT) Register Latency” on page 1-25

• “NORM and EXP Instruction Execution” on page 1-25

• “Shifter Result (SR) Register as Multiplier Dual Accumulator” on

page 1-25

• “Shifter Exponent (SE) Register is Not Memory Accessible” on

page 1-26

• “Software Condition (SWCOND) Register and Condition Code

(CCODE) Register” on page 1-26

• “Unified Memory Space” on page 1-28

• “Data Memory Page (DMPG1 and DMPG2) Registers” on

page 1-28

• “Data Address Generator (DAG) Addressing Modes” on page 1-28

• “Base Registers for Circular Buffers” on page 1-29

• “Program Sequencer, Instruction Pipeline, and Stacks” on

page 1-30

• “Conditional Execution (Difference in Flag Input Support)” on

page 1-30

• “Execution Latencies (Different for JUMP Instructions)” on

page 1-31

1-24 ADSP-219x/2191 DSP Hardware Reference

Introduction

Computational Units and Data Register File

The ADSP-219x DSP computational units differ from those on the
ADSP-218x, because the ADSP-219x data registers act as a register file for
unconditional, single-function instructions. In these instructions, any data
register may be an input to any computational unit. For conditional
and/or multifunction instructions, the ADSP-219x and ADSP-218x DSP
families have the same data register usage restrictions — AX and AY for
ALU, MX and MY for the multiplier, and SI for shifter inputs. For more

information, see “Multifunction Computations” on page 2-64.

Arithmetic Status (ASTAT) Register Latency

The ADSP-219x ASTAT register has a one-cycle effect latency. This is dis­cussed in “ALU Status Flags” on page 2-19.

NORM and EXP Instruction Execution

The ADSP-219x NORM and EXP instructions execute slightly differently
from previous ADSP-218x DSPs. This issue is discussed in “Normalize,

ALU Result Overflow” on page 2-48.

Shifter Result (SR) Register as Multiplier Dual Accumulator

The ADSP-219x architecture introduces a new 16-bit register in addition
to the
40-bit- wide

SR2, can be used in multiplier or shift operations (lower 8 bits) and as a

full 16-bit-wide scratch register. As a result, the ADSP-219x DSP has two
40-bit-wide accumulators,
replaced the multiplier feedback register
example:

ADSP-219x/2191 DSP Hardware Reference 1-25

SR0 and SR1 registers, the combination of which comprise the

SR register on ADSP-218x DSPs. This new register, called

MR and SR. The SR dual accumulator has

MF, as shown in the following

Differences from Previous DSPs

Table 1-1. SR2 Register

ADSP-218x Instruction ADSP-219x Instruction (Replacement)

MF=MR+MX0*MY1(UU);
IF NOT MV MR=AR*MF;

SR=MR+MX0*MY1(UU);
IF NOT MV MR=AR*SR2;

Shifter Exponent (SE) Register is Not Memory Accessible

The ADSP-218x DSPs use SE as a data or scratch register. The SE register
of the ADSP-219x architecture is not accessible from the data or program
memory buses. Therefore, the multifunction instructions of the
ADSP-218x that use SE as a data or scratch register should use one of the
data file registers (DREG) as a scratch register on the ADSP-219x DSP.

Table 1-2. SE is Not Memory Accessible

ADSP-218x Instruction ADSP-219x Instruction (Replacement)

SR=Lshift MR1(HI),
SE=DM(I6,M5);

SR=Lshift MR1(HI),
AX0=DM(I6,M5);

Software Condition (SWCOND) Register and Condition Code (CCODE) Register

The ADSP-219x DSP changes support for the ALU signed (AS) condition
and supports additional arithmetic and status condition testing with the
Condition Code (
The two conditions are

CCODE) register and software condition (SWCOND) test.

SWCOND and NOT SWCOND. The usage of the

ADSP-219x’s and most ADSP-218x’s arithmetic conditions (EQ, NE, GE,

GT, LE, LT, AV, Not AV, AC, Not AC, MV, Not MV) are compatible.

The new shifter overflow (

SV) condition of the ADSP-219x architecture is

a good example of how the CCODE register and SWCOND test work. The
ADSP-219x DSP’s Arithmetic Status (

ASTAT) register contains a bit indi-

1-26 ADSP-219x/2191 DSP Hardware Reference

Introduction

cating the status of the shifter’s result. The shifter is a computational unit
that performs arithmetic or logical bitwise shifts on fields within a data
register. The result of the operation goes into the Shifter Result (

SR2, SR1,

and SR0, which are combined into SR) register. If the result overflows the

SR register, the shifter overflow (SV) bit in the ASTAT register records this

overflow/underflow condition for the SR result register (0 = no overflow or
underflow, 1 = overflow or underflow).

For the most part, bits (status condition indicators) in the ASTAT register
correspond to condition codes that appear in conditional instructions. For
example, the ALU zero (AZ) bit in ASTAT corresponds to the ALU result
equals zero (EQ) condition and would be used in code like this:

IF EQ AR = AX0 + AY0;
/* if the ALU result (AR) register is zero, add AX0 and AY0 */

The SV status condition in the ASTAT bits does not correspond to a condi­tion code that can be directly used in a conditional instruction. To test for
this status condition, software selects a condition to test by loading a value
into the Condition Code (CCODE) register and uses the software condition
(SWCOND) condition code in the conditional instruction. The DSP code
would look like this:

CCODE = 0x09; NOP; // set CCODE for SV condition
IF SWCOND SR = MR0 * SR1 (UU); // mult unsigned X and Y

The NOP instruction after loading the CCODE register accommodates the
one-cycle effect latency of the

CCODE register.

The ADSP-218x DSP supports two conditions to detect the sign of the
ALU result. On the ADSP-219x, these two conditions (

POS and NEG) are

supported as AS and NOT AS conditions in the CCODE register. For more
information on

CCODE register values and SWCOND conditions, see “Condi-

tional Sequencing” on page 3-41.

ADSP-219x/2191 DSP Hardware Reference 1-27

Differences from Previous DSPs

Unified Memory Space

The ADSP-219x architecture has a unified memory space with separate
memory blocks to differentiate between 24- and 16-bit memory. In the
unified memory, the term program or data memory only has semantic sig­nificance; the address determines the “PM” or “DM” functionality. It is best
to revise any code with non-symbolic addressing in order to use the new
tools.

Data Memory Page (DMPG1 and DMPG2) Registers

The ADSP-219x processor introduces a paged memory architecture that
uses 16-bit DAG registers to access 64K pages. The 16-bit DAG registers
correspond to the lower 16 bits of the DSP’s address buses, which are
24-bit wide. To store the upper 8 bits of the 24-bit address, the
ADSP-219x DSP architecture uses two additional registers, DMPG1 and

DMPG2. DMPG1 and DMPG2 work with the DAG registers I0-I3 and I4-I7,

respectively.

Data Address Generator (DAG) Addressing Modes

The ADSP-219x architecture provides additional flexibility over the
ADSP-218x DSP family in DAG addressing modes:

• Pre-modify without update addressing in addition to the
post-modify with update mode of the ADSP-218x instruction set:

DM(IO+M1) = AR; /* pre-modify syntax */
DM(IO+=M1) = AR; /* post-modify syntax */

• Pre-modify and post-modify with an 8-bit twos-complement
immediate modify value instead of an

AX0=PM(I5+-4); /* pre-modify syntax (for modifier = -4)*/
AX0=PM(I5+=4); /* post-modify syntax (for modifier = 4) */

1-28 ADSP-219x/2191 DSP Hardware Reference

M register:

Introduction

• DAG modify with an 8-bit twos-complement immediate-modify
value:

MODIFY(I7+=0x24);

Base Registers for Circular Buffers

The ADSP-219x processor eliminates the existing hardware restriction of
the ADSP-218x DSP architecture on a circular buffer starting address.
ADSP-219x enables declaration of any number of circular buffers by des­ignating B0-B7 as the base registers for addressing circular buffers; these
base registers are mapped to the “register” space on the core.

ADSP-219x/2191 DSP Hardware Reference 1-29

Differences from Previous DSPs

Program Sequencer, Instruction Pipeline, and Stacks

The ADSP-219x DSP core and inputs to the sequencer differ for various
members of the ADSP-219x family DSPs. The main differences between
the ADSP-218x and ADSP-219x sequencers are that the ADSP-219x
sequencer has:

• A 6-stage instruction pipeline, which works with the sequencer’s
loop and PC stacks, conditional branching, interrupt processing,
and instruction caching.

• A wider branch execution range, supporting:

— 13-bit, non-delayed or delayed relative conditional JUMP

— 16-bit, non-delayed or delayed relative unconditional JUMP

or CALL

— Conditional non-delayed or delayed indirect JUMP or CALL

with address pointed to by a DAG register

— 24-bit conditional non-delayed absolute long JUMP or CALL

• A narrowing of the DO/UNTIL termination conditions to counter
expired (CE) and FOREVER.

Conditional Execution (Difference in Flag Input Support)

Unlike the ADSP-218x DSP family, ADSP-219x DSPs do not directly
support a conditional
ADSP-219x supports this type of conditional execution with the
register and SWCOND condition. For more information, see “Software Con-

dition (SWCOND) Register and Condition Code (CCODE) Register” on
page 1-26.

1-30 ADSP-219x/2191 DSP Hardware Reference

JUMP/CALL based on flag input. Instead, the

CCODE

Introduction

The ADSP-219x architecture has 16 programmable flag pins that can be
configured as either inputs or outputs. The flags can be checked by read­ing the

FLAGS register, or by using a software condition flag.

Table 1-3. Conditional Execution

ADSP-218x Instruction ADSP-219x Instruction (Replacement)

If Not FLAG_IN AR=MR0 And 8192; SWCOND=0x03;

If Not SWCOND AR=MR0 And 8192;

IOPG = 0x06;
AX0=IO(FLAGS);
AXO=Tstbit 11 OF AXO;
If EQ AR=MRO And 8192;

Execution Latencies (Different for JUMP Instructions)

The ADSP-219x processor has an instruction pipeline (unlike ADSP-218x
DSPs) and branches execution for immediate JUMP and CALL instructions
in four clock cycles if the branch is taken. To minimize branch latency,
ADSP-219x programs can use the delayed branch option on jumps and
calls, reducing branch latency by two cycles. This savings comes from exe­cution of two instructions following the branch before the JUMP/CALL
occurs.

Development Tools

The ADSP-219x is supported by VisualDSP++®, an easy-to-use project
management environment, comprised of an Integrated Development
Environment (IDE) and Debugger. VisualDSP++ lets you manage
projects from start to finish from within a single, integrated interface.
Because the project development and debug environments are integrated,
you can move easily between editing, building, and debugging activities.

ADSP-219x/2191 DSP Hardware Reference 1-31

Development Tools

Flexible Project Management. The IDE provides flexible project manage­ment for the development of DSP applications. The IDE includes access
to all the activities necessary to create and debug DSP projects. You can
create or modify source files or view listing or map files with the IDE edi­tor. This powerful editor is part of the IDE and includes multiple
language syntax highlighting, OLE drag and drop, bookmarks, and stan­dard editing operations such as undo/redo, find/replace, copy/paste/cut,
and go to.

Also, the IDE includes access to the DSP C/C++ compiler, C run-time
library, assembler, linker, loader, simulator, and splitter. You specify
options for these tools through dialog boxes. These dialog boxes are easy
to use and make configuring, changing, and managing your projects sim­ple. The options you select control how the tools process inputs and
generate outputs, and the options have a one-to-one correspondence to
the tools’ command-line switches. You can define these options once or
modify them to meet changing development needs. You also can access
the Tools from the operating system command line if you choose.

Greatly Reduced Debugging Time. The debugger has an easy-to-use,
common interface for all processor simulators and emulators available
through Analog Devices and third parties or custom developments. The
debugger has many features that greatly reduce debugging time. You can
view C source interspersed with the resulting assembly code. You can pro­file execution of a range of instructions in a program; set simulated
watchpoints on hardware and software registers, program and data mem­ory; and trace instruction execution and memory accesses. These features
enable you to correct coding errors, identify bottlenecks, and examine
DSP performance. You can use the custom register option to select any
combination of registers to view in a single window. The debugger can
also generate inputs, outputs, and interrupts so you can simulate real
world application conditions.

1-32 ADSP-219x/2191 DSP Hardware Reference

Introduction

Software Development Tools. Software development tools, which sup­port the ADSP-219x DSP family, let you develop applications that take
full advantage of the architecture, including shared memory and memory
overlays. Software development tools include C/C++ compiler, C
run-time library, DSP and math libraries, assembler, linker, loader, simu­lator, and splitter.

C/C++ Compiler & Assembler. The C/C++ compiler generates efficient
code that is optimized for both code density and execution time. The
C/C++ compiler allows you to include assembly language statements
inline. Because of this, you can program in C and still use assembly for
time-critical loops. You can also use pretested math, DSP, and C run-time
library routines to help shorten your time to market. The ADSP-219x
DSP family assembly language is based on an algebraic syntax that is easy
to learn, program, and debug.

Linker & Loader. The linker provides flexible system definition through
Linker Description Files (

.LDF). In a single LDF, you can define different

types of executables for a single or multiprocessor system. The linker
resolves symbols over multiple executables, maximizes memory use, and
easily shares common code among multiple processors. The loader sup­ports creation of PROM, host, SPI, and UART boot images. The loader
allows multiprocessor system configuration with smaller code and faster
boot time.

3rd-Party Extensible. The VisualDSP++ environment enables third-party
companies to add value using Analog Devices’ published set of application
programming interfaces (API). Third-party products—real-time operating
systems, emulators, high-level language compilers, multiprocessor hard­ware —can interface seamlessly with VisualDSP++ thereby simplifying the
tools integration task. VisualDSP++ follows the COM API format. Two
API tools, Target Wizard and API Tester, are also available for use with
the API set. These tools help speed the time-to-market for vendor prod­ucts. Target Wizard builds the programming shell based on API features
the vendor requires. The API tester exercises the individual features inde-

ADSP-219x/2191 DSP Hardware Reference 1-33

Development Tools

pendently of VisualDSP++. Third parties can use a subset of these APIs
that meet their application needs. The interfaces are fully supported and
backward compatible.

Further details and ordering information are available in the VisualDSP++
development tools data sheet. This data sheet can be requested from any
Analog Devices sales office or distributor.

1-34 ADSP-219x/2191 DSP Hardware Reference

2 COMPUTATIONAL UNITS

This chapter provides the following topics:

• “Overview” on page 2-1

• “Data Formats” on page 2-5

• “Setting Computational Modes” on page 2-11

• “Using Computational Status” on page 2-18

• “Arithmetic Logic Unit (ALU)” on page 2-18

• “Multiply/Accumulates (Multiplier)” on page 2-30

• “Barrel Shifter (Shifter)” on page 2-39

• “Data Register File” on page 2-61

• “Secondary (Alternate) Data Registers” on page 2-63

• “Multifunction Computations” on page 2-64

Overview

The DSP’s computational units perform numeric processing for DSP
algorithms. The three computational units are the arithmetic/logic unit
(ALU), multiplier/accumulator (multiplier), and shifter. These units get
data from registers in the data register file. Computational instructions for
these units provide fixed-point operations, and each computational
instruction can execute in a single cycle.

ADSP-219x/2191 DSP Hardware Reference 2-1

Overview

The computational units handle different types of operations. The ALU
performs arithmetic and logic operations. The multiplier does multiplica­tion and executes multiply/add and multiply/subtract operations. The
shifter executes logical shifts and arithmetic shifts. Also, the shifter can
derive exponents.

Data flow paths through the computational units are arranged in parallel,
as shown in Figure 2-1 on page 2-3. The output of any computational
unit may serve as the input of any computational unit on the next instruc­tion cycle. Data moving in and out of the computational units goes
through a data register file, consisting of sixteen primary registers and six­teen secondary registers. Two ports on the register file connect to the PM
and DM data buses, allowing data transfer between the computational
units and memory.

The DSP’s assembly language provides access to the data register file. The
syntax lets programs move data to and from these registers and specify a
computation’s data format at the same time. For information on the data
registers, see “Data Register File” on page 2-61.

Figure 2-1 on page 2-3 provides a graphical guide to the other topics in

this chapter. First, a description of the

MSTAT register shows how to set

rounding, data format, and other modes for the computational units.
Next, an examination of each computational unit provides details on
operation and a summary of computational instructions. Looking at
inputs to the computational units, details on register files, and data buses
identify how to flow data for computations. Finally, details on the DSP’s
advanced parallelism reveal how to take advantage of conditional and mul­tifunction instructions.

The diagrams in Figure 2-1 on page 2-3 describe the relationship between
the ADSP-219x data register file and computational units: multiplier,
ALU, and shifter.

2-2 ADSP-219x/2191 DSP Hardware Reference

Computational Units

The ALU stores the computation results either

AR or in AF, where only AR

is part of the register file. The AF register is intended for intermediate ALU
data store and has a dedicated feedback path to the ALU. It cannot be
accessed by move instructions.

There are two 40-bit units, MR and SR, built by the 16-bit registers SR2,

SR1, SR0 and MR2, MR1, MR0. The individual register may input to any com-

putation unit, but grouped together they function as accumulators for the
MAC unit (multiply and accumulate). SR also functions as a shifter result
register.

DM DATA BUS

PM DATA BUS

IO DATA BUS

E
R

R

REGISTER FILE

MX0 MY0 MX1 MY1

AX0 AX1 AY0 AY1

SR2 SR1 SR0

MR2 MR1 MR0

AR

ASTAT

MSTAT

ALU

R

YX

AFMAC

EXPONENT STATUS

SBSE SI

SHIFTER

I

X

Y

Figure 2-1. Register Access—Unconditional, Single-Function Instructions

ADSP-219x/2191 DSP Hardware Reference 2-3

Overview

Figure 2-1 on page 2-3 shows how unconditional, single-function multi-

plier, ALU, and shifter instructions have unrestricted access to the data
registers in the register file. Due to opcode limitations, conditional and
multi-function instructions provide ADSP-218x legacy register access
only. Details are located in the corresponding sections.

The

MR2 and SR2 registers differ from the other results registers. As a data

register file register, MR2 and SR2 are 16-bit registers that may be X- or
Y-inputs to the multiplier, ALU, or shifter. As result registers (part of MR
or SR), only the lower 8-bits of MR2 or SR2 hold data (the upper 8-bits are
sign extended). This difference (16-bits as input, 8-bits as output) influ­ences how code can use the MR2 and SR2 registers. This sign extension
appears in Figure 2-12 on page 2-32.

Using register-to-register move instructions, the data registers can load (or
be loaded from) the Shifter Block (SB) and Shifter Exponent (SE) registers,
but the SB and SE registers may not provide X- or Y-input to the computa­tional units. The SB and SE registers serve as additional inputs to the
shifter.

The MR2 and SR2 registers differ from the other results registers. As a data
register file register, MR2 and SR2 are 16-bit registers that may be X- or
Y-inputs to the multiplier, ALU, or shifter. As result registers (part of MR
or SR), only the lower 8-bits of MR2 or SR2 hold data (the upper 8-bits are
sign extended). This difference (16-bits as input, 8-bits as output) influ­ences how code can use the MR2 and SR2 registers. This sign extension
appears in Figure 2-12 on page 2-32.

Using register-to-register move instructions, the data registers can load (or
be loaded from) the Shifter Block (
but the
tional units. The

SB and SE registers may not provide X- or Y-input to the computa-

SB and SE registers serve as additional inputs to the

SB) and Shifter Exponent (SE) registers,

shifter.

2-4 ADSP-219x/2191 DSP Hardware Reference

Computational Units

The shaded boxes behind the data register file and the
ters indicate that secondary registers are available for these registers. There
are two sets of data registers. Only one bank is accessible at a time. The
additional bank of registers can be activated (such as during an interrupt
service routine) for extremely fast context switching. A new task, like an
interrupt service routine, can be executed without transferring current
states to storage. For more information, see “Secondary (Alternate) Data

Registers” on page 2-63.

The Mode Status (MSTAT) register input sets arithmetic modes for the
computational units, and the Arithmetic Status (ASTAT) register records
status/conditions for the computation operations’ results.

SB, SE, and AF regis-

Data Formats

ADSP-219x DSPs are 16-bit, fixed-point machines. Most operations
assume a twos complement number representation, while others assume
unsigned numbers or simple binary strings. Special features support multi­word arithmetic and block floating-point. For detailed information on
each number format, see “Numeric Formats” on page C-1.

In ADSP-219x family arithmetic, signed numbers are always in twos com­plement format. These DSPs do not use signed magnitude, ones
complement, BCD, or excess-n formats.

ADSP-219x/2191 DSP Hardware Reference 2-5

Data Formats

This section provides the following topics:

• “Binary String” on page 2-6

• “Unsigned” on page 2-6

• “Signed Numbers: Twos Complement” on page 2-7

• “Signed Fractional Representation: 1.15” on page 2-7

• “ALU Data Types” on page 2-7

• “Multiplier Data Types” on page 2-8

• “Shifter Data Types” on page 2-9

• “Arithmetic Formats Summary” on page 2-9

Binary String

This format is the least complex binary notation; sixteen bits are treated as
a bit pattern. Examples of computations using this format are the logical
operations: NOT, AND, OR, and XOR. These ALU operations treat their oper­ands as binary strings with no provision for sign bit or binary point
placement.

Unsigned

Unsigned binary numbers may be thought of as positive, having nearly
twice the magnitude of a signed number of the same length. The DSP
treats the least significant words of multiple precision numbers as
unsigned numbers.

2-6 ADSP-219x/2191 DSP Hardware Reference

Computational Units

Signed Numbers: Twos Complement

In ADSP-219x DSP arithmetic, the term “signed” refers to twos comple­ment. Most ADSP-219x family operations presume or support twos
complement arithmetic.

Signed Fractional Representation: 1.15

ADSP-219x DSP arithmetic is optimized for numerical values in a frac­tional binary format denoted by 1.15 (“one dot fifteen”). In the 1.15
format, there is one sign bit (the MSB) and fifteen fractional bits repre­senting values from –1 up to one LSB less than +1.

Figure 2-2 on page 2-7 shows the bit weighting for 1.15 numbers. These

are examples of 1.15 numbers and their decimal equivalents.

1.15 NUMBER (HEXADECIMAL)
0X0001

0X7FFF
0XFFFF

0X8000

–202–12–22–32–42–52–62–72–82–92

DECIMAL EQUIVALENT

0.000031

0.999969
–0.000031
–1.000000

–102–112–122–132–142–15

Figure 2-2. Bit Weighting for 1.15 Numbers

ALU Data Types

All operations on the ALU treat operands and results as 16-bit binary
strings, except the signed division primitive (DIVS). ALU result status bits
treat the results as signed, indicating status with the overflow (
tion code and the negative (

AN) flag.

ADSP-219x/2191 DSP Hardware Reference 2-7

AV) condi-

Data Formats

The logic of the overflow bit (
metic. It is set if the MSB changes in a manner not predicted by the signs
of the operands and the nature of the operation. For example, adding two
positive numbers generates a positive result; a change in the sign bit signi­fies an overflow and sets AV. Adding a negative and a positive may result in
either a negative or positive result, but cannot overflow.

The logic of the carry bit (AC) is based on unsigned-magnitude arithmetic.
It is set if a carry is generated from bit 16 (the MSB). The (AC) bit is most
useful for the lower word portions of a multiword operation.

ALU results generate status information. For more information on using
ALU status, see “ALU Status Flags” on page 2-19.

L

Except for division, the ALU operations do not need to distinguish
between signed or unsigned, integer or fractional formats. Formats
are a matter of result interpretation only.

AV) is based on twos complement arith-

Multiplier Data Types

The multiplier produces results that are binary strings. The inputs are
“interpreted” according to the information given in the instruction itself
(signed times signed, unsigned times unsigned, a mixture, or a rounding
operation). The 32-bit result from the multiplier is assumed to be signed,
in that it is sign-extended across the full 40-bit width of the
ter set.

MR or SR regis-

The ADSP-219x DSPs support two modes of format adjustment: frac­tional mode for fractional operands (1.15 format with 1 signed bit and 15
fractional bits) and integer mode for integer operands (16.0 format).

When the processor multiplies two 1.15 operands, the result is a 2.30
(two sign bits and 30 fractional bits) number. In fractional mode, the mul­tiplier automatically shifts the multiplier product (P) left one bit before

2-8 ADSP-219x/2191 DSP Hardware Reference

Computational Units

transferring the result to the multiplier result register (
causes the multiplier result to be in 1.31 format, which can be rounded to

1.15 format. This result format appears in Figure 2-3 on page 2-14.

In integer mode, the left shift does not occur. For example, if the operands
are in the 16.0 format, the 32-bit multiplier result would be in 32.0 for­mat. A left shift is not needed; it would change the numerical
representation. This result format appears in Figure 2-4 on page 2-15.

Multiplier results generate status information. For more information on
using multiplier status, see “Multiplier Status Flags” on page 2-34.

MR). This shift

Shifter Data Types

Many operations in the shifter are explicitly geared to signed (twos com­plement) or unsigned values: logical shifts assume unsigned-magnitude or
binary string values, and arithmetic shifts assume twos complement
values.

The exponent logic assumes twos complement numbers. The exponent
logic supports block floating-point, which is also based on twos comple­ment fractions.

Shifter results generate status information. For more information on using
shifter status, see “Shifter Status Flags” on page 2-54.

Arithmetic Formats Summary

Table 2-1 on page 2-10, Table 2-2 on page 2-10, and Table 2-3 on
page 2-11 summarize some of the arithmetic characteristics of computa-

tional operations.

ADSP-219x/2191 DSP Hardware Reference 2-9

Data Formats

Table 2-1. ALU Arithmetic Formats

Operation Operands Formats Result Formats

Addition Signed or unsigned Interpret flags

Subtraction Signed or unsigned Interpret flags

Logical Operations Binary string same as operands

Division Explicitly signed/unsigned same as operands

ALU Overflow Signed same as operands

ALU Carry Bit 16-bit unsigned same as operands

ALU Saturation Signed same as operands

Table 2-2. Multiplier Arithmetic Formats

Operation (by Mode) Operands Formats Result Formats

Multiplier, Fractional Mode

Multiplication (MR/SR) 1.15 Explicitly signed/unsigned 2.30 shifted to 1.31

Mult / Add 1.15 Explicitly signed/unsigned 2.30 shifted to 1.31

Mult / Subtract 1.15 Explicitly signed/unsigned 2.30 shifted to 1.31

Multiplier Saturation Signed same as operands

Multiplier, Integer Mode

Multiplication (MR/SR) 16.0 Explicitly signed/unsigned 32.0 no shift

Mult / Add 16.0 Explicitly signed/unsigned 32.0 no shift

Mult / Subtract 16.0 Explicitly signed/unsigned 32.0 no shift

Multiplier Saturation Signed same as operands

2-10 ADSP-219x/2191 DSP Hardware Reference

Computational Units

Table 2-3. Shifter Arithmetic Formats

Operation Operands Formats Result Formats

Logical Shift Unsigned / binary string same as operands

Arithmetic Shift Signed same as operands

Exponent Detection Signed same as operands

Setting Computational Modes

The MSTAT and ICNTL registers control the operating mode of the computa­tional units. Figure A-2 on page A-10 lists all the bits in MSTAT, and

Figure A-5 on page A-16 lists all the bits in ICNTL. The following bits in

MSTAT and ICNTL control computational modes:

• ALU overflow latch mode. MSTAT Bit 2 (AV_LATCH) determines how

the ALU overflow flag, AV, gets cleared (0=AV is “not-sticky”, 1=AV
is “sticky”).

• ALU saturation mode. MSTAT Bit 3 (AR_SAT) determines (for signed

values) whether ALU AR results that overflowed or underflowed are
saturated or not (0=unsaturated, 1=saturated).

• Multiplier result mode. MSTAT Bit 4 (M_MODE) selects fractional 1.15

format (=0) or integer 16.0 format (=1) for all multiplier opera­tions. The multiplier adjusts the format of the result according to
the selected mode.

• Multiplier biased rounding mode. ICNTL Bit 7 (BIASRND) selects

unbiased (=0) or biased (=1) rounding for multiplier results.

ADSP-219x/2191 DSP Hardware Reference 2-11

Setting Computational Modes

This section provides the following topics:

• “Latching ALU Result Overflow Status” on page 2-12

• “Saturating ALU Results on Overflow” on page 2-12

• “Using Multiplier Integer and Fractional Formats” on page 2-13

• “Rounding Multiplier Results” on page 2-15

Latching ALU Result Overflow Status

The DSP supports an ALU overflow latch mode with the AV_LATCH bit in
the MSTAT register. This bit determines how the ALU overflow flag, AV,
gets cleared.

If AV_LATCH is disabled (=0), the AV bit is “not-sticky”. When an ALU
overflow sets the AV bit in the ASTAT register, the AV bit only remains set
until cleared by a subsequent ALU operation that does not generate an
overflow (or is explicitly cleared).

If AV_LATCH is enabled (=1), the AV bit is “sticky”. When an ALU overflow
sets the AV bit in the ASTAT register, the AV bit remains set until the appli­cation explicitly clears it.

Saturating ALU Results on Overflow

The DSP supports an ALU saturation mode with the AR_SAT bit in the

MSTAT register. This bit determines (for signed values) whether ALU AR

results that overflowed or underflowed are saturated or not. This bit
enables (if set, =1) or disables (if cleared, =0) saturation for all subsequent
ALU operations. If AR_SAT is disabled, AR results remain unsaturated and is

2-12 ADSP-219x/2191 DSP Hardware Reference

Computational Units

returned unchanged. If

AR_SAT is enabled, AR results are saturated accord-

ing to the state of the AV and AC status flags in ASTAT shown in Table 2-4

on page 2-13.

Table 2-4. ALU Result Saturation With AR_SAT Enabled

AV AC A R register

0 0 ALU output not saturated

0 1 ALU output not saturated

1 0 ALU output saturated, maximum positive 0x7FFF

1 1 ALU output saturated, maximum negative 0x8000

The AR_SAT bit in MSTAT only affects the AR register. Only the

L

results written to the AR register are saturated. If results are written
to the AF register, wraparound occurs, but the AV and AC flags
reflect the saturated result.

Using Multiplier Integer and Fractional Formats

For multiply/accumulate functions, the DSP provides two modes: frac­tional mode for fractional numbers (1.15), and integer mode for integers
(16.0).

In the fractional mode, the 32-bit product output is format adjusted—
sign-extended and shifted one bit to the left—before being added to

MR.

For example, bit 31 of the product lines up with bit 32 of MR (which is bit
0 of MR2) and bit 0 of the product lines up with bit 1 of MR (which is bit 1
of

MR0). The LSB is zero-filled. The fractional multiplier result format

appears in Figure 2-3 on page 2-14.

ADSP-219x/2191 DSP Hardware Reference 2-13

Setting Computational Modes

SHIFTED

OUT

PSIGN,7

BITS

313131313131313130292827262524232221201918171615141312111098765432103

MR2 MR1 MR0

1

MULTIPLIER P OUTPUT

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0151413121110987654321076543210

Figure 2-3. Fractional Multiplier Results Format

After adjustment the result of a 1.15 by 1.15 fractional multiplication is
available in 1.31 format (

MR1:MR0 or SR1:SR0). If 32-bit precision is not

required MR1 or SR1 hold the result in 1.15 data representation. MR2
and SR2 do not contain multiplication results. They are needed for accu­mulation only.

ZERO

FILLED

In integer mode, the 32-bit Product register is not shifted before being
added to MR. Figure 2-4 on page 2-15 shows the integer-mode result place-
ment. After a 16.0 by 16.0 multiplication

MR1:MR0 (SR1:SR0) hold the

32.0 result.

The mode is selected by the M_MODE bit in the Mode Status (MSTAT) regis­ter. If

M_MODE is set (=1), integer mode is selected. If M_MODE is cleared (=0),

fractional mode is selected. In either mode, the multiplier output Product
is fed into a 40-bit adder/subtracter, which adds or subtracts the new
product with the current contents of the MR register to form the final
40-bit result.

2-14 ADSP-219x/2191 DSP Hardware Reference

Computational Units

PSIGN,8

BITS

313131313131313130292827262524232221201918171615141312111098765432103

MR2 MR1 MR0

1

MULTIPLIE R P OUTP UT

1514131211109876543210151413121110987654321076543210

Figure 2-4. Integer Multiplier Results Format

Rounding Multiplier Results

The DSP supports multiplier results rounding (RND option) on most mul­tiplier operations. With the BIASRND bit in the ICNTL register, programs
select whether the Rnd option provides biased or unbiased rounding.

Unbiased Rounding

Unbiased rounding uses the multiplier’s capability for rounding the 40-bit
result at the boundary between bit 15 and bit 16. Rounding can be speci­fied as part of the instruction code. The rounded output is directed to
either

MR or SR. When rounding is selected, MR1/SR1 contains the rounded

16-bit result; the rounding effect in MR1/SR1 affects MR2/SR2 as well. The

MR2/MR1 and SR2/SR1 registers represent the rounded 24-bit result.

ADSP-219x/2191 DSP Hardware Reference 2-15

Setting Computational Modes

The accumulator uses an unbiased rounding scheme. The conventional
method of biased rounding is to add a 1 into bit position 15 of the adder
chain. This method causes a net positive bias, because the midway value
(when

MR0=0x8000) is always rounded upward. The accumulator elimi-

nates this bias by forcing bit 16 in the result output to zero when it detects
this midway point. This has the effect of rounding odd MR1 values upward
and even MR1 values downward, yielding a zero large-sample bias assuming
uniformly distributed values.

Using x to represent any bit pattern (not all zeros), here are two examples
of rounding. The example in Figure 2-5 on page 2-16 shows a typical
rounding operation for MR; these also apply for SR.

...MR2..|.......MR1......|.......MR0......

Unrounded value:
Add 1 and carry:
Rounded value:

xxxxxxxx|xxxxxxxx00100101|1xxxxxxxxxxxxxxx

........|................|1...............

xxxxxxxx|xxxxxxxx00100110|0xxxxxxxxxxxxxxx

Figure 2-5. Typical Unbiased Multiplier Rounding Operation

The compensation to avoid net bias becomes visible when the lower 15
bits are all zero and bit 15 is one (the midpoint value) as shown in

Figure 2-6 on page 2-16.

...MR2..|.......MR1......|.......MR0......

Unrounded value:
Add 1 and carry:
MR bit 16=1:
Rounded value:

xxxxxxxx|xxxxxxxx01100110|1000000000000000

........|................|1...............

xxxxxxxx|xxxxxxxx01100111|0000000000000000
xxxxxxxx|xxxxxxxx01100110|0000000000000000

Figure 2-6. Avoiding Net Bias in Unbiased Multiplier Rounding
Operation

2-16 ADSP-219x/2191 DSP Hardware Reference

Computational Units

In Figure 2-6 on page 2-16,

MR bit 16 is forced to zero. This algorithm is

employed on every rounding operation, but is only evident when the bit
patterns shown in the lower 16 bits of the last example are present.

Biased Rounding

The BIASRND bit in the ICNTL register enables biased rounding. When the

BIASRND bit is cleared (=0), the RND option in multiplier instructions uses

the normal unbiased rounding operation (as discussed in “Unbiased

Rounding” on page 2-15). When the BIASRND bit is set to 1, the DSP uses

biased rounding instead of unbiased rounding. When operating in biased
rounding mode, all rounding operations with MR0 set to 0x8000 round up,
rather than only rounding odd MR1 values up. For an example, see

Figure 2-7 on page 2-17.

MR before RND

Biased RND result

Unbiased RND result

0x00 0000 8000 0x00 0001 0000 0x00 0000 0000

0001 8000 0x00 0002 0000 0x00 0002 0000

0x00

0000 8001 0x00 0001 0001 0x00 0001 0001

0x00

0001 8001 0x00 0002 0001 0x00 0002 0001

0x00

0000 7FFF 0x00 0000 FFFF 0x00 0000 FFFF

0x00

0001 7FFF 0x00 0001 FFFF 0x00 0001 FFFF

0x00

Figure 2-7. Bias Rounding in Multiplier Operation

This mode only has an effect when the

MR0 register contains 0x8000; all

other rounding operations work normally. This mode allows more effi­cient implementation of bit-specified algorithms that use biased rounding,
for example the GSM speech compression routines. Unbiased rounding is
preferred for most algorithms. Note that the content of

MR0 and SR0 is

invalid after rounding.

ADSP-219x/2191 DSP Hardware Reference 2-17

Using Computational Status

Using Computational Status

The multiplier, ALU, and shifter update overflow and other status flags in
the DSP’s Arithmetic Status (ASTAT) register. To use status conditions
from computations in program sequencing, use conditional instructions to
test the exception flags in the ASTAT register after the instruction executes.
This method permits monitoring each instruction’s outcome.

More information on ASTAT appears in the sections that describe the com­putational units. For summaries relating instructions and status bits, see

“ALU Status Flags” on page 2-19, “Multiplier Status Flags” on page 2-34,

and “Shifter Status Flags” on page 2-54.

Arithmetic Logic Unit (ALU)

The ALU performs arithmetic and logical operations on fixed-point data.
ALU fixed-point instructions operate on 16-bit fixed-point operands and
output 16-bit fixed-point results. ALU instructions include:

• Fixed-point addition and subtraction

• Fixed-point add with carry, subtract with borrow, increment,
decrement

•Logical

• Functions: ABS, PASS, division primitives

2-18 ADSP-219x/2191 DSP Hardware Reference

AND, OR, XOR, or NOT

Computational Units

This section provides the following topics:

• “ALU Operation” on page 2-19

• “ALU Status Flags” on page 2-19

• “ALU Instruction Summary” on page 2-20

• “ALU Data Flow Details” on page 2-23

• “ALU Division Support Features” on page 2-25

ALU Operation

ALU instructions take one or two inputs: X input and Y input. For uncon­ditional, single-function instructions, these inputs (also known as
operands) can be any data registers in the register file. Most ALU opera­tions return one result, but in PASS operations the ALU operation returns
no result (only status flags are updated). ALU results are written to the
ALU Result (AR) register or ALU Feedback (AF) register.

The DSP transfers input operands from the register file during the first
half of the cycle and transfers results to the result register during the sec­ond half of the cycle. With this arrangement, the ALU can read and write
the AR register file location in a single cycle.

ALU Status Flags

ALU operations update status flags in the DSP’s Arithmetic Status (ASTAT)
register. Table A-1 on page A-9 lists all the bits in this register. Table 2-5

on page 2-20 shows the bits in ASTAT that flag ALU status (a 1 indicates

the condition is true) for the most recent ALU operation.

ADSP-219x/2191 DSP Hardware Reference 2-19

Arithmetic Logic Unit (ALU)

Table 2-5. ALU Status Bits in the ASTAT Register

Flag Name Definition

AZ Zero Logical NOR of all the bits in the ALU result register. True if ALU out-

put equals zero.

AN Negative Sign bit of the ALU result. True if the ALU output is negative.

AV Overflow Exclusive-OR of the carry outputs of the two most significant adder

stages. True if the ALU overflows.

AC Carry Carry output from the most significant adder stage.

AS Sign Sign bit of the ALU X input port. Affected only by the ABS instruction.

AQ Quotient Quotient bit generated only by the DIVS and DIVQ instructions.

Flag updates occur at the end of the cycle in which the status is generated
and are available in the next cycle.

L

POS (AS bit =1) and NEG (AS bit =0) conditions permit checking the

ALU result’s sign. On ADSP-219x-based DSPs, the CCODE register
and SWCOND condition support this feature.

Unlike previous ADSP-218x DSPs, ASTAT writes on

On previous 16-bit, fixed-point DSPs (ADSP-2100 family), the

L

ADSP-219x-based DSPs have a one cycle effect latency. Code
being ported from ADSP-218x to ADSP-219x-based DSPs that
check ALU status during the instruction following an
(

ASTAT=0) instruction may not function as intended. Re-arranging

ASTAT clear

the order of instructions to accommodate the one cycle effect
latency on the ADSP-219x-based

ASTAT register corrects this issue.

ALU Instruction Summary

Table 2-6 on page 2-21 lists the ALU instructions and describes how they

relate to
same whether the result goes to the AR or AF registers. For more informa-

ASTAT flags. As indicated by the table, the ALU handles flags the

2-20 ADSP-219x/2191 DSP Hardware Reference

Computational Units

tion on assembly language syntax, see the ADSP-219x DSP Instruction Set
Reference. In Table 2-6 on page 2-21, note the meaning of the following

symbols:

• Dreg, Dreg1, Dreg2 indicate any register file location

• XOP, YOP indicate any X- and Y-input registers, indicating a reg-

ister usage restriction for conditional and/or multifunction
instructions. For more information, see “Multifunction Computa-

tions” on page 2-64.

• * indicates the flag may be set or cleared, depending on results of

instruction

• ** indicates the flag is cleared, regardless of the results of

instruction

• – indicates no effect

Table 2-6. ALU Instruction Summary

Instruction ASTAT Status Flags

AZ AV A N AC AS AQ

|AR, AF| = Dreg1 + |Dreg2, Dreg2 + C, C |; *

[IF Cond] |AR, AF| = Xop + |Yop, Yop + C, C, Const, Const + C|; * ***––

|AR, AF| = Dreg1 - |Dreg2, Dreg2 + C 1, +C -1|; * ***––

[IF Cond]|AR,AF| = Xop - |Yop,Yop+C-1,+C-1,Const,Const+C -1|; *

|AR, AF| = Dreg2 - |Dreg1, Dreg1 + C -1|; * ***––

[IF Cond] |AR, AF| = Yop - |Xop, Xop+C-1|; * ***––

[IF Cond] |AR,AF| = - |Xop+C -1, Xop+Const, Xop+Const+C-1|; *

|AR, AF| = Dreg1 |AND, OR, XOR| Dreg2; *

[IF Cond] |AR, AF| = Xop |AND, OR, XOR| |Yop, Const|; *

[IF Cond]|AR,AF| = |TSTBIT,SETBIT,CLRBIT,TGLBIT| n of Xop; *

|AR, AF| = PASS |Dreg1, Dreg2, Const|; *

|AR, AF| = PASS 0; ** ** * ** – –

***––

***––

***––

** * ** – –

** * ** – –

** * ** – –

** * ** – –

ADSP-219x/2191 DSP Hardware Reference 2-21

Arithmetic Logic Unit (ALU)

Table 2-6. ALU Instruction Summary (Cont’d)

Instruction ASTAT Status Flags

AZ AV A N AC AS AQ

[IF Cond] |AR, AF| = PASS |Xop, Yop, Const|; * ** * ** – –

|AR, AF| = NOT |Dreg|; * ** * ** – –

[IF Cond] |AR, AF| = NOT |Xop, Yop|; * ** * ** – –

|AR, AF| = ABS Dreg; *

[IF Cond] |AR, AF| = ABS Xop; * ** ** ** * –

|AR, AF| = Dreg +1; * ***––

[IF Cond] |AR, AF| = Yop +1; *

|AR, AF| = Dreg -1; * ***––

[IF Cond] |AR, AF| = Yop -1; * ***––

DIVS Yop, Xop; –

DIVQ Xop; – ––––*

** ** ** * –

***––

–––– *

2-22 ADSP-219x/2191 DSP Hardware Reference

Computational Units

ALU Data Flow Details

Figure 2-8 shows a more detailed diagram of the ALU, which appears in
Figure 2-1 on page 2-3.

REGISTER FILE

MR2 MR1 MR0

AR AX1

AQ

AC

AR_SAT

AV_LATCH

AX0 AY0

AY1SR1 S R0

16

XY

ALU

R

16

AR

MX1 MY1 SR2

16

AQ

AC

AV

AZ
AN

AS

SIMX0 MY0

CONSTANT

AF

16

Figure 2-8. ALU Block Diagram

ADSP-219x/2191 DSP Hardware Reference 2-23

Arithmetic Logic Unit (ALU)

The ALU is 16 bits wide with two 16-bit input ports, X and Y, and one
output port, R. The ALU accepts a carry-in signal (

CI) which is the carry

bit (AC) from the processor arithmetic status register (ASTAT). The ALU
generates six status signals:

• Zero (AZ)

• Negative (AN)

• Carry (AC)

• Overflow (AV)

• X-input sign (AS)

• Quotient (AQ)

All arithmetic status signals are latched into the Arithmetic Status (ASTAT)
register at the end of the cycle. For information on how each instruction
affects the ALU flags, see Table 2-6 on page 2-21.

Unless a NONE= instruction is executed, the output of the ALU goes into
the ALU Feedback (AF) register or the ALU Result (AR) register, which is
part of the register file. The AF register is an ALU internal register.

In unconditional and single-function instructions, both the X and the Y
port may read any register of the register file including AR. Alternatively,
the Y port may access the ALU Feedback (

AF) register.

For conditional and multi-function instructions only, a subset of registers
can be used as input operands. For legacy support this register usage
restriction mirrors the ADSP-218x instruction set. Then the X port can
access the AR, SR1, SR0, MR2, MR1, MR0, AX0, and AX1 registers. The Y port
accesses

AY0, AY1, and AF.

2-24 ADSP-219x/2191 DSP Hardware Reference

Computational Units

If the X port accesses
tor may be a constant coded in the instruction word.

L

The ALU can read and write any of its associated registers in the same
cycle. Registers are read at the beginning of the cycle and written at the
end of the cycle. A register read gets the value loaded at the end of a previ­ous cycle. A new value written to a register cannot be read out until a
subsequent cycle. This read/write pattern lets an input register provide an
operand to the ALU at the beginning of the cycle and be updated with the
next operand from memory at the end of the same cycle. Also, this
read/write pattern lets a result register be stored in memory and updated
with a new result in the same cycle.

Multiprecision operations are supported in the ALU with the carry-in sig­nal and ALU carry (AC) status bit. The carry-in signal is the AC status bit
that was generated by a previous ALU operation. The “add with carry”
(+C) operation is intended for adding the upper portions of multipreci­sion numbers. The “subtract with borrow” (C–1 is effectively a “borrow”)
operation is intended for subtracting the upper portions of multiprecision
numbers.

For more information on register usage restrictions in conditional
and multifunction instructions, see “Multifunction Computations”

on page 2-64.

AR, SR1, SR0, MR2, MR1, MR0, AX0, or AX1, the Y opera-

ALU Division Support Features

The ALU supports division with two special divide primitives. These
instructions (
tional (error checking), add-subtract division algorithm. The division can
be either signed or unsigned, but the dividend and divisor must both be of
the same type. More details on using division and programming examples
are available in the ADSP-219x DSP Instruction Set Reference.

ADSP-219x/2191 DSP Hardware Reference 2-25

DIVS, DIVQ) let programs implement a non-restoring, condi-

Arithmetic Logic Unit (ALU)

A single-precision divide, with a 32-bit dividend (numerator) and a 16-bit
divisor (denominator), yielding a 16-bit quotient, executes in 16 cycles.
Higher- and lower-precision quotients can also be calculated. The divisor
can be stored in

AX0, AX1, or any of the R registers. The upper half of a

signed dividend can start in either AY1 or AF. The upper half of an
unsigned dividend must be in AF. The lower half of any dividend must be
in AY0. At the end of the divide operation, the quotient is in AY0.

The first of the two primitive instructions “divide-sign” (DIVS) is executed
at the beginning of the division when dividing signed numbers. This oper­ation computes the sign bit of the quotient by performing an exclusive OR
of the sign bits of the divisor and the dividend. The AY0 register is shifted
one place so that the computed sign bit is moved into the LSB position.
The computed sign bit is also loaded into the AQ bit of the arithmetic sta­tus register. The MSB of AY0 shifts into the LSB position of AF, and the
upper 15 bits of AF are loaded with the lower 15 R bits from the ALU,
which simply passes the Y input value straight through to the R output.
The net effect is to left shift the AF-AY0 register pair and move the quotient
sign bit into the LSB position. The operation of Divs is illustrated in

Figure 2-9 on page 2-27.

When dividing unsigned numbers, the DIVS operation is not used. Instead,
the AQ bit in the arithmetic status register (ASTAT) should be initialized to
zero by manually clearing it. The AQ bit indicates to the following opera­tions that the quotient should be assumed positive.

The second division primitive is the “divide-quotient” (

DIVQ) instruction,

which generates one bit of quotient at a time and is executed repeatedly to
compute the remaining quotient bits.

For unsigned single-precision divides, the

Divq instruction is executed 16

times to produce 16 quotient bits. For signed single-precision divides, the

DIVQ instruction is executed 15 times after the sign bit is computed by the
DIVS operation. DIVQ instruction shifts the AY0 register left by one bit so

that the new quotient bit can be moved into the LSB position.

2-26 ADSP-219x/2191 DSP Hardware Reference

Computational Units

15

LEFT SHIFT

L

S

B

LOWER

DIVIDEND

AQ

15 LSBS

R-BUS

AX1 AY1 A FAX0 AY0

16

MUX

DIVISOR

DIVIDEND

MSB

X

ALU

R=PASSY

MUX

UPPER

MSB

Y

Figure 2-9. DIVS Operation

The status of the AQ bit generated from the previous operation determines
the ALU operation to calculate the partial remainder. If
adds the divisor to the partial remainder in

AF. If AQ = 0, the ALU sub-

AQ = 1, the ALU

tracts the divisor from the partial remainder in AF.

The ALU output R is offset loaded into AF just as with the Divs operation.
The

AQ bit is computed as the exclusive-OR of the divisor MSB and the

ALU output MSB, and the quotient bit is this value inverted. The quo­tient bit is loaded into the LSB of the
by one bit. The

DIVQ operation is illustrated in Figure 2-10 on page 2-28.

AY0 register which is also shifted left

ADSP-219x/2191 DSP Hardware Reference 2-27

Arithmetic Logic Unit (ALU)

AX0

MUX

AX1

PARTIAL

REMAINDER

15

LEFTSHIFT

L

AF

16

S
B

AY0

LOWER

DIVIDEND

DIVISOR

R-BUS

MSB

X

ALU

R=Y+X IF AQ=1
R=Y-X IF AQ=0

Y

AQ

1MSB

15 LSBS

Figure 2-10. DIVQ Operation

The format of the quotient for any numeric representation can be deter­mined by the format of the dividend and divisor as shown in Figure 2-11

on page 2-29. Let NL represent the number of bits to the left of the binary

point, let NR represent the number of bits to the right of the binary point
of the dividend, let DL represent the number of bits to the left of the
binary point, and let DR represent the number of bits to the right of the

2-28 ADSP-219x/2191 DSP Hardware Reference