ANALOG DEVICES ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 Service Manual

SHARC Processor

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 Stage

Sequencer

PEx PEy

PMD

64-BIT

IOD0 32-BIT

EPD BUS 64-BIT

Core Bus

Cross Bar

DAI Routing/Pins

S/PDIF Tx/Rx

PCG A

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI

SDRAM

CTL

External Port Pin MUX

TIMER

SPORT

ASRC

3-0

PWM

DAG1/2

Core

Timer

PDAP/

IDP 7

TWI

IOD0 BUS

DTCP/

MTM

PCG C

PERIPHERAL BUS

32-BIT

CORE

FLAGS/

PWM3

JTAG

Internal Memory

DMD

64-BIT

PMD 64-BIT

CORE

FLAGS

IOD1 32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals DAI Peripherals Peripherals

External Port

SIMD Core

THERMAL

DIODE

FFT FIR

IIR

SPEP BUS

DMD

64-BIT

FLAGx/IRQx/ TMREXP

WDT

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip

ROM Up to 400 MHz operating frequency Code compatible with all other members of the SHARC family

The ADSP-2148x processors are available with unique audio-

centric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more

For complete ordering information, see Ordering Guide on

Page 66

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Summary ............................................................... 1

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 7

I/O Processor Features ......................................... 10

System Design .................................................... 11

Development Tools ............................................. 12

Additional Information ........................................ 12

Related Signal Chains .......................................... 12

Pin Function Descriptions ....................................... 13

Specifications ........................................................ 17

Operating Conditions .......................................... 17

Electrical Characteristics ....................................... 18

Absolute Maximum Ratings .................................. 20

REVISION HISTORY

4/12—Revision 0 to Revision A

Corrected outstanding document errata.

Corrected EMU

Corrected units in Power Up Sequencing Timing Requirements

(Processor Startup) .................................................. 22

Corrected t

Corrected parameter descriptions in Serial Ports—TDV (Trans-

mit Data Valid) ...................................................... 38

Added new product models to Automotive Products ....... 65

Ordering Guide ...................................................... 66

pin type in Pin Descriptions .................13

parameter in Serial Ports—External Clock 34

SCLKW

Package Information ............................................ 20

ESD Sensitivity ................................................... 20

Maximum Power Dissipation ................................. 20

Timing Specifications ........................................... 20

Output Drive Currents ......................................... 54

Test Conditions .................................................. 54

Capacitive Loading .............................................. 54

Thermal Characteristics ........................................ 55

100-LQFP_EP Lead Assignment ................................ 57

176-Lead LQFP_EP Lead Assignment ......................... 59

Outline Dimensions ................................................ 63

Surface-Mount Design .......................................... 64

Automotive Products .............................................. 65

Ordering Guide ..................................................... 66

Rev. A | Page 2 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

GENERAL DESCRIPTION

The ADSP-2148x SHARC® processors are members of the

Table 1. Processor Benchmarks

SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2148x processors are 32-bit/40-bit floating point processors optimized for high performance audio applications with large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI).

Table 1 shows performance benchmarks for the ADSP-2148x

processors. Table 2 shows the features of the individual product offerings.

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with Reversal) 23 s FIR Filter (per Tap) IIR Filter (per Biquad)

Matrix Multiply (Pipelined) [3 × 3] × [3 × 1] [4 × 4] × [4 × 1]

Divide (y/×) 7.5 ns Inverse Square Root 11.25 ns

Assumes two files in multichannel SIMD mode

Speed (at 400 MHz)

1.25 ns 5 ns

11.25 ns 20 ns

Table 2. ADSP-2148x Family Features

Feature ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489

Maximum Instruction Rate 400 MHz RAM 3 Mbits 5 Mbits 3 Mbits 5 Mbits ROM 4 Mbits No Audio Decoders in ROM

Ye s N o Pulse-Width Modulation 4 Units (3 Units on 100-Lead Packages) DTCP Hardware Accelerator Contact Analog Devices External Port Interface (SDRAM, AMI)

Yes (16-bit) AMI Only Yes (16-bit) Serial Ports 8 Di rect D MA from S PORTs t o Ex tern al Por t

Ye s

(External Memory) FIR, IIR, FFT Accelerator Yes Watchdog Timer Yes (176-Lead Package Only) MediaLB Interface Automotive Models Only IDP/PDAP Ye s UART 1 DAI (SRU)/DPI (SRU2) Yes S/PDIF Transceiver Yes SPI Ye s TWI 1 SRC Performance

–128 dB Thermal Diode Yes VISA Support Yes Package

ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby Labs and DTS. Decoder/post-processor algorithm

The 100-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function

Some models have –140 dB performance. For more information, see Ordering Guide on page 66.

combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information.

Descriptions on Page 13. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP Lead Assignment on page 59.

176-Lead LQFP EPAD 100-Lead LQFP EPAD

176-Lead LQFP

EPAD

176-Lead LQFP EPAD 100-Lead LQFP EPAD

Rev. A | Page 3 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

The diagram on Page 1 shows the two clock domains that make up the ADSP-2148x processors. The core clock domain contains the following features:

• Two processing elements (PEx, PEy), each of which comprises an ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting 2x64-bit data transfers between memory and the core at every core processor cycle

• One periodic interval timer with pinout

• On-chip SRAM (5 Mbit) and mask-programmable ROM (4 Mbit)

• JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints which allows flexible exception handling.

The block diagram of the ADSP-2148x on Page 1 also shows the peripheral clock domain (also known as the I/O processor) which contains the following features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an AMI and SDRAM controller

•4 units for PWM control

• 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers

• Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP) for serial and parallel interconnects, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial ports, and a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, a 2-wire interface (TWI), one UART, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG), pulse width modulation (PWM), and a flexible signal routing unit (DPI SRU2).

As shown in the SHARC core block diagram on Page 5, the processor uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. With its SIMD computational hardware, the processors can perform 2.4 GFLOPS running at 400 MHz.

FAMILY CORE ARCHITECTURE

The ADSP-2148x is code compatible at the assembly level with the ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2148x shares architectural features with the ADSP-2126x, ADSP2136x, ADSP-2137x, ADSP-2146x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections.

SIMD Computational Engine

The ADSP-2148x contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms.

SIMD mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or register file access.

Independent, Parallel Computation Units

Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle and are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit fixed-point data formats.

Timer

The processor contains a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal.

Data Register File

Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register.

Rev. A | Page 4 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1 16x32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

Rx/Fx

PEx

16x40-BIT

JTAG

DMD/PMD 64

PM DATA 48

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

USTAT

4x32-BIT

64-BIT

DAG2 16x32

MULTIPLIER

DATA SWAP

PM ADDRESS 24

ALU SHIFTER

Universal Registers

These registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all peripheral registers (control/status).

The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-2148x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data. With the its separate program and data memory buses and onchip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.

Instruction Cache

The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.

Data Address Generators With Zero-Overhead Hardware Circular Buffer Support

The two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.

Figure 2. SHARC Core Block Diagram

Rev. A | Page 5 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the processor can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory, all in a single instruction.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from previous SHARC processors, the ADSP-2148x supports new instructions of 16 and 32 bits. This feature, called Variable Instruction Set Architecture (VISA), drops redundant/unused bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external SDRAM memory. This support is not extended to the asynchronous memory interface (AMI). Source modules need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes.

Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF

Reserved 0x0004 8000–0x0004 8FFF

Block 0 SRAM 0x0004 9000–0x0004 CFFF

Reserved 0x0004 D000–0x0004 FFFF

Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF

Reserved 0x0005 8000–0x0005 8FFF

Block 1 SRAM 0x0005 9000–0x0005 CFFF

Reserved 0x0005 D000–0x0005 FFFF

Block 2 SRAM 0x0006 0000–0x0006 1FFF

Reserved 0x0006 2000– 0x0006 FFFF

Block 3 SRAM 0x0007 0000–0x0007 1FFF

Reserved 0x0007 2000–0x0007 FFFF

Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog

Devices sales representative for additional details.

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9

Reserved 0x0008 AAAA–0x0008 BFFF

Block 0 SRAM 0x0008 C000–0x0009 1554

Reserved 0x0009 1555–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9

Reserved 0x000A AAAA–0x000A BFFF

Block 1 SRAM 0x000A C000–0x000B 1554

Reserved 0x000B 1555–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 2AA9

Reserved 0x000C 2AAA–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 2AA9

Reserved 0x000E 2AAA–0x000F FFFF

On-Chip Memory

The ADSP-21483 and the ADSP-21488 processors contain 3 Mbits of internal RAM (Table 3) and the ADSP-21486, ADSP-21487, and ADSP-21489 processors contain 5 Mbits of internal RAM (Table 4). Each memory block supports singlecycle, independent accesses by the core processor and I/O processor.

The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.

Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF

Reserved 0x0009 0000–0x0009 1FFF

Block 0 SRAM 0x0009 2000–0x0009 9FFF

Reserved 0x0009 A000–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000A FFFF

Reserved 0x000B 0000–0x000B 1FFF

Block 1 SRAM 0x000B 2000–0x000B 9FFF

Reserved 0x000B A000–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 3FFF

Reserved 0x000C 4000–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 3FFF

Reserved 0x000E 4000–0x000F FFFF

Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF

Reserved 0x0012 0000–0x0012 3FFF

Block 0 SRAM 0x0012 4000–0x0013 3FFF

Reserved 0x0013 4000–0x0013 FFFF

Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF

Reserved 0x0016 0000–0x0016 3FFF

Block 1 SRAM 0x0016 4000–0x0017 3FFF

Reserved 0x0017 4000–0x0017 FFFF

Block 2 SRAM 0x0018 0000–0x0018 7FFF

Reserved 0x0018 8000–0x001B FFFF

Block 3 SRAM 0x001C 0000–0x001C 7FFF

Reserved 0x001C 8000–0x001F FFFF

Rev. A | Page 6 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 4. Internal Memory Space (5 MBits—ADSP-21486/ADSP-21487/ADSP-21489)

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF

Reserved 0x0004 8000–0x0004 8FFF

Block 0 SRAM 0x0004 9000–0x0004 EFFF

Reserved 0x0004 F000–0x0004 FFFF

Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF

Reserved 0x0005 8000–0x0005 8FFF

Block 1 SRAM 0x0005 9000–0x0005 EFFF

Reserved 0x0005 F000–0x0005 FFFF

Block 2 SRAM 0x0006 0000–0x0006 3FFF

Reserved 0x0006 4000– 0x0006 FFFF

Block 3 SRAM 0x0007 0000–0x0007 3FFF

Reserved 0x0007 4000–0x0007 FFFF

Some ADSP-2148x processors include a customer-definable ROM block and are not reserved as shown on this table. Please contact your Analog Devices sales representative

for additional details.

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9

Reserved 0x0008 AAAA–0x0008 BFFF

Block 0 SRAM 0x0008 C000–0x0009 3FFF

Reserved 0x0009 4000–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9

Reserved 0x000A AAAA–0x000A BFFF

Block 1 SRAM 0x000A C000–0x000B 3FFF

Reserved 0x000B 4000–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 5554

Reserved 0x000C 5555–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 5554

Reserved 0x000E 5555–0x0000F FFFF

Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF

Reserved 0x0009 0000–0x0009 1FFF

Block 0 SRAM 0x0009 2000–0x0009 DFFF

Reserved 0x0009 E000–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000A FFFF

Reserved 0x000B 0000–0x000B 1FFF

Block 1 SRAM 0x000B 2000–0x000B DFFF

Reserved 0x000B E000–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 7FFF

Reserved 0x000C 8000–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 7FFF

Reserved 0x000E 8000–0x000F FFFF

Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF

Reserved 0x0012 0000–0x0012 3FFF

Block 0 SRAM 0x0012 4000–0x0013 BFFF

Reserved 0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF

Reserved 0x0016 0000–0x0016 3FFF

Block 1 SRAM 0x0016 4000–0x0017 BFFF

Reserved 0x0017 C000–0x0017 FFFF

Block 2 SRAM 0x0018 0000–0x0018 FFFF

Reserved 0x0019 0000–0x001B FFFF

Block 3 SRAM 0x001C 0000–0x001C FFFF

Reserved 0x001D 0000–0x001F FFFF

Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

The memory maps in Table 3 and Table 4 display the internal memory address space of the processors. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory.

ROM Based Security

The ADSP-2148x has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processor does not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port will be assigned to each customer. The device will ignore a wrong key. Emulation features are available after the correct key is scanned.

Rev. A | Page 7 of 68 | April 2012

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bits, CCLK speed) and the IOD0/1 buses (2 × 32-bit, PCLK speed).

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2148x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications.

External Memory

The external port interface supports access to the external memory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. The external ports are comprised of the following modules.

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

• An Asynchronous Memory Interface which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 6M words of external memory in bank 0 and 8M words of external memory in bank 1, bank 2, and bank 3.

• A SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in bank 0, and 64M words of external memory in bank 1, bank 2, and bank 3. NOTE: this feature is not available on the ADSP-21486 product.

• Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port.

Non-SDRAM external memory address space is shown in

Table 5.

Table 5. External Memory for Non-SDRAM Addresses

Size in

Bank

Bank 0 6M 0x0020 0000–0x007F FFFF Bank 1 8M 0x0400 0000–0x047F FFFF Bank 2 8M 0x0800 0000–0x087F FFFF Bank 3 8M 0x0C00 0000–0x0C7F FFFF

Words Address Range

External Port

The external port provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The external port, available on the 176-lead LQFP, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3 occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic.

SDRAM Controller

The SDRAM controller provides an interface of up to four separate banks of industry-standard SDRAM devices at speeds up to f

. Fully compliant with the SDRAM standard, each bank has

SDCLK

its own memory select line (MS0

–MS3), and can be configured

to contain between 4M bytes and 256M bytes of memory.

SDRAM external memory address space is shown in Table 6. NOTE: this feature is not available on the ADSP-21486 model.

Table 6. External Memory for SDRAM Addresses

Size in

Bank

Bank 0 62M 0x0020 0000–0x03FF FFFF Bank 1 64M 0x0400 0000–0x07FF FFFF Bank 2 64M 0x0800 0000–0x0BFF FFFF Bank 3 64M 0x0C00 0000–0x0FFF FFFF

Words Address Range

A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. Note that 32-bit wide devices are not supported on the SDRAM and AMI interfaces.

The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF.

Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap.

SIMD Access to External Memory

The SDRAM controller on the processor supports SIMD access on the 64-bit EPD (external port data bus) which allows access to the complementary registers on the PEy unit in the normal word space (NW). This removes the need to explicitly access the complimentary registers when the data is in external SDRAM memory.

VISA and ISA Access to External Memory

The SDRAM controller on the ADSP-2148x processors supports VISA code operation which reduces the memory load since the VISA instructions are compressed. Moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. Code execution from the traditional ISA operation is also supported. Note that code execution is only supported from bank 0 regardless of VISA/ISA. Table 7 shows the address ranges for instruction fetch in each mode.

Table 7. External Bank 0 Instruction Fetch

Size in

Access Type

ISA (NW) 4M 0x0020 0000–0x005F FFFF

VISA (SW) 10M 0x0060 0000–0x00FF FFFF

Words Address Range

Rev. A | Page 8 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms).

The entire PWM module has four groups of four PWM outputs generating 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs.

The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single-update mode or double-update mode. In single-update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double-update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters.

PWM signals can be mapped to the external port address lines or to the DPI pins.

MediaLB

The automotive models of the ADSP-2148x processors have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin as well as 5-pin media local bus protocols. It supports speeds up to 1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. For a list of automotive models, see Automotive Products on

Page 65.

Digital Applications Interface (DAI)

The digital applications interface (DAI) allows the connection of various peripherals to any of the DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU).

The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths.

The DAI includes eight serial ports, four precision clock generators (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports.

Serial Ports (SPORTs)

The ADSP-2148x features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame.

Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard serial mode

•Multichannel (TDM) mode

S mode

•I

•Packed I

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the receiver/transmitter can be formatted as left-justified, I right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, or the precision clock generators (PCGs), and are controlled by the SRU control registers.

Asynchronous Sample Rate Converter (SRC)

The asynchronous sample rate converter contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver.

Input Data Port

The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided

S mode

S or

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

into two 32-bit words. The serial protocol is designed to receive audio channels in I mode.

The IDP also provides a parallel data acquisition port (PDAP), which can be used for receiving parallel data. The PDAP port has a clock input and a hold input. The data for the PDAP can be received from DAI pins or from the external port pins. The PDAP supports a maximum of 20-bit data and four different packing modes to receive the incoming data.

Precision Clock Generators

The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair.

The outputs of PCG A and B can be routed through the DAI pins and the outputs of PCG C and D can be driven on to the DAI as well as the DPI pins.

S, left-justified sample pair, or right-justified

Digital Peripheral Interface (DPI)

The ADSP-2148x SHARC processors have a digital peripheral interface that provides connections to two serial peripheral interface ports (SPI), one universal asynchronous receivertransmitter (UART), 12 flags, a 2-wire interface (TWI), three PWM modules (PWM3–1), and two general-purpose timers.

Serial Peripheral (Compatible) Interface (SPI)

The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O)—The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access)—The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

Ti me rs

The ADSP-2148x has a total of three timers: a core timer that can generate periodic software interrupts and two generalpurpose timers that can generate periodic interrupts and be independently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer expired signal, and the general-purpose timers have one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables the generalpurpose timer.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the I The TWI master incorporates the following features:

• 7-bit addressing

• Simultaneous master and slave operation on multiple device systems with support for multi master data arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

C bus protocol.

I/O PROCESSOR FEATURES

The I/O processors provide up to 65 channels of DMA, as well as an extensive set of peripherals.

DMA Controller

The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-2148x’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the PDAP, or the UART. The DMA channel summary is shown in Table 8.

Programs can be downloaded to the ADSP-2148x using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers.

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Table 8. DMA Channels

Peripheral DMA Channels

SPORTs 16 IDP/PDAP 8 SPI 2 UART 2 External Port 2 Accelerators 2 Memory-to-Memory 2

MLB

Automotive models only.

Delay Line DMA

The processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction.

Scatter/Gather DMA

The processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from non contiguous memory blocks.

FFT Accelerator

The FFT accelerator implements a radix-2 complex/real input, complex output FFT with no core intervention. The FFT accelerator runs at the peripheral clock frequency.

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency.

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data, and one MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency.

Watchd og Tim er

The watchdog timer is used to supervise the stability of the system software. When used in this way, software reloads the watchdog timer in a regular manner so that the downward counting timer never expires. An expiring timer then indicates that system software might be out of control.

The 32-bit watchdog timer that can be used to implement a software watchdog function. A software watchdog can improve system reliability by forcing the processor to a known state through generation of a system reset, if the timer expires before being reloaded by software. Software initializes the count value of the timer, and then enables the timer. The watchdog timer resets both the core and the internal peripherals. Note that this feature is available on the 176-lead package only.

SYSTEM DESIGN

The following sections provide an introduction to system design options and power supply issues.

Program Booting

The internal memory of the ADSP-2148x boots at system power-up from an 8-bit EPROM via the external port, an SPI master, or an SPI slave. Booting is determined by the boot configuration (BOOT_CFG2–0) pins in Table 9 for the 176-lead package and Table 10 for the 100-lead package.

Table 9. Boot Mode Selection, 176-Lead Package

BOOT_CFG2–0 Booting Mode

000 SPI Slave Boot 001 SPI Master Boot 010 AMI User Boot (for 8-bit Flash Boot) 011 No boot (processor executes from internal

ROM after reset)

1xx Reserved

Table 10. Boot Mode Selection, 100-Lead Package

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot 01 SPI Master Boot 10 Reserved 11 No boot (processor executes from internal

ROM after reset)

The “Running Reset” feature allows a user to perform a reset of the processor core and peripherals, but without resetting the PLL and SDRAM controller, or performing a boot. The functionality of the RESETOUT extended to also act as the input for initiating a Running Reset. For more information, see the ADSP-214xx SHARC Processor Hardware Reference.

Power Supplies

The processors have separate power supply connections for the internal (V

) and external (V

DD_INT

internal supply must meet the V external supply must meet the V nal supply pins must be connected to the same power supply.

To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for V

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-2148x processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator will not affect target system loading or timing.

/RUNRSTIN pin has now been

) power supplies. The

DD_EXT

specifications. The

DD_INT

specification. All exter-

DD_EXT

and GND.

DD_INT

Rev. A | Page 11 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The ADSP-2148x processors are supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-2148x processors.

EZ-KIT Lite Evaluation Board

For evaluation of the processors, use the EZ-KIT Lite® board from Analog Devices. The board comes with on-chip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

software and hardware development tools,

and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board Flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2148x architecture and functionality. For detailed information on the ADSP-2148x family core architecture and instruction set, refer to the SHARC Processor Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab provides:

• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection guides and application information

• Reference designs applying best practice design techniques

site (www.analog.com/circuits)

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute,

Rev. A | Page 12 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

PIN FUNCTION DESCRIPTIONS

Table 11. Pin Descriptions

State During/

Name Type

ADDR

23–0

DATA

15–0

AMI_ACK I (ipu) Memory Acknowledge. External devices can deassert AMI_ACK (low) to add wait

0–1

AMI_RD

AMI_WR

FLAG0/IRQ0

FLAG1/IRQ1 I/O (ipu) FLAG[1]

FLAG2/IRQ2

FLAG3/TMREXP/MS3

The following symbols appear in the Type column of Tab le 11 : A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the ex ternal pads to the expected logic levels, use external resistors. I nternal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63k . The range of an ipd resistor can be between 31k–85k . The three-state voltage of ipu pads will not reach to the full V conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

/MS2 I/O (ipu) FLAG[2]

I/O/T (ipu) High-Z/

I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory

O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asserted whenever the processor reads a word from

O/T (ipu) High-Z AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to

I/O (ipu) FLAG[0]

I/O (ipu) FLAG[3]

After Reset Description

External Address. The processor outputs addresses for external memory and periph-

driven low (boot)

INPUT

erals on these pins. The ADDR pins can be multiplexed to support the external memory interface address, and FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in external memory interface mode and FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR for parallel input data.

interface data (I/O), and FLAGS

states to an external memory access. AMI_ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access.

sponding banks of external memory. The MS that change at the same time as the other address lines. When no external memory access is occurring the MS tional memory access instruction is executed, whether or not the condition is true. The MS1 ADSP-214xx SHARC Processor Hardware Reference.

external memory.

FLAG0/Interrupt Request0.

FLAG1/Interrupt Request1.

FLAG2/Interrupt Request2/Memory Select2.

FLAG3/Timer Expired/Memory Select3.

pin can be used in EPORT/FLASH boot mode. For more information, see the

23–4

(I/O).

7–0

lines are decoded memory address lines

1-0

lines are inactive; they are active however when a condi-

1-0

level; at typical

DD_EXT

pins

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Table 11. Pin Descriptions (Continued)

State During/

Name Type

SDRAS O/T (ipu) High-Z/

SDCAS O/T (ipu) High-Z/

SDWE

SDCKE O/T (ipu) High-Z/

SDA10 O/T (ipu) High-Z/

SDDQM O/T (ipu) High-Z/

SDCLK O/T (ipd) High-Z/

DAI _P

20–1

DPI _P

14–1

WDT_CLKIN I Watchdog Timer Clock Input. This pin should be pulled low when not used. WDT_CLKO O Watchdog Resonator Pad Output. WDTRSTO THD_P I Thermal Diode Anode. When not used, this pin can be left floating. THD_M O Thermal Diode Cathode. When not used, this pin can be left floating. The following symbols appear in the Type column of Tab le 11: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,

O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the ex ternal pads to the expected logic levels, use external resistor s. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63k . The range of an ipd resistor can be between 31k–85k . The three-state voltage of ipu pads will not reach to the full V conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

O/T (ipu) High-Z/

I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI

I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

O (ipu) Watchdog Timer Reset Out.

After Reset Description

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

driven high

driving

SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform. SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device. SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-SDRAM

accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses. DQM Data Mask. SDRAM Input mask signal for write accesses and output mask signal

for read accesses. Input data is masked when DQM is sampled high during a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM is sampled high during a read cycle. SDDQM is driven high from reset de-assertion until SDRAM initialization completes. Afterwards it is driven low irrespective of whether any SDRAM accesses occur or not.

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See

Figure 41 on Page 54. For models in the 100-lead package, the SDRAM interface should

be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference

SRU. The DAI SRU configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins.

level; at typical

DD_EXT

Rev. A | Page 14 of 68 | April 2012

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Table 11. Pin Descriptions (Continued)

State During/

Name Type

MLBCLK

MLBDAT

I Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-

I/O/T in 3 pin mode. I in 5 pin mode.

MLBSIG

I/O/T in 3 pin mode. I in 5 pin mode

MLBDO

MLBSO

O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.

O/T High-Z Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB

TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path. TMS I (ipu) Test Mode Select (JTAG). Used to control the test state machine. TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

TRST

EMU

I (ipu) Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

O (O/D, ipu) High-Z Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools

After Reset Description

nized to the MOST network and provides the timing for the entire MLB interface at

49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be grounded.

High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and

is received by all other MLB devices including the MLB controller. The MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB controller is not used, this pin should be grounded.

High-Z Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address

generated by the MLB Controller, as well as the Command and RxStatus bytes from MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, this pin should be grounded.

This serves as the output data pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground.

mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is not used, this pin should be connected to ground.

(pulsed low) after power-up or held low for proper operation of the device.

after power-up or held low for proper operation of the processor.

product line of JTAG emulators target board connector only.

level; at typical

DD_EXT

Rev. A | Page 15 of 68 | April 2012

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Table 11. Pin Descriptions (Continued)

State During/

Name Type

CLK_CFG

1–0

I Core to CLKIN Ratio Control. These pins set the start up clock frequency.

CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It configures

XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

RESET

RESETOUT/

I Processor Reset. Resets the processor to a known state. Upon deassertion, there is a

I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also

RUNRSTIN

BOOT_CFG

2–0

I Boot Configuration Select. These pins select the boot mode for the processor (see

The following symbols appear in the Type column of Tab le 11: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the ex ternal pads to the expected logic levels, use external resistor s. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26k–63k . The range of an ipd resistor can be between 31k–85k . The three-state voltage of ipu pads will not reach to the full V conditions the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.

The MLB pins are only available on the automotive models.

After Reset Description

Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. The allowed values are: 00 = 8:1

01 = 32:1 10 = 16:1

11 = reserved

the processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency.

crystal.

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up.

has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor Hardwa re Reference.

Tab le 9). The BOOT_CFG pins must be valid before RESET

asserted.

(hardware and software) is

level; at typical

DD_EXT

Table 12. Pin List, Power and Ground

Name Type Description

DD_INT

DD_EXT

GND V

DD_THD

The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. No separate GND pins are provided in the package.

P Internal Power Supply P I/O Power Supply G Ground P Thermal Diode Power Supply. When not used, this pin can be left floating.

Rev. A | Page 16 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

SPECIFICATIONS

OPERATING CONDITIONS

300 MHz 350 MHz 400 MHz

Description Min Nom Max Min Nom Max Min Nom Max

DD_INT

DD_EXT

DD_THD

Low Level Input Voltage @

IH_CLKIN

IL_CLKIN

Internal (Core) Supply Voltage 1.05 1.1 1.15 1.05 1.1 1.15 1.05 1.1 1.15 V External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V Thermal Diode Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V High Level Input Voltage @

= Max

DD_EXT

2.0 3.6 2.0 3.6 2.0 3.6 V

–0.3 0.8 –0.3 0.8 –0.3 0.8 V

= Min

DD_EXT

High Level Input Voltage @

= Max

DD_EXT

Low Level Input Voltage @ V

= Min

DD_EXT

Junction Temperature 100-Lead LQFP_EP @ T

AMBIENT

2.2 V

DD_EXT

2.2 V

DD_EXT

2.2 V

–0.3 +0.8 –0.3 +0.8 –0.3 +0.8 V

0 110 0 110 0 110 °C

DD_EXT

0°C to +70°C

Junction Temperature 100-Lead LQFP_EP @ T

AMBIENT

–40 125 –40 125 –40 125 °C

–40°C to +85°C

Junction Temperature 176-Lead LQFP_EP @ T

AMBIENT

0 110 0 110 0 110 °C

0°C to +70°C

Junction Temperature 176-Lead LQFP_EP @ T

AMBIENT

–40 125 –40 125 –40 125 °C

–40°C to +85°C

Specifications subject to change without notice.

Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST,

AMI_ACK, MLBCLK, MLBDAT, MLBSIG.

Applies to input pins CLKIN, WDT_CLKIN.

UnitParameter

Rev. A | Page 17 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

ELECTRICAL CHARACTERISTICS

300 MHz 350 MHz 400 MHz

Parameter1Description Test Conditions Min Max Min Max Min Max Unit

4, 5

ILPU

6, 7

OZH

OZL

OZLPU

OZHPD

DD-INTYP

11, 12

Specifications subject to change without notice.

Applies to output and bidirectional pins: ADDR23–0, DATA15–0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

See Output Drive Currents on Page 54 for typical drive current capabilities.

Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

Applies to input pins with internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pin: TDO.

Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

Applies to three-statable pin with pull-down: SDCLK.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-214xx SHARC Processors (EE-348) for further information.

Applies to all signal pins.

Guaranteed, but not tested.

High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Low Level Input Current Pull-up Three-State Leakage Current Three-State Leakage Current

Three-State Leakage Current Pull-up

Three-State Leakage Current Pull-down

9, 10

Supply Current (Internal) Input Capacitance T

@ V –1.0 mA @ V

1.0 mA @ V = V @ V

DD_EXT

= Min, IOH =

= Min, IOL =

= Max, VIN

Max

= Max, VIN

2.4 2.4 2.4 V

0.4 0.4 0.4 V

10 10 10 µA

10 10 10 µA = 0 V @ V

DD_EXT

= Max, VIN

200 200 200 µA = 0 V @ V = V @ V

DD_EXT

= Max, VIN

Max

= Max, VIN

10 10 10 µA

10 10 10 µA = 0 V @ V

DD_EXT

= Max, VIN

200 200 200 µA = 0 V @ V = V V

DDINT

DD_EXT

=1.1 V,

= Max, VIN

Max

200 200 200 µA

410 450 500 mA ASF = 1, TJ = 25°C

= 25°C 5 5 5 pF

CASE

Rev. A | Page 18 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Total Power Dissipation

Total power dissipation has two components:

1. Internal power consumption

2. External power consumption

Internal power consumption also comprises two components:

1. Static, due to leakage current. Table 13 shows the static current consumption (I temperature (T

2. Dynamic (I

DD-DYNAMC

DD-STATIC

) and core voltage (V

) as a function of junction

DD_INT

), due to transistor switching characteristics and activity level of the processor. The activity level is reflected by the Activity Scaling Factor (ASF), which represents application code running on the processor core and having various levels of peripheral and external port activity (Table 13). Dynamic current consumption is calculated by scaling the specific application by the ASF and using baseline dynamic current consumption as a reference.

External power consumption is due to the switching activity of the external pins.

The ASF is combined with the CCLK frequency and V

DD_INT

dependent data in Table 14 to calculate this part. The second part is due to transistor switching in the peripheral clock (PCLK) domain, which is included in the I

DD_INT

specification

equation.

Table 13. Activity Scaling Factors (ASF)

Table 14. Static Current—I

TJ (°C)

1.05 V 1.10 V 1.15 V

DD-STATIC

DD_INT

–45 96 118 144 –35 103 126 154 –25 113 138 168 –15 127 155 187 –5 147 177 212 +5 171 206 245 +15 201 240 285 +25 237 280 331 +35 279 329 388 +45 331 389 455 +55 391 458 533 +65 464 539 626 +75 547 633 731 +85 645 746 860 +95 761 877 1007 +105 897 1026 1179 +115 1047 1198 1372 +125 1219 1397 1601

Valid temperature and voltage ranges are model-specific. See Operating Condi-

tions on Page 17.

(mA)

(V)

Activity Scaling Factor (ASF)

Idle 0.29 Low 0.53 Medium Low 0.61 Medium High 0.77 Peak Typical (50:50) Peak Typical (60:40) Peak Typical (70:30)

0.85

0.93

1.00 High Typical 1.16 High 1.25 Peak 1.31

See Estimating Power for ADSP-214xx SHARC Processors (EE-348) for more

information on the explanation of the power vectors specific to the ASF table.

Ratio of continuous instruction loop (core) to SDRAM control code reads and

writes.

Table 15. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)

CCLK

(MHz)

1, 2

Voltage (V

DD_INT

)

1.05 V 1.10 V 1.15 V

100 84 88 92 150 126 133 139 200 165 174 183 250 207 217 229 300 246 260 273 350 286 302 318 400 326 344 361

The values are not guaranteed as standalone maximum specifications. They must

be combined with static current per the equations of Electrical Characteristics

on Page 18.

Valid frequency and voltage ranges are model-specific. See Operating Conditions

on Page 17.

Rev. A | Page 19 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

vvvvvv.x n.n

tppZ-cc

ADSP-2148x

#yyww country_of_origin

ESD

(electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 16 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 16. Absolute Maximum Ratings

Parameter Rating

Internal (Core) Supply Voltage (V External (I/O) Supply Voltage (V Thermal Diode Supply Voltage

(V Input Voltage –0.5 V to +3.6 V Output Voltage Swing –0.5 V to V Storage Temperature Range –65°C to +150°C Junction Temperature While Biased 125°C

DD_THD

)

) –0.3 V to +1.32 V

DD_INT

)–0.3 V to +3.6 V

DD_EXT

–0.3 V to +3.6 V

DD_EXT

+0.5 V

PACKAGE INFORMATION

The information presented in Figure 3 provides details about the package branding for the ADSP-2148x processors. For a complete listing of product availability, see Ordering Guide on

Page 66.

Figure 3. Typical Package Brand

Table 17. Package Brand Information

Brand Key Field Description

t Temperature Range pp Package Type Z RoHS Compliant Option cc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision # RoHS Compliant Designation yyww Date Code

Non automotive only. For branding information specific to automotive products,

contact Analog Devices Inc.

ESD SENSITIVITY

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-214xx SHARC Processors” (EE-348) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see

Thermal Characteristics on Page 55.

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See

Figure 43 on Page 54 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.

Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, the processor core, and the serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 4). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock.

Rev. A | Page 20 of 68 | April 2012

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

LOOP

FILTER

CLKIN

PCLK

SDRAM

DIVIDER

BYPASS

MUX

PMCTL

(SDCKR)

CCLK

PLL

XTAL

CLKIN

DIVIDER

RESET

VCO

÷ (2 × PLLM)

BUF

VCO

BUF

PMCTL (INDIV)

PLL

DIVIDER

RESETOUT

CLKOUT (TEST ONLY)*

DELAY OF

4096 CLKIN

CYCLES

PCLK

PMCTL

(PLLBP)

PMCTL (PLLD)

VCO

CCLK

INPUT

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f

INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

CLK_CFGx/

PMCTL (2 × PLLM)

DIVIDE

BY 2

MUX

PMCTL

(PLLBP)

CCLK

RESETOUT

CORESRST

SDCLK

BYPASS

MUX

Voltage Controlled Oscillator (VCO)

In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds

specified in Table 20.

VCO

• The product of CLKIN and PLLM must never exceed 1/2 of f

(max) in Table 20 if the input divider is not enabled

VCO

(INDIV = 0).

• The product of CLKIN and PLLM must never exceed f

VCO

(max) in Table 20 if the input divider is enabled (INDIV = 1).

The VCO frequency is calculated as follows:

= 2 × PLLM × f

VCO

= (2 × PLLM × f

CCLK

INPUT

) ÷ PLLD

where:

= VCO output

VCO

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware.

PLLD = 2, 4, 8, or 16 based on the divider value programmed on the PMCTL register. During reset this value is 2.

= is the input frequency to the PLL.

INPUT

= CLKIN when the input divider is disabled or

INPUT

= CLKIN ÷ 2 when the input divider is enabled

INPUT

Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 18. All of the timing specifications for the ADSP-2148x peripherals are defined in relation to t

. See the peripheral specific section

PCLK

for each peripheral’s timing information.

Table 18. Clock Periods

Timing Requirements Description

CCLK

PCLK

SDCLK

CLKIN Clock Period Processor Core Clock Period Peripheral Clock Period = 2 × t SDRAM Clock Period = (t

CCLK

) × SDCKR

Figure 4 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-214xx SHARC Processor Hard- ware Reference.

Figure 4. Core Clock and System Clock Relationship to CLKIN

Rev. A | Page 21 of 68 | April 2012

+ 47 hidden pages

ANALOG DEVICES ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SUMMARY

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

FAMILY CORE ARCHITECTURE

SIMD Computational Engine

Independent, Parallel Computation Units

Timer

Data Register File

Context Switch

Universal Registers

Single-Cycle Fetch of Instruction and Four Operands

Instruction Cache

Data Address Generators With Zero-Overhead Hardware Circular Buffer Support

Flexible Instruction Set

Variable Instruction Set Architecture (VISA)

On-Chip Memory

ROM Based Security

On-Chip Memory Bandwidth

FAMILY PERIPHERAL ARCHITECTURE

External Memory

External Port

Asynchronous Memory Controller

SDRAM Controller

SIMD Access to External Memory

VISA and ISA Access to External Memory

Pulse-Width Modulation

MediaLB

Digital Applications Interface (DAI)

Serial Ports (SPORTs)

S/PDIF-Compatible Digital Audio Receiver/Transmitter

Asynchronous Sample Rate Converter (SRC)

Input Data Port

Precision Clock Generators

Digital Peripheral Interface (DPI)

Serial Peripheral (Compatible) Interface (SPI)

UART Port

Ti me rs

2-Wire Interface Port (TWI)

I/O PROCESSOR FEATURES

DMA Controller

Delay Line DMA

Scatter/Gather DMA

FFT Accelerator

FIR Accelerator

IIR Accelerator

Watchd og Tim er

SYSTEM DESIGN

Program Booting

Power Supplies

Target Board JTAG Emulator Connector

DEVELOPMENT TOOLS

EZ-KIT Lite Evaluation Board

Designing an Emulator-Compatible DSP Board (Target)

ADDITIONAL INFORMATION

RELATED SIGNAL CHAINS

Evaluation Kit

PIN FUNCTION DESCRIPTIONS

SPECIFICATIONS

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Total Power Dissipation

ABSOLUTE MAXIMUM RATINGS

PACKAGE INFORMATION

ESD SENSITIVITY

MAXIMUM POWER DISSIPATION

TIMING SPECIFICATIONS

Core Clock Requirements

Voltage Controlled Oscillator (VCO)