Analog Devices ADSP 21364 prc Datasheet
a
SHARC® Processor
Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for professional audio processing
At 333 MHz/2 GFLOPs, with unique audio centric peripherals
such as the digital audio interface that includes a high-precision 8-channel asynchronous sample rate converter
among others, the ADSP-21364 SHARC processor is ideal
for applications that require industry leading equalization,
reverberation and other effects processing
Single-Instruction Multiple-Data (SIMD) computational
architecture
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit
extended precision floating-point computational units,
each with a multiplier, ALU, shifter, and register file
CORE PROCESSOR
INSTRUCTION
TIMER
CACHE
32 X 48-BIT
ADSP-21364
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21364 is available with a 333 MHz core instruction
rate and unique audiocentric peripherals such as the digi-
tal audio interface, S/PDIF transceiver, serial ports, 8-
channel asynchronous sample rate converter, precision
clock generators, and more. For complete ordering infor-
mation, see Ordering Guide on page 54.
BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3
SRAM
1M BIT ROM
2M BIT
4 BLOCKS OF ON-CHIP MEMORY
SRAM
1M B IT ROM
2M BIT
SRAM
0.5M BIT
SRAM
0.5M BIT
DAG1
8X4X32
PROCESSING
ELEMENT
(PEX)
DAG2
8X4X32
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
PROCESSING
ELEMENT
(PEY)
JTAG TEST & EMULATION
PX REGISTER
PROGRAM
SEQUENCER
DM DATA BUS
32
32
64
64
6
S
Figure 1. Functional Block Diagram—Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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ADDR DATA
IOA
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
ADDR DATA
IOD
IOP REGISTERS
(MEMORY MAPPED)
IOA
ADDR DATA
IOD IOA IOD IOD
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
I/O PROCESSOR
AND PERIPHERALS
SEE “ADSP-21364 MEMORY
AND I/O INTERFACE FEATURES”
SECTIO N FOR DETA ILS
ADDR DATA
IOA
ROUTING
SIGNAL
UNIT
ADSP-21364 Preliminary Technical Data
KEY FEATURES—PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-21364
performs 2 GFLOPS/666 MMACS
3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit
in blocks 2 and 3) for simultaneous access by core processor and DMA
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
4M bit on-chip, single-ported mask-programmable ROM (2M
bit in block 0 and 2M bit in block 1)
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single-Instruction Multiple-Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Parallelism in buses and computational units allows single
cycle execution (with or without SIMD) of a multiply or
ALU operation, a dual memory read or write, and an
instruction fetch
Transfers between memory and core at a sustained 5.4
Gbytes/s bandwidth at 333 MHz core instruction rate
INPUT/OUTPUT FEATURES
DMA Controller supports:
25 DMA channels for transfers between ADSP-21364 internal
memory and a variety of peripherals
32-bit DMA transfers at peripheral clock speed, in parallel
with full-speed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55 Mbyte per sec transfer rate
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
cision clock generators, an input data port, three timers,
eight-channel asynchronous sample rate converter, and a
signal routing unit
Six dual data line serial ports that operate at up to 50M bit/s
on each data line—each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
Left justified sample pair and I
direction for up to 24 simultaneous receive or transmit
channels using two I
port
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
2
2
S support, programmable
S compatible stereo devices per serial
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the
SHARC core, configurable as eight channels of serial data
or seven channels of serial data and up to a 20-bit wide
parallel data channel
Signal routing unit provides configurable and flexible con-
nections between all DAI components–six serial ports, two
precision clock generators, an input data port with a data
acquisition port, one SPI port, eight channels of asynchro-
nous sample rate converters, three timers, 10 interrupts,
six flag inputs, six flag outputs, and 20 SRU I/O pins
(DAI_Px)
Two serial peripheral interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI
Full-duplex operation
Master slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
DEDICATED AUDIO COMPONENTS
S/PDIF compatible digital audio receiver/transmitter
supports:
EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left justified, I
18, 20 or 24 bit word widths (transmitter)
Two channel mode and single channel double frequency
(SCDF) mode
Four independent Asynchronous Sample Rate Converters
(SRC). Each converter has separate serial input and output
ports, a deemphasis filter providing up to -140dB SNR per-
formance, stereo sample rate converter (SRC) and supports
left-justified, I
20, 18 and 16 audio data word lengths
Pulse-Width Modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in nonpaired mode
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball mini-BGA and 144-lead LQFP Packages
2
S or right justified serial data input with 16,
2
S, TDM and right-justified modes and 24,
Rev. PrC | Page 2 of 54 | February 2005
CONTENTS
Summary ............................................................... 1
Key Features – Processor Core ................................. 2
Input/Output Features ........................................... 2
Dedicated Audio Components ................................. 2
General Description ................................................. 3
ADSP-21364 Family Core Architecture ...................... 3
ADSP-21364 Memory and I/O Interface Features ......... 5
Development Tools ............................................... 8
Additional Information ......................................... 10
Pin Function Descriptions ........................................ 11
Address Data Pins as FLAGs .................................. 14
Address Data Modes ............................................. 14
Boot Modes ........................................................ 14
Core Instruction Rate to CLKIN Ratio Modes ............. 14
ADSP-21364 Specifications ....................................... 15
Recommended Operating Conditions ....................... 15
Electrical Characteristics ........................................ 15
Maximum Power Dissipation ................................. 16
Absolute Maximum Ratings ................................... 16
ESD Sensitivity .................................................... 16
Timing Specifications ........................................... 16
Output Drive Currents .......................................... 41
Test Conditions ................................................... 41
Capacitive Loading ............................................... 41
Thermal Characteristics ........................................ 42
136-Ball BGA Pin Configurations ............................... 44
144-Lead LQFP Pin Configurations ............................. 47
Package Dimensions ................................................ 48
Ordering Guide ...................................................... 50
ADSP-21364Preliminary Technical Data
REVISION HISTORY
2/05–Data sheet changed from REV. PrB to REV PrC.
Power Supplies .........................................................9
Core Clock and System Clock Relationship to CLKIN ..... 18
Precision Clock Generator (Direct Pin Routing) ............. 25
Memory Read—Parallel Port ..................................... 27
Memory Write—Parallel Port .................................... 29
SPDIF Transmitter .................................................. 39
Sample Rate Converter—Serial Output Port .................. 38
Rev. PrC | Page 3 of 54 | February 2005
ADSP-21364 Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-21364 SHARC processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices' Super Harvard Architecture. The ADSP-21364 is source code compatible
with the ADSP-2126x, and ADSP-2116x DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. The ADSP-21364 is a 32bit/40-bit floating-point processor optimized for professional
audio applications with a large on-chip SRAM, multiple internal
buses to eliminate I/O bottlenecks, and an innovative digital
audio interface (DAI).
As shown in the functional block diagram on Page 1, the
ADSP-21364 uses two computational units to deliver a significant performance increase over previous SHARC processors on
a range of signal processing algorithms. Fabricated in a state-ofthe-art, high speed, CMOS process, the ADSP-21364 processor
achieves an instruction cycle time of 3.0 ns at 333 MHz. With its
SIMD computational hardware, the ADSP-21364 can perform 2
GFLOPS running at 333 MHz.
Table 1 shows performance benchmarks for the ADSP-21364.
Table 1. ADSP-21364 Benchmarks (at 333 MHz)
Benchmark Algorithm Speed
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9 µs
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/x) 10.5 ns
Inverse Square Root 16.3 ns
1
Assumes two files in multichannel SIMD mode
1
1
1.5 ns
6.0 ns
13.5 ns
23.9 ns
The ADSP-21364 continues SHARC’s industry leading standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21364 on Page 1, illustrates the
following architectural features:
• Two processing elements, each of which comprises an
ALU, multiplier, shifter and data register file
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core processor cycle
• Three programmable interval timers with PWM Generation, PWM capture/pulse-width measurement, and
external event counter capabilities
•On-chip SRAM (3M bit)
• On-chip mask-programmable ROM (4M bit)
• 8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals
• JTAG test access port
The block diagram of the ADSP-21364 on Page 7, illustrates the
following architectural features:
• DMA controller
• Six full duplex serial ports
• Two SPI-compatible interface ports—primary on dedicated pins secondary on DAI pins
• Digital audio interface that includes two precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, six serial ports, eight serial interfaces, a 20bit parallel input port, 10 interrupts, six flag outputs, six
flag inputs, three timers, and a flexible signal routing unit
(SRU)
Figure 2 on Page 5 shows one sample configuration of a SPORT
using the precision clock generators to interface with an I
ADC and an I
2
S DAC with a much lower jitter clock than the
2
S
serial port would generate itself. Many other SRU configurations are possible.
ADSP-21364 FAMILY CORE ARCHITECTURE
The ADSP-21364 is code compatible at the assembly level with
the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC DSPs. The ADSP-21364
shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC processors, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21364 contains two computational processing elements that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive signal processing algorithms.
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Rev. PrC | Page 4 of 54 | February 2005
ADSP-21364Preliminary Technical Data
CLOCK
ADC
(OPTIONAL)
CLK
SDAT
DAC
(OPTIONAL)
CLK
SDAT
ADSP-21364
CLKIN
XTAL
2
CLK_CFG1-0
2
BOOTC FG1-0
3
FLAG3-1
FS
FS
DAI_P1
DA I_ P2
DA I_ P3
SRU
DA I_P18
DAI_P19
DA I_ P2 0
CLK
FS
DAI
RESET JTA G
PCGA
PCGB
SCLK0
SFS0
SD0A
SD0B
SP ORT0- 5
TIMERS
SP DI F
SRC
IDP
SPI
6
CLKOUT
ALE
AD 1 5- 0
RD
WR
CO NT RO L
LATCH
ADDR
PARALLEL
DATA
OE
WE
CSFLAG0
DATA
ADDRESS
PORT
RAM, ROM
BOO T R OM
I/O DEVICE
Figure 2. ADSP-21364 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit, singleprecision floating-point, 40-bit, extended-precision floatingpoint, and 32-bit, fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21364 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the ADSP-21364’s separate program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a single cycle.
Instruction Cache
The ADSP-21364 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
The ADSP-21364’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital
Rev. PrC | Page 5 of 54 | February 2005
ADSP-21364 Preliminary Technical Data
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21364 contain
sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21364 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single
instruction.
ADSP-21364 MEMORY AND I/O INTERFACE FEATURES
The ADSP-21364 adds the following architectural features to
the SIMD SHARC family core.
Table 2. ADSP-21364 Internal Memory Space
IOP Registers 0x0000 0000–0003 FFFF
Long Word (64 Bits) Extended Precision Normal or
Instruction Word (48 Bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
Reserved
0x0004 8000–0x0004 BFFF
BLOCK 0 RAM
0x0004 C000–0x0004 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
Reserved
0x0005 8000–0x0005 BFFF
BLOCK 1 RAM
0x0005 C000–0x0005 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 1FFF
Reserved
0x0006 2000–0x0006 FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 1FFF
Reserved
0x0007 2000–0x0007 FFFF
BLOCK 0 ROM
0x0008 0000–0x0008 AAAA
BLOCK 0 RAM
0x0009 0000–0x0009 5555
BLOCK 1 ROM
0x000A 0000–0x000A AAAA
BLOCK 1 RAM
0x000B 0000–0x000B 5555
BLOCK 2 RAM
0x000C 0000–0x000C 2AAA
BLOCK 3 RAM
0x000E 0000–0x000E 2AAA
On-Chip Memory
The ADSP-21364 contains three megabits of internal SRAM.
Each block can be configured for different combinations of code
and data storage (see Table 2 on Page 6). Each memory block
supports single-cycle, independent accesses by the core processor and I/O processor. The ADSP-21364 memory architecture,
in combination with its separate on-chip buses, allow two data
transfers from the core and one from the I/O processor, in a single cycle.
The ADSP-21364’s, SRAM can be configured as a maximum of
96K words of 32-bit data, 192K words of 16-bit data, 64K words
of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to three megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Normal Word (32 Bits) Short Word (16 Bits)
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
BLOCK 0 RAM
0x0009 8000–0x0009 FFFF
BLOCK 1 ROM
0x000A 0000–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
BLOCK 1 RAM
0x000B 8000–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 3FFF
Reserved
0x000C 4000–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 3FFF
Reserved
0x000E 4000–0x000F FFFF
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0013 0000–0x0013 FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0017 0000–0x0017 FFFF
BLOCK 2 RAM
0x0018 0000–0x0018 7FFF
Reserved
0x0018 8000–0x001B FFFF
BLOCK 3 RAM
0x001C 0000–0x001C 7FFF
Reserved
0x001C 8000–0x001F FFFF
Reserved
0x0020 0000–0xFFFF FFFF
Rev. PrC | Page 6 of 54 | February 2005
ADSP-21364Preliminary Technical Data
Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
DMA Controller
The ADSP-21364’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can
occur between the ADSP-21364’s internal memory and its serial
ports, the SPI-compatible (serial peripheral interface) ports, the
IDP (input data port), the parallel data acquisition port (PDAP),
or the parallel port. Twenty-five channels of DMA are available
on the ADSP-21364—two for the SPI interface, two for memory-to-memory transfers, twelve via the serial ports, eight via
the Input Data Port, and one via the processor’s parallel port.
Programs can be downloaded to the ADSP-21364 using DMA
transfers. Other DMA features include interrupt generation
upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.
TO PR OCESSOR BUSSES AN D
SYSTEM MEMORY
IO DATA
BUS (32)
Figure 3. ADSP-21364 I/O Processor and Peripherals Block Diagram
S
R
E
T
S
I
G
E
R
P
O
I
)
D
E
P
P
A
M
Y
R
O
M
E
M
(
IOADDRESS
BUS (18)
GPI O FLAGS/I RQ/TIM EXP
S
R
E
F
F
U
B
A
T
A
D
&
,
S
U
T
A
T
S
,
L
O
R
T
N
O
C
DMA CONTROLLER
25 CHANNELS
CON TR O L/G P IO
ADD RESS/ DATA B US/GP IO
PARAL LEL PO RT
PWM (16)
SPI PORT (1)
SPI PORT(1)
SERIAL PORTS (6)
INPU T
DATA PORTS(8)
PREC ISION CLOCK
GEN ERATORS (2)
TI ME R S ( 3)
SPDIF (RX/TX)
SRC (8 CHANNELS)
4
3
4
4
3
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
16
T
I
N
U
G
N
I
T
20
U
O
R
L
A
N
G
I
S
Digital Audio Interface (DAI)
The digital audio interface (DAI) provides the ability to connect
various peripherals to any of the SHARC’s DAI pins
(DAI_P20–1).
Programs make these connections using the signal routing unit
(SRU, shown in Figure 3).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with nonconfigurable signal paths.
The DAI also includes six serial ports, two precision clock generators (PCGs), eight channels of asynchronous sample rate
converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and three timers. The IDP provides an
additional input path to the ADSP-21364 core, configurable as
either eight channels of I
2
S serial data or as seven channels plus
a single 20-bit wide synchronous parallel data acquisition port.
Each data channel has its own DMA channel that is independent from the ADSP-21364’s serial ports.
For complete information on using the DAI, see the ADSP-
2136x SHARC Processor Hardware Reference for the ADSP21363/4/5/6 Processors.
Serial Ports
The ADSP-21364 features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTS are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in four modes:
• Standard DSP serial mode
•Multichannel (TDM) mode
2
S mode
•I
• Left justified sample pair mode
Left justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over various attributes of this mode.
Rev. PrC | Page 7 of 54 | February 2005
ADSP-21364 Preliminary Technical Data
Each of the serial ports supports the left justified sample pair
2
S protocols (I2S is an industry standard interface com-
and I
monly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left justified sample pair or I
devices) per serial port, with a maximum of up to 24 I
2
S channels (using two stereo
2
S channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left justified sample pair and I
2
S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional µ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be internally or externally generated.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16bit, the maximum data transfer rate is 55M bytes/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD
, WR, and ALE
(address latch enable) pins are the control pins for the parallel
port.
Serial Peripheral (Compatible) Interface
The ADSP-21364 SHARC processor contains two serial peripheral interface ports (SPIs). The SPI is an industry standard
synchronous serial link, enabling the ADSP-21364 SPI compatible port to communicate with other SPI-compatible devices.
The SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI-compatible devices, either acting as a master or slave
device. The ADSP-21364 SPI-compatible peripheral implementation also features programmable baud rate and clock phase
and polarities. The ADSP-21364 SPI-compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.
The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz Stereo
asynchronous sample rate converter providing up to 140dB
SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.
S/PDIF-Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter
The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left justified, I
2
S or right justified with word
widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF
transmitter are routed through the Signal Routing Unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.
The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz Stereo
Asynchronous Sample Rate Converter providing up to 140dB
SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
each. Therefore this module generates 16 PWM outputs in total.
Each PWM group produces two pairs of PWM signals on the
four PWM outputs.
The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode, or double update mode. In single update mode
the duty cycle values are programmable only once per PWM
period. This results in PWM patterns that are symmetrical
around the midpoint of the PWM period. In double update
mode, a second updating of the PWM registers is implemented
at the mid-point of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters.
Rev. PrC | Page 8 of 54 | February 2005
Timers
The ADSP-21364 has a total of four timers: a core timer able to
generate periodic software interrupts and three general purpose
timers that can generate periodic interrupts and be independently set to operate in one of three modes:
• Pulse Waveform Generation mode
• Pulse-Width Count/Capture mode
• External Event Watchdog mode
The core timer can be configured to use FLAG3 as a timer
expired signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse-width register. A single control and status register enables or disables all three
general-purpose timers independently.
Program Booting
The internal memory of the ADSP-21364 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1–0) pins (see Table 6 on
Page 15). Selection of the boot source is controlled via the SPI as
either a master or slave device.
Phase-Locked Loop
The ADSP-21364 uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. On power up, the
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1
(see Table 7 on Page 15). After booting, numerous other ratios
can be selected via software control. The ratios are made up of
software configurable numerator values from 1 to 32 and software configurable divisor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21364 has separate power supply connections for the
internal (V
DDINT
), external (V
), and analog (A
DDEXT
VDD/AVSS
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply pin (A
) powers the ADSP-
VDD
21364’s internal clock generator PLL. To produce a stable clock,
it is recommended that PCB designs use an external filter circuit
for the A
ble to the A
pin. Place the filter components as close as possi-
VDD
VDD/AVSS
pins. For an example circuit, see Figure 4.
(A recommended ferrite chip is the muRata
BLM18AG102SN1D). To reduce noise coupling, the PCB
should use a parallel pair of power and ground planes for
V
and GND. Use wide traces to connect the bypass capac-
DDINT
itors to the analog power (A
that the A
VDD
and A
pins specified in Figure 4 are inputs to
VSS
) and ground (A
VDD
) pins. Note
VSS
the processor and not the analog ground plane on the board—
the A
pin should connect directly to digital ground (GND) at
VSS
the chip.
ADSP-21364Preliminary Technical Data
V
DDINT
HI Z FERRITE
BEAD CHIP
Figure 4. Analog Power (A
100nF 10nF 1nF
LOCATE ALL COMPONENTS
CLOSE TO A
VDD
AND A
) Filter Circuit
VDD
VSS
PINS
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21364 processor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appropriate “Emulator Hardware User's Guide”.
DEVELOPMENT TOOLS
The ADSP-21364 is supported with a complete set of
CROSSCORE
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21364.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
)
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ run-time library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Statistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
®
software and hardware development tools,
ADSP-213xx
A
VDD
A
VSS
®
devel-
Rev. PrC | Page 9 of 54 | February 2005
ADSP-21364 Preliminary Technical Data
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved source
and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applications. It also can be used for downloading components from the
Web and dropping them into the application, and publishing
component archives from within VisualDSP++. VCSE supports
component implementation in C/C++ or assembly language.
Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with a
drag of the mouse, and examine run time stack and heap usage.
The expert linker is fully compatible with the existing linker definition file (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
The Analog Devices family of emulators are tools that every
developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test
Access Port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and commands, but once an operation has been completed by the
emulator, the processor system is set running at full speed with
no impact on system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.
Evaluation Kit
Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.
The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor incircuit. This permits the customer to download, execute, and
debug programs for the EZ-KIT Lite system. It also allows in-
Rev. PrC | Page 10 of 54 | February 2005
circuit programming of the on-board Flash device to store userspecific boot code, enabling the board to run as a standalone
unit without being connected to the PC.
With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, nonintrusive emulation.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21364
architecture and functionality. For detailed information on the
ADSP-2136x family core architecture and instruction set, refer
to the ADSP-2136x SHARC Processor Hardware Reference for
the ADSP-21363/4/5/6 Processors and the ADSP-2136x SHARC
Processor Programming Reference.
ADSP-21364Preliminary Technical Data
Rev. PrC | Page 11 of 54 | February 2005
ADSP-21364 Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS
ADSP-21364 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS and TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST
V
or GND, except for the following:
DDEXT
). Tie or pull unused inputs to
• DAI_Px, SPICLK, MISO, MOSI, EMU
, TMS, TRST, TDI,
and AD15–0 (Note: These pins have pull-up resistors.)
The following symbols appear in the Type column of Table 3:
A = asynchronous, G = ground, I = input, O = output,
P = power supply, S = synchronous, (A/D) = active drive, (O/D)
= open drain, and T = three-state, (pd) = pull-down resistor,
(pu) = pull-up resistor.
Table 3. Pin Descriptions
Pin Type State During &
After Reset
AD15–0 I/O/T
(pu)
RD
WR
ALE O
FLAG3–0 I/O/A Three-state Flag Pins. Each flag pin is configured via control bits as either an input or output. As
O
(pu)
O
(pu)
(pd)
Three-state with
pull-up enabled
Three-state, driven
1
high
Three-state, driven
1
high
Three-state, driven
1
low
Func tion
Parallel Port Address/Data. The ADSP-21364 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address
Data Modes on page 15 for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A23–8; ALE is used in conjunction with an external latch to
retain the values of the A23–8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15–0; ALE is used in conjunction with an external latch to retain the
values of the A15–0. To use these pins as flags (FLAGS15–0) or PWMs (PWM15–0), 1)
set (=1) Bit 20 of the SYSCTL register to disable the parallel port, 2) set (=1) Bits 22–25
of the SYSCTL register to enable FLAGS in groups of four (Bit 22 for FLAGS3–0, Bit 23
for FLAGS7–4 etc.) or, set (=1) Bits 26–29 of the SYSCTL register to enable PWMs in
groups of four (Bit 26 for PWM0–3, Bit 27 for PWM4–7, and so on). When configured
in the IDP_PDAP_CTL register, IDP Channel 0 can use these pins for parallel input data.
Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or
16-bit data from an external memory device. When AD15–0 are flags, this pin remains
deasserted. RD has a 22.5 kΩ internal pull-up resistor.
Parallel Port Write Enable. WR is asser ted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD15–0 are flags, this pin remains
deasserted. WR
Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives
a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15–0 are flags, this
pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor.
an inp ut, it ca n be test ed a s a c ond itio n. A s an o utp ut, it ca n be used to s ign al ex ter nal
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an
SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit 16
is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1
When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2
When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which
indicates that the system timer has expired.
has a 22.5 kΩ internal pull-up resistor.
and the TIMEXP signals.
.
.
Rev. PrC | Page 12 of 54 | February 2005
Table 3. Pin Descriptions (Continued)
ADSP-21364Preliminary Technical Data
Pin Type State During &
After Reset
DAI_P20–1 I/O/T
(pu)
SPICLK I/O
(pu)
SPIDS
MOSI I/O (O/D)
MISO I/O (O/D)
BOOTCFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor.
I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select
(pu)
(pu)
Three-state with
programmable
pull-up
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Three-state with
pull-up enabled
Func tion
Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the serial ports, input data port, precision clock generators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins
have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can
be disabled in the DAI_PIN_PULLUP register.
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.
the processor as an SPI slave device. This input signal behaves like a chip select, and
is provided by the master device for the slave devices. In multimaster mode the DSPs
signal can be driven by a slave device to signal to the processor (as SPI master)
SPIDS
that an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multimaster error.
For a single-master, multiple-slave configuration where flag pins are used, this pin
must be tied or pulled high to V
ADSP-21364 SPI interaction, any of the master ADSP-21364's flag pins can be used to
drive the SPIDS signal on the ADSP-21364 SPI slave device.
SPI Master Out Slave In. If the ADSP-21364 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21364 is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In an ADSP-21364 SPI interconnection, the data is shifted out from the MOSI
output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a
22.5 kΩ internal pull-up resistor.
SPI Master In Slave Out. If the ADSP-21364 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21364 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting
output data. In an ADSP-21364 SPI interconnection, the data is shifted out from the
MISO output pin of the slave and shifted into the MISO input pin of the master. MISO
has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the
OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI-slaves, the processor's MISO pin may be disabled by
setting (=1) Bit 5 (DMISO) of the SPICTL register.
The BOOTCFG pins must be valid before reset is asserted. See Ta ble 6 for a description
of the boot modes.
on the master device. For ADSP-21364 to
DDEXT
Rev. PrC | Page 13 of 54 | February 2005
ADSP-21364 Preliminary Technical Data
Table 3. Pin Descriptions (Continued)
Pin Type State During &
Func tion
After Reset
CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21364 clock input.
It configures the ADSP-21364 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21364 to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.
XTAL O Output only
2
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
CLKCFG1–0 I Input only Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 7
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.
RSTOUT
/CLKOUT O Output only Local Clock Out/Reset Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin.The functionality can be switched
between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.
The default is reset out.
RESET I/A Input only Processor Reset. Resets the ADSP-21364 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET
input must be
asserted (low) at power-up.
TCK I Input only
3
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21364.
TMS I/S
(pu)
TDI I/S
(pu)
TDO O Three-state
TRST
I/A
(pu)
Three-state with
pull-up enabled
Three-state with
pull-up enabled
4
Three-state with
pull-up enabled
Tes t M ode Select ( JTAG ). Used to control the test state machine. TMS has a 22.5 kΩ
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5
kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21364. TRST
has a
22.5 kΩ internal pull-up resistor.
EMU
O (O/D)
(pu)
Three-state with
pull-up enabled
Emulation Status. Must be connected to the ADSP-21364 Analog Devices processor
Tools product line of JTAG emulators target board connector only. EMU
has a 22.5 kΩ
internal pull-up resistor.
V
DDINT
P Core Power Supply. Nominally +1.2 V dc and supplies the processor’s core processor
(13 pins on the Mini-BGA package, 32 pins on the LQFP package).
V
DDEXT
P I/O Power Supply. Nominally +3.3 V dc (6 pins on the mini-BGA package, 10 pins on
the LQFP package).
A
VDD
P Analog Power Supply. Nominally +1.2 V dc and supplies the processor’s internal PLL
(clock generator). This pin has the same specifications as V
, except that added
DDINT
filtering circuitry is required. For more information, see Power Supplies on page 9.
A
VSS
G Analog Power Supply Return.
GND G Power Supply Return. (54 pins on the Mini-BGA package, 39 pins on the LQFP
package).
1
RD, WR, and ALE are three-stated (and not driven) only when RESET is active.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver with both output path and pull-up disabled.
4
Three-state is a three-state driver with pull-up disabled.
Rev. PrC | Page 14 of 54 | February 2005
ADSP-21364Preliminary Technical Data
ADDRESS DATA PINS AS FLAGS
To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the
SYSCTL register to disable the parallel port. Then set (=1) Bits
22 to 25 in the SYSCTL register accordingly.
Table 4. AD15–0 to Flag Pin Mapping
AD Pin Flag Pin AD Pin Flag Pin
AD0 FLAG8 AD8 FLAG0
AD1 FLAG9 AD9 FLAG1
AD2 FLAG10 AD10 FLAG2
AD3 FLAG11 AD11 FLAG3
AD4 FLAG12 AD12 FLAG4
AD5 FLAG13 AD13 FLAG5
AD6 FLAG14 AD14 FLAG6
AD7 FLAG15 AD15 FLAG7
ADDRESS DATA MODES
The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address Bits A23–A8 when asserted, followed by address Bits A7–A0 and data Bits D7–D0 when
deasserted. For 16-bit data transfers, ALE latches address bits
A15–A0 when asserted, followed by data bits D15–D0 when
deasserted.
BOOT MODES
Table 6. Boot Mode Selection
BOOTCFG1–0 Booting Mode
00 SPI Slave Boot
01 SPI Master Boot
10 Parallel Port Boot via EPROM
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see Timing Specifications and
Figure 5 on Page 18.
Table 7. Core Instruction Rate/CLKIN Ratio Selection
CLKCFG1–0 Core to CLKIN Ratio
00 6:1
01 32:1
10 16:1
Table 5. Address/Data Mode Selection
EP Data
Mode
8-bit Asserted A15–8 A23–16
8-bit Deasserted D7–0 A7–0
16-bit Asserted A7–0 A15–8
16-bit Deasserted D7–0 D15–8
ALE AD7–0
Func tion
AD15–8
Func tion
Rev. PrC | Page 15 of 54 | February 2005
ADSP-21364 Preliminary Technical Data
ADSP-21364 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
1
K Grade B Grade C Grade
Min Max Min Max Min Max Unit
V
DDINT
A
VDD
V
DDEXT
2
V
IH
2
Low Level Input Voltage @ V
V
IL
V
IH_CLKIN
V
IL_CLKIN
4, 5
T
AMB
1
Specifications subject to change without notice.
2
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
4
See Thermal Characteristics on page 46 for information on thermal specifications.
5
See Engineer-to-Engineer Note (No. TBD) for further information.
Internal (Core) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V
Analog (PLL) Supply Voltage 1.14 1.26 1.14 1.26 0.95 1.05 V
External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 3.13 3.47 V
High Level Input Voltage @ V
3
High Level Input Voltage @ V
Low Level Input Voltage @ V
= max 2.0 V
DDEXT
= min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V
DDEXT
= max 1.74 V
DDEXT
= min –0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V
DDEXT
+ 0.5 2.0 V
DDEXT
+ 0.5 1.74 V
DDEXT
+ 0.5 2.0 V
DDEXT
+ 0.5 1.74 V
DDEXT
DDEXT
DDEXT
+ 0.5 V
+ 0.5 V
Ambient Operating Temperature 0 +70 –40 +85 –40 +105 °C
ELECTRICAL CHARACTERISTICS
Parameter
V
OH
V
OL
4, 5
I
IH
4
I
IL
I
ILPU
I
OZH
I
OZL
I
OZLPU
I
DD-INTYP
AI
DD
11, 12
C
IN
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.
3
See Output Drive Currents on page 45 for typical drive current capabilities.
4
Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 kΩ pull-ups: AD15-0, DAI_Px, SPICLK, EMU, MISO, MOSI.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note (No. TBD) for further information.
10
Characterized, but not tested.
11
Applies to all signal pins.
12
Guaranteed, but not tested.
1
2
2
High Level Output Voltage @ V
Low Level Output Voltage @ V
High Level Input Current @ V
Low Level Input Current @ V
5
6, 7
6
7
8, 9
10
Low Level Input Current Pull-up @ V
Three-State Leakage Current @ V
Three-State Leakage Current @ V
Three-State Leakage Current Pull-up @ V
Supply Current (Internal) t
Supply Current (Analog) A
Input Capacitance fIN = 1 MHz, T
Test Conditions Min Max Unit
= min, IOH = –1.0 mA
DDEXT
= min, IOL = 1.0 mA
DDEXT
= max, VIN = V
DDEXT
= max, VIN = 0 V 10 µA
DDEXT
= max, VIN = 0 V 200 µA
DDEXT
= max, VIN = V
DDEXT
= max, VIN = 0 V 10 µA
DDEXT
= max, VIN = 0 V 200 µA
DDEXT
= min, V
CCLK
= max 10 mA
VDD
= nom 500 mA
DDINT
= 25°C, VIN = 1.2V 4.7 pF
CASE
3
3
max 10 µA
DDEXT
max 10 µA
DDEXT
2.4 V
0.4 V
Rev. PrC | Page 16 of 54 | February 2005
MAXIMUM POWER DISSIPATION
The data in this table is based on theta JA (θJA) established per
JEDEC standards JESD51-2 and JESD51-6. See Engineer-toEngineer note (EE-TBD) for further information. For information on package thermal specifications, see Thermal
Characteristics on page 46.
ADSP-21364Preliminary Technical Data
Max Ambient
1
Te mp
144 INT–HS
2
LQFP
144 INT–HS
3
LQFP
136 Mini-
4
BGA
136 Mini-
5
BGA
70°C 3.33 W 2.10 W 2.44 W 2.18 W
85°C 2.42 W N/A 1.77 W N/A
105°C 1.21 W N/A N/A N/A
1
Power dissipation greater than that listed above may cause permanent damage to the device.
For more information, see Thermal Characteristics on page 46.
2
Heat slug soldered to PCB
3
Heat slug not soldered to PCB
4
Thermal vias in PCB
5
No thermal vias in PCB
ABSOLUTE MAXIMUM RATINGS
Parameter Rating
Internal (Core) Supply Voltage (V
Analog (PLL) Supply Voltage (A
External (I/O) Supply Voltage (V
Input Voltage –0.5 V to V
DDEXT
1
Output Voltage Swing –0.5 V to V
Load Capacitance
Storage Temperature Range
1
1
–65°C to +150°C
Junction Temperature under Bias 125°C
1
Stresses greater than those listed above may cause permanent damage to the device. These
are stress ratings only; functional operation of the device at these or any other conditions
greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DDINT
VDD
DDEXT
DDEXT
1
)
1
)
1
)
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
+0.5 V
1
+0.5 V
200 pF
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21364 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrC | Page 17 of 54 | February 2005
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