Analog Devices ADSP 21266 a Datasheet

SHARC® Processor

ADSP-21266

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing
Code compatible with all other SHARC DSPs
The ADSP-21266 processes high performance audio while

enabling low system costs
Audio decoders and post processor-algorithms support.

Nonvolatile memory can be configured to contain a combi-

nation of PCM 96kHz, Dolby Digital, Dolby Digital EX, DTS-

ES Discrete 6.1, DTS-ES Matrix 6.1, DTS 96/24 5.1, MPEG2

AAC LC, MPEG2 BC 2ch, Dolby Pro Logic II, Dolby Pro Logic

2x and DTS Neo:6
Single-Instruction Multiple-Data (SIMD) computational archi-

tecture—two 32-bit IEEE floating-point/32-bit fixed-point/

40-bit extended precision floating-point computational

units, each with a multiplier, ALU, shifter, and register file

CORE PROCESSOR

INSTRUCTION

32 ⴛ 48-B IT

PROGR AM

SEQUENCER

CACHE

DAG1

8 ⴛ 4 ⴛ 32

DAG 2

8 ⴛ 4 ⴛ 32

TIMER

High bandwidth I/O—a parallel port, an SPI port, six serial

ports, a digital audio interface (DAI), and JTAG

DAI incorporates two precision clock generators (PCGs), an

input data port (IDP) that includes a parallel data acquisi­tion port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)

On-chip memory—2M bits of on-chip SRAM and a dedicated

4M bits of on-chip mask-programmable ROM

Serial ports offer left-justified sample pair and I

2

S support via
12 programmable and simultaneous receive or transmit
pins, which support up to 24 transmit or 24 receive I2S
channels of audio when all 6 serial ports (SPORTs) are
enabled or six full duplex TDM streams of up to 128 chan­nels per frame

The ADSP-21266 is available with a 150 MHz or a 200 MHz

core instruction rate. For complete ordering information,
see Ordering Guide on Page 44.

DUALPORTED MEMORY

SRAM
1MBIT ROM

ADDR DATA

BLOCK 0

2MBIT

DUAL PORTED MEMORY

BLO CK 1

SRAM
1MBIT ROM

2MBIT

ADDR

DATA

32

32

6

20

SI GNAL

RO U TI NG

UNIT

PROCES SING

EL EMEN T

(PEX )

PM ADDRESS BUS

DM ADDRESS BUS

PROCESS ING

ELEMENT

(P EY)

JTAGTEST & EMULATION

PX REGI STER

S

DIGITAL AUDIO INTERFACE

Figure 1. Functional Block Diagram

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

64

64

4

3

PM DATABUS

IOD

DMDATA BUS

DMA CONTROLLER

22CHANNELS

SPI PORT ( 1)

SER IAL POR TS (6 )

INPUT
DATA PORTS (8)
PARALLEL DATA

ACQUIS ITION POR T

PRECISI ON C LOCK

GENERATORS(2)

TIMERS( 3)

I/O PROCESSOR

IOA

(32)

(18)

IOP

REGISTERS

(MEMORY MAPPED)

CONTROL,

STATUS,

DATA BUFFERS

GPIO F LAGS/

IRQ/TIMEX P

ADDRESS/

DATA BUS/GPIO

CONTROL/GPIO

PARALLEL

PORT

4

16

3

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
FAX: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADSP-21266

KEY FEATURES

At 200 MHz (5 ns) core instruction rate, the ADSP-21266

operates at 1200 MFLOPS peak/800 MFLOPS sustained
performance whether operating on fixed or floating point
data

400 MMACS sustained performance at 200 MHz

Code compatibility— At assembly level, uses the same

instruction set as other SHARC DSPs

Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero­overhead I/O

2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit

block 1) for simultaneous access by core processor and
DMA

4M bits on-chip dual-ported mask-programmable ROM

(2M bits in block 0 and 2M bits in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing
Zero-overhead looping with single-cycle loop setup, pro-

viding efficient program sequencing
Single instruction multiple data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution—Each processing element executes

the same instruction, but operates on different data

Parallelism in busses and computational units allows sin-

gle cycle executions (with or without SIMD) of a multiply
operation; an ALU operation; a dual memory read or
write; and an instruction fetch

Transfers between memory and core at up to four 32-bit

floating- or fixed-point words per cycle, sustained

2.4G bytes/s bandwidth at 200 MHz core instruction rate.
In addition, 900M Bytes/sec is available via DMA

Accelerated FFT butterfly computation through a multiply
with add and subtract instruction

DMA Controller supports:

22 zero-overhead DMA channels for transfers between the

ADSP-21266 internal memory and serial ports (12), the
input data port (IDP) (eight), the SPI-compatible port
(one), and the parallel port (one)

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

Asynchronous parallel/external port provides:

Access to asynchronous external memory
16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit

address external address range with 16-bit data
66M Byte per sec transfer rate for 200 MHz core rate
50M Byte per sec transfer rate for 150 MHz core rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLK

Digital audio interface (DAI) includes six serial ports, two pre-

cision clock generators, an input data port, three
programmable timers, and a signal routing unit

Serial ports provide:

Six dual data line serial ports that operate at up to

50M bits/s for a 200 MHz core and up to 37.5M bits/s for
a 150 MHz core on each data line—each has a clock,
frame sync, and two data lines that can be configured as
either a receiver or transmitter pair

Left-justified sample pair and I

direction for up to 24 simultaneous receive or transmit
channels using two I

2

2

S support, programmable

S compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter­faces such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the

SHARC core configurable as either eight channels of I

2

S or
serial data or as seven channels plus a single 20-bit wide
synchronous parallel data acquisition port

Supports receive audio channel data in I

2

S, left-justified

sample pair, or right-justified mode

Signal routing unit (SRU) provides configurable and flexible

connections between all DAI components, six serial ports,
two precision clock generators, three timers, an input data
port/parallel data acquisition port, 10 interrupts, six flag
inputs, six flag outputs, and 20 SRU I/O pins (DAI_Px)

Serial Peripheral Interface (SPI)
Master or slave serial boot through SPI
Full-duplex operation
Master-slave mode multimaster support
Open drain outputs
Programmable baud rates, clock polarities, and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
ROM based security features:

JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages

Also available in lead-free packages

Rev. A | Page 2 of 44 | May 2004

TABLE OF CONTENTS

ADSP-21266

General Description ..................................................4

ADSP-21266 Family Core Architecture . . .....................4

SIMD Computational Engine ................................4

Independent, Parallel Computation Units ................5

Data Register File ................................................5

Single-Cycle Fetch of Instruction and

Four Operands ................................................5

Instruction Cache ...............................................5

Data Address Generators With Zero-Overhead

Hardware Circular Buffer Support .......................5

Flexible Instruction Set ........................................6

ADSP-21266 Memory and I/O Interface Features . ......6

Dual-Ported On-Chip Memory ..............................6

DMA Controller .................................................6

Digital Audio Interface (DAI) ................................6

Serial Ports ........................................................6

Serial Peripheral (Compatible) Interface ...................8

Parallel Port ......................................................8

Timers .............................................................8

ROM Based Security ............................................8

Program Booting ................................................8

Phase-Locked Loop ............................................8

Power Supplies ...................................................8

Target Board JTAG Emulator Connector ..................9

Development Tools ...................................................9

Designing an Emulator-Compatible DSP

Board(Target) ................................................. 10

Additional Information ......................................... 10

Pin Function Descriptions ..................................... 11

Address Data Pins as Flags .................................. 14

Boot Modes ..................................................... 14

Core Instruction Rate to CLKIN Ratio Modes .......... 14

Address Data Modes ......................................... 14

ADSP-21266 Specifications ....................................... 15

Recommended Operating Conditions ....................... 15

Electrical Characteristics ........................................ 15

Absolute Maximum Ratings ................................... 16

ESD Sensitivity .................................................... 16

Timing Specifications ........................................... 16

Power-up Sequencing ........................................ 18

Clock Input ..................................................... 19

Clock Signals ................................................... 19

Reset ..............................................................19

Interrupts ........................................................20

Core Timer ......................................................20

Timer PWM_OUT Cycle Timing ..........................21

Timer WDTH_CAP Timing ................................21

DAI Pin to Pin Direct Routing .............................22

Precision Clock Generator (Direct Pin Routing) .......23

Flags ..............................................................24

Memory Read–Parallel Port .................................25

Memory Write—Parallel Port ..............................27

Serial Ports ......................................................29

Input Data Port (IDP) ........................................32

Parallel Data Acquisition Port (PDAP)................... 33

SPI Interface—Master ........................................34

SPI Interface—Slave ...........................................35

JTAG Test Access Port and Emulation ...................36

Output Drive Currents ..........................................37

Test Conditions ...................................................37

Capacitive Loading ...............................................37

Environmental Conditions .....................................38

Thermal Characteristics .........................................38

136-Ball BGA Pin Configurations ................................39

144-Lead LQFP Pin Configurations .. ...........................42

Package Dimensions ................................................43

Ordering Guide ......................................................44

REVISION HISTORY

4/04–Data Sheet Changed from Rev. 0 to Rev. A

Added notes to AD pins ............................................11

Added V

Changed specifications (t

Updated 136-BGA package drawing . ...........................43

Added new part ......................................................44

IHCLKIN

and V

specifications .....................15

ILCLKIN

ALERW

, and t

) ................25-28

ALEHZ

Rev. A | Page 3 of 44 | May 2004

ADSP-21266

GENERAL DESCRIPTION

The ADSP-21266 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices Super Har­vard Architecture. The ADSP-21266 is source code compatible
with the ADSP-2126x, ADSP-21160 and ADSP-21161 DSPs as
well as with first generation ADSP-2106x SHARC processors in
SISD (Single-Instruction, Single-Data) mode. Like other
SHARC DSPs, the ADSP-21266 is a 32-bit/40-bit floating-point
processor optimized for high performance audio applications
with its dual-ported on-chip SRAM, mask-programmable
ROM, multiple internal buses to eliminate I/O bottlenecks, and
an innovative Digital Audio Interface (DAI).

As shown in the Functional Block Diagram on Page 1, the
ADSP-21266 uses two computational units to deliver a 5 to 10
times performance increase over previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art,
high speed, CMOS process, the ADSP-21266 DSP achieves an
instruction cycle time of 5 ns at 200 MHz or 6.6 ns at150 MHz.
With its SIMD computational hardware, the ADSP-21266 can
perform 1200 MFLOPS running at 200 MHz, or 900 MFLOPS
running at150 MHz.

Table 1 shows performance benchmarks for the ADSP-21266.

Table 1. ADSP-21266 Benchmarks (at 200 MHz)

Benchmark Algorithm Speed

(at 200 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 46 µs
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)

[3×3] × [3×1]
[4×4] × [4×1]

Divide (y/×) 15 ns
Inverse Square Root 22.5 ns

1

Assumes two files in multichannel SIMD mode.

1

1

2.5 ns
10 ns

22.5 ns
40 ns

The ADSP-21266 continues SHARC’s industry leading stan­dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2 Mbits dual-ported SRAM memory, 4 Mbits
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and Digital Audio Interface (DAI).

The block diagram of the ADSP-21266 on Page 1, illustrates the
following architectural features:

• Two processing elements, each containing an ALU, multi­plier, shifter, and data register file

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro­cessor cycle

• Three Programmable Interval Timers with PWM Genera­tion, PWM Capture/Pulse Width Measurement, and
External Event Counter Capabilities

• On-chip dual-ported SRAM (2M bits)

• On-chip dual-ported, mask-programmable ROM
(4M bits)

• JTAG test access port

• 8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals

• DMA controller

• Six full-duplex serial ports

• SPI compatible interface

• Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit synchronous parallel input
port, 10 interrupts, six flag outputs, six flag inputs, three
programmable timers, and a flexible signal routing unit
(SRU)

Figure 2 on Page 5 shows one sample configuration of a SPORT

using the precision clock generator to interface with an I
and an I

2

S DAC with a much lower jitter clock than the serial

2

S ADC

port would generate itself. Many other SRU configurations are
possible.

ADSP-21266 FAMILY CORE ARCHITECTURE

The ADSP-21266 is code compatible at the assembly level with
the ADSP-2136x and ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-21266 shares architec­tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.

SIMD Computational Engine

The ADSP-21266 contains two computational processing ele­ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg­ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro­cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive audio algorithms.

Entering SIMD mode also has an effect on the way data is trans­ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band­width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Rev. A | Page 4 of 44 | May 2004

ADSP-21266

CLOCK

ADC

(OPTIONAL)

CLK

SDAT

DAC

(OPTIONAL)

CLK

SDAT

FS

FS

2

2
3

CLKIN
XTA L

CLK_CFG1-0

BOOTCFG1-0
FLAG3-1

DA I_ P1
DAI_P2
DAI_P3

DA I_P 18

DA I_P 19

DA I_P 20

ADSP-21266

SCLK0

CLK
FS

PCG A

PCGB

SFS0
SD0A

SD0B

SPORT0

SPORT 1

SPO RT2

SPORT3

SPORT4

SPORT5

SRU

DAI

RESE T JTAG

CLKOUT

AD15-0

FL AG 0

6

ALE

RD

WR

CONTROL

LATCH

ADDR

PARALLEL

DA TA

OE

WE

CS

DATA

ADDRESS

PO RT

RA M, R OM

BOOT ROM

I/O DEVIC E

Figure 2. ADSP-21266 System Sample Configuration

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera­tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele­ments. These computation units support IEEE 32-bit single­precision floating-point, 40-bit extended precision floating­point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har­vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21266 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the ADSP-21266’s separate pro­gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin­gle cycle.

Instruction Cache

TheADSP-21266 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The ADSP-21266’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program­ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and

Rev. A | Page 5 of 44 | May 2004

ADSP-21266

Fourier transforms. The two DAGs of the ADSP-21266 contain
sufficient registers to allow the creation of up to 32 circular buff­ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over­head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21266 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch­ing up to four 32-bit values from memory—all in a single
instruction.

ADSP-21266 MEMORY AND I/O INTERFACE FEATURES

The ADSP-21266 adds the following architectural features to
the SIMD SHARC family core:

Dual-Ported On-Chip Memory

The ADSP-21266 contains two megabits of internal SRAM and
four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see ADSP-21266 Memory Map on Page 7). Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual­ported memory, in combination with three separate on-chip
buses, allows two data transfers from the core and one from the
I/O processor, in a single cycle.

The ADSP-21266’s SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ­ent word sizes up to two megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float­ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for­mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.

Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.

DMA Controller

The ADSP-21266’s on-chip DMA controller allows zero-over­head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul­taneously executing its program instructions. DMA transfers
can occur between the ADSP-21266’s internal memory and its
serial ports, the SPI-compatible (Serial Peripheral Interface)
port, the IDP (Input Data Port), Parallel Data Acquisition Port

(PDAP), or the parallel port. Twenty-two channels of DMA are
available on the ADSP-21266—one for the SPI interface, 12 via
the serial ports, eight via the Input Data Port, and one via the
processor’s parallel port. Programs can be downloaded to the
ADSP-21266 using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans­fers, and DMA chaining for automatic linked DMA transfers.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con­nect various peripherals to any of the SHARCs DAI pins
(DAI_P[20:1]).

Connections are made using the Signal Routing Unit (SRU,
shown in the block diagram on Page 1).

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon­nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon­figurable signal paths.

The DAI also includes six serial ports, two precision clock gen­erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the ADSP-21266 core, configurable as either eight
channels of I
20-bit wide synchronous parallel data acquisition port. Each
data channel has its own DMA channel that is independent
from the ADSP-21266's serial ports.

For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual.

2

S or serial data, or as seven channels plus a single

Serial Ports

The ADSP-21266 features six full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the Analog
Devices AD183x family of audio codecs, ADCs, and DACs. The
serial ports are made up of two data lines, a clock, and frame
sync. The data lines can be programmed to either transmit or
receive and each data line has its own dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of
50M bits/s for a 200 MHz core and 37.5M bits/s for a 150 MHz
core. Serial port data can be automatically transferred to and
from on-chip memory via a dedicated DMA. Each of the serial
ports can work in conjunction with another serial port to pro­vide TDM support. One SPORT provides two transmit signals
while the other SPORT provides the two receive signals. The
frame sync and clock are shared.

Rev.A | Page 6 of 44 | May 2004

ADDRESS

ADSP-21266

LONG WORD

ADDRESS

SPACE

NORMAL WORD

ADDRESS

SPACE

SHORT WORD

ADDRESS

SPACE

IOP REGISTERS

BLOCK 0 SRAM (1Mbit)

RESERVED

BLOCK 0 ROM (2 Mbit)

BLOCK 1 SRAM (1 Mbit)

RESERVED

BLOCK 1 ROM (2 Mbit)

BLOCK 0 SRAM (1 Mbit)

RESERVED

BLOCK 0 ROM (2 Mbit)

BLOCK 1 SRAM (1 Mbit)

RESERVED

BLOCK 1 ROM (2 Mbit)

BLOCK 0 SRAM (1 Mbit)

RESERVED

BLOCK 0 ROM (2 Mbit)

BLOCK 1 SRAM (1 Mbit)

RESERVED

BLOCK 1 ROM (2 Mbit)

0x0000 0000 - 0x0003 FFFF

0x0004 0000

0x0004 3FFF
0x0004 4000 - 0x0005 7FFF

0x0005 8000

0x0005 FFFF
0x0006 0000

0x0006 3FFF
0x0006 4000 - 0x0007 7FFF

0x0007 8000

0x0007 FFFF
0x0008 0000

0x0008 7FFF

0x0008 8000 - 0x000A FFFF
0x000B 0000

2

0x000B FFFF
0x000C 0000

0x000C 7FFF

0x000C 8000 - 0x000E FFFF
0x000F 0000

3

0x000F FFFF

0x0010 0000

0x0010 FFFF
0x0011 0000 - 0x0015 FFFF

0x0016 0000

0x0017 FFFF
0x0018 0000

0x0018 FFFF
0x0019 0000 - 0x001D FFFF

0x001E 0000

0x001F FFFF

ADDRESS

RESERVED

EXTERNAL DMA

ADDRESS SPACE

RESERVED

1, 4

0x0020 0000

0x00FF FFFF
0x0100 0000

0x02FF FFFF
0x0300 0000

0x3FFF FFFF

EXTERNAL MEMORY

SPACE

1

EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE
CORE. DMA MUST BE USED TO READ OR WRITE TO THIS
MEMORY USING THE SPI OR PARALLEL PORT.

2

BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE
(0x000A 0000 - 0x000A AAAA).

3

BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE
(0x000E 0000 - 0x000EAAAA).

4

USE THE EXTERNAL ADDRESSES LISTED HERE WITH THE
PARALLEL PORT DMA REGISTERS. THE PARALLEL PORT
GENERATES ADDRESS WITHIN THE
RANGE 0x0000 0000-0x00FF FFFF.

INTERNAL MEMORY

SPACE

Figure 3. ADSP-21266 Memory Map

Rev. A | Page 7 of 44 | May 2004

ADSP-21266

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

2

S mode

•I

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var­ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

2

S protocols (I2S is an industry-standard interface com-

and I
monly used by audio codecs, ADCs and DACs), with two data
pins, allowing four left-justified sample pair or I

2

S channels
(using two stereo devices) per serial port, with a maximum of up
to 24 audio channels. The serial ports permit little-endian or
big-endian transmission formats and word lengths selectable
from 3 bits to 32 bits. For the left-justified sample pair and I

2

S
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry-standard syn­chronous serial link, enabling the ADSP-21266 SPI-compatible
port to communicate with other SPI-compatible devices. SPI is
an interface consisting of two data pins, one device select pin,
and one clock pin. It is a full-duplex synchronous serial inter­face, supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI compatible devices, either acting as a master or
slave device. The ADSP-21266 SPI-compatible peripheral
implementation also features programmable baud rates up to

37.5 MHz, clock phases, and polarities. The ADSP-21266 SPI­compatible port uses open drain drivers to support a multimas­ter configuration and to avoid data contention.

Parallel Port

The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15-0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16­bit, the maximum data transfer rate is one-third the core clock
speed. As an example, a clock rate of 200 MHz, is equivalent to
66M Bytes/sec, and a clock rate of 150 MHz is equivalent to
50M Bytes/sec.

DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral­lel port register read/write functions. The RD

, WR, and ALE
(Address Latch Enable) pins are the control pins for the
parallel port.

Timers

The ADSP-21266 has a total of four timers: a core timer able to
generate periodic software interrupts, and three general-pur­pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:

• Pulse Waveform Generation mode

• Pulse Width Count/Capture mode

• External Event Watchdog mode

The core timer can be configured to use FLAG3 as a Timer
Expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin­gle control and status register enables or disables all three
general-purpose timers independently.

ROM Based Security

The ADSP-21266 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the DSP does not boot-load any exter­nal code, executing exclusively from internal SRAM/ROM.
Additionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port, will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.

Program Booting

The internal memory of the ADSP-21266 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave, or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1-0) pins. Selection of
the boot source is controlled via the SPI as either a master or
slave device, or it can immediately begin executing from ROM.

Phase-Locked Loop

The ADSP-21266 uses an on-chip Phase-Locked Loop (PLL) to
generate the internal clock for the core. On power-up, the
CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft­ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi­sor values of 1, 2, 4, 8, and 16.

Power Supplies

The ADSP-21266 has separate power supply connections for
the internal (V

), external (V

DDINT

), and analog (A

DDEXT

VDD/AVSS

power supplies. The internal and analog supplies must meet the

1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.

Note that the analog supply (A

) powers the ADSP-21266’s

VDD

clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to

)

Rev.A | Page 8 of 44 | May 2004

ADSP-21266

the A

pin. Place the filter as close as possible to the pin. For

VDD

an example circuit, see Figure 4. To prevent noise coupling, use
a wide trace for the analog ground (A

) signal and install a

VSS

decoupling capacitor as close as possible to the pin. Note that
the A

VSS

and A

pins specified in Figure 4 are inputs to the

VDD

DSP and not the analog ground plane on the board.

10⍀

V

DDINT

Figure 4. Analog Power (A

A

VDD

0.01␮F0.1␮F

VSS

) Filter Circuit

A

VDD

TARGET BOARD JTAG EMULATOR CONNECTOR

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21266 pro­cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces­sor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro­priate emulator hardware user's guide.

DEVELOPMENT TOOLS

The ADSP-21266 is supported by a complete automotive refer­ence design and development board as well as by a complete
home audio reference design board available from Analog
Devices. These boards implement complete audio decoding and
post processing algorithms that are factory programmed into
the ROM space of the ADSP-21266. SIMD optimized libraries
consume less processing resources, which results in more avail­able processing power for custom proprietary features.

The nonvolatile memory of the ADSP-21266 can be configured
to contain a combination of Dolby Digital, Dolby Pro Logic,
Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24,
and Neo:6. Multiple S/PDIF and analog I/Os are provided to
maximize end system flexibility.

The ADSP-21266 is also supported with a complete set of
CROSSCORE
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21266.

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and

TM

software and hardware development tools,

TM

devel-

mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-21266
SHARC DSP has architectural features that improve the effi­ciency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea­tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta­tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi­ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source
and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,
and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel­opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and
generate outputs

• Maintain a one-to-one correspondence with the tool’s
command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling

Rev. A | Page 9 of 44 | May 2004

ADSP-21266

approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen­eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices technology for creating, using, and reusing soft­ware components (independent modules of substantial
functionality) to quickly and reliably assemble software applica­tions. Download components from the Web and drop them into
the application. Publish component archives from within
VisualDSP++. VCSE supports component implementation in
C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with the drag
of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi­nition File (LDF), allowing the developer to move between the
graphical and textual environments.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard­ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD (TARGET)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in­circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea­tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on sys­tem timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21266
architecture and functionality. For detailed information on the
ADSP-2126x family core architecture and instruction set, refer
to the ADSP-2126x DSP Core Manual and the ADSP-21160
SHARC DSP Instruction Set Reference.

Rev.A | Page 10 of 44 | May 2004

PIN FUNCTION DESCRIPTIONS

ADSP-21266

ADSP-21266 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden­tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST

or GND, except for the following:

V

DDEXT

). Tie or pull unused inputs to

• DAI_Px, SPICLK, MISO, MOSI, EMU

, TMS,TRST, TDI
and AD15-0 (NOTE: These pins have internal pull-up
resistors.)

The following symbols appear in the Type column of Table 2:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State.

Table 2. Pin Descriptions

Pin Type State During and

After Reset

AD15-0 I/O/T Three-state with

pull-up enabled.
Applies to silicon
revision 0.1.

Pins are driven low
during and after
reset. Applies to
silicon revision 0.2
only.

RD

WR

ALE O Output only, driven

FLAG3-0 I/O/A Three-state Flag Pins. Each FLAG pin is configured via control bits as either an input or output.

O Output only, driven

O Output only, driven

high

high

low

1

1

1

Function

Parallel Port Address/Data. The ADSP-21266 parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See Address

Data Modes on Page 14 for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the
upper 16 external address bits, A23-8; ALE is used in conjunction with an external
latch to retain the values of the A23-8.

For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15-0; ALE is used in conjunction with an external latch to retain the
values of the A15-0. To use these pins as flags (FLAG15-0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port. See Table 3 on Page 14 for a list of how
the AD15-0 pins map to the flag pins. When used as an input, the IDP Channel 0 can
use these pins for parallel input data.

Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or
16-bit data from an external memory device. When AD15-0 are flags, this pin
remains deasserted.

Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or
16- bit da ta to a n external memory de vice. When AD15-0 are flags, this pin remains
deasserted.

Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a
new address on the parallel port address pin. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15-0 are flags, this
pin remains deasserted.

As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals. These pins can be used as an SPI interface slave select output
during SPI mastering. These pins are also multiplexed with the IRQx
signals.

In SPI master boot mode, FLAG0 is the slave select pin that must be connected to
an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When
Bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.

When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1
When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2
When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which

indicates that the system timer has expired.

and the TIMEXP

.
.

Rev. A | Page 11 of 44 | May 2004

ADSP-21266

Table 2. Pin Descriptions (Continued)

Pin Type State During and

After Reset

DAI_P20-1 I/O/T Three-state with

programmable
pull-up

SPICLK I/O Three-state with

pull-up enabled

SPIDS

MOSI I/O (O/D) Three-state with

MISO I/O (O/D) Three-state with

BOOTCFG1-0 I Input only Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins

I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select

pull-up enabled

pull-up enabled

Function

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral
inputs or outputs connected to the pin and to the pin’s output enable. The config­uration registers of these peripherals then determine the exact behavior of the pin.
Any input or output signal present in the SRU may be routed to any of these pins.
The SRU provides the connection from the serial ports, input data port, precision
clock generators, and timers to the DAI_P20-1 pins. These pins have internal

22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can be disabled
in the DAI_PIN_PULLUP register.

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of
baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that
is active during data transfers, only for the length of the transferred word. Slave
devices ignore the serial clock if the slave select input is driven inactive (HIGH).
SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines.
The data is always shifted out on one clock edge and sampled on the opposite edge
of the clock. Clock polarity and clock phase relative to data are programmable into
the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ
internal pull-up resistor.

the DSP as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multimaster mode the DSP’s

si gna l ca n be d riv en b y a sl ave dev ice to signal to the DSP (as SPI master) that

SPIDS
an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multimaster
error. For a single master, multiple-slave configuration where flag pins are used, this
pin must be tied or pulled high to V
ADSP-21266 SPI interaction, any of the master ADSP-21266's flag pins can be used
to drive the SPIDS

SPI Master Out Slave In. If the ADSP-21266 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21266
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21266 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s).
MOSI has a 22.5 kΩ internal pull-up resistor.

SPI Master In Slave Out. If the ADSP-21266 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21266 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, trans­mitting output data. In an ADSP-21266 SPI interconnection, the data is shifted out
from the MISO output pin of the slave and shifted into the MISO input pin of the
master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D
by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable
broadcast transmission to multiple SPI slaves, the DSP's MISO pin may be disabled
by setting (=1) Bit 5 (DMISO) of the SPICTL register.

must be valid before reset is asserted. See Table 4 on Page 14 for a description of
the boot modes.

signal on the ADSP-21266 SPI slave device.

on the master device. For ADSP-21266 to

DDEXT

Rev.A | Page 12 of 44 | May 2004

Table 2. Pin Descriptions (Continued)

ADSP-21266

Pin Type State During and

Function

After Reset

CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21266 clock input.

It configures the ADSP-21266 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables
the internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the ADSP-21266 to use the external clock source
such as an external clock oscillator. The core is clocked either by the PLL output or
this clock input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted,
changed, or operated below the specified frequency.

XTAL O Output only

2

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.

CLKCFG1-0 I Input only Core /CLKIN Ratio Cont rol. These pins set the start up clock frequency. See Table 5

on Page 14 for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multi­plier and divider in the PMCTL register at any time after the core comes out of reset.

RSTOUT

/CLKOUT O Output only Reset Out/Local Clock Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can
be switched between the PLL output clock and reset out by setting Bit 12 of the
PMCTL register. The default is reset out.

RESET I/A Input only Processor Reset. Resets the ADSP-21266 to a known state. Upon deassertion, there

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET

input must

be asserted (low) at power-up.

TCK I Input only

3

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21266.

TMS I/S Three-state with

pull-up enabled

TDI I/S Three-state with

pull-up enabled
TDO O Three-state
TRST

I/A Three-state with

4

pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a

22.5 kΩ internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed

low) after power-up or held low for proper operation of the ADSP-21266. TRST

has

a 22.5 kΩ internal pull-up resistor.

EMU

O (O/D) Three-state with

pull-up enabled

Emulation Status. Must be connected to the ADSP-21266 Analog Devices DSP
Tools product line of JTAG emulators target board connector only. EMU

has a

22.5 kΩ internal pull-up resistor.

V

DDINT

P Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor

(13 pins on the BGA package, 32 pins on the LQFP package).

V

DDEXT

P I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the

LQFP package).

A

VDD

P Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL

(clock generator). This pin has the same specifications as V

, except that added

DDINT

filtering circuitry is required. For more information, see Power Supplies on Page 8.

A

VSS

G Analog Power Supply Return.

GND G Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

1

RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.

2

Output only is a three-state driver with its output path always enabled.

3

Input only is a three-state driver with both output paths.

4

Three-state is a three-state driver.

Rev. A | Page 13 of 44 | May 2004

ADSP-21266

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAG15-0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port.

Table 3. AD[15:0] to FLAG Pin Mapping

AD Pin Flag Pin

AD0 FLAG8
AD1 FLAG9
AD2 FLAG10
AD3 FLAG11
AD4 FLAG12
AD5 FLAG13
AD6 FLAG14
AD7 FLAG15
AD8 FLAG0
AD9 FLAG1
AD10 FLAG2
AD11 FLAG3
AD12 FLAG4
AD13 FLAG5
AD14 FLAG6
AD15 FLAG7

ADDRESS DATA MODES

The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address bits A23-A8 when asserted, fol­lowed by address bits A7-A0 and data bits D7-D0 when
deasserted. For 16-bit data transfers, ALE latches address bits
A15-A0 when asserted, followed by data bits D15-D0 when
deasserted.

Table 6. Address/Data Mode Selection

EP Data
Mode

8-bit Asserted A15-8 A23-16
8-bit Deasserted D7-0 A7-0
16-bit Asserted A7-0 A15-8
16-bit Deasserted D7-0 D15-8

ALE AD7-0

Function

AD15-8
Function

Boot Modes

Table 4. Boot Mode Selection

BOOTCFG1-0 Booting Mode

00 SPI Slave Boot
01 SPI Master Boot
10 Parallel Port Boot via EPROM
11 Internal Boot Mode (ROM code only)

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

Table 5. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1-0 Core to CLKIN Ratio

00 3:1
01 16:1
10 8:1
11 Reserved

Rev.A | Page 14 of 44 | May 2004