ANALOG DEVICES ADRF6806 Service Manual

50 MHz to 525 MHz Quadrature

V

Demodulator with Fractional-N PLL and VCO

Data Sheet

FEATURES

IQ demodulator with integrated fractional-N PLL LO frequency range: 50 MHz to 525 MHz For the following specifications (LPEN = 0)/(LPEN = 1):

Input P1dB: 12.2 dBm/10.6 dBm Input IP3: 28.5 dBm/25.2 dBm Noise figure (DSB): 12.2/11.4 Voltage conversion gain: 1 dB/4.2 dB

Quadrature demodulation accuracy

Phase accuracy: <0.5°

Amplitude accuracy: <0.1 dB Baseband demodulation: 135 MHz, 3 dB bandwidth SPI serial interface for PLL programming 40-lead, 6 mm × 6 mm LFCSP

APPLICATIONS

QAM/QPSK RF/IF demodulators Cellular W-CDMA/CDMA/CDMA2000 Microwave point-to-(multi)point radios Broadband wireless and WiMAX

ADRF6806

GENERAL DESCRIPTION

The ADRF6806 is a high dynamic range IQ demodulator with integrated PLL and VCO. The fractional-N PLL/synthesizer generates a frequency in the range of 2.8 GHz to 4.2 GHz. A programmable quadrature divider (divide ratio = 4 to 80) divides the output frequency of the VCO down to the required local oscillator (LO) frequency to drive the mixers in quadrature. Additionally, an output divider (divide ratio = 4 to 8) generates a divided-down VCO signal for external use.

The PLL reference input is supported from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO.

The IQ demodulator mixes the differential RF input with the complex LO derived from the quadrature divider. The differential I and Q output paths have excellent quadrature accuracy and can handle baseband signaling or complex IF up to 120 MHz.

A reduced power mode of operation is also provided by programming the serial interface registers to reduce current consumption, with slightly degraded input linearity and output current drive.

The ADRF6806 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, exposed-paddle, RoHS-compliant, 6 mm × 6 mm LFCSP package. Performance is specified over the −40°C to +85°C temperature range.

FUNCTIONAL BLOCK DIAGRAM

CCLO

GND

34

35

LON

37

38

LOP

MUX

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

TEMP

SENSOR

GND

DATA

CLK

GND

REFIN

GND

MUXOUT

11

12

13

14

LE

15

6

7

8

SPI

INTERFACE

×2

÷2

÷4

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

17

1

VCC1

LOSEL

36

MODULUS

– +

FREQUENCY

DETECTOR

BUFFER

CTRL

INTEGER

REG

N COUNTE R

PHASE

2

VCC1

PRESCALER

CHARGE PUMP 250µA, 500µA (DEFAULT),

750µA, 1000µA

3

CPOUT

÷2

4

GND

Figure 1.

IBBNIBBP

GND

3233

31

30

RSET

BUFFER

9 105

DECL2 VCC2

DIV

÷4, ÷6, ÷8

MUX

VCO

CORE

39

VTUNE

DIVIDER

÷2 TO ÷40

VCO LDO2.5V LDO

40

DECL1

ADRF6806

QUAD

÷2

16

GND

18

QBBP

19

QBBN

20

GND

29

28

27

26

25

24

23

22

21

GND

DECL3

VCCRF

GND

RFIN

RFIP

GND

VOCM

VCCBB

GND

09335-001

ADRF6806 Data Sheet

REVISION HISTORY

3/12—Rev. A to Rev. B

Changes to Phase Noise—Using 67 kHz Loop Filter Parameter,

Table 1; Added Phase Noise—Using 2.5 kHz Loop Filter Parameter, Table 1; Added PLL Figure of Merit (FOM)

Parameter, Table 1 ........................................................................ 4

Changes to Figure 21 and Figure 24 to Figure 26....................... 12

Changes to Figure 34...................................................................... 16

Changes to Figure 37...................................................................... 18

Changes to Figure 38...................................................................... 19

Changes to Figure 39...................................................................... 20

Changes to EVM Measurements Section and Figure 42,

Deleted Figure 43; Renumbered Sequentially ........................ 24

Changes to Figure 43...................................................................... 25

Added Figure 44.............................................................................. 26

Changes to Figure 46 and Figure 47............................................. 27

Changes to Table 7.......................................................................... 29

Changes to Figure 48...................................................................... 30

Changes to Figure 49...................................................................... 31

6/11—Rev. Sp0 to Rev. A

Rev. B | Page 2 of 36

Data Sheet ADRF6806

SPECIFICATIONS

VS1 (V

= 4.5 MHz, R

f

BB

differential RF input port impedance, all register and PLL settings use the recommended values shown in the Register Structure section, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

FREQUENCY RANGE 50 525 MHz RF INPUT @ 140 MHz RFIP, RFIN pins

Input Return Loss Relative to 100 Ω −11.7 dB Input P1dB LPEN = 0 (standard power mode) 12.2 dBm LPEN = 1 (low power mode) 10.6 dBm Second-Order Input Intercept (IIP2) LPEN = 0; −5 dBm each tone >65 dBm LPEN = 1; −5 dBm each tone >60 dBm Third-Order Input Intercept (IIP3) LPEN = 0; −5 dBm each tone 28.5 dBm LPEN = 1; −5 dBm each tone 25.2 dBm Noise Figure Double sideband from RF to either I or Q output; LPEN = 0 12.2 dB Double sideband from RF to either I or Q output; LPEN = 1 11.4 dB With a −5 dBm interferer 5 MHz away 14 dB LO-to-RF Leakage At 1×LO frequency, 100 Ω termination at the RF port −70 dBm

I/Q BASEBAND OUTPUTS IBBP, IBBN, QBBP, QBBN pins

Voltage Conversion Gain

Demodulation Bandwidth 1 V p-p signal 3 dB bandwidth; LPEN = 0 170 MHz 1 V p-p signal 3 dB bandwidth; LPEN = 1 135 MHz Quadrature Phase Error 0.3 Degrees I/Q Amplitude Imbalance 0.05 dB Output DC Offset (Differential) ±8 mV Output Common-Mode Reference VOCM applied input voltage 1.55 1.65 1.75 V Common-Mode Offset |(V Gain Flatness Any 5 MHz 0.2 dB p-p Maximum Output Swing Differential 450 Ω load 3 V p-p Differential 200 Ω load 2.4 V p-p Maximum Output Current Each pin 6 mA p-p

LO INPUT/OUTPUT LOP, LON

Output Level (LPEN = 0)

Output Level (LPEN = 1)

Input Level Externally applied 2×LO, PLL disabled 0 dBm Input Impedance Externally applied 2×LO, PLL disabled 50 Ω LO Main Divider Range

VCO Output Divider Range

VCO Operating Frequency 2800 4200 MHz

SYNTHESIZER SPECIFICATIONS

Channel Spacing f PLL Bandwidth

VCCB B

and V

) = 5 V, and VS2 (V

VCCRF

= 450  differential, RF port driven from a 1:2 balun to step up the 50 Ω source impedance to match the 100 Ω

LOAD

, V

VCC1

VCC2

, and V

) = 3.3 V; ambient temperature (TA) = 25°C; f

VCCLO

450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);

= 26 MHz, fLO = 140 MHz,

REF

1 dB

LPEN = 0 450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);

4.2 dB

LPEN = 1

+ V

IBBN

)/2 − V

IBBP

Into a differential 50 Ω load, LO buffer enabled (output

VOCM

|, |(V

QBBP

+ V

QBBN

)/2 − V

| 25 mV

VOCM

1 dBm

frequency = 800 MHz) Into a differential 50 Ω load, LO buffer enabled (output

−0.75 dBm

frequency = 800 MHz)

VCO to mixer, including quadrature divider, see Table 5 for

8 80

supported divider modes VCO to (LOP, LON), see Table 6 for supported output divider

4 8

modes

All synthesizer specifications measured with recommended settings provided in Figure 33 through Figure 40

= 26 MHz 25 kHz

PFD

Can be adjusted with off-chip loop filter component values and R

SET

67 kHz

Rev. B | Page 3 of 36

ADRF6806 Data Sheet

Parameter Test Conditions/Comments Min Typ Max Unit

SPURS

= 140 MHz, f

f

LO

outputs with f

= 26 MHz, f

REF

= 50 MHz

BB

= 26 MHz, measured at BB

PFD

Reference Spurs f f f f PHASE NOISE—USING 67 kHz LOOP

FILTER

= 26 MHz, f

REF

/2 −106 dBc

REF

× 2 −100 dBc

REF

× 3 −105 dBc

REF

fLO = 140 MHz, f outputs with f

= 26 MHz −95 dBc

PFD

= 26 MHz, f

REF

= 50 MHz

BB

= 26 MHz, measured at BB

PFD

@ 1 kHz offset −117 dBc/Hz @ 10 kHz offset −124 dBc/Hz @ 100 kHz offset −127 dBc/Hz @ 500 kHz offset −146 dBc/Hz @ 1 MHz offset −149 dBc/Hz @ 5 MHz offset −151 dBc/Hz @ 10 MHz offset −153 dBc/Hz

Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.03

PHASE NOISE—USING 2.5 kHz LOOP

FILTER

fLO = 900 MHz, f outputs with f

= 26 MHz, f

REF

= 50 MHz

BB

= 26 MHz, measured at BB

PFD

@ 1 kHz offset −95 dBc/Hz @ 10 kHz offset −110 dBc/Hz @ 100 kHz offset −136 dBc/Hz @ 500 kHz offset −149 dBc/Hz @ 1 MHz offset −149.5 dBc/Hz @ 5 MHz offset −151 dBc/Hz @ 10 MHz offset −153 dBc/Hz PLL FIGURE OF MERIT (FOM) Measured with f Measured with f

= 26 MHz, f

REF

= 104 MHz, f

REF

= 26 MHz −215.4 dBc/Hz/Hz

PFD

= 26 MHz −220.9 dBc/Hz/Hz

PFD

Phase Detector Frequency 20 26 40 MHz REFERENCE CHARACTERISTICS REFIN, MUXOUT pins

REFIN Input Frequency Usable range 9 160 MHz

REFIN Input Capacitance 4 pF

MUXOUT Output Level VOL (lock detect output selected) 0.25 V

V

(lock detect output selected) 2.7 V

OH

REFOUT Duty Cycle 50 % CHARGE PUMP

Pump Current 500 μA

Output Compliance Range 1 2.8 V LOGIC INPUTS CLK, DATA, LE pins

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INH/IINL

1.4 3.3 V

INH

0 0.7 V

INL

0.1 μA

Input Capacitance, CIN 5 pF POWER SUPPLIES VCC1, VCC2, VCCLO, VCCBB, VCCRF pins

Voltage Range (3.3 V) VCC1, VCC2, VCCLO 3.135 3.3 3.465 V

Voltage Range (5 V) VCCBB, VCCRF 4.75 5 5.25 V

Supply Current (3.3 V) (LPEN = 0) Normal Rx mode 209 mA

Rx mode with LO buffer enabled 270 mA

Supply Current (5 V) (LPEN = 0) Normal Rx mode 86 mA

Rx mode with LO buffer enabled 86 mA

Supply Current (3.3 V) (LPEN = 1) Normal Rx mode 205 mA

Rx mode with LO buffer enabled 258 mA

°rms

Rev. B | Page 4 of 36

Data Sheet ADRF6806

C

K

Parameter Test Conditions/Comments Min Typ Max Unit

Supply Current (5 V) (LPEN = 1) Normal Rx mode 75 mA Rx mode with LO buffer enabled 75 mA Supply Current (5 V) Power-down mode 10 mA Supply Current (3.3 V) Power-down mode 15 mA

TIMING CHARACTERISTICS

VS1 (V

Table 2.

Parameter Limit at T

t1 20 ns min LE Setup Time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width

VCCB B

and V

LOC

) = 5 V, and VS2 (V

VCCRF

MIN

, V

VCC2

, and V

VCC1

to T

(B Version) Unit Test Conditions/Comments

MAX

VCCLO

) = 3.3 V.

t

4

t

5

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

1

LE

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

09335-002

Figure 2. Timing Diagram

Rev. B | Page 5 of 36

ADRF6806 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage, VCCBB and VCCRF (VS1) −0.5 V to +5.5 V Supply Voltage, VCC1, VCC2, and VCCLO (VS2) −0.5 V to +3.6 V Digital I/O, CLK, DATA, and LE −0.3 V to +3.6 V RFIP and RFIN (Each Pin AC-Coupled) 13 dBm θJA (Exposed Paddle Soldered Down) 30°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 6 of 36

Data Sheet ADRF6806

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCC1

CPOUT

GND

RSET

REFIN

GND

MUXOUT

DECL2

VCC2

10

1

2

3

4

5

6

7

8

9

ENABLE

2.5V LDO

DECL1

VTUNE

40

39

VCO LDO

PHASE DETECTO R

AND

CHARGE PUMP

×2

÷2

MUX

÷4

FRACTION

LOP

38

SCALE

BLEED

VCO

BAND

CURRENT

CAL/SET

PROGRAMABLE

DIVIDER

THIRD-ORDER

SDM

MODULUS

SERIAL

PORT

LON

37

6

LOSEL

36

BUFFER

CTRL

VCO

2800MHz

TO

2H400MHz

PRESCALER

GND

35

÷2

INTEGER

MUX

VCCLO

34

DIV

÷4, ÷6, ÷8

DIV

CTRL

DIV

÷2 TO

÷40

33

IBBP

DIV

CTRL

QUADRATURE

IBBN

32

GND

31

30

GND

29

DECL3

28

VCCRF

27

GND

26

RFIN

÷2

COMMON-

MODE

LEVEL

CONTROL

25

RFIP

24

GND

23

VOCM

VCCBB

22

GND

21

11

12

13

14

15

LE

GND

NOTES

1. THE EXPO SED PADDLE SHOULD BE SOL DERED TO A LOW IMPEDANCE GROUND PLANE .

CLK

DATA

GND

17

16

GND

VCCLO

19

18

QBBP

QBBN

20

GND

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2 VCC1 The 3.3 V power supply for VCO and PLL. 3 CPOUT Charge Pump Output Pin. Connect this pin to VTUNE through the loop filter. 4, 7, 11, 15, 16, 20,

GND Connect these pins to a low impedance ground plane.

21, 24, 27, 30, 31, 35 5 RSET

Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no external R

is required. If DB18 is set to 1, the four nominal charge pump currents (I

SET

externally tweaked according to the following equation where the resulting value is in units of ohms.

⎡

=

R

⎢

SET

⎣

I

NOMINAL

⎤

×

I

4.217

CP

⎥

8.37

−

⎦

6 REFIN Reference Input. Nominal input level is 1 V p-p. Input range is 9 MHz to 160 MHz.

Rev. B | Page 7 of 36

NOMINAL

09335-003

) can be

ADRF6806 Data Sheet

Pin No. Mnemonic Description

8 MUXOUT

9 DECL2 Connect a 0.1 μF capacitor between this pin and ground. 10 VCC2 The 3.3 V power supply for the 2.5 V LDO. 12 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. 13 CLK

14 LE

17, 34 VCCLO The 3.3 V power supply for the LO path blocks. 18, 19 QBBP, QBBN Demodulator Q-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω). 22 VCCBB The 5 V power supply for the demodulator blocks. 23 VOCM

25, 26 RFIP, RFIN Differential 100 Ω, Internally Biased RF Inputs. These pins must be ac-coupled. 28 VCCRF The 5 V power supply for the demodulator blocks. 29 DECL3 Connect a 2.2 μF capacitor between this pin and ground. 32, 33 IBBN, IBBP Demodulator I-Channel Differential Baseband Outputs (Differential Output Impedance of 28 Ω). 36 LOSEL

37, 38 LON, LOP

39 VTUNE

40 DECL1

EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.

Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.

Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.

Baseband Common-Mode Reference Input; 1.65 V nominal. It sets the dc common-mode level of the IBBx and QBBx outputs.

LO Select. Connect this pin to ground for the simplest operation and to completely control the LO path and input/output direction from the register SPI programming. For additional control without register reprogramming, this input pin can determine whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the LOSEL pin is set low, the LDRV bit of Register 5 is set low, and the LXL bit of Register 5 is set high. The externally applied LO drive must be at M×LO frequency (where M corresponds to the main LO divider setting). LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set high and the LXL bit of Register 5 (DB4) low. The output frequency is controlled by the LO output divider bits in Register 7. This pin should not be left floating.

Local Oscillator Input/Output. When these pins are used as output pins, a differential frequency divided version of the internal VCO is available on these pins. When the internal LO generation is disabled, an external M×LO frequency signal can be applied to these pins (where M corresponds to the main divider setting). (Differential Input/Output Impedance of 50 Ω)

VCO Control Voltage Input. This pin is driven by the output of the loop filter. The nominal input voltage range on this pin is 1.0 V to 2.8 V.

Connect a 10 μF capacitor between this pin and ground as close to the device as possible because this pin serves as the VCO supply and loop filter reference.

Rev. B | Page 8 of 36

Data Sheet ADRF6806

A

R

A

TYPICAL PERFORMANCE CHARACTERISTICS

VS1 = 5 V, VS2 = 3.3 V, TA = 25°C, RF input balun loss is de-embedded, unless otherwise noted. LO = 50 MHz to 525 MHz; Mini-Circuits ADTL2-18 balun on RF inputs.

16

80

14

IP1dB

12

10

TA = +85°C

8

= +25°C

T

A

TA = –40°C

6

4

GAIN

2

CONVERSIO N GAIN (dB) AND INPUT P1dB (dBm)

0

50

75

100

LPEN = 0 LPEN = 1

125

150

175

200

LO FREQUENCY (MHz)

225

250

275

300

325

350

375

400

425

450

Figure 4. Conversion Gain and Input P1dB vs. LO Frequency

40

38

36

50

TA = +85°C T TA = –40°C

75

100

= +25°C

A

125

34

32

30

28

INPUT IP3 (dBm)

26

24

22

20

LPEN = 0 LPEN = 1

150

175

200

225

250

LO FREQUENCY (M Hz)

275

300

325

350

375

400

425

450

Figure 5. Input IP3 vs. LO Frequency

1.0

0.8

0.6

0.4

0.2

TCH (dB)

–0.2

–0.4

IQ GAIN MISM

–0.6

–0.8

–1.0

TA = +85°C T

= +25°C

A

T

= –40°C

A

0

50

75

100

125

LPEN = 0 LPEN = 1

150

175

200

225

250

LO FREQUENCY (MHz)

275

300

325

350

375

400

425

Figure 6. IQ Gain Mismatch vs. LO Frequency

450

475

500

525

75

LPEN = 1

70

65

50

LPEN = 0

TA = +85°C T T

75

100

= +25°C

A

= –40°C

A

125

150

175

I CHANNEL Q CHANNEL

200

225

250

275

300

LO FREQUENCY (MHz)

325

350

375

400

425

450

475

500

525

09335-007

INPUT IP2 (dBm)

60

55

50

09335-004

Figure 7. Input IP2 vs. LO Frequency

17

50

75

100

TA = +85°C T

= +25°C

A

TA = –40°C

125

16

15

14

13

12

11

10

9

NOISE FIGURE (dB)

8

7

6

5

09335-005

LPEN = 0 LPEN = 1

150

175

200

225

250

LO FREQUENCY (MHz)

275

300

325

350

375

400

425

450

475

500

525

09335-008

Figure 8. Noise Figure vs. LO Frequency

2.0

1.5

TA = +85°C T

50

TA = –40°C

75

100

= +25°C

A

125

1.0

0.5

0

–0.5

TURE PHASE ERROR (Degrees)

–1.0

–1.5

IQ QUAD

–2.0

09335-006

LPEN = 0 LPEN = 1

150

175

200

225

250

LO FRE QUENCY (MHz)

275

300

325

350

375

400

425

450

475

500

525

9335-009

Figure 9. IQ Quadrature Phase Error vs. LO Frequency

Rev. B | Page 9 of 36

ADRF6806 Data Sheet

–

50

–55

–60

–65

–70

–75

–80

LO-TO-RF FE EDTHROUGH (d Bm)

–85

–90

LPEN = 0 LPEN = 1

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

425

450

475

500

LO FRE QUENCY (M Hz)

525

9335-010

Figure 10. LO-to-RF Feedthrough vs. LO Frequency, LO Output Turned Off

30

–35

–40

–45

–50

–55

–60

LO-TO-BB FEE DTHROUGH (d BV rms)

–65

–70

LPEN = 0 LPEN = 1

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

425

450

475

500

LO FREQUENCY (MHz)

525

09335-011

Figure 11. LO-to-BB Feedthrough vs. LO Frequency, LO Output Turned Off

30

–35

–40

–45

–50

–55

–60

RF-TO-BB FEE DTHROUGH (dBc)

–65

–70

LPEN = 0 LPEN = 1

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

425

450

475

500

RF FREQUENCY (MHz)

525

09335-012

Figure 12. RF-to-BB Feedthrough vs. RF Frequency

1

0

–1

–2

–3

–4

–5

–6

–7

–8

NORMALIZED BASEBAND

–9

FREQUE NCY RESP ONSE ( dB)

–10

–11

–12

1 10 100 400

LPEN = 0 LPEN = 1

BASEBAND FREQUENC Y (MHz)

Figure 13. Normalized BB Frequency Response

80

70

60

50

40

30

AND INPUT IP3 (dBm)

20

INPUT P1dB (dBm), INPUT IP2 (dBm),

10

0

5 101520253035404550

LPEN = 0

LPEN = 1

BASEBAND FREQUENC Y (MHz)

IIP2

TA = +85°C T

= +25°C

A

TA = –40°C

IIP3

IP1dB

I CHANNEL Q CHANNEL

Figure 14. Input P1dB, Input IP2, and Input IP3 vs. BB Frequency

30

28

26

24

22

20

18

16

NOISE FIGURE (dB)

14

12

10

8 –30

–25 –20 –15 –10 –5 0 5 10

LPEN = 0 LPEN = 1

INPUT BLOCKER P OWER (dBm)

Figure 15. Noise Figure vs. Input Blocker Level,

f

= 140 MHz (RF Blocker 5 MHz Offset)

LO

09335-013

09335-014

9335-015

Rev. B | Page 10 of 36

Data Sheet ADRF6806

A

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

RF RETURN LOSS (dB)

–22

–24

–26

–28

–30

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

RF FREQUENCY (MHz)

425

Figure 16. RF Input Return Loss vs. RF Frequency,

Measured Through ADTL2-18 2-to-1 Input Balun

0

–2

–4

–6

–8

–10

–12

–14

–16

–18

–20

–22

–24

LO OUTPUT RETURN LOSS (dB)

–26

–28

–30

350

400

450

500

550

600

650

700

750

800

850

900

LO OUTPUT FREQUE NCY (MHz)

Figure 17. LO Output Return Loss vs. LO Output Frequency,

LO Output Enabled (350 MHz to 1050 MHz)

260

235

3.3V SUPPLY

450

475

500

525

09335-016

950

1000

1050

09335-017

2.0

1.9

1.8

1.7

1.6

T VOLTAGE (V)

1.5

VPT

1.4

1.3

1.2 –40 –20 0 20 40 60 80

LPEN = 0 LPEN = 1

TEMPERATURE (°C)

Figure 19. VPTAT vs. Temperature

3.5

TA = +85°C T

3.0

2.5

2.0

1.5

VTUNE VOLTAGE (V)

1.0

0.5

350 370 390 410 430 450 470 490 510

= +25°C

A

T

= –40°C

A

LO FREQUE NCY (MHz)

Figure 20. VTUNE vs. LO Frequency

09335-019

09335-020

210

185

160

135

CURRENT (mA)

110

85

60

50

75

100

125

150

175

200

225

LO FREQUENCY (MHz)

Figure 18. 5 V and 3.3 V Supply Currents vs. LO Frequency,

LO Output Disabled

5V SUPPLY

250

275

300

TA = +85°C

= +25°C

T

A

= –40°C

T

A

325

350

LPEN = 0 LPEN = 1

375

400

425

450

475

500

525

09335-018

Rev. B | Page 11 of 36

ANALOG DEVICES ADRF6806 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS