ANALOG DEVICES ADRF6750 Service Manual

950 MHz to 1575 MHz Quadrature Modulator

V

with Integrated Fractional-N PLL and VCO

ADRF6750

FEATURES

I/Q modulator with integrated fractional-N PLL and VCO Gain control span: 47 dB in 1 dB steps Output frequency range: 950 MHz to 1575 MHz Output 1 dB compression: 8.5 dBm Output IP3: 23 dBm Noise floor: −162 dBm/Hz Baseband modulation bandwidth: 250 MHz (1 dB) Output frequency resolution: 1 Hz Functions with external VCO for extended frequency range SPI and I Power supply: 5 V/310 mA

2

C-compatible serial interfaces

GENERAL DESCRIPTION

The ADRF6750 is a highly integrated quadrature modulator, frequency synthesizer, and programmable attenuator. The device covers an operating frequency range from 950 MHz to 1575 MHz for use in satellite, cellular and broadband communications.

The ADRF6750 modulator includes a high modulus fractional-N frequency synthesizer with integrated VCO, providing better than 1 Hz frequency resolution, and a 47 dB digitally controlled output attenuator with 1 dB steps.

Control of all the on-chip registers is through a user-selected SPI interface or I power supply ranging from 4.75 V to 5.25 V.

2

C interface. The device operates from a single

FUNCTIONAL BLOCK DIAGRAM

CC1VCC2VCC3VCC4

REGOUT

VREG1 VREG2 VREG3 VREG4 VREG5 VREG6

LOMONP LOMONN

RFOUT

TXDIS

REFIN

SDI/SDA

CLK/SCL

SDO

CS

3.3V

REGULATOR

47dB

GAIN CONTROL

RANGE

×2

DOUBLER

SPI/

2

I

C

INTERFACE

ADRF6750

0°/90°

5-BIT

DIVIDER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRACTIONAL

REGISTER

OUTPUT

STAGE

÷2

MODULUS

25

2

VCO

CORE

+

FREQUENCY

DETECTOR

–

N-COUNTER

INTEGER

REGISTER

PHASE

REFERENCE

CHARGE

PUMP

CURRENT SETTING

RFCP4 RFCP3 RFCP2 RFCP1

IBBP IBBN

CCOMP1 CCOMP2 CCOMP3

VTUNE

TESTLO TESTLO

QBBP QBBN

RSET

CP

LF3 LF2 LDET

AGND DGND

08201-001

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADRF6750

REVISION HISTORY

4/10—Rev. 0 to Rev. A

Changes to Table 5 ............................................................................ 9

Changes to LOMON Outputs Section ......................................... 33

Changes to Ordering Guide .......................................................... 39

1/10—Revision 0: Initial Version

Rev. A | Page 2 of 40

ADRF6750

SPECIFICATIONS

VCC = 5 V, TA = 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, REFIN = 10 MHz, PFD = 20 MHz, loop bandwidth = 50 kHz, and LOMONx is off, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

RF OUTPUT RFOUT pin

Operating Frequency Range 950 1575 MHz Nominal Output Power VIQ = 0.9 V p-p differential −1.6 dBm Gain Flatness Any 40 MHz ±0.5 dB Output P1dB 8.5 dBm Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P Output Return Loss Attenuator setting = 0 dB −12 dB LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −45 dBc 2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −45 dBm Sideband Suppression −45 dBc Noise Floor I/Q inputs = 0 V p-p differential, Attenuator setting = 0 dB −162 dBm/Hz Attenuator setting = 0 dB to 21 dB, carrier offset = 15 MHz −147 dBc/Hz Attenuator setting = 21 dB to 47 dB, carrier offset = 15 MHz −170 dBm/Hz Harmonics −60 dBc

REFERENCE CHARACTERISTICS REFIN pin

Input Frequency With R/2 divider enabled 10 300 MHz With R/2 divider disabled 10 165 MHz Input Sensitivity AC-coupled 0.4 VREG V p-p Input Capacitance 10 pF Input Current ±100 µA

CHARGE PUMP

ICP Sink/Source Programmable

High Value With RSET = 4.7 kΩ 5 mA

Low Value 312.5 µA Absolute Accuracy With RSET = 4.7 kΩ 4.0 % RSET Value 4.7 kΩ VCO Gain K

SYNTHESIZER SPECIFICATIONS

Frequency Resolution 1 Hz Spurs Integer boundary < loop bandwidth −55 dBc >10 MHz offset from carrier −85 dBc Phase Noise1 Frequency = 950 MHz to 1575 MHz 100 Hz offset −80 dBc/Hz 1 kHz offset −88 dBc/Hz 10 kHz offset −93 dBc/Hz 100 kHz offset −107 dBc/Hz 1 MHz offset −133 dBc/Hz >15 MHz offset −152 dBc/Hz Integrated Phase Noise1 1 kHz to 8 MHz integration bandwidth 0.4

Frequency Settling1 Maximum frequency error = 100 Hz 170 s Maximum Frequency Step for

No Autocalibration

Phase Detector Frequency 10 30 MHz

25 MHz/V

VCO

Frequency step with no autocalibration routine; Register CR24, Bit 0 = 1

= −6 dBm per tone 23 dBm

OUT

100 kHz

°rms

Rev. A | Page 3 of 40

ADRF6750

Parameter Test Conditions/Comments Min Typ Max Unit

GAIN CONTROL

Gain Range 47 dB Step Size 1 dB

Relative Step Accuracy Fixed frequency, adjacent steps All attenuation steps ±0.3 dB Over full frequency range, adjacent steps ±1.5 dB

Absolute Step Accuracy2 47 dB attenuation step −2.0 dB

Output Settling Time Any step; output power settled to ±0.2 dB 10 µs OUTPUT DISABLE TXDIS pin

Off Isolation RF OUT, attenuator setting = 0 dB to 47 dB, TXDIS high −110 dBm

LO, Attenuator setting = 0 dB to 47 dB, TXDIS high −90 dBm

2 x LO, Attenuator setting = 0 dB to 47 dB, TXDIS high −50 dBm

Turn-On Settling Time TXDIS high to low (90% of envelope) 180 ns

Turn-Off Settling Time TXDIS low to high (to −55 dBm) 270 ns MONITOR OUTPUT LOMONP, LOMONN pins

Nominal Output Power −24 dBm BASEBAND INPUTS IBBP, IBBN, QBBP, QBBN pins

I and Q Input Bias Level 500 mV

1 dB Bandwidth 250 MHz LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INH/IINL

Input Capacitance, CIN CS, TXDIS, SDI/SDA, CLK/SCL pins 10 pF LOGIC OUTPUTS

Output High Voltage, VOH SDO, LDET pins; IOH = 500 A 2.8 V

Output Low Voltage, VOL SDO, LDET pins; IOL = 500 A 0.4 V SDA (SDI/SDA); IOL = 3 mA 0.4 V POWER SUPPLIES

Voltage Range VCC1, VCC2, VCC3, and VCC4 4.75 5 5.25 V

REGOUT, VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 3.3 V

Supply Current

Operating Temperature −40 +85 °C

1

LBW = 50 kHz at LO = 1200 MHz; ICP = 2.5 mA.

2

All other attenuation steps have an absolute error of <±2.0 dB.

CS, TXDIS pins 1.4 V

INH

CS, TXDIS pins 0.6 V

INL

SDI/SDA, CLK/SCL pins 2.1 V

INH

SDI/SDA, CLK/SCL pins 1.1 V

INL

CS, TXDIS, SDI/SDA, CLK/SCL pins ±1 µA

VCC1, VCC2, VCC3, VCC4, VREG1, VREG2, VREG3, VREG4, VREG5, VREG6, and REGOUT pins REGOUT normally connected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6

VCC1, VCC2, VCC3, and VCC4 combined; REGOUT con-

310 340 mA

nected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6

Rev. A | Page 4 of 40

ADRF6750

TIMING CHARACTERISTICS

I2C Interface Timing

Table 2.

Parameter1 Symbol Limit Unit

SCL Clock Frequency f SCL Pulse Width High t SCL Pulse Width Low t Start Condition Hold Time t Start Condition Setup Time t Data Setup Time t Data Hold Time t Stop Condition Setup Time t Data Valid Time t Data Valid Acknowledge Time t Bus Free Time t

1

See Figure 2.

SDA

400 kHz max

SCL

600 ns min

HIGH

1300 ns min

LOW

600 ns min

HD;STA

600 ns min

SU;STA

100 ns min

SU;DAT

300 ns min

HD;DAT

600 ns min

SU;STO

900 ns max

VD;DAT

900 ns max

VD;ACK

1300 ns min

BUF

t

SU;DAT

VD;DAT AND

t

VD;ACK (ACK SIGNAL ONLY)

t

BUF

SCL

t

HD;STA

t

LOW

S SSP

START

CONDITION

1/f

SCL

t

HD;DAT

t

HIGH

Figure 2. I

2

C Port Timing Diagram

t

SU;STA

t

SU;STO

STOP

CONDITION

08201-003

Rev. A | Page 5 of 40

ADRF6750

SPI Interface Timing

Table 3.

Parameter1 Symbol Limit Unit

CLK Frequency f CLK Pulse Width High t1 15 ns min CLK Pulse Width Low t2 15 ns min Start Condition Hold Time t3 5 ns min Data Setup Time t4 10 ns min Data Hold Time t5 5 ns min Stop Condition Setup Time t6 5 ns min SDO Access Time t7 15 ns min CS to SDO High Impedance t8 25 ns max

1

See Figure 3.

t

3

CS

20 MHz max

CLK

t

1

CLK

SDI

t

2

t

5

4

SDO

t

7

6

t

8

08201-004

Figure 3. SPI Port Timing Diagram

Rev. A | Page 6 of 40

ADRF6750

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage VCC1, VCC2, VCC3, and VCC4 −0.3 V to +6 V Supply Voltage VREG1, VREG2, VREG3, VREG4,

VREG5, and VREG6 IBBP, IBBN, QBBP, and QBBN 0 V to 2.5 V Digital I/O −0.3 V to +4 V Analog I/O (Other Than IBBP, IBBN, QBBP,

and QBBN) TESTLO, TESTLO Difference θJA (Exposed Paddle Soldered Down) 26°C/W Maximum Junction Temperature 120°C Storage Temperature Range −65°C to +150°C

−0.3 V to +4 V

1.5 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 7 of 40

ADRF6750

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D

VCC2

VCC2 56

1VCC4 2IBBP 3IBBN 4QBBN 5QBBP 6AGND 7RSET 8LF3

9CP 10LF2 11VCC1 12REGOUT 13VREG1 14VREG2

AGN

AGND

55

52

53

54

PIN 1 INDICATOR

ADRF6750

TOP VIEW

(Not to Scale)

AGND

50

51

TXDIS

AGND

AGN

RFOUT

AGND

LDET

MUXOUT

45

46

47

48

49

44

43

42 VCC3 41 VCC3 40 AGND 39 AGND 38 VTUNE 37 AGND 36 VREG6 35 CCOMP3 34 CCOMP2 33 CCOMP1 32 DGND 31 VREG5 30 CLK/SCL 29 SDI/SDA

16

15

VREG3

VREG4

NOTES

1. CONNECT EXPOSED PAD TO GROUND PLANE VIA A LOW IMPEDANCE PATH.

21

17

19

20

22

23

24

25

26

27

18

D

IN

AGND

AGN

AGND

REF

TESTLO

28

S C

SDO

AGND

MONP

TESTLO

LO

LOMONN

08201-005

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

11, 55, 56, 41, 42, 1 VCC1 to VCC4

Positive Power Supplies for I/Q Modulator. Apply a 5 V power supply to VCC1, which should be decoupled with power supply decoupling capacitors. Connect VCC2, VCC3, and VCC4 to the same

5 V power supply. 12 REGOUT 3.3 V Output Supply. Drives VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6. 13, 14, 15, 16, 31,

36 6, 19, 20, 21, 24, 37,

VREG1 to VREG6

Positive Power Supplies for PLL Synthesizer, VCO, and Serial Port. Connect these pins to REGOUT

(3.3 V) and decouple them separately.

AGND Analog Ground. Connect to a low impedance ground plane. 39, 40, 46, 47, 49, 50, 51, 52, 53, 54

32 DGND Digital Ground. Connect to the same low impedance ground plane as the AGND pins. 2, 3 IBBP, IBBN

Differential In-Phase Baseband Inputs. These high impedance inputs must be dc-biased to approximately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with a 500 mV dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These inputs are not self-biased and must be externally biased.

4, 5 QBBN, QBBP

Differential Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to approximately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with a 500 mV dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These inputs are not self-biased and must be externally biased.

33, 34, 35

CCOMP1 to

Internal Compensation Nodes. These pins must be decoupled to ground with a 100 nF capacitor.

CCOMP3 38 VTUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.

7 RSET

9 CP

Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship between I

5.23

I

CPmax

where R

=

R

SET

= 4.7 kΩ and I

SET

CP max

= 5 mA.

and R

CP

Charge Pump Output. When enabled, this output provides ±I

is as follows:

SET

to the external loop filter, which, in

CP

turn, drives the internal VCO.

Rev. A | Page 8 of 40

ADRF6750

Pin No. Mnemonic Description

27 CS

29 SDI/SDA

30 CLK/SCL

28 SDO Serial Data Output for SPI Port. Register states can be read back on the SDO data output line. 17 REFIN Reference Input. This high impedance CMOS input should be ac-coupled. 18

REFIN

48 RFOUT

45 TXDIS

25, 26

LOMONP, LOMONN

22, 23

TESTLO, TESTLO

10, 8 LF2, LF3 No connect pins. 44 LDET

43 MUXOUT

Exposed Paddle EP Exposed Paddle. Connect to ground plane via a low impedance path.

Chip Select, CMOS Input. When CS is high, the data stored in the shift registers is loaded into one of 31 latches. In I2C mode, when CS is high, the slave address of the device is 0x60, and when CS is low, the slave address is 0x40.

2

Serial Data Input for SPI Port/Serial Data Input/Output for I impedance CMOS data input, and data is loaded in an 8-bit word. In I

C Port. In SPI mode, this pin is a high

2

C mode, this pin is a bidirec-

tional port.

2

Serial Clock Input for SPI/I

C Port. This serial clock is used to clock in the serial data to the registers.

This input is a high impedance CMOS input.

Reference Input Bar. This pin should be either grounded or ac-coupled to ground. RF Output. Single-ended, 50 Ω, internally biased RF output. This pin must be ac-coupled to the

load. Nominal output power is −1.6 dBm for a single sideband baseband drive of 0.9 V p-p differential on the I and Q inputs (attenuation = minimum).

Output Disable. This pin can be used to disable the RF output. Connect to high logic level to disable the output. Connect to low logic level for normal operation.

Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency (1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately. These open-collector outputs must be terminated with external resistors to REGOUT. These outputs can be disabled through serial port programming and should be tied to REGOUT if not used.

Differential Test Inputs. These inputs provide an option for an external 2× LO to drive the modulator. This option can be selected by serial port programming. These inputs must be externally dc-biased and should be grounded if not used.

Lock Detect. This output pin indicates the state of the PLL: a high level indicates a locked condition, whereas a low level indicates a loss of lock condition.

Muxout. This output is a test output for diagnostic use only. It should be left unconnected by the customer.

Rev. A | Page 9 of 40

ADRF6750

TYPICAL PERFORMANCE CHARACTERISTICS

VCC = 5 V, TA = 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, REFIN = 10 MHz, PFD = 20 MHz, baseband frequency = 1 MHz, LOMONx is off, unless otherwise noted. A nominal condition is defined as 25°C, 5.00 V, and worst-case frequency. A worst-case condition is defined as having the worst-case temperature, supply voltage, and frequency.

2

1

0

–1

–2

–3

OUTPUT POWER (dBm)

–4

–5

950

+25°C; 5.00 V +85°C; 4.75 V +85°C; 5.25 V

1050

-40°C; 4.75V

-40°C; 5.25V 0°C; 4.75V

1150

LO F REQUENCY (MHz)

1250

0°C; 5.25V +70°C; 4.75V +70°C; 5.25V

1350

1450

1550

1575

Figure 5. Output Power vs. LO Frequency, Supply, and Temperature

40

35

30

25

20

15

OCCURRENCE (%)

10

5

0

–3.0

–3.2

–2.8

–2.6

–2.4

–2.2

–2.0

–1.8

OUTPUT PO WER (dBm)

–1.6

–1.4

–1.2

–1.0

NOMINAL WORST CASE

–0.8

–0.6

–0.4

–0.2

Figure 6. Output Power Distribution at Nominal and

Worst-Case Conditions

1

08201-105

0

08201-106

0

+25°C; 5.00V

1300

1350

+85°C; 4.75V +85°C; 5.25V –40°C; 4.75V –40°C; 5.25V

1400

1450

1500

1550

1575

08201-108

SIDEBAND SUPPRESS ION (dBc)

–10

–20

–30

–40

–50

–60

950

1000

1100

1150

1050

LO FR EQUENCY (MHz)

1200

1250

Figure 8. Sideband Suppression vs. LO Frequency, Supply, and Temperature

35

NOMINAL

30

WORST CASE

25

20

15

OCCURRENCE (%)

10

5

0

–60.0

–62.5

–57.5

–55.0

–52.5

–50.0

SIDEBAND SUPPRESSION (dBc)

–47.5

–45.0

–42.5

–40.0

–37.5

–35.0

–32.5

08201-109

Figu re 9. Sideband Suppression Distribution at Nominal and

Worst-Case Conditions

–40

0

–1

–2

–3

OUTPUT PO WER (dBm)

–4

–5

500 750 1000 1250 1500 1750 2000

LO FREQ UE NCY (M Hz )

Figure 7. Output Power vs. LO Frequency for External VCO Mode

at Nominal Conditions

08201-107

Rev. A | Page 10 of 40

–45

–50

–55

–60

–65

–70

CARRIER FEEDTHROUGH (dBc)

–75

–80

950

1150

1050

LO FREQUENCY (MHz)

1250

1350

1450

Figure 10. LO Carrier Feedthrough vs. Attenuation, LO Frequency,

Supply, and Temperature

1550

1575

08201-110

ADRF6750

60

50

40

30

OCCURENCE (%)

20

10

0

NOMINAL WORST-CASE

–75–80 –70 –65 –60 –55 –50 –45 –40 –35 –30

LO CARRIER FEEDTHROUGH (dBc)

08201-111

Figure 11. LO Carrier Feedthrough Distribution at Nominal and Worst-Case

Conditions and Attenuation Setting

–40

–50

–60

–70

–80

–90

ATTENUATION = 0dB ATTENUATION = 12dB ATTENUATION = 21dB ATTENUATION = 33dB ATTENUATION = 47dB

1150

LO FREQUE NCY (MHz)

1250

1350

1450

1550

1575

08201-112

2 × LO CARRIER FEEDTHROUGH (dBm)

–100

–110

–120

950

1050

Figure 12. 2 × LO Carrier Feedthrough vs. Attenuation, LO Frequency,

Supply, and Temperature

10

5

0

–5

–10

–15

OUTPUT PO WER (dBm)

–20

–25

0.1 1 10 DIFFERENTIAL INPUT VOLTAGE (V p-p)

COMPRESSION

1dB

POINT

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

IDEAL OUTPUT POWER – OUTPUT POWER (dBm)

Figure 13. Output P1dB Compression Point at Worst-Case LO Frequency

vs. Supply and Temperature

08201-113

50

45

40

35

30

25

20

OCCURENCE (%)

15

10

5

0

NOMINAL WORST-CASE

7.06.8 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 OUTPUT P1d B (dBm)

Figure 14. Output P1dB Compression Point Distribution at Nominal

and Worst-Case Conditions

10.5

10.0

9.5

9.0

8.5

8.0

7.5

OUTPUT P1dB (dBm)

7.0

6.5

6.0 950

1100

1000

1150

1050

LO FREQUENCY (MHz)

1200

1250

1300

1350

1400

1450

1500

1550

1575

Figure 15. Output P1dB Compression Point vs. LO Frequency at

Nominal Conditions

45

21.00

NOMINAL WORST-CASE

21.25

21.50

21.75

22.00

22.25

OUTPUT I P 3 (dBm)

22.50

22.75

23.00

23.25

23.50

23.75

24.00

40

35

30

25

20

OCCURENCE (%)

15

10

5

0

Figure 16. Output IP3 Distribution at Nominal and Worst-Case

Conditions

08201-114

08201-116

08201-115

Rev. A | Page 11 of 40

ADRF6750

30

29

28

27

26

25

24

23

LO FREQ UE NCY (M Hz )

22

21

20

950

1100

1000

1150

1050

OUTPUT IP3 INTERCEPT POINT (dBm)

1200

1250

1300

1350

1400

1450

1500

1550

1575

Figure 17. Output IP3 vs. LO Frequency at Nominal Conditions

–60

–70

ATION (dBm)

LO OFF ISOL

–80

–90

–100

–110

–120

–130

–140

950

ATTENUATION = 0dB

ATTENUATION = 4 7dB

1100

1000

1050

1150

1200

1250

LO FREQ UENCY (MHz)

1300

1350

1400

ATTENUATION

= 21dB

1450

1500

1550

1575

Figure 18. LO Off Isolation vs. Attenuation, LO Frequency, Supply,

and Temperature

–20

–30

–40

–50

–60

ATION (dBm)

–70

–80

–90

2 × LO OFF ISOL

–100

–110

–120

950

1000

ATTENUATION = 0dB

ATTENUATION = 2 1dB

ATTENUATION = 47dB

1100

1150

1050

1200

LO FREQ UE NCY (M Hz )

1250

1300

1350

1400

1450

1500

1550

1575

Figure 19. 2 × LO Off Isolation vs. Attenuation, LO Frequency, Supply,

and Temperature

08201-119

08201-117

08201-118

–40

–50

–60

–70

–80

–90

OUTPUT P OWER (dBc)

–100

LOWER SECOND HARMONIC (fLO –2×fBB)

–110

–120

950

UPPER THIRD HARMONIC (fLO+3×fBB)

UPPER SECOND HARMONIC (fLO+ 2 × fBB)

LOWER THIRD HARMONIC (fLO–3×fBB)

1050

1150

1250

LO FREQUENCY (MHz)

1350

1450

1550

Figure 20. Second-Order and Third-Order Harmonic Distortion vs.

LO Frequency, Supply, and Temperature

100

90

80

70

60

50

40

OCCURENCE (%)

30

20

10

0 –180 –176 –172 –168 –164 –160 –156 –152 –148 –144 –140

(dBm/Hz) NOISE FLOOR AT 15MHz O FFSET FREQUENCY (dBc/Hz)

ATTENUATIO N =

47dB (dBm/Hz)

ATTENUATIO N =

21dB (dBm/Hz)

ATTENUATIO N =

ATTENUATION =

21dB (dBc/Hz)

0dB (dBc/Hz)

Figure 21. Noise Floor at 15 MHz Offset Frequency Distribution at

Worst-Case Conditions and Different Attenuation Settings

–140

–145

–150

–155

–160

NOISE FLOOR (dBm/ Hz)

–165

–170

–25 –20 –15 –10

OUTPUT POWER (dBm)

–5 0 5 10

Figure 22. Noise Floor at 0 dB Attenuation vs. Output Power

at Nominal Conditions

1575

08201-128

08201-121

08201-120

Rev. A | Page 12 of 40

ANALOG DEVICES ADRF6750 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

I2C Interface Timing

SPI Interface Timing

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS