ANALOG DEVICES ADRF6750 Service Manual

950 MHz to 1575 MHz Quadrature Modulator

V

with Integrated Fractional-N PLL and VCO

ADRF6750

FEATURES

I/Q modulator with integrated fractional-N PLL and VCO
Gain control span: 47 dB in 1 dB steps
Output frequency range: 950 MHz to 1575 MHz
Output 1 dB compression: 8.5 dBm
Output IP3: 23 dBm
Noise floor: −162 dBm/Hz
Baseband modulation bandwidth: 250 MHz (1 dB)
Output frequency resolution: 1 Hz
Functions with external VCO for extended frequency range
SPI and I
Power supply: 5 V/310 mA

2

C-compatible serial interfaces

GENERAL DESCRIPTION

The ADRF6750 is a highly integrated quadrature modulator,
frequency synthesizer, and programmable attenuator. The
device covers an operating frequency range from 950 MHz
to 1575 MHz for use in satellite, cellular and broadband
communications.

The ADRF6750 modulator includes a high modulus fractional-N
frequency synthesizer with integrated VCO, providing better
than 1 Hz frequency resolution, and a 47 dB digitally controlled
output attenuator with 1 dB steps.

Control of all the on-chip registers is through a user-selected
SPI interface or I
power supply ranging from 4.75 V to 5.25 V.

2

C interface. The device operates from a single

FUNCTIONAL BLOCK DIAGRAM

CC1VCC2VCC3VCC4

REGOUT

VREG1
VREG2
VREG3
VREG4
VREG5
VREG6

LOMONP
LOMONN

RFOUT

TXDIS

REFIN

REFIN

SDI/SDA

CLK/SCL

SDO

CS

3.3V

REGULATOR

47dB

GAIN CONTROL

RANGE

×2

DOUBLER

SPI/

2

I

C

INTERFACE

ADRF6750

0°/90°

5-BIT

DIVIDER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRACTIONAL

REGISTER

OUTPUT

STAGE

÷2

MODULUS

25

2

VCO

CORE

+

FREQUENCY

DETECTOR

–

N-COUNTER

INTEGER

REGISTER

PHASE

REFERENCE

CHARGE

PUMP

CURRENT SETTING

RFCP4 RFCP3 RFCP2 RFCP1

IBBP
IBBN

CCOMP1
CCOMP2
CCOMP3

VTUNE

TESTLO
TESTLO

QBBP
QBBN

RSET

CP

LF3
LF2
LDET

AGND DGND

08201-001

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADRF6750

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 18

Overview ...................................................................................... 18

PLL Synthesizer and VCO ......................................................... 18

Quadrature Modulator .............................................................. 20

Attenuator .................................................................................... 21

Voltage Regulator ....................................................................... 21

EXTERNAL vco OPERATION ................................................ 21

I2C Interface ................................................................................ 21

SPI Interface ................................................................................ 23

Program Modes .......................................................................... 25

Register Map ................................................................................... 27

Register Map Summary ............................................................. 27

Register Bit Descriptions ........................................................... 28

Suggested Power-Up Sequence ..................................................... 31

Initial Register Write Sequence ................................................ 31

Evaluation Board ............................................................................ 32

General Description ................................................................... 32

Hardware Description ............................................................... 32

PCB Artwork............................................................................... 35

Bill of Materials ........................................................................... 38

Outline Dimensions ....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

4/10—Rev. 0 to Rev. A

Changes to Table 5 ............................................................................ 9

Changes to LOMON Outputs Section ......................................... 33

Changes to Ordering Guide .......................................................... 39

1/10—Revision 0: Initial Version

Rev. A | Page 2 of 40

ADRF6750

SPECIFICATIONS

VCC = 5 V, TA = 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz,
REFIN = 10 MHz, PFD = 20 MHz, loop bandwidth = 50 kHz, and LOMONx is off, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

RF OUTPUT RFOUT pin

Operating Frequency Range 950 1575 MHz
Nominal Output Power VIQ = 0.9 V p-p differential −1.6 dBm
Gain Flatness Any 40 MHz ±0.5 dB
Output P1dB 8.5 dBm
Output IP3 f1BB = 3.5 MHz, f2BB = 4.5 MHz, P
Output Return Loss Attenuator setting = 0 dB −12 dB
LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −45 dBc
2× LO Carrier Feedthrough Attenuator setting = 0 dB to 47 dB −45 dBm
Sideband Suppression −45 dBc
Noise Floor I/Q inputs = 0 V p-p differential, Attenuator setting = 0 dB −162 dBm/Hz
Attenuator setting = 0 dB to 21 dB, carrier offset = 15 MHz −147 dBc/Hz
Attenuator setting = 21 dB to 47 dB, carrier offset = 15 MHz −170 dBm/Hz
Harmonics −60 dBc

REFERENCE CHARACTERISTICS REFIN pin

Input Frequency With R/2 divider enabled 10 300 MHz
With R/2 divider disabled 10 165 MHz
Input Sensitivity AC-coupled 0.4 VREG V p-p
Input Capacitance 10 pF
Input Current ±100 µA

CHARGE PUMP

ICP Sink/Source Programmable

High Value With RSET = 4.7 kΩ 5 mA

Low Value 312.5 µA
Absolute Accuracy With RSET = 4.7 kΩ 4.0 %
RSET Value 4.7 kΩ
VCO Gain K

SYNTHESIZER SPECIFICATIONS

Frequency Resolution 1 Hz
Spurs Integer boundary < loop bandwidth −55 dBc
>10 MHz offset from carrier −85 dBc
Phase Noise1 Frequency = 950 MHz to 1575 MHz
100 Hz offset −80 dBc/Hz
1 kHz offset −88 dBc/Hz
10 kHz offset −93 dBc/Hz
100 kHz offset −107 dBc/Hz
1 MHz offset −133 dBc/Hz
>15 MHz offset −152 dBc/Hz
Integrated Phase Noise1 1 kHz to 8 MHz integration bandwidth 0.4

Frequency Settling1 Maximum frequency error = 100 Hz 170 s
Maximum Frequency Step for

No Autocalibration

Phase Detector Frequency 10 30 MHz

25 MHz/V

VCO

Frequency step with no autocalibration routine;
Register CR24, Bit 0 = 1

= −6 dBm per tone 23 dBm

OUT

100 kHz

°rms

Rev. A | Page 3 of 40

ADRF6750

Parameter Test Conditions/Comments Min Typ Max Unit

GAIN CONTROL

Gain Range 47 dB
Step Size 1 dB

Relative Step Accuracy Fixed frequency, adjacent steps
All attenuation steps ±0.3 dB
Over full frequency range, adjacent steps ±1.5 dB

Absolute Step Accuracy2 47 dB attenuation step −2.0 dB

Output Settling Time Any step; output power settled to ±0.2 dB 10 µs
OUTPUT DISABLE TXDIS pin

Off Isolation RF OUT, attenuator setting = 0 dB to 47 dB, TXDIS high −110 dBm

LO, Attenuator setting = 0 dB to 47 dB, TXDIS high −90 dBm

2 x LO, Attenuator setting = 0 dB to 47 dB, TXDIS high −50 dBm

Turn-On Settling Time TXDIS high to low (90% of envelope) 180 ns

Turn-Off Settling Time TXDIS low to high (to −55 dBm) 270 ns
MONITOR OUTPUT LOMONP, LOMONN pins

Nominal Output Power −24 dBm
BASEBAND INPUTS IBBP, IBBN, QBBP, QBBN pins

I and Q Input Bias Level 500 mV

1 dB Bandwidth 250 MHz
LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INH/IINL

Input Capacitance, CIN CS, TXDIS, SDI/SDA, CLK/SCL pins 10 pF
LOGIC OUTPUTS

Output High Voltage, VOH SDO, LDET pins; IOH = 500 A 2.8 V

Output Low Voltage, VOL SDO, LDET pins; IOL = 500 A 0.4 V
SDA (SDI/SDA); IOL = 3 mA 0.4 V
POWER SUPPLIES

Voltage Range VCC1, VCC2, VCC3, and VCC4 4.75 5 5.25 V

REGOUT, VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6 3.3 V

Supply Current

Operating Temperature −40 +85 °C

1

LBW = 50 kHz at LO = 1200 MHz; ICP = 2.5 mA.

2

All other attenuation steps have an absolute error of <±2.0 dB.

CS, TXDIS pins 1.4 V

INH

CS, TXDIS pins 0.6 V

INL

SDI/SDA, CLK/SCL pins 2.1 V

INH

SDI/SDA, CLK/SCL pins 1.1 V

INL

CS, TXDIS, SDI/SDA, CLK/SCL pins ±1 µA

VCC1, VCC2, VCC3, VCC4, VREG1, VREG2, VREG3, VREG4,
VREG5, VREG6, and REGOUT pins
REGOUT normally connected to VREG1, VREG2, VREG3,
VREG4, VREG5, and VREG6

VCC1, VCC2, VCC3, and VCC4 combined; REGOUT con-

310 340 mA

nected to VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6

Rev. A | Page 4 of 40

ADRF6750

TIMING CHARACTERISTICS

I2C Interface Timing

Table 2.

Parameter1 Symbol Limit Unit

SCL Clock Frequency f
SCL Pulse Width High t
SCL Pulse Width Low t
Start Condition Hold Time t
Start Condition Setup Time t
Data Setup Time t
Data Hold Time t
Stop Condition Setup Time t
Data Valid Time t
Data Valid Acknowledge Time t
Bus Free Time t

1

See Figure 2.

SDA

400 kHz max

SCL

600 ns min

HIGH

1300 ns min

LOW

600 ns min

HD;STA

600 ns min

SU;STA

100 ns min

SU;DAT

300 ns min

HD;DAT

600 ns min

SU;STO

900 ns max

VD;DAT

900 ns max

VD;ACK

1300 ns min

BUF

t

t

SU;DAT

VD;DAT AND

t

VD;ACK (ACK SIGNAL ONLY)

t

BUF

SCL

t

HD;STA

t

LOW

S SSP

START

CONDITION

1/f

SCL

t

HD;DAT

t

HIGH

Figure 2. I

2

C Port Timing Diagram

t

SU;STA

t

SU;STO

STOP

CONDITION

08201-003

Rev. A | Page 5 of 40

ADRF6750

SPI Interface Timing

Table 3.

Parameter1 Symbol Limit Unit

CLK Frequency f
CLK Pulse Width High t1 15 ns min
CLK Pulse Width Low t2 15 ns min
Start Condition Hold Time t3 5 ns min
Data Setup Time t4 10 ns min
Data Hold Time t5 5 ns min
Stop Condition Setup Time t6 5 ns min
SDO Access Time t7 15 ns min
CS to SDO High Impedance t8 25 ns max

1

See Figure 3.

t

3

CS

20 MHz max

CLK

t

1

CLK

SDI

t

t

2

t

t

5

4

SDO

t

7

6

t

8

08201-004

Figure 3. SPI Port Timing Diagram

Rev. A | Page 6 of 40

ADRF6750

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage VCC1, VCC2, VCC3, and VCC4 −0.3 V to +6 V
Supply Voltage VREG1, VREG2, VREG3, VREG4,

VREG5, and VREG6
IBBP, IBBN, QBBP, and QBBN 0 V to 2.5 V
Digital I/O −0.3 V to +4 V
Analog I/O (Other Than IBBP, IBBN, QBBP,

and QBBN)
TESTLO, TESTLO Difference
θJA (Exposed Paddle Soldered Down) 26°C/W
Maximum Junction Temperature 120°C
Storage Temperature Range −65°C to +150°C

−0.3 V to +4 V

−0.3 V to +4 V

1.5 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 7 of 40

ADRF6750

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D

D

D

VCC2

VCC2
56

1VCC4
2IBBP
3IBBN
4QBBN
5QBBP
6AGND
7RSET
8LF3

9CP
10LF2
11VCC1
12REGOUT
13VREG1
14VREG2

AGN

AGN

AGND

55

52

53

54

PIN 1
INDICATOR

ADRF6750

TOP VIEW

(Not to Scale)

AGND

AGND

50

51

TXDIS

AGND

AGN

RFOUT

AGND

LDET

MUXOUT

45

46

47

48

49

44

43

42 VCC3
41 VCC3
40 AGND
39 AGND
38 VTUNE
37 AGND
36 VREG6
35 CCOMP3
34 CCOMP2
33 CCOMP1
32 DGND
31 VREG5
30 CLK/SCL
29 SDI/SDA

16

15

VREG3

VREG4

NOTES

1. CONNECT EXPOSED PAD TO GROUND PLANE VIA
A LOW IMPEDANCE PATH.

21

17

19

20

22

23

24

25

26

27

18

D

IN

IN

AGND

AGN

AGND

REF

REF

TESTLO

28

S
C

SDO

AGND

MONP

TESTLO

LO

LOMONN

08201-005

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

11, 55, 56, 41, 42, 1 VCC1 to VCC4

Positive Power Supplies for I/Q Modulator. Apply a 5 V power supply to VCC1, which should be
decoupled with power supply decoupling capacitors. Connect VCC2, VCC3, and VCC4 to the same

5 V power supply.
12 REGOUT 3.3 V Output Supply. Drives VREG1, VREG2, VREG3, VREG4, VREG5, and VREG6.
13, 14, 15, 16, 31,

36
6, 19, 20, 21, 24, 37,

VREG1 to
VREG6

Positive Power Supplies for PLL Synthesizer, VCO, and Serial Port. Connect these pins to REGOUT

(3.3 V) and decouple them separately.

AGND Analog Ground. Connect to a low impedance ground plane.
39, 40, 46, 47, 49,
50, 51, 52, 53, 54

32 DGND Digital Ground. Connect to the same low impedance ground plane as the AGND pins.
2, 3 IBBP, IBBN

Differential In-Phase Baseband Inputs. These high impedance inputs must be dc-biased to approx­imately 500 mV dc and should be driven from a low impedance source. Nominal characterized ac
signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with a 500 mV
dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These inputs are
not self-biased and must be externally biased.

4, 5 QBBN, QBBP

Differential Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to
approximately 500 mV dc and should be driven from a low impedance source. Nominal charac­terized ac signal swing is 450 mV p-p on each pin. This results in a differential drive of 0.9 V p-p with
a 500 mV dc bias, resulting in a single sideband output power of approximately −1.6 dBm. These
inputs are not self-biased and must be externally biased.

33, 34, 35

CCOMP1 to

Internal Compensation Nodes. These pins must be decoupled to ground with a 100 nF capacitor.

CCOMP3
38 VTUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from
filtering the CP output voltage.

7 RSET

9 CP

Charge Pump Current Set. Connecting a resistor between this pin and ground sets the maximum
charge pump output current. The relationship between I

5.23

I

CPmax

where R

=

R

SET

= 4.7 kΩ and I

SET

CP max

= 5 mA.

and R

CP

Charge Pump Output. When enabled, this output provides ±I

is as follows:

SET

to the external loop filter, which, in

CP

turn, drives the internal VCO.

Rev. A | Page 8 of 40

ADRF6750

Pin No. Mnemonic Description

27 CS

29 SDI/SDA

30 CLK/SCL

28 SDO Serial Data Output for SPI Port. Register states can be read back on the SDO data output line.
17 REFIN Reference Input. This high impedance CMOS input should be ac-coupled.
18

REFIN

48 RFOUT

45 TXDIS

25, 26

LOMONP,
LOMONN

22, 23

TESTLO,
TESTLO

10, 8 LF2, LF3 No connect pins.
44 LDET

43 MUXOUT

Exposed Paddle EP Exposed Paddle. Connect to ground plane via a low impedance path.

Chip Select, CMOS Input. When CS is high, the data stored in the shift registers is loaded into one of
31 latches. In I2C mode, when CS is high, the slave address of the device is 0x60, and when CS is low,
the slave address is 0x40.

2

Serial Data Input for SPI Port/Serial Data Input/Output for I
impedance CMOS data input, and data is loaded in an 8-bit word. In I

C Port. In SPI mode, this pin is a high

2

C mode, this pin is a bidirec-

tional port.

2

Serial Clock Input for SPI/I

C Port. This serial clock is used to clock in the serial data to the registers.

This input is a high impedance CMOS input.

Reference Input Bar. This pin should be either grounded or ac-coupled to ground.
RF Output. Single-ended, 50 Ω, internally biased RF output. This pin must be ac-coupled to the

load. Nominal output power is −1.6 dBm for a single sideband baseband drive of 0.9 V p-p differ­ential on the I and Q inputs (attenuation = minimum).

Output Disable. This pin can be used to disable the RF output. Connect to high logic level to disable
the output. Connect to low logic level for normal operation.

Differential Monitor Outputs. These pins provide a replica of the internal local oscillator frequency
(1× LO) at four different power levels: −6 dBm, −12 dBm, −18 dBm, and −24 dBm, approximately.
These open-collector outputs must be terminated with external resistors to REGOUT. These outputs
can be disabled through serial port programming and should be tied to REGOUT if not used.

Differential Test Inputs. These inputs provide an option for an external 2× LO to drive the modulator.
This option can be selected by serial port programming. These inputs must be externally dc-biased and
should be grounded if not used.

Lock Detect. This output pin indicates the state of the PLL: a high level indicates a locked condition,
whereas a low level indicates a loss of lock condition.

Muxout. This output is a test output for diagnostic use only. It should be left unconnected by the
customer.

Rev. A | Page 9 of 40

ADRF6750

TYPICAL PERFORMANCE CHARACTERISTICS

VCC = 5 V, TA = 25°C, I/Q inputs = 0.9 V p-p differential sine waves in quadrature on a 500 mV dc bias, REFIN = 10 MHz, PFD = 20 MHz,
baseband frequency = 1 MHz, LOMONx is off, unless otherwise noted. A nominal condition is defined as 25°C, 5.00 V, and worst-case
frequency. A worst-case condition is defined as having the worst-case temperature, supply voltage, and frequency.

2

1

0

–1

–2

–3

OUTPUT POWER (dBm)

–4

–5

950

+25°C; 5.00 V
+85°C; 4.75 V
+85°C; 5.25 V

1050

-40°C; 4.75V

-40°C; 5.25V
0°C; 4.75V

1150

LO F REQUENCY (MHz)

1250

0°C; 5.25V
+70°C; 4.75V
+70°C; 5.25V

1350

1450

1550

1575

Figure 5. Output Power vs. LO Frequency, Supply, and Temperature

40

35

30

25

20

15

OCCURRENCE (%)

10

5

0

–3.0

–3.2

–2.8

–2.6

–2.4

–2.2

–2.0

–1.8

OUTPUT PO WER (dBm)

–1.6

–1.4

–1.2

–1.0

NOMINAL
WORST CASE

–0.8

–0.6

–0.4

–0.2

Figure 6. Output Power Distribution at Nominal and

Worst-Case Conditions

1

08201-105

0

08201-106

0

+25°C; 5.00V

1300

1350

+85°C; 4.75V
+85°C; 5.25V
–40°C; 4.75V
–40°C; 5.25V

1400

1450

1500

1550

1575

08201-108

SIDEBAND SUPPRESS ION (dBc)

–10

–20

–30

–40

–50

–60

950

1000

1100

1150

1050

LO FR EQUENCY (MHz)

1200

1250

Figure 8. Sideband Suppression vs. LO Frequency, Supply, and Temperature

35

NOMINAL

30

WORST CASE

25

20

15

OCCURRENCE (%)

10

5

0

–60.0

–62.5

–57.5

–55.0

–52.5

–50.0

SIDEBAND SUPPRESSION (dBc)

–47.5

–45.0

–42.5

–40.0

–37.5

–35.0

–32.5

08201-109

Figu re 9. Sideband Suppression Distribution at Nominal and

Worst-Case Conditions

–40

0

–1

–2

–3

OUTPUT PO WER (dBm)

–4

–5

500 750 1000 1250 1500 1750 2000

LO FREQ UE NCY (M Hz )

Figure 7. Output Power vs. LO Frequency for External VCO Mode

at Nominal Conditions

08201-107

Rev. A | Page 10 of 40

–45

–50

–55

–60

–65

–70

CARRIER FEEDTHROUGH (dBc)

–75

–80

950

1150

1050

LO FREQUENCY (MHz)

1250

1350

1450

Figure 10. LO Carrier Feedthrough vs. Attenuation, LO Frequency,

Supply, and Temperature

1550

1575

08201-110

ADRF6750

60

50

40

30

OCCURENCE (%)

20

10

0

NOMINAL
WORST-CASE

–75–80 –70 –65 –60 –55 –50 –45 –40 –35 –30

LO CARRIER FEEDTHROUGH (dBc)

08201-111

Figure 11. LO Carrier Feedthrough Distribution at Nominal and Worst-Case

Conditions and Attenuation Setting

–40

–50

–60

–70

–80

–90

ATTENUATION = 0dB
ATTENUATION = 12dB
ATTENUATION = 21dB
ATTENUATION = 33dB
ATTENUATION = 47dB

1150

LO FREQUE NCY (MHz)

1250

1350

1450

1550

1575

08201-112

2 × LO CARRIER FEEDTHROUGH (dBm)

–100

–110

–120

950

1050

Figure 12. 2 × LO Carrier Feedthrough vs. Attenuation, LO Frequency,

Supply, and Temperature

10

5

0

–5

–10

–15

OUTPUT PO WER (dBm)

–20

–25

0.1 1 10
DIFFERENTIAL INPUT VOLTAGE (V p-p)

COMPRESSION

1dB

POINT

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

IDEAL OUTPUT POWER – OUTPUT POWER (dBm)

Figure 13. Output P1dB Compression Point at Worst-Case LO Frequency

vs. Supply and Temperature

08201-113

50

45

40

35

30

25

20

OCCURENCE (%)

15

10

5

0

NOMINAL
WORST-CASE

7.06.8 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2
OUTPUT P1d B (dBm)

Figure 14. Output P1dB Compression Point Distribution at Nominal

and Worst-Case Conditions

10.5

10.0

9.5

9.0

8.5

8.0

7.5

OUTPUT P1dB (dBm)

7.0

6.5

6.0
950

1100

1000

1150

1050

LO FREQUENCY (MHz)

1200

1250

1300

1350

1400

1450

1500

1550

1575

Figure 15. Output P1dB Compression Point vs. LO Frequency at

Nominal Conditions

45

21.00

NOMINAL
WORST-CASE

21.25

21.50

21.75

22.00

22.25

OUTPUT I P 3 (dBm)

22.50

22.75

23.00

23.25

23.50

23.75

24.00

40

35

30

25

20

OCCURENCE (%)

15

10

5

0

Figure 16. Output IP3 Distribution at Nominal and Worst-Case

Conditions

08201-114

08201-116

08201-115

Rev. A | Page 11 of 40

ADRF6750

30

29

28

27

26

25

24

23

LO FREQ UE NCY (M Hz )

22

21

20

950

1100

1000

1150

1050

OUTPUT IP3 INTERCEPT POINT (dBm)

1200

1250

1300

1350

1400

1450

1500

1550

1575

Figure 17. Output IP3 vs. LO Frequency at Nominal Conditions

–60

–70

ATION (dBm)

LO OFF ISOL

–80

–90

–100

–110

–120

–130

–140

950

ATTENUATION = 0dB

ATTENUATION = 4 7dB

1100

1000

1050

1150

1200

1250

LO FREQ UENCY (MHz)

1300

1350

1400

ATTENUATION

= 21dB

1450

1500

1550

1575

Figure 18. LO Off Isolation vs. Attenuation, LO Frequency, Supply,

and Temperature

–20

–30

–40

–50

–60

ATION (dBm)

–70

–80

–90

2 × LO OFF ISOL

–100

–110

–120

950

1000

ATTENUATION = 0dB

ATTENUATION = 2 1dB

ATTENUATION = 47dB

1100

1150

1050

1200

LO FREQ UE NCY (M Hz )

1250

1300

1350

1400

1450

1500

1550

1575

Figure 19. 2 × LO Off Isolation vs. Attenuation, LO Frequency, Supply,

and Temperature

08201-119

08201-117

08201-118

–40

–50

–60

–70

–80

–90

OUTPUT P OWER (dBc)

–100

LOWER SECOND HARMONIC (fLO –2×fBB)

–110

–120

950

UPPER THIRD HARMONIC (fLO+3×fBB)

UPPER SECOND HARMONIC (fLO+ 2 × fBB)

LOWER THIRD HARMONIC (fLO–3×fBB)

1050

1150

1250

LO FREQUENCY (MHz)

1350

1450

1550

Figure 20. Second-Order and Third-Order Harmonic Distortion vs.

LO Frequency, Supply, and Temperature

100

90

80

70

60

50

40

OCCURENCE (%)

30

20

10

0
–180 –176 –172 –168 –164 –160 –156 –152 –148 –144 –140

(dBm/Hz) NOISE FLOOR AT 15MHz O FFSET FREQUENCY (dBc/Hz)

ATTENUATIO N =

47dB (dBm/Hz)

ATTENUATIO N =

21dB (dBm/Hz)

ATTENUATIO N =

ATTENUATION =

21dB (dBc/Hz)

0dB (dBc/Hz)

Figure 21. Noise Floor at 15 MHz Offset Frequency Distribution at

Worst-Case Conditions and Different Attenuation Settings

–140

–145

–150

–155

–160

NOISE FLOOR (dBm/ Hz)

–165

–170

–25 –20 –15 –10

OUTPUT POWER (dBm)

–5 0 5 10

Figure 22. Noise Floor at 0 dB Attenuation vs. Output Power

at Nominal Conditions

1575

08201-128

08201-121

08201-120

Rev. A | Page 12 of 40

ADRF6750

1

0

–1

–2

–3

–4

NORMALIZED OUTPUT POWER (dB)

–5

1 10M 100M 1G

I AND Q BASEBAND INPUT FREQUENCY (Hz)

Figure 23. Normalized I and Q Input Bandwidth

0

–5

–10

–15

S22 (dB)

–20

–25

ATTENUATION = 0 dB

ATTENUATION = 21dB AND 47dB

08201-141

0

–10

–20

–30

–40

–50

–60

RF OUTPUT ( dBm)

–70

–80

–90

LOWER AND UPPER

SECOND HARM ONICS

1150 1170 1190 1210 1230 1250

LOWER

SIDEBAND

FEEDTHROUGH

SUPPRESSED

LO FREQUENCY (MHz )

CARRIER

SIDEBAND

THIRD

HARMONIC

Figure 26. RF Output Spectral Plot over a 100 MHz Span

0

–10

–20

–30

–40

–50

POWER (dBm)

–60

–70

LOWER
SIDEBAND

HARMONIC

2 × LO

HARMONIC

3 × LO

4 × LO

HARMONIC

5 × LO

HARMONIC

HARMONIC

8 × LO

08201-123

–30

500 750 1000 1250 1500 1750 2000

OUTPUT F RE QUENCY (MHz)

Figure 24. Output Return Loss at Worst-Case Attenuation vs.

LO Frequency, Supply, and Temperature

0

10

20

30

40

50

60

RF OUTPUT ( d Bm)

70

80

90

1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205

LOWER

SIDEBAND

CARRIER

FEEDTHROUGH

HARMONIC

LO FREQUENCY (MHz)

SUPPRESSED

SIDEBAND

SECOND

HARMONIC

Figure 25. RF Output Spectral Plot over a 10 MHz Span

THIRD

–80

012345

08201-150

FREQUENCY ( M Hz )

678910

08201-124

Figure 27. RF Output Spectral Plot over a Wide Span

–60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

100 1k 10k 100k 1M 1

08201-122

OFFSET FREQUENCY (Hz )

0M 100M

08201-129

Figure 28. Phase Noise Performance vs. LO Frequency, Supply,

and Temperature

Rev. A | Page 13 of 40

ADRF6750

–60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

100 1k 10k 100k 1M

OFFSET FREQUENCY (Hz )

10M 100M

Figure 29. Phase Noise Performance Distribution at Worst-Case Conditions

–40

+25°C; 5.00 V

1350

+85°C; 4.75 V
+85°C; 5.25 V
–40°C; 4.75V
–40°C; 5.25V

1450

1550

1575

INTEGER BO UNDARY SPUR (dBc)

–45

–50

–55

–60

–65

–70

950

1150

1050

LO FREQUENCY (MHz)

1250

Figure 30. Integer Boundary Spur Performance vs. LO Frequency,

Supply, and Temperature

–60

–70

–80

–90

–100

–110

SPURS > 10MHz OFFSET FREQUENCY (dBc)

–120

900

08201-130

1000

PFD SPURS AT 20MHz OFFSET
REFERE NC E SPURS AT 10MHz OFF S ET

1100

1200

1300

LO FREQUENCY (MHz)

1400

1500

1600

1625

08201-127

Figure 32. Spurs > 10 MHz from Carrier vs. LO Frequency,

Supply, and Temperature

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

RMS JITTER (Degrees)

0.10

0.05

0

950

08201-125

1000

1100

1150

1050

LO FR EQUENCY (MHz)

1200

1250

1300

1350

1400

1450

1500

1550

1575

08201-131

Figure 33. Integrated Phase Noise vs. LO Frequency at

Nominal Conditions

80

70

60

50

40

30

OCCURENCE (%)

20

10

0

–85

–80 –75 –70 –65 –60 –55 –50 –45 –40

INTEGER BOUNDARY SPURS (dBc)

NOMINAL
WORST CASE

Figure 31. Integer Boundary Spur Distribution at Nominal

and Worst-Case Conditions

08201-126

Rev. A | Page 14 of 40

60

50

40

30

OCCURENCE (%)

20

10

0

NOMINAL
WORST CASE

0.3000.275 0.325 0.350 0.375 0.400 0.425 0.450 0.475 0.500
RMS JITT E R ( Degrees)

Figure 34. Integrated Phase Noise at Nominal and

Worst-Case Conditions

08201-137

ADRF6750

1G

100M

10M

1M

100k

10k

START OF ACQUISITION

1k

100

FREQUENCY ERROR (Hz)

10

1

0.1
–50 –25 0 25 50 75 100 125 150 175 200 225 250

ON CR0 WRITE

LDET

LDET

CR23[3] = 1

CR23[3] = 0

TIME (µs)

ACQUISITION

TO 100Hz

Figure 35. PLL Frequency Settling Time at Worst-Case Low Frequency

with Lock Detect Shown

0

–5

–10

–15

–20

–25

–30

–35

OUPTUT POWER (dBm)

–40

–45

–50

950

1100

1000

1050

LO FREQUENCY (MHz)

1250

1150

1200

1400

1300

1350

1550

1450

1575

1500

08201-133

Figure 36. Attenuator Gain vs. LO Frequency by Gain Code,

All Attenuator Code Steps

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

ATTENUATOR RELATIVE STEP ACCURACY (dB)

–1.0

950

1000

1100

1150

1050

LO FREQ UE NCY (M Hz )

1200

1250

1300

1350

1400

1450

1500

1550

1575

Figure 37. Attenuator Relative Step Accuracy over all Attenuation Steps

vs. LO Frequency, Nominal Conditions

08201-132

08201-134

50

45

40

35

30

25

20

OCCURENCE (%)

15

10

5

0

–0.8–1.0 –0.6 –0.4 –0.2 0

ATTENUATO R RELATIVE STEP ACCURACY (dB)

NOMINAL
WORST CASE

0.2 0.4 0.6 0.8 1.0

08201-135

Figure 38. Attenuator Relative Step Accuracy Distribution at Nominal

and Worst-Case Conditions

50

0.25

0.50

NOMINAL
WORST CASE

0.75

1.00

1.25

1.50

1.75

2.00

2.25

08201-140

45

40

35

30

25

20

OCCURENCE (%)

15

10

5

0

–2.00

–2.25

–1.75

–1.50

–1.25

–1.00

ATTENUATO R RELATIVE STEP ACCURACY ACROSS

FULL OUT P UT FREQUENCY RANG E ( dB)

–0.75

0

–0.50

–0.25

Figure 39. Attenuator Relative Step Accuracy Across Full Output

Frequency Range Distribution at Nominal and Worst-Case Conditions

0.5

0.3

0.1

–0.1

–0.3

–0.5

–0.7

–0.9

–1.1

–1.3

ATTENUATOR RELATIVE STEP ACCURACY (d B)

–1.5

500

600

800

700

900

1100

1000

1200

1300

1400

1500

1600

1700

1800

1900

2000

LO FREQUENCY (MHz)

Figure 40. Attenuator Relative Step Accuracy over all Attenuation Steps

vs. LO Frequency for External VCO Mode, Nominal Conditions

08201-136

Rev. A | Page 15 of 40

ADRF6750

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

ATTENUATOR ABSOLUTE S T EP ACCURACY (dB)

–3.0

950

1000

1100

1150

1050

LO FREQ UE NCY (MHz)

1200

1250

1300

1350

1400

1450

1500

1550

1575

08201-139

Figure 41. Attenuator Absolute Step Accuracy over all Attenuation Steps

vs. LO Frequency, Nominal Conditions

1.0

0.8

0.6

0.4

0.2

0

–0.2

ATNESS IN ANY 40MHz (dB)

–0.4

–0.6

GAIN FL

–0.8

1.0

950

1000

1100

1150

1050

LO FREQ UE NCY (MHz)

1200

1250

1300

1350

1400

1450

1500

1550

1575

Figure 44. Gain Flatness in any 40 MHz for all Attenuation Steps vs.

LO Frequency at Nominal Conditions

08201-149

70

60

50

40

30

OCCURENCE (%)

20

10

0

–3.2

–3.4

–3.0

–2.8

–2.6

–2.4

–2.2

ATTENUATO R ABSOLUTE ST E P ACCURACY ( d B)

–2.0

–1.8

NOMINAL
WORST CASE

–1.6

–1.4

–1.2

–1.0

–0.8

–0.6

–0.4

08201-138

Figure 42. Attenuator Absolute Step Accuracy Distribution at Nominal

and Worst-Case Conditions

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

ATTENUATORABSOLUTE STEP ACCURACY (dB)

–2.5

500

600

700

800

900

1100

1000

1200

1300

1400

1500

1600

1700

1800

1900

LO FREQUENCY (MHz)

2000

08201-142

Figure 43. Attenuator Absolute Step Accuracy over all Attenuation Steps

vs. LO Frequency for External VCO Mode, Nominal Conditions

5.0

4.5

4.0

3.5

3.0

2.5

2.0

SETTLING TIME (µs)

1.5

1.0

0.5

0

INCREASING STEP SIZE

1dB TO 6dB ATTENUATOR STEP SIZ E S

SETTLING TIMETO 0.2dB
SETTLING TIMETO 0.5dB

08201-143

Figure 45. Attenuator Settling Time to 0.2 dB and 0.5 dB for Small Steps

(1 dB to 6 dB) at Nominal Conditions

20

18

16

14

12

10

8

SETTLING TIME (µs)

6

4

2

0

INCREASING STEP SIZE

7dB TO 47dB ATTENUATOR STEP SI ZES

SETTLING TIMETO 0.2dB
SETTLING TIMETO 0.5dB

08201-144

Figure 46. Attenuator Settling Time to 0.2 dB and 0.5 dB for Large Steps

(7 dB to 47 dB) at Nominal Conditions

Rev. A | Page 16 of 40

ADRF6750

100

90

80

70

60

50

40

OCCURENCE (%)

30

20

10

0

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

NOMINAL SETTLING TIMETO 0.2dB
NOMINAL SETTLING TIMETO 0.5dB
WORST-CASE SET TLING T IME TO 0.2dB
WORST-CASE SET TLING T IME TO 0.5dB

ATTENUATOR SETTLING TIME (µ s)

Figure 47. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution

at Nominal and Worst-Case Conditions for Typical Small Step

100

90

80

70

60

50

40

OCCURENCE (%)

30

20

10

0

20 4 6 8 10 12 14 16 18 20

NOMINAL SETTLING T I M E TO 0.2dB
NOMINAL SETTLING T I M E TO 0.5dB
WORST-CAS E SETT LING TIME TO 0. 2 dB
WORST-CAS E SETT LING TIME TO 0. 5 dB

ATTENUATOR SETTLING TIME (µs )

Figure 48. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution

at Nominal and Worst-Case Conditions for Worst-Case Small Step

(36 dB to 42 dB)

100

90

80

70

60

50

40

OCCURENCE (%)

30

20

10

0

NOMINAL SETTLING TIME TO 0.2dB
NOMINAL SETTLING TIME TO 0.5dB
WORST-CASE SETTLING TIME TO 0.2dB
WORST-CASE SETTLING TIME TO 0.5dB

20 4 6 8 10 12 14 16 18 20

ATTENUATOR SETTLING TIME (µs)

08201-146

08201-145

08201-147

80

70

60

50

40

30

OCCURENCE (%)

20

10

0

30 6 9 12151821242730

NOMINAL SETTLING TIMETO 0.2dB
NOMINAL SETTLING TIMETO 0.5dB
WORST-CASE SET TLING T IME TO 0.2dB
WORST-CASE SET TLING T IME TO 0.5dB

ATTENUATOR SETTLING TIME (µs )

Figure 50. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at

Nominal and Worst-Case Conditions for Worst-Case Large Step

(47 dB to 0 dB)

0

–10

–20

–30

–40

–50

OUTPUT POWER (dBm)

–60

–70

0 0.51.01.52.02.53.03.54.04.55.0

TURN-ON = 180n s

TURN-OFF = 270ns

TXDIS

TXDIS SETTLING TIME (µs)

Figure 51. TXDIA Turn-On Settling Time at Worst-Case Supply

and Temperature

08201-148

08201-151

Figure 49. Attenuator Settling Time to 0.2 dB and 0.5 dB Distribution at

Nominal and Worst-Case Conditions for Typical Large Step (0 dB to 47 dB)

Rev. A | Page 17 of 40

ADRF6750

THEORY OF OPERATION

OVERVIEW

The ADRF6750 device can be divided into the following basic
building blocks:

• PLL synthesizer and VCO

• Quadrature modulator

• Attenuator

• Vo lt age r e gu l ator

2

• I

C/SPI interface

Each of these building blocks is described in detail in the
sections that follow.

PLL SYNTHESIZER AND VCO

Overview

The phase-locked loop (PLL) consists of a fractional-N frequency
synthesizer with a 25-bit fixed modulus, allowing a frequency
resolution of less than 1 Hz over the entire frequency range. It
also has an integrated voltage-controlled oscillator (VCO) with
a fundamental output frequency ranging from 1900 MHz to
3150 MHz. This allows the PLL to generate a stable frequency at
2× LO, which is then divided down to provide a local oscillator
(LO) frequency ranging from 950 MHz to 1575 MHz to the
quadrature modulator.

Reference Input Section

The reference input stage is shown in Figure 52. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
open. This ensures that there is no loading of the REFIN pin at
power-down.

POWER-DOWN

CONTROL

100kΩ

NC

SW1

NC

SW2

SW3

REFIN

NC

Figure 52. Reference Input Stage

Reference Input Path

The on-chip reference frequency doubler allows the input
reference signal to be doubled. This is useful for increasing the
PFD comparison frequency. Making the PFD frequency higher
improves the noise performance of the system. Doubling the
PFD frequency usually improves the in-band phase noise
performance by 3 dBc/Hz.

The 5-bit R-divider allows the input reference frequency
(REF

) to be divided down to produce the reference clock

IN

to the PFD. Division ratios from 1 to 32 are allowed.

An additional divide-by-2 function in the reference input path
allows for a greater division range.

BUFFER

TO
R-DIVIDER

08201-006

FROM

REFIN

PIN

×2

DOUBLER

Figure 53. Reference Input Path

5-BIT

R-DIVIDER

÷2

TO
PFD

The PFD frequency equation is

= f

f

PFD

× [(1 + D)/(R × (1 + T))] (2)

REFIN

where:
f

is the reference input frequency.

REFIN

D is the doubler bit.
R is the programmed divide ratio of the binary 5-bit
programmable reference divider (1 to 32).
T is the divide-by-2 bit (0 or 1).

RF Fractional-N Divider

The RF fractional-N divider allows a division ratio in the PLL
feedback path that can range from 23 to 4095. The relationship
between the fractional-N divider and the LO frequency is
described in the following section.

INT and FRAC Relationship

The integer (INT) and fractional (FRAC) values make it
possible to generate output frequencies that are spaced by
fractions of the phase frequency detector (PFD) frequency.
See the Example—Changing the LO Frequency section for
more information.

The LO frequency equation is

LO = f

× (INT + (FRAC/225)) (1)

PFD

where:

LO is the local oscillator frequency.
f

is the PFD frequency.

PFD

INT is the integer component of the required division factor

and is controlled by the CR6 and CR7 registers.
FRAC is the fractional component of the required division
factor and is controlled by the CR0 to CR3 registers.

25

TO

PFD

08201-007

FROM VCO

OUTPUT

DIVIDERS

RF N-DIVIDER N = INT + FRAC/2

N-COUNTER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

INT

REG

Figure 54. RF Fractional-N Divider

FRAC

VALUE

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the R-divider and the N-counter and
produces an output proportional to the phase and frequency differ­ence between them (see Figure 55 for a simplified schematic).
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, ensuring that there is no dead zone in
the PFD transfer function.

08201-008

Rev. A | Page 18 of 40

ADRF6750

HI

+IN

HI

–IN

U1

CLR1

CLR2

U2

UP

Q1D1

DELAY

DOWN

Q2D2

U3

CHARGE

PUMP

CP

08201-009

Figure 55. PFD Simplified Schematic

Lock Detect (LDET)

LDET (Pin 44) signals when the PLL has achieved lock to an
error frequency of less than 100 Hz. On a write to Register CR0,
a new PLL acquisition cycle starts, and the LDET signal goes
low. When lock has been achieved, this signal returns high.

Voltage-Controlled Oscillator (VCO)

The VCO core in the ADRF6750 consists of two separate VCOs,
each with 16 overlapping bands. Figure 56 shows an acquisition
plot demonstrating both the VCO overlap at roughly 1260 MHz
and the multiple overlapping bands within each VCO. The
choice of two 16-band VCOs allows a wide frequency range to
be covered without a large VCO sensitivity (K

) and resultant

VCO

poor phase noise and spurious performance. Note that the VCO
range is larger than the 2× LO frequency range of the part to
ensure that the device has enough margin to cover the full
frequency range over all conditions.

2.5

2.3

2.1

1.9

1.7

1.5

VTUNE (V)

1.3

1.1

0.9

0.7

0.5
800 900 1000 1100 1200 1300 1400 1500 1600 1700

LO FREQUENCY (MHz)

Figure 56. V

vs. LO Frequency

TUNE

08201-057

The correct VCO and band are chosen automatically by the
VCO and band select circuitry when Register CR0 is updated.
This is referred to as autocalibration.

The autocalibration time is set to 50 µs. During this time, the
VCO V

is disconnected from the output of the loop filter

TUNE

and is connected to an internal reference voltage. A typical
frequency acquisition is shown in Figure 57.

G

1

100M

10M

1M

AUTOCAL

TIME (µs)

100k

10k

FREQUENCY E RRO R (Hz)

1k

100

10

0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300

ACQUISIT ION TO 100Hz

TIME (µs)

08201-158

Figure 57. PLL Acquisition

After autocalibration, normal PLL action resumes and the
correct frequency is acquired to within a frequency error of
100 Hz in 170 s typically.

For a maximum cumulative step of 100 kHz, autocalibration
can be turned off by Register CR24, Bit 0. This enables cumu­lative PLL acquisitions of 100 kHz or less to occur without the
autocalibration procedure, which improves acquisition times
significantly (see Figure 58).

100k

10k

1k

ACQUISITION TO 100Hz

FREQUENCY E RRO R (Hz)

100

10

0 50 100 150 200

TIME (µs)

08201-159

Figure 58. PLL Acquisition Without Autocalibration for 100 kHz Step

The VCO displays a variation of K

VCO

as V

varies within

TUNE

the band and from band to band. Figure 59 shows how the
K

varies across the full LO frequency range. Also shown

VCO

is the average value for each of the frequency bands. Figure 59
is useful when calculating the loop filter bandwidth and
individual loop filter components.

Rev. A | Page 19 of 40

ADRF6750

40

35

30

25

20

15

10

VCO SENSITIVITY (MHz/V)

5

0

950

1150

1050

LO FREQ UE NCY (M Hz )

Figure 59. K

1250

vs. LO Frequency

VCO

1350

1450

1550

1575

08201-160

QUADRATURE MODULATOR

Overview

A basic block diagram of the ADRF6750 quadrature modulator
circuit is shown in Figure 60. The VCO generates a signal at the
2× LO frequency, which is then divided down to give a signal at the
LO frequency. This signal is then split into in-phase and quadrature
components to provide the LO signals that drive the mixers.

V-TO-I

P

IBB
IBBN

VCO

RFOUT TO

ATTENUATOR

BALUN

Figure 60. Block Diagram of the Quadrature Modulator

The I and Q baseband input signals are converted to currents by
the V-to-I stages, which then drive the two mixers. The outputs
of these mixers combine to feed the output balun, which provides a
single-ended output. This single-ended output is then fed to the
attenuator and, finally, to the external RFOUT signal pin.

Baseband Inputs

The baseband inputs, QBBP, QBBN, IBBP, and IBBN, must be
driven from a differential source. The nominal drive level of

0.9 V p-p differential (450 mV p-p on each pin) should be
biased to a common-mode level of 500 mV dc.

To set the dc bias level at the baseband inputs, refer to Figure 61.
The average output current on each of the AD9779 outputs is
10 mA. A current of 10 mA flowing through each of the 50 Ω
resistors to ground produces the desired dc bias of 500 mV at
each of the baseband inputs.

QUAD

PHASE

SPLITTER

÷2

V-TO-I

QBBP
QBBN

08201-012

CURRENT OUTPUT DAC

(EXAMPLE : AD9779 )

OUT1_P

OUT1_N

OUT2_N

OUT2_P

50Ω

50Ω

50Ω

50Ω

ADRF6750

IBBP

IBBN

QBBN

QBBP

08201-013

Figure 61. Establishing DC Bias Level on Baseband Inputs

The differential baseband inputs (QBBP, QBBN, IBBN, and
IBBP) consist of the bases of PNP transistors, which present
a high impedance of about 30 kΩ in parallel with roughly 2 pF
of capacitance. The impedance looks like 30 kΩ below 1 MHz
and starts to roll off at higher frequency. A 100 Ω differential
termination is recommended at the baseband inputs, and this
dominates the input impedance as seen by the input baseband
signal. This ensures that the input impedance, as seen by the
input circuit, remains flat across the baseband bandwidth. See
Figure 62 for a typical configuration.

CURRENT OUTPUT DAC

(EXAMPLE : AD977 9)

OUT1_P

OUT1_N

OUT2_N

OUT2_P

Figure 62. Typical Baseband Input Configuration

50Ω

50Ω

50Ω

50Ω

LOW­PASS

FILTER

LOW­PASS

FILTER

100Ω

100Ω

ADRF6750

IBBP

IBBN

QBBN

QBBP

08201-014

The swing of the AD9779 output currents ranges from 0 mA to
20 mA. The ac voltage swing is 1 V p-p single-ended or 2 V p-p
differential with the 50 Ω resistors in place. The 100 Ω differen­tial termination resistors at the baseband inputs have the effect
of limiting this swing without changing the dc bias condition of
500 mV. The low-pass filter is used to filter the DAC outputs
and remove images when driving a modulator.

Another consideration is that the baseband inputs actually
source a current of 240 A out of each of the four inputs. This
current must be taken into account when setting up the dc bias
of 500 mV. In the initial example based on Figure 61, an error
of 12 mV occurs due to the 240 A current flowing through
the 50 Ω resistor. Analog Devices, Inc., recommends that the
accuracy of the dc bias should be 500 mV ±25 mV. It is also
important that this 240 A current have a dc path to ground.

Rev. A | Page 20 of 40

ADRF6750

Optimization

The carrier feedthrough and the sideband suppression perfor­mance of the ADRF6750 can be improved over the numbers
specified in Tabl e 1 by using the following optimization
techniques.

Carrier Feedthrough Nulling

Carrier feedthrough results from dc offsets that occur between
the P and N inputs of each of the differential baseband inputs.
Normally these inputs are set to a dc bias of approximately 500 mV.

However, if a dc offset is introduced between the P and N inputs of
either or both I and Q inputs, the carrier feedthrough is affected
in either a positive or a negative fashion. Note that the dc bias
level remains at 500 mV (average P and N level). The I channel
offset is often held constant while the Q channel offset is varied
until a minimum carrier feedthrough level is obtained. Then,
while retaining the new Q channel offset, the I channel offset is
adjusted until a new minimum is reached. This is usually per­formed at a single frequency and, thus, is not optimized over
the complete frequency range. Multiple optimizations at different
frequencies must be performed to ensure optimum carrier feed­through across the full frequency range.

Sideband Suppression Nulling

Sideband suppression results from relative gain and relative
phase offsets between the I channel and Q channel and can
be optimized through adjustments to those two parameters.
Adjusting only one parameter improves the sideband suppression
only to a point. For optimum sideband suppression, an iterative
adjustment between phase and amplitude is required.

ATTENUATOR

The digital attenuator consists of six attenuation blocks: 1 dB,
2 dB, 4 dB, 8 dB, and two 16 dB blocks; each is separately
controlled. Each attenuation block consists of field effect
transistor (FET) switches and resistors that form either a pi­shaped or a T-shaped attenuator. By controlling the states of the
FET switches through the control lines, each attenuation block
can be set to the pass state (0 dB) or the attenuation state (n dB).
The various combinations of the six blocks provide the
attenuation states from 0 dB to 47 dB in 1 dB increments.

VOLTAGE REGULATOR

The voltage regulator is powered from a 5 V supply that is
provided by VCC1 (Pin 11) and produces a 3.3 V nominal
regulated output voltage, REGOUT, on Pin 12. This pin must
be connected (external to the IC) to the VREG1 through VREG6
package pins.

The regulator output (REGOUT) should be decoupled by
a parallel combination of 10 pF and 220 µF capacitors. The
220 µF capacitor, which is recommended for best performance,
decouples broadband noise, leading to better phase noise. Each
VREGx pin should have the following decoupling capacitors:
100 nF multilayer ceramic with an additional 10 pF in parallel,
both placed as close as possible to the DUT power supply pins.

Rev. A | Page 21 of 40

X7R or X5R capacitors are recommended. See the Evaluation
Board section for more information.

EXTERNAL VCO OPERATION

The ADRF6750 can be operated with an external VCO. This
can be useful if the user wants to improve the phase noise
performance or extend the frequency range. Note that the
external VCO needs to operate at a frequency of 2× LO.
To operate the ADRF6750 with an external VCO, follow
these steps:

1. Connect the charge pump output (Pin 9) to the loop filter

and onward to the external VCO input.
The K

of the external VCO needs to be taken into

VCO

account when calculating the loop bandwidth and loop
filter components. Note that a 50 kHz loop bandwidth is
recommended when using the internal VCO. This takes
into account the phase noise performance of the internal
VCO. It is possible for an external VCO to provide better
phase noise performance and a 50 kHz loop bandwidth
may not be optimal in that case. When selecting a loop
bandwidth, consider rms jitter, phase noise performance,
and acquisition time. ADISimPLL™ can be used to optim­ize the loop bandwidth with a variety of external VCOs.

2. Connect the output of the external VCO to the TESTLO

and

TESTLO

input pins.

It is likely that a low-pass filter will be needed to filter the
output of the external VCO. This is very important if the
external VCO has poor second harmonic performance.
Second harmonic performance directly impacts sideband
suppression performance. For example, −30 dBc second
harmonic performance leads to −30 dBc sideband suppres­sion. Both TESTLO and

TESTLO

need to be dc biased. A

dc bias of 1.7 V to 3.3 V is recommended. The REGOUT
output provides a 3.3 V output voltage.

3. Select external VCO operation by setting the following bits:

• Set Register CR27[3] = 1. This bit multiplexes the

TESTLO and

TESTLO

through to the quadrature

modulator.

• Set Register CR28[5] = 1. This bit powers down the

internal VCO and connects the external VCO to
the PLL.

4. Set the correct polarity for the PFD based on the slope of

the K

. The default is for positive polarity. This bit is

VCO

accessed by Register CR12[3].
When selecting an external VCO, at times it is difficult to select
one with an appropriate frequency range and K

. One solu-

VCO

tion may be the ADF4350, which can function as VCO only
with a range of 137.5 MHz to 4.4 GHz. Note that the ADF4350
requires an autocalibration time of 100 µs which directly
impacts acquisition time.

I2C INTERFACE

The ADRF6750 supports a 2-wire, I2C-compatible serial bus
that drives multiple peripherals. The serial data (SDA) and serial

ADRF6750

clock (SCL) inputs carry information between any devices that
are connected to the bus. Each slave device is recognized by
a unique address. The ADRF6750 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is set to 1. Bit 5 of the slave address is set by
the CS pin (Pin 27). Bits[4:0] of the slave address are set to all
0s. The slave address consists of the seven MSBs of an 8-bit
word. The LSB of the word sets either a read or a write oper­ation (see Figure 63). Logic 1 corresponds to a read operation,
whereas Logic 0 corresponds to a write operation.

To control the device on the bus, the following protocol must
be followed. The master initiates a data transfer by establishing
a start condition, defined by a high-to-low transition on SDA
while SCL remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices then withdraw from the bus
and maintain an idle condition. During the idle condition, the
device monitors the SDA and SCL lines waiting for the start
condition and the correct transmitted address. The R/W bit
determines the direction of the data. Logic 0 on the LSB of the

SLAVE ADDRESS[6:0]

1A500000X

MSB = 1 SET BY

PIN 27

(CS)

Figure 63. Slave Address Configuration

S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S)DATASUBADDR A(S) PDATA

S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE

Figure 64. I

S

S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOW L E DGE BY MASTER

Figure 65. I

START BIT

SLAVE ADDRESS SUBADDRESS DATA

2

C Write Data Transfer

SSLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD)A(S) A(S)SUBADDR A(S) DATA A(M) DATA PA(M)

2

C Read Data Transfer

first byte indicates that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte indicates that the
master reads information from the peripheral.

The ADRF6750 acts as a standard slave device on the bus. The
data on the SDA pin (Pin 29) is eight bits long, supporting the
7-bit addresses plus the R/W bit. The ADRF6750 has 34 subad­dresses to enable the user-accessible internal registers. Therefore,
it interprets the first byte as the device address and the second
byte as the starting subaddress. Autoincrement mode is supported,
which allows data to be read from or written to the starting sub­address and each subsequent address without manually addressing
the subsequent subaddress. A data transfer is always terminated
by a stop condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.

Stop and start conditions can be detected at any stage of the data
transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. If an invalid subaddress is issued by the
user, the ADRF6750 does not issue an acknowledge and returns
to the idle condition. In a no acknowledge condition, the SDA
line is not pulled low on the ninth pulse. See

Figure 64 and
Figure 65 for sample write and read data transfers, Figure 66 for
the timing protocol, and Figure 2 for a more detailed timing
diagram.

R/W
CTRL

0 = WR
1 = RD

08201-016

08201-017

A(M) = NO ACKNOWLEDGE BY MASTER

08201-018

STOP BIT

SDA

SCL

S

SLAVE

ADDR[4:0]

Figure 66. I

SUBADDR[6:1] DATA[6:1]

2

C Data Transfer Timing

D0D7A0A7A5A6

ACKACKWR ACK

P

08201-002

Rev. A | Page 22 of 40

ADRF6750

SPI INTERFACE

The ADRF6750 also supports the SPI protocol. The part powers

2

C mode but is not locked in this mode. To stay in I2C

up in I
mode, it is recommended that the user tie the CS line to either

3.3 V or GND, thus disabling SPI mode. It is not possible to lock

2

the I

C mode, but it is possible to select and lock the SPI mode.

To select and lock the SPI mode, three pulses must be sent to the
CS pin, as shown in Figure 67. When the SPI protocol is locked
in, it cannot be unlocked while the device is still powered up. To
reset the serial interface, the part must be powered down and
powered up again.

Serial Interface Selection

The CS pin controls selection of the I2C or SPI interface.
Figure 67 shows the selection process that is required to lock
the SPI mode. To communicate with the part using the SPI
protocol, three pulses must be sent to the CS pin. On the third
rising edge, the part selects and locks the SPI protocol. Consistent
with most SPI standards, the CS pin must be held low during all
SPI communication to the part and held high at all other times.

SPI Serial Interface Functionality

The SPI serial interface of the ADRF6750 consists of the CS,
SDI (SDI/SDA), CLK (CLK/SCL), and SDO pins. CS is used to
select the device when more than one device is connected to the
serial clock and data lines. CLK is used to clock data in and out
of the part. The SDI pin is used to write to the registers. The
SDO pin is a dedicated output for the read mode. The part
operates in slave mode and requires an externally applied serial
clock to the CLK pin. The serial interface is designed to allow
the part to be interfaced to systems that provide a serial clock
that is synchronized to the serial data.

Figure 68 shows an example of a write operation to the ADRF6750.
Data is clocked into the registers on the rising edge of CLK using
a 24-bit write command. The first eight bits represent the write
command 0xD4, the next eight bits are the register address, and
the final eight bits are the data to be written to the specific register.
Figure 69 shows an example of a read operation. In this example,
a shortened 16-bit write command is first used to select the
appropriate register for a read operation, the first eight bits
representing the write command 0xD4 and the final eight bits
representing the specific register. Then the CS line is pulsed low
for a second time to retrieve data from the selected register
using a 16-bit read command, the first eight bits representing
the read command 0xD5 and the final eight bits representing
the contents of the register being read. Figure 3 shows the
timing for both SPI read and SPI write operations.

CS

(STARTING

HIGH)

CS

(STARTING

LOW)

SPI LOCKED ON

THIRD RISING ED G E

SPI LOCKED ON

THIRD RISING ED G E

Figure 67. Selecting the SPI Protocol

CBA

SPI FRAMING
EDGE

CBA

SPI FRAMING
EDGE

08201-019

Rev. A | Page 23 of 40

ADRF6750

CS

• • •

CLK

SDI D7D6D5D4D3D2D1D0 D0

START

WRITE

COMMAND [0xD4]

(CONTINUED)

(CONTINUED)

(CONTINUED)

CS

CLK

SDI

•••

•••

•••

D7 D6 D5 D4 D3 D2 D1

REGISTER

ADDRESS

D7 D6 D5 D4 D3 D2 D1 D0

DATA
BYTE

STOP

Figure 68. SPI Byte Write Example

CS

• • •

• • •

• • •

08201-020

CLK

SDI

CS

CLK

SDI

SDO

D7 D6 D5 D4 D3 D2 D1 D0 D0

START

D7 D6 D5 D4 D3 D2 D1 D0

START

WRITE

COMMAND [0xD4]

READ

COMMAND [0xD5]

D7 D6 D5 D4 D3 D2 D1

REGISTER
ADDRESS

XXXXXXX

D7 D6 D5 D4 D3 D2 D1 D0

XXXXXXXX

DATA
BYTE

Figure 69. SPI Byte Read Example

• • •

• • •

X

STOP

08201-021

Rev. A | Page 24 of 40

ADRF6750

PROGRAM MODES

The ADRF6750 has 34 8-bit registers to allow program control
of a number of functions. Either an SPI or an I
can be used to program the register set. For details about the
interfaces and timing, see Figure 63 to Figure 69. The registers
are documented in Ta b le 6 to Table 2 4.

Several settings in the ADRF6750 are double-buffered. These
settings include the FRAC value, the INT value, the 5-bit
R-divider value, the reference frequency doubler, the R/2
divider, and the charge pump current setting. This means that
two events must occur before the part uses a new value for
any of the double-buffered settings. First, the new value is
latched into the device by writing to the appropriate register.
Next, a new write must be performed on Register CR0. When
Register CR0 is written, a new PLL acquisition takes place.

For example, updating the fractional value involves a write to
Register CR3, Register CR2, Register CR1, and Register CR0.
Register CR3 should be written to first, followed by Register CR2
and Register CR1 and, finally, Register CR0. The new acquisition
begins after the write to Register CR0. Double buffering ensures
that the bits written to do not take effect until after the write to
Register CR0.

12-Bit Integer Value

Register CR7 and Register CR6 program the integer value (INT)
of the feedback division factor. The INT value is a 12-bit number
whose MSBs are programmed through Register CR7, Bits[3:0].
The LSBs are programmed through Register CR6, Bits[7:0]. The
INT value is used in Equation 1 to set the LO frequency. Note
that these registers are double-buffered.

25-Bit Fractional Value

Register CR3 to Register CR0 program the fractional value
(FRAC) of the feedback division factor. The FRAC value is a
25-bit number whose MSB is programmed through Register CR3,
Bit 0. The LSB is programmed through Register CR0, Bit 0. The
FRAC value is used in Equation 1 to set the LO frequency. Note
that these registers are double-buffered.

Reference Input Path

The reference input path consists of a reference frequency doubler,
a 5-bit reference divider, and a divide-by-2 function (see Figure 53).
The doubler is programmed through Register CR10, Bit 5. The
5-bit divider is enabled by programming Register CR5, Bit 4,
and the division ratio is programmed through Register CR10,
Bits[4:0]. The R/2 divider is programmed through Register CR10,
Bit 6. Note that these registers are double-buffered.

When using a 10 MHz reference input frequency, enable the
doubler and disable the 5-bit divider and divide-by-2 to ensure
a PFD frequency of 20 MHz. As mentioned in the Reference
Input Path section, making the PFD frequency higher improves
the system noise performance.

2

C interface

Charge Pump Current

Register CR9, Bits[7:4], specify the charge pump current
setting. With an R

value of 4.7 kΩ, the maximum charge

SET

pump current is 5 mA. The following equation applies:

I

CPmax

= 23.5/R

SET

The charge pump current has 16 settings from 312.5 µA to 5 mA.
For the loop filter that is specified in the application solution, a
charge pump current of 2.5 mA (Register CR9[7:4] = 7) gives a
loop bandwidth of 50 kHz, which is the recommended loop
bandwidth setting.

Transmit Disable Control (TXDIS)

The transmit disable control (TXDIS) is used to disable the RF out­put. TXDIS is normally held low. When asserted (brought high), it
disables the RF output. Register CR14 is used to control which
circuit blocks are powered down when TXDIS is asserted. To meet
both the off isolation power specifications and the turn-on/
turn-off settling time specifications, a value of 0x1B should be
loaded into Register CR14. This effectively ensures that the
attenuator is always enabled when TXDIS is asserted, even if other
circuitry is disabled.

Power-Down/Power-Up Control Bits

The three programmable power-up and power-down control
bits are as follows:

• Register CR12, Bit 2. Master power control bit for the PLL,

including the VCO. This bit is normally set to a default
value of 0 to power up the PLL.

• Register CR27, Bit 2. Controls the LO monitor outputs,

LOMONP and LOMONN. The default is 0 when the monitor
outputs are powered down. Setting this bit to 1 powers up
the monitor outputs to one of −6 dBm, −12 dBm, −18 dBm,
or −24 dBm, as controlled by Register CR27, Bits[1:0].

• Register CR29, Bit 0. Controls the quadrature modulator

power. The default is 0, which powers down the modulator.
Write a 1 to this bit to power up the modulator.

Lock Detect (LDET)

Lock detect is enabled by setting Register CR23, Bit 4, to 1.
Register CR23, Bit 3 sets the number of up/down pulses
generated by the PFD before lock detect is declared. The default
is 3072 pulses, which is selected when Bit 3 is set to 0. A more
aggressive setting of 2048 is selected when Bit 3 is set to 1. This
improves the lock detect time by 50 µs. Note, however, that it
does not affect the acquisition time to 100 Hz. Register CR23,
Bit 2 should be set to 0 for best operation. This bit sets up the
PFD up/down pulses to a coarse or low precision setting.

Rev. A | Page 25 of 40

ADRF6750

VCO Autocalibration

The VCO uses an autocalibration technique to select the correct
VCO and band, as explained in the Volt ag e- C ont rol l ed O sc i ll ator
(VCO) section. Register CR24, Bit 0, controls whether the auto­calibration is enabled. For normal operation, autocalibration needs
to be enabled. However, if using cumulative frequency steps of
100 kHz or less, autocalibration can be disabled by setting this

bit to 1 and then a new acquisition is initiated by writing to
Register CR0.

Attenuator

The attenuator can be programmed from 0 dB to 47 dB in steps
of 1 dB. Control is through Register CR30, Bits[5:0].

Revision Readback

The revision of the silicon die can be read back via Register CR33.

Rev. A | Page 26 of 40

ADRF6750

REGISTER MAP

REGISTER MAP SUMMARY

Table 6. Register Map Summary

Register Address (Hex) Register Name Type Description

0x00 CR0 Read/write Fractional Word 4
0x01 CR1 Read/write Fractional Word 3
0x02 CR2 Read/write Fractional Word 2
0x03 CR3 Read/write Fractional Word 1
0x04 CR4 Read/write Reserved
0x05 CR5 Read/write 5-bit reference divider enable
0x06 CR6 Read/write Integer Word 2
0x07 CR7 Read/write Integer Word 1 and muxout control
0x08 CR8 Read/write Reserved
0x09 CR9 Read/write Charge pump current setting
0x0A CR10 Read/write Reference frequency control
0x0B CR11 Read/write Reserved
0x0C CR12 Read/write PLL power-up
0x0D CR13 Read/write Reserved
0x0E CR14 Read/write TXDIS control
0x0F CR15 Read/write Reserved
0x10 CR16 Read/write Reserved
0x11 CR17 Read/write Reserved
0x12 CR18 Read/write Reserved
0x13 CR19 Read/write Reserved
0x14 CR20 Read/write Reserved
0x15 CR21 Read/write Reserved
0x16 CR22 Read/write Reserved
0x17 CR23 Read/write Lock detector control
0x18 CR24 Read/write Autocalibration
0x19 CR25 Read/write Reserved
0x1A CR26 Read/write Reserved
0x1B CR27 Read/write LO monitor output and External VCO control
0x1C CR28 Read/write Internal VCO power-down
0x1D CR29 Read/write Modulator
0x1E CR30 Read/write Attenuator
0x1F CR31 Read only Reserved
0x20 CR32 Read only Reserved
0x21 CR33 Read only Revision code

Rev. A | Page 27 of 40

ADRF6750

REGISTER BIT DESCRIPTIONS

Table 7. Register CR0 (Address 0x00), Fractional Word 4

Bit Description1

7 Fractional Word F7
6 Fractional Word F6
5 Fractional Word F5
4 Fractional Word F4
3 Fractional Word F3
2 Fractional Word F2
1 Fractional Word F1
0 Fractional Word F0 (LSB)

1

Double-buffered. Loaded on the write to Register CR0.

Table 8. Register CR1 (Address 0x01), Fractional Word 3

Bit Description1

7 Fractional Word F15
6 Fractional Word F14
5 Fractional Word F13
4 Fractional Word F12
3 Fractional Word F11
2 Fractional Word F10
1 Fractional Word F9
0 Fractional Word F8

1

Double-buffered. Loaded on the write to Register CR0.

Table 9. Register CR2 (Address 0x02), Fractional Word 2

Bit Description1

7 Fractional Word F23
6 Fractional Word F22
5 Fractional Word F21
4 Fractional Word F20
3 Fractional Word F19
2 Fractional Word F18
1 Fractional Word F17
0 Fractional Word F16

1

Double-buffered. Loaded on the write to Register CR0.

Table 10. Register CR3 (Address 0x03), Fractional Word 1

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Fractional Word F24 (MSB)1

1

Double-buffered. Loaded on the write to Register CR0.

Table 11. Register CR5 (Address 0x05), 5-Bit Reference
Divider Enable

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 5-bit R-divider enable1
0 = disable 5-bit R-divider (default)
1 = enable 5-bit R-divider
3 Reserved
2 Reserved
1 Reserved
0 Reserved

1

Double-buffered. Loaded on the write to Register CR0.

Table 12. Register CR6 (Address 0x06), Integer Word 2

Bit Description1

7 Integer Word N7
6 Integer Word N6
5 Integer Word N5
4 Integer Word N4
3 Integer Word N3
2 Integer Word N2
1 Integer Word N1
0 Integer Word N0

1

Double-buffered. Loaded on the write to Register CR0.

Table 13. Register CR7 (Address 0x07), Integer Word 1 and
Muxout Control

Bit Description

[7:4] Muxout control
0000 = tristate
0001 = logic high
0010 = logic low
1101 = RCLK/2
1110 = NCLK/2
3 Integer Word N111
2 Integer Word N101
1 Integer Word N91
0 Integer Word N81

1

Double-buffered. Loaded on the write to Register CR0.

Rev. A | Page 28 of 40

ADRF6750

Table 14. Register CR9 (Address 0x09), Charge Pump
Current Setting

Bit Description

[7:4] Charge pump current1
0000 = 0.31 mA (default)
0001 = 0.63 mA
0010 = 0.94 mA
0011 = 1.25 mA
0100 = 1.57 mA
0101 = 1.88 mA
0110 = 2.19 mA
0111 = 2.50 mA
1000 = 2.81 mA
1001 = 3.13 mA
1010 = 3.44 mA
1011 = 3.75 mA
1100 = 4.06 mA
1101 = 4.38 mA
1110 = 4.69 mA
1111 = 5.00 mA
3 Reserved
2 Reserved
1 Reserved
0 Reserved

1

Double-buffered. Loaded on the write to Register CR0.

Table 15. Register CR10 (Address 0x0A), Reference
Frequency Control

Bit Description

7 Reserved1
6 R/2 divider enable1
0 = bypass R/2 divider (default)
1 = enable R/2 divider
5 R-doubler enable1
0 = disable doubler (default)
1 = enable doubler
[4:0] 5-bit R-divider setting1
00000 = divide by 32 (default)
00001 = divide by 1
00010 = divide by 2
…
11110 = divide by 30
11111 = divide by 31

1

Double-buffered. Loaded on the write to Register CR0.

Table 16. Register CR12 (Address 0x0C), PLL Power-Up

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Power down PLL
0 = power up PLL (default)
1 = power down PLL
1 Reserved
0 Reserved

Table 17. Register CR14 (Address 0x0E), TXDIS Control

Bit Description

7 Reserved
6 Reserved
5 TxDis_attenuator
0 = attenuator always enabled (default)
1 = disable attenuator when TXDIS = 1
4 TxDis_LOBuf
0 = LOBuf always enabled (default)
1 = disable LOBuf when TXDIS = 1
3 TxDis_QuadDiv
0 = QuadDiv always enabled (default)
1 = disable QuadDiv when TXDIS = 1
2 Reserved
1 TxDis_LOX2
0 = LOX2 always enabled (default)
1 = Disable LOX2 when TXDIS = 1
0 TxDis_RFMON
0 = RFMON always enabled (default)
1 = Disable RFMON when TXDIS = 1

Table 18. Register CR23 (Address 0x17), Lock Detector Control

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 Lock detector enable
0 = lock detector disabled (default)
1 = lock detector enabled
3 Lock detector up/down count
0 = 3072 up/down pulses
1 = 2048 up/down pulses
2 Lock detector precision
0 = low, coarse (16 ns)
1 = high, fine (6 ns)
1 Reserved
0 Reserved

Rev. A | Page 29 of 40

ADRF6750

Table 19. Register CR24 (Address 0x18), Autocalibration

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Disable autocalibration
0 = enable autocalibration (default)
1 = disable autocalibration

Table 20. Register CR27 (Address 0x1B), LO Monitor Output
and External VCO Control

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 External VCO control
0 = internal VCO selected
1 = external VCO selected
2 Power up LO monitor output
0 = power down (default)
1 = power up
[1:0] Monitor output power into 50 Ω
00 = −24 dBm (default)
01 = −18 dBm
10 = −12 dBm
11 = −6 dBm

Table 21. Register CR28 (Address 0x1C), Internal VCO
Power-Down

Bit Description

7 Reserved
6 Reserved
5 Internal VCO power-down
0 = power up (default)
1 = power down
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved

Table 22. Register CR29 (Address 0x1D), Modulator

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Power up modulator
0 = power down (default)
1 = power up

Table 23. Register CR30 (Address 0x1E), Attenuator

Bit Description

7 Reserved
6 Reserved
[5:0] Attenuator A5 to Attenuator A0
000000 = 0 dB
000001 = 1 dB
000010 = 2 dB
…
011111 = 31 dB
110000 = 32 dB
110001 = 33 dB
…
111101 = 45 dB
111110 = 46 dB
111111 = 47 dB

Table 24. Register CR33 (Address 0x21), Revision Code1

Bit Description

7 Revision code
6 Revision code
5 Revision code
4 Revision code
3 Revision code
2 Revision code
1 Revision code
0 Revision code

1

Read-only register.

Rev. A | Page 30 of 40

ADRF6750

SUGGESTED POWER-UP SEQUENCE

INITIAL REGISTER WRITE SEQUENCE

After applying power to the part, perform the initial register write
sequence that follows. Note that Register CR33, Register CR32,
and Register CR31 are read-only registers. Also note that all writ­able registers should be written to on power-up. Refer to the
Register Map section for more details on all registers.

1. Write Register CR30: 0x00. Set attenuator to 0 dB gain.

2. Write Register CR29: 0x00. Modulator is powered down.

The modulator is powered down by default to ensure that
no spurious signals can occur on the RF output when the
PLL is carrying out its first acquisition. The modulator
should be powered up only when the PLL is locked.

3. Write Register CR28: 0x01. Power up the internal VCO.

Write 0x21 if using an external VCO.

4. Write Register CR27: 0x00. Power down the LO monitor

and select the internal VCO. Write 0x08 to select an
external VCO.

5. Write Register CR26: 0x00. Reserved register.

6. Write Register CR25: 0x32. Reserved register.

7. Write Register CR24: 0x18. Enable autocalibration.

8. Write Register CR23: 0x70. Enable lock detector and

choose the recommended lock detect timing.

9. Write Register CR22: 0x00. Reserved register.

10. Write Register CR21: 0x00. Reserved register.

11. Write Register CR20: 0x00. Reserved register.

12. Write Register CR19: 0x00. Reserved register.

13. Write Register CR18: 0x00. Reserved register.

14. Write Register CR17: 0x00. Reserved register.

15. Write Register CR16: 0x00. Reserved register.

16. Write Register CR15: 0x00. Reserved register.

17. Write Register CR14: 0x1B. The attenuator is always

enabled, even when TXDIS is asserted.

18. Write Register CR13: 0x18. Reserved register.

19. Write Register CR12: 0x08. PLL powered up.

20. Write Register CR11: 0x00. Reserved register.

21. Write Register CR10: 0x21. The reference frequency doubler

is enabled, and the 5-bit divider and R/2 divider are bypassed.

22. Write Register CR9: 0x70. With the recommended loop

filter component values and R
Figure 71, the charge pump current is set to 2.5 mA for
a loop bandwidth of 50 kHz.

23. Write Register CR8: 0x00. Reserved register.

24. Write Register CR7: 0x0X. Set according to Equation 1 in

the Theory of Operation section. Also sets the MUXOUT
pin to tristate.

= 4.7 kΩ, as shown in

SET

Rev. A | Page 31 of 40

25. Write Register CR6: 0xXX. Set according to Equation 1 in

the Theory of Operation section.

26. Write Register CR5: 0x00. Disable the 5-bit reference divider.

27. Write Register CR4: 0x01. Reserved register.

28. Write Register CR3: 0x0X. Set according to Equation 1 in

the Theory of Operation section.

29. Write Register CR2: 0xXX. Set according to Equation 1 in

the Theory of Operation section.

30. Write Register CR1: 0xXX. Set according to Equation 1 in

the Theory of Operation section.

31. Write Register CR0: 0xXX. Set according to Equation 1 in

the Theory of Operation section. Register CR0 must be the
last register written for all the double-buffered bit writes to
take effect.

32. Monitor the LDET output or wait 170 s to ensure that the

PLL is locked.

33. Write Register CR29: 0x01. Power up modulator. The write

to Register CR29 does not need to be followed by a write to
Register CR0 because this register is not double-buffered.

Example—Changing the LO Frequency

Following is an example of how to change the LO frequency
after the initialization sequence. Using an example in which
the PLL is locked to 1200 MHz, the following conditions apply:

• f

• Divide ratio N = 60, so INT = 60 decimal and FRAC = 0

The INT registers contain the following values:
Register CR7 = 0x00 and Register CR6 = 0x3C

The FRAC registers contain the following values:
Register CR3 = 0x00, Register CR2 = 0x00,
Register CR1 = 0x00, and Register CR0 = 0x00

To change the LO frequency to 1230 MHz, the divide ratio N
must be set to 61.5. Therefore, INT must be set to 61 decimal
and FRAC must be set to 16777216 by writing to the following
registers:

1. Set the INT registers as follows:

2. Set the FRAC registers as follows:

Note that Register CR0 should be the last write in this sequence.
Writing to Register CR0 causes all double-buffered registers to
be updated, including the INT and FRAC registers, and starts a
new PLL acquisition.

If the cumulative frequency step is 100 kHz or less, the user can
turn off autocalibration. This process involves an additional
write of 0x19 to Register CR24, resulting in a smoother
frequency step and shorter acquisition time.

= 20 MHz (assumed)

PFD

Register CR7 = 0x00, Register CR6 = 0x3D

Register CR3 = 0x01, Register CR2 = 0x00,
Register CR1 = 0x00, Register CR0 = 0x00

ADRF6750

EVALUATION BOARD

GENERAL DESCRIPTION

This board is designed to allow the user to evaluate the
performance of the ADRF6750. It contains the following:

• I/Q modulator with integrated fractional-N PLL and VCO

• SPI and I

2

C interface connectors

• DC biasing and filter circuitry for the baseband inputs

• Low-pass loop filter circuitry

• 10 MHz reference clock

• Circuitry to support differential signaling to the TESTLO

inputs, including dc biasing circuitry

• Circuitry to monitor the LOMON outputs

• SMA connectors for power supplies and the RF output

The evaluation board comes with associated software to allow
easy programming of the ADRF6750.

HARDWARE DESCRIPTION

For more information, refer to the circuit diagram in Figure 71.

Power Supplies

An external 5 V supply (DUT +5 V) drives both an on-chip

3.3 V regulator and the quadrature modulator.

The regulator feeds the VREG1 through VREG6 pins on the
chip with 3.3 V. These pins power the PLL circuitry.

The external reference clock generator can be driven by a 3 V
supply or by a 5 V supply. These supplies can be connected via
an SMA connector, VCO +V.

Recommended Decoupling for Supplies

The external 5 V supply is decoupled initially by a 10 µF capacitor
and then further by a parallel combination of 100 nF and 10 pF
capacitors that are placed as close to the DUT as possible for good
local decoupling. The regulator output should be decoupled by a
parallel combination of 10 pF and 220 µF capacitors. The 220 µF
capacitor decouples broadband noise, which leads to better phase
noise and is recommended for best performance. Case Size C
220 µF capacitors are used to minimize area. A parallel combi­nation of 100 nF and 10 pF capacitors should be placed on each
VREGx pin. Again, these capacitors are placed as close to the pins
as possible. The impedance of all these capacitors should be low
and constant across a broad frequency range. Surface-mount
multilayered ceramic chip (MLCC) Class II capacitors provide
very low ESL and ESR, which assist in decoupling supply noise
effectively. They also provide good temperature stability and good
aging characteristics. Capacitance also changes vs. applied bias
voltage. Larger case sizes have less capacitance change vs. applied
bias voltage and also lower ESR but higher ESL. The 0603 size
capacitors provide a good compromise. X5R and X7R capacitors
are examples of these types of capacitors and are recommended
for decoupling.

SPI and I2C Interface

The SPI interface connector is a 9-way, D-type connector that can
be connected to the printer port of a PC. Figure 70 shows the
PC cable diagram that must be used with the provided software.

2

There is also an option to use the I
receptacle connector. This is a standard I

C interface by using the I2C

2

C connector. Pull-up
resistors are required on the signal lines. The CS pin can be used
to set the slave address of the ADRF6750. CS high sets the slave
address to 0x60, and CS low sets the slave address to 0x40.

1

6

2

7

3

8

4

9

5

9-WAY

FEMALE

D-TYPE

1

CLK

DATA

Figure 70. SPI PC Cable Diagram

Rev. A | Page 32 of 40

2
3

LE

4
5
6

GND

7
8

9

10

11
12

13

25-WAY

MALE

D-TYPE

TO PC

PRINTER PORT

14
15

16
17

18

19
20

21
22
23
24
25

PC

08201-022

ADRF6750

Baseband Inputs

The pair of I and Q baseband inputs are served by SMA inputs
so that they can be driven directly from an external generator,
which can also provide the dc bias required. An option is
provided to supply this dc bias through Connector J1, as well.
There is also an option to filter the baseband inputs, although
filtering may not be required, depending on the quality of the
baseband source.

Loop Filter

A fourth-order loop filter is provided at the output of the charge
pump and is required to adequately filter noise from the Σ-
modulator used in the N-divider. With the charge pump current
set to a midscale value of 2.5 mA and using the on-chip VCO,
the loop bandwidth is approximately 60 kHz, and the phase
margin is 55°. C0G capacitors are recommended for use in the
loop filter because they have low dielectric absorption, which is
required for fast and accurate settling time. The use of non-C0G
capacitors may result in a long tail being introduced into the
settling time transient.

Reference Input

The reference input can be supplied by a 10 MHz Taitien clock
generator or by an external clock through the use of Connector J7.
The frequency range of the reference input is from 10 MHz to
20 MHz; if the lower frequency clock is used, the on-chip reference
frequency doubler should be used to set the PFD frequency to
20 MHz to optimize phase noise performance.

TESTLO Inputs

These pins are differential test inputs that allow a variety of
debug options. On this board, the capability is provided to drive
these pins with an external 2× LO signal that is then applied to
an Anaren balun to provide a differential input signal.

When driving the TESTLO pins, the PLL can be bypassed, and the
modulator can be driven directly by this external 2× LO signal.

These inputs also require a dc bias; the following two options
are provided:

• A dc bias point of 3.3 V through a series inductor path.

A resistor in parallel is provided to de-Q any resonance.

• A dc bias point, which can be varied from 0 V to 3.3 V

through a resistor divider network. Note that these resistors
should be large in value to ensure that the current drawn is
small and that the resistors have little effect on the input
resistance.

If these pins are not used, ground them by inserting 0 Ω resistors
in R47 and R54.

LOMON Outputs

These pins are differential LO monitor outputs that provide a
replica of the internal LO frequency at 1× LO. The single-ended
power in a 50 Ω load can be programmed to −24 dBm, −18 dBm,

−12 dBm, or −6 dBm. These open-collector outputs must be
terminated to 3.3 V. Because both outputs must be terminated
to 50 Ω, options are provided to terminate to 3.3 V using on­board 50 Ω resistors or by series inductors (or a ferrite bead),
in which case the 50 Ω termination is provided by the measuring
instrument. If not used, these outputs should be tied to REGOUT.

CCOMPx Pins

The CCOMPx pins are internal compensation nodes that must
be decoupled to ground with a 100 nF capacitor.

MUXOUT

MUXOUT is a test output that allows different internal nodes
to be monitored. It is a CMOS output stage that requires no
termination.

Lock Detect (LDET)

Lock detect is a CMOS output that indicates the state of the
PLL. A high level indicates a locked condition, and a low level
indicates a loss of lock condition.

TXDIS

This input disables the RF output. It can be driven from an exter­nal stimulus or simply connected high or low by Jumper J18.

RF Output (RFOUT)

RFOUT is the RF output of the ADRF6750. RFOUT MOD
should be grounded in the user application.

Rev. A | Page 33 of 40

ADRF6750

08201-072

Figure 71. Applications Circuit Schematic

Rev. A | Page 34 of 40

USER-DEFINED VALUE

ADRF6750

PCB ARTWORK

Component Placement

08201-073

Figure 72. Evaluation Board, Top Side Component Placement

Figure 73. Evaluation Board, Bottom Side Component Placement

Rev. A | Page 35 of 40

08201-074

ADRF6750

PCB Layer Information

08201-075

Figure 74. Evaluation Board, Top Side—Layer 1

Figure 75. Evaluation Board, Bottom Side—Layer 4

Rev. A | Page 36 of 40

08201-076

ADRF6750

Figure 76. Evaluation Board, Ground—Layer 2

08201-077

08201-078

Figure 77. Evaluation Board Power—Layer 3

Rev. A | Page 37 of 40

ADRF6750

BILL OF MATERIALS

Table 25. Bill of Materials

Qty Reference Designator Description Manufacturer Part Number

1 DUT ADRF6750 LFCSP, 56-lead 8 mm × 8 mm Analog Devices ADRF6750ACPZ
1 Y2 VCO, 10 MHz Jauch O 10.0-VX3Y-T1
1 SPI Connector, 9-pin, D-sub plug, SDEX9PNTD ITW McMurdo FEC 150750
1 CONN Connector, I2C, SEMCONN receptacle Molex 15830064
2 C1, C21 Capacitor, 10 µF, 25 V, tantalum, TAJ-C AVX FEC 197518
13

15

1 C20 Capacitor, 220 µF, 6.3 V, tantalum, Case Size C AVX FEC 197087
4 C30 to C33 Capacitor spacing, 0402 (do not install)
1 C26 Capacitor, 1 nF, 50 V, XR7, ceramic, 0603 Murata FEC 722170
1 C24 Capacitor, 47 nF, 50 V, Xr7, ceramic, 1206 Murata FEC 1740542
2 C23, C25 Capacitor, 680 pF, 50 V, NPO, ceramic, 0603 Murata FEC 430997
4 C38, C39 Capacitor, 1 nF, 50 V, C0G, ceramic, 0402 Murata FEC 8819556
4 C40, C44, C46, C57 Capacitor, 100 pF, 50 V, C0G, ceramic, 0402 Murata FEC 8819572
12

3 J18, J20, J21 Jumper, 3-pin + shunt Harwin

4 L1, L2 Inductor, 20 nH, 0402, LQW series Murata LQW15AN20N
4 L3, L4 Inductor, 10 µH, 0805, LQM series Murata LQM21FN1N100M
4 R2 to R5 Resistor spacing, 0603 (user-defined values)
5 R6 to R9, R36 Resistor, 0 Ω, 1/16 W, 1%, 0402 Vishay Draloric FEC 1158241
2 R10, R11 Resistor, 0402, spacing (do not install)
1 R13 Resistor, 4.7 kΩ, 1/10 W, 1%, 0603 Bourns CR0603-FX-472
2 R14, R39 Resistor, 1.2 kΩ, 1/10 W, 5%, 0603 Yageo FEC 9233393
2 R12, R16 Resistor, 270 Ω, 1/16 W, 1%, 0603 Multicomp FEC 9330917
1 R15 Resistor, 300 Ω, 1/16 W, 1%, 0603 Multicomp FEC 93330968
2 R17, R18 Resistor, 0603, spacing (do not install)
3 R35, R44, R45 Resistor, 51 Ω, 1/16 W, 5%, 0402 Bourns CR0402-JW-510
4 R48 to R51 Resistor, 330 Ω, 1/10 W, 5%, 0805 Bourns CR0805-JW-331
3 R59 to R61 Resistor, 100 Ω, 1/10 W, 5%, 0805 Bourns CR0805-JW-101

C2, C4, C6, C8, C10, C12, C14, C16,
C18, C19, C48, C53, C55

C3, C5, C7, C9, C11, C13, C15, C17,
C22, C47, C49 to C52, C54

J1 to J5, J7, J10 to J12, J14, J15,
TXDIS

Capacitor, 10 pF, 50 V, ceramic, C0G, 0402 Murata FEC 8819564

Capacitor, 100 nF, 25 V, X7R, ceramic, 0603 AVX FEC 317287

SMA end launch connector Johnson/Emerson 142-0701-851

FEC 148533 and
FEC 150411

Rev. A | Page 38 of 40

ADRF6750

OUTLINE DIMENSIONS

PAD

0.30

0.23

0.18
PIN 1
INDICATOR

56

1

4.95

4.80 SQ

4.65

PIN 1

INDICATOR

8.00

BSC SQ

TOP

VIEW

7.75

BSC SQ

0.60 MAX

43

42

0.60 MAX

EXPOSED

(BOTTOM VIEW)

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

0.20 REF

0.05 MAX

0.02 NOM

29

28

COPLANARITY

0.08

6.50
REF

14

15

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

0.30 MIN

041807-B

Figure 78. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm Body, Very Thin Quad

(CP-56-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADRF6750ACPZ-R7 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7" Tape and Reel CP-56-3
ADRF6750-EVALZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. A | Page 39 of 40

ADRF6750

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08201-0-4/10(0)

Rev. A | Page 40 of 40