ANALOG DEVICES ADRF6655 Service Manual

Broadband Up/Downconverting Mixer with

V

Integrated Fractional-N PLL and VCO

FEATURES

Broadband active mixer with integrated fractional-N PLL RF input frequency range: 100 MHz to 2500 MHz Internal LO frequency range: 1050 MHz to 2300 MHz Flexible IF output interface Input P1dB: 12 dBm Input IP3: 29 dBm Noise figure (SSB): 12 dB Voltage conversion gain: 6 dB Matched 200 Ω output impedance SPI serial interface for PLL programming 40-lead 6 mm × 6 mm LFCSP

GENERAL DESCRIPTION

The ADRF6655 is a high dynamic range active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 × f oscillator (LO) divider as well as to a programmable PLL divider.

is then applied to a local

LO

ADRF6655

The programmable divider is controlled by an Σ-Δ modulator (SDM). The modulus of the SDM can be programmed between 1 and 2047.

The broadband, active mixer employs a bias adjustment to allow for enhanced IP3 performance at the expense of increased supply current. The mixer provides an input IP3 exceeding 25 dBm with 12 dB single sideband NF under typical conditions. The IIP3 can be boosted to ~29 dBm with roughly 20 mA of additional supplied current. The mixer provides a typical voltage conversion gain of 6 dB with a 200 Ω differential IF output impedance. The IF output can be externally matched to support upconversion over a limited frequency range.

The ADRF6655 is fabricated using an advanced silicon-germanium BiCMOS process. It is packaged in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a

−40°C to +85°C temperature range.

FUNCTIONAL BLOCK DIAGRAM

CCLO

GNDGND

36

LON

37

38

LOP

11

GND

12

DATA

13

CLK

LE

GND

REFIN

GND

MUXOUT

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

14 15

6

7

8

INTERFACE

×2

÷2 ÷4

SPI

35

MUX

34

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

TEMP

SENSOR

VCC1

LOSEL

MODULUS

1

INTEGER

REG

LOSEL

N COUNTER

21 TO 123

–

PHASE

+

FREQUENCY

DETECTOR

3.3V LDO VCO LDO2.5V LDO

2

DECL1

PRESCALER

CHARGE PUMP 250µA, 500µA (DEFAUL T), 750µA, 1000µA

3

CP

BUFFER

4

GND

9 105

RSET NC

DECL2 VCC2

MUX

DIVIDER ÷2 OR ÷3

VCO

CORE

39

VTUNE

Figure 1.

40

DECL3

33

VCCLO

GND

NCNC

31

32

ADRF6655

19

181716

OUTP

OUTN

20

GND

30 29 28 27

26 25

24

23

22

21

GND IP3SET GND VCCMIX

INP INN

GND GND VCCV2I GND

8817-001

ADRF6655

REVISION HISTORY

2/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

ADRF6655

SPECIFICATIONS

VCC = 5 V; ambient temperature (TA) = 25°C; REFIN = 20 MHz, phase frequency detector (PFD) frequency = 20 MHz, IF output loaded into 4-to-1 transformer matched to a 50 Ω system, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

RF INPUT FREQUENCY RANGE 100 2500 MHz IF OUTPUT FREQUENCY RANGE

Can be matched externally for improved return loss at higher

frequencies (see the Output Matching and Biasing section) INTERNAL LO FREQUENCY RANGE Divide-by-3 mode Divide-by-2 mode

1

EXTERNAL LO FREQUENCY RANGE Divide-by-2 mode2 500 2300 MHz MIXER

Input Return Loss

Output Return Loss

INP, INN; relative to 50 Ω, from 350 MHz to 2200 MHz using

TC1-1-13M+ balun

OUTP, OUTN; relative to 50 Ω out to 200 MHz using TC4-1W

output transformer option

3

IF Output Impedance OUTP, OUTN 200 Ω Output Common Mode OUTP, OUTN; external pull-up balun or inductors required V Voltage Conversion Gain IF output loaded into 200 Ω differential load 6 dB Output Swing 2 V p-p LO-to-IF Output Leakage Can be improved using external filtering −40 dBm

DYNAMIC PERFORMANCE IP3Set = 3.2 V

Upconversion

340 MHz RF input, 1200 MHz IF output using 1540 MHz

LO (see Figure 56 for output matching network)

Gain Flatness

Over ±50 MHz bandwidth for 1200 MHz output center

frequency

Gain Temperature Coefficient Average values from −40°C to +85°C −10 Output P1dB 11 dBm

Second-Order Output Intercept (IIP2) −5 dBm each tone 60 dBm Third-Order Output Intercept (IIP3) −5 dBm each tone, IP3SET = 3.2 V 31 dBm

−5 dBm each tone, IP3SET = open 28 dBm Output Noise Spectral Density IP3SET = 3.2 V, RF input terminated with 50 Ω −160 dBm/Hz

IP3SET = 3.2 V, RF input = −5 dBm, f

= 380 MHz applied, measured noise at fIF = 915 MHz

f

RF

= 1315 MHz with

LO

Downconversion 1880 MHz RF input, 140 MHz IF output using 1740 MHz LO

Gain Flatness

Over ±50 MHz bandwidth for 1880 MHz input center

frequency

Gain Temperature Coefficient Average values from −40°C to +85°C −10 Input P1dB IP3SET = 3.2 V 14 dBm

IP3SET = open 12 dBm Second-Order Input Intercept (IIP2) −5 dBm each tone 50 dBm Third-Order Input Intercept (IIP3) −5 dBm each tone, IP3SET = 3.2 V 27 dBm

−5 dBm each tone, IP3SET = open 26 dBm SSB Noise Figure (NF) IP3SET = 3.2 V 14 dB IP3SET = open 12 dB SSB Noise Figure Under Blocking

Conditions

−5 dBm RF input blocker applied at 995 MHz, fLO = 1200 MHz,

noise measured at 5 MHz offset from IF output blocker

IP3SET = 3.2 V 20.75 dB IP3SET = open 20.25 dB IF/2 Spurious −5 dBm RF input power −65 dBc

LO OUTPUT LOP, LON

Output Level 1 × LO into a 50 Ω load, LO buffer enabled −7 dBm

LF 2200 MHz

1050 1530 MHz 1530 2300 MHz

12 dB

V

POS

0.25 dB p-p

mdB/°C

−155 dBm/Hz

0.25 dB p-p

mdB/°C

Rev. 0 | Page 3 of 44

ADRF6655

Parameter Test Conditions/Comments Min Typ Max Unit

SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1 × LO4

Fundamental VCO Sensitivity VCO tuning sensitivity before divide-by-2 or divide-by-3 75 MHz/V Spurs Measured at LO output

Reference/PFD Spurs f

f 2 × f 4 × f

Phase Noise PFD frequency = 20 MHz

LO Frequency = 1330 MHz

@ 10 kHz offset −85 dBc/Hz @ 100 kHz offset −114 dBc/Hz @ 1 MHz offset −138 dBc/Hz @ 10 MHz offset −154 dBc/Hz

Integrated Phase Noise 10 kHz to 40 MHz integration bandwidth 0.3 °rms LO Frequency = 1840 MHz

@ 10 kHz offset −83 dBc/Hz @ 100 kHz offset −111 dBc/Hz @ 1 MHz offset −136 dBc/Hz @ 10 MHz offset −152 dBc/Hz

Integrated Phase Noise 10 kHz to 40 MHz integration bandwidth 0.4 °rms

PFD Frequency 19.33 20 40 MHz

REFERENCE CHARACTERISTICS REFIN, MUXOUT

REFIN Input Frequency 10 20 160 MHz REFIN Input Capacitance 4 pF REFIN Input Current ±100 μA REFIN Input Sensitivity AC-coupled 0.25 1 3.3 V p-p MUXOUT Output Levels VOL (lock detect output selected) 0.25 V V

CHARGE PUMP CP

Pump Current

Output Compliance Range 1 2.8 V

LOGIC INPUTS CLK, DATA, LE

V

, Input High Voltage 1.4 3.3 V

INH

V

, Input Low Voltage 0 0.7 V

INL

I

, Input Current ±1 μA

INH/IINL

CIN, Input Capacitance 3 pF

POWER SUPPLIES VCC1, VCC2, VCCLO

Voltage Range 4.75 5 5.25 V Supply Current LO output buffer disabled

PLL only 115 mA Normal TX mode, IP3SET = 3.2 V, fLO ≤1530 MHz (divide-by-3) 310 mA Normal TX mode, IP3SET = 3.2 V, fLO > 1530 MHz (divide-by-2) 270 mA Normal RX mode, IP3SET = open, fLO ≤ 1530 MHz (divide-by-3) 285 mA Normal RX mode, IP3SET = open, fLO > 1530 MHz (divide-by-2) 245 mA

Power-down mode 15 mA

1

Internal LO path divider programmed via serial interface. See the section for additional information. LO Signal Chain

2

See the section. External LO Interface

3

Improved return loss can be achieved using external matching. See the section for more details. Circuit Description

4

Measured on standard evaluation board with 1.5 kHz loop filter (C13 = 47 nF, C14 = 0.1 μF, C15 = 4.7 μF, R9 = 270 Ω, R10 = 68 Ω).

/2 −95 dBc

PFD

−83 dBc

PFD

−85 dBc

PFD

−88 dBc

PFD

(lock detect output selected) 2.7 V

OH

Charge pump current adjustable using Register 4 and/or

(see Pin 5 description)

R

SET

4

500 μA

Rev. 0 | Page 4 of 44

ADRF6655

TIMING CHARACTERISTICS

Table 2. Serial Interface Timing, VCC = 5 V ± 5%

Parameter Limit Unit Test Conditions/Comments

t1 20 ns minimum LE setup time t2 10 ns minimum DATA to CLK setup time t3 10 ns minimum DATA to CLK hold time t4 25 ns minimum CLK high duration t5 25 ns minimum CLK low duration t6 10 ns minimum CLK to LE setup time t7 20 ns minimum LE pulse width

CLK

t

4

t

5

DATA

DB23 (MSB) DB22

LE

t

2

t

3

DB2 DB1

(CONTROL BIT C2)(CONTROL BIT C3)

DB0 (LSB)

(CONTROLBIT C1)

t

7

6

1

08817-002

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 44

ADRF6655

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltage, VCC 5.5 V Digital I/O CLK, DATA, LE −0.3 V to +3.6 V OUTP, OUTN VCC LOP, LON 16 dBm INN, INP 20 dBm DECL3 Using External Bias Option 3.5 V θJA (Exposed Paddle Soldered Down)1 35°C/W Maximum Junction Temperature 150°C Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C

1

Per JDEC standard JESD 51-2. For information on optimizing thermal

impedance, see the Evaluation Board Layout and Thermal Grounding section.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 6 of 44

ADRF6655

PIN CONFIGURATION AND FUNCTION DESPCRIPTIONS

ND

C

NC 33

G

N 32

31

VCO LDO

VCCLO

GND

LON

LOP

VTUNE

DECL3

34

35

36

37

38

39

40

1VCC1

2DECL1

3CP

4GND

5RSET

6REFIN

7GND

8MUXOUT

9DECL2

10VCC2

NC = NO CONNECT

3.3V LDO

ENABLE

2.5V LDO

PD +

CHARGE

PUMP

×2

÷2 OR ÷4

PFD

MUX

FRACTION

11

GND

12

DATA

THIRD-ORDER

MODULUS

SERIAL

PORT

13

CLK

VCO

BAND

AND

CURRENT

CAL/SET

PROGRAMMABLE

DIVIDER

SDM

INTEGER

15

14 LE

GND

ADRF6655

WIDEBAND

UP/DOWN

CONVERTER

6

VCO

6

CORE

16 NC

PRESCALER

17

18

UTN O

VCCLO

MUX

÷2 OR ÷3

19

OUTP

20

GND

30 GND

29 IP3SET

28 GND

27 VCCMIX

26 INP

25 INN

24 GND

23 GND

22 VCCV2I

21 GND

08817-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC1

Power Supply for Internal 3.3 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

2 DECL1

Decoupling Node for 3.3 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors

located close to the pin. 3 CP Charge Pump Output Pin. Connect this pin to V 4, 7, 11, 15,

GND Ground. Connect these pins to a low impedance ground plane. 20, 21, 23, 24, 28, 30, 31, 35, 36

Rev. 0 | Page 7 of 44

through the loop filter.

TUNE

ADRF6655

Pin No. Mnemonic Description

5 RSET

6 REFIN

8 MUXOUT

9 DECL2

10 VCC2

12 DATA Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits. 13 CLK

14 LE

16, 32, 33 NC No Connection. 17, 34 VCCLO

18,19 OUTN, OUTP Mixer IF Outputs. These pins should be pulled to VCC with RF chokes. 22 VCCV2I

25, 26 INN, INP Mixer RF Inputs. Differential RF Inputs. Internally matched to 50 Ω. This pin must be ac-coupled. 27 VCCMIX

29 IP3SET Connect Resistor to VCC to Adjust IP3. 37, 38 LON, LOP

39 VTUNE

40 DECL3

EPAD (EP) The exposed paddle should be soldered to a low impedance ground plane.

Charge Pump Current. The nominal charge pump current can be set to either 250 μA, 500 μA, 750 μA, or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current). In this mode, no external R

) can be externally tweaked according to

(I

NOMINAL

⎡

[]

RSET

where I

CP, BASE

=Ω

⎢ ⎣

is the base charge pump current in μA.

is required. If DB18 is set to 1, the four nominal charge pump currents

SET

4.217

I

×

250

⎤

,

BASECP

⎥ ⎦

8.37

−

For further details on the charge pump current,see the Register 4—Charge Pump, PFD, and Reference Path Control section.

Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. This pin must be ac-coupled.

Multiplexer Output. This output allows either a digital lock detect, a voltage proportional to temperature, or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by programming the appropriate bits in Register 4.

Decoupling Node for 2.5 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors located close to the pin.

Power Supply for Internal 2.5 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.

Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.

Power Supply for LO Path. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Power Supply for Voltage to Current Input Stage. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Power Supply for Mixer. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Local Oscillator Input/Output. The internally generated 1 × f LO generation is disabled, an external 2 × f

or 3 × fLO (depending on divider selection) can be applied

LO

is available on these pins. When internal

LO

to these pins. This pin must be ac-coupled. VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage

range on this pin is 1 V to 2.8 V. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin

and ground.

Rev. 0 | Page 8 of 44

ADRF6655

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = 3.2 V, unless otherwise noted.

DOWNCONVERSION

Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, unless otherwise noted.

5

LOW-SIDE LO

HIGH-SIDE L O

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

900 1100130015001700190021002300

INPUT FREQUENCY (MHz)

Figure 4. Conversion Gain vs. Input Frequency

20

IP3SET = 3.2V

IP3SET = OPEN

18

16

14

NOISE FI G URE (d B)

12

10

900 1100 1300 1500 1700 1900 2100

RF FREQUENC Y ( MHz)

Figure 5. SSB Noise Figure vs. RF Frequency

30

IP3SET = 3.2V IP3SET = OPEN

28

26

24

22

20

18

NOISE FI GURE (dB)

16

14

12

10

–50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0

CW BLOCKER LEVEL (dBm)

Figure 6. SSB Noise Figure vs. CW Blocker Level

+25°C –40°C +85°C

08817-086

08817-123

08817-104

32 31 30 29 28 27 26 25 24 23 22 21 20 19

INPUT IP3 (dBm)

18 17 16 15 14

IP3SET = 3 .2V

13

IP3SET = OPEN

12

900 1100 1300 1500 1700 1900 2100

INPUT FREQ UE NC Y ( MHz )

Figure 7. Input IP3 vs. Input Frequency

100

LOW-SIDE LO

95

HIGH-SIDE LO

90 85 80 75 70 65 60 55 50

INPUT IP2 (dBm)

45 40 35 30 25 20

900 1100 1300 1500 1700 1900 2100 2300 2500

INPUT FREQUENCY (MHz)

Figure 8. Input IP2 vs. Input Frequency

20

IP3SET = 3 .2V

19

IP3SET = OPEN

18 17 16 15 14 13 12 11 10

9 8 7

INPUT P1 dB (dBm)

6 5 4 3 2 1 0

900 1100 1300 1500 1700 1900 2100

INPUT FREQUENCY (MHz)

Figure 9. Input P1dB vs. Input Frequency

+25°C –40°C +85°C

08817-087

8817-088

08817-089

Rev. 0 | Page 9 of 44

ADRF6655

–

0

–5

–10

–15

–20

–25

S11 (dB)

–30

–35

–40

–45

0 500 1000 1500 2000 2500 3000

FREQUENCY ( M Hz )

Figure 10. RF Port Input Return Loss (S11) vs.

Frequency Measured through TC1-1-13M+

300 270

240

210

180

150

120

90

OUTPUT RESISTANCE (Ω)

60

30

0

50 100 150 200 250 300 350 400 4500500

FREQUENCY ( MHz)

Figure 11. IF Port Output Impedance vs. Frequency

40 –45 –50 –55 –60 –65 –70 –75 –80 –85

LO-TO-RF I NP UT LEAKAGE (dBm)

–90 –95

–100

1050 1250 1450 1650 1850 2050 2250

LO FREQUENCY (MHz)

Figure 12. LO-to-RF Input Port Leakage vs. LO Frequency

+25°C –40°C +85°C

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2 0

08817-122

OUTPUT CAPACITANCE (pF)

08817-124

08817-090

400 380 360 340 320 300 280 260 240 220 200 180 160 140 120

SUPPLY CURRENT ( mA)

100

80 60 40

IP3SET = 3.2 V

20

IP3SET = OPEN

0

1050 1250 1450 1650 1850 2050 2250

LO FREQ UENCY ( M Hz )

Figure 13. Supply Current vs. LO Frequency

0 –1 –2 –3 –4 –5 –6 –7 –8 –9

–10 –11 –12 –13 –14 –15

LO OUTP UT POWER (dBm)

–16 –17 –18 –19 –20

1050 1250 1450 1650 1850 2050 2250

LO FREQ UE NCY (M Hz )

Figure 14. LO Port Output Power vs. LO Frequency

20

–25 –30 –35 –40 –45 –50 –55 –60 –65 –70

LO-TO-IF OUTPUT LE AKAG E (dBm)

–75 –80

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

LO FREQUE NCY (MHz)

Figure 15. LO-to-IF Output Port Leakage vs. LO Frequency

+25°C –40°C +85°C

08817-091

08817-092

08817-014

Rev. 0 | Page 10 of 44

ADRF6655

–

UPCONVERSION

Measured using typical upconversion circuit schematic with high-side LO and 340 MHz RF input, unless otherwise noted.

5

4

3

2

1

0

GAIN (dB)

–1

–2

–3

–4

–5

710 810 910 1010 1110 1210 1310 1410 1510 1610

OUTPUT FREQUE NC Y ( M H z )

Figure 16. Conversion Gain vs. Output Frequency

0

–10

–20

–30

–40

–50

–60

SPURIOUS RESPONSE (dBc)

–70

RF

f

–80

– 2 ×

LO

–90

f

–100

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

LO FREQ UENCY ( M Hz )

+25°C –40°C +85°C

8817-093

08817-016

35

IP3SET = 3 .2V

34

IP3SET = OPEN

33 32 31 30 29 28 27 26 25

OUTPUT IP3 (dBm)

24 23 22 21 20

710 810 910 1010 1110 1210 1310 1410 1510 1610

OUTPUT FREQUENCY (M H z)

Figure 19. Output IP3 vs. Output Frequency

20 19

IP3SET = 3.2V

18

IP3SET = OPEN 17 16 15 14 13 12 11 10

9 8 7

OUTPUT P1dB (dBm)

6 5 4 3 2 1 0

710 810 910 1010 1110 1210 1310 1410 1510 1610

OUTPUT F RE QUENCY (MHz)

+25°C –40°C +85°C

8817-094

08817-095

Figure 17. f

− 2 × fRF Spurious Response vs.

LO

LO Frequency (Relative to IF Output Power)

0

–10

–20

–30

–40

–50

–60

LO-TO-IF OUTPUT LEAKAGE (dBm)

–70

–80

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050

LO FREQ UENCY (MHz)

Figure 18. LO-to-IF Output Leakage vs. Frequency

+25°C –40°C +85°C

08817-105

Rev. 0 | Page 11 of 44

Figure 20. Output P1dB vs. Output Frequency

100

–110

–120

–130

–140

–150

–160

NOISE SPECTRAL DENSITY ( dBm/Hz)

–170

710 810 910 1010 1110 1210 1310 1410 1510 1610

OUTPUT F RE QUENCY (MHz)

Figure 21. Output Noise Spectral Density vs. Output Frequency

8817-121

ADRF6655

A

PLL CHARACTERISTIC

Measured using typical downconversion circuit schematic with high-side LO and 140 MHz IF output, loop filter = 1.5 kHz, unless otherwise noted.

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

–100 –110 –120

PHASE NOISE ( dBc/Hz)

–130 –140 –150 –160 –170

1k 10k 100k 1M 10M 100M

LO = 2275MHz

LO = 1100MHz

OFFSET FREQUENCY ( kHz)

+25°C –10°C –40°C +70°C +85°C

08817-021

Figure 22. Typical Fractional-N Phase Noise Plot

1.0

0.9

0.8

0.7

0.6

0.5

0.4

TED PHASE NOI S E (° C rms)

0.3

0.2

INTEGR

0.1

0

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

LO FREQ UENCY (MHz)

+25°C –10°C –40°C +70°C +85°C

08817-022

Figure 23.10 kHz to 40 MHz Integrated Phase Noise vs. LO Frequency

2500

2000

1500

1000

500

2.290G

TION FROM 2.29GHz (Hz)

–500

–1000

–1500

–2000

FREQUENCY DEVI

–2500

025

1

10

TIME (ms)

1: 10ms 2.289999883GHz

08817-120

Figure 24. Lock Time for 10 MHz Step with 1.5 kHz Loop Filter

0

1 × PFD OFFSET 2 × PFD OFFSET

–10

4 × PFD OFFSET

–20 –30 –40 –50 –60 –70 –80 –90

LO REFERENCE P F D SP URS (d Bc)

–100 –110

1050 1250 1450 1650 1850 2050 2250

LO FREQ UE NCY (M Hz )

Figure 25. LO Reference/PFD Spurs vs. LO Frequency

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

VTUNE (V)

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

HIGH-SIDE LO LOW-SIDE LO

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

LO FREQ UENCY (MHz)

Figure 26. Tuning Voltage vs. LO Frequency

1.9

LO = 1100MHz, IP3SET = 3.2V

1.8

1.7

T (V)

1.6

VPT

1.5

1.4

1.3

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

LO = 2300MHz, IP3SET = 3.2V

LO =2300MHz, IP3SET = OPEN

TEMPERATURE (°C)

Figure 27. VPTAT MUXOUT Voltage vs. Temperature

+25°C –40°C +85°C

08817-096

08817-025

8817-097

Rev. 0 | Page 12 of 44

ADRF6655

–

60

AVERAGE

–65

AVERAGE + 3 × ST DEV

–70 –75 –80 –85 –90

–95 –100 –105 –110 –115 –120

PHASE NOISE ( dBc/Hz)

–125 –130 –135 –140 –145 –150

1050 1150 1250 1350 14501550 1650 1750 1850 1950 2050 2150 2250

100kHz OFFS E T

1MHz OFFSET

LO FREQUENCY (MHz)

10kHz OFFSET

08817-039

Figure 28. −40°C Spot Phase Noise vs. LO Frequency

60

AVERAGE

–65

AVERAGE + 3 × ST DEV

–70

–75

–80

–85

–90

–95 –100 –105 –110 –115 –120

PHASE NOISE (dBc/Hz)

–125 –130 –135 –140 –145 –150

1050 1150 1250 1350 14501550 1650 1750 1850 1950 2050 2150 2250

100kHz OFFS E T

1MHz OFFSET

LO FREQUENCY (MHz)

10kHz OFFS ET

08817-040

Figure 29. −10°C Spot Phase Noise vs. LO Frequency

60

AVERAGE

–65

AVERAGE + 3 × ST DEV

–70

–75

–80

–85

–90

–95 –100 –105 –110 –115 –120

PHASE NOISE (dBc/Hz)

–125 –130 –135 –140 –145 –150

1050 1150 1250 1350 14501550 1650 1750 1850 1950 2050 2150 2250

100kHz OFFS E T

1MHz OFFSET

LO FREQUENCY (MHz)

10kHz OFFS ET

08817-041

Figure 30. 25°C Spot Phase Noise vs. LO Frequency

60

AVERAGE

–65

AVERAGE + 3 × S T DEV

–70 –75 –80 –85 –90

–95 –100 –105 –110 –115 –120

PHASE NOISE (dBc/Hz)

–125 –130 –135 –140 –145 –150

1050 1150 1250 1350 14501550 1650 1750 1850 1950 2050 2150 2250

100kHz OFF S E T

1MHz OFF S E T

LO FREQUENCY (MHz)

10kHz OFF S E T

08817-042

Figure 31. 70°C Spot Phase Noise vs. LO Frequency

60

AVERAGE

–65

AVERAGE + 3 × S T DEV

–70

–75

–80

–85

–90

–95 –100 –105 –110 –115 –120

PHASE NOISE (dBc/Hz)

–125 –130 –135 –140 –145 –150

1050 1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

100kHz OFFSET

1MHz OFF S E T

LO FREQUENCY (MHz)

10kHz OFFS ET

08817-043

Figure 32. 85°C Spot Phase Noise vs. LO Frequency

Rev. 0 | Page 13 of 44

ADRF6655

COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): DOWNCONVERSION, LO = 1100 MHz, RF = 900 MHz

VS = 5 V, TA = 25°C, PFD = 20 MHz, REFIN = 20 MHz, IP3SET = open, as measured using typical downconversion circuit schematic with high-side LO and 200 MHz IF output, unless otherwise noted.

100

IP3SET = 3.2V

95

IP3SET = OPEN

90 85 80 75 70 65 60 55 50 45 40 35 30 25 20

DISTRIBUT ION PERCENTAGE (%)

15 10

5 0

–10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20

GAIN

GAIN (dB), INPUT P1dB (dBm)

INPUT P1dB

+25°C –40°C +85°C

08817-106

Figure 33. Gain and Input P1dB CCDF

100

IP3SET = 3.2V

95

IP3SET = OPEN

90 85 80 75 70 65 60 55 50 45 40 35 30 25 20

DISTRIBUT ION PERCENTAGE (%)

15 10

5 0

12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

INPUT IP3 (dBm)

+25°C –40°C +85°C

8817-107

Figure 34. Rx Input IP3 CCDF

100

+25°C

95

–40°C

90

+85°C

85 80 75 70 65 60 55 50 45 40 35 30 25 20

DISTRIBUTION PERCENTAGE (%)

15 10

5 0 –100 –95 –90 –85 –80 –75 –70 –65 –60 –55 –50

LO-TO-RF L E AKAGE (dBm)

08817-098

Figure 35. Rx LO-to-RF Leakage CCDF

Rev. 0 | Page 14 of 44

100

IP3SET = 3.2V

95

IP3SET = OPEN

90 85 80 75 70 65 60 55 50 45 40 35 30 25 20

DISTRIBUTION PERCENTAGE (%)

15 10

5 0

0 2 4 6 8 101214161820

NOISE FIGURE (dB)

+25°C –40°C +85°C

08817-108

Figure 36. Noise Figure CCDF

100

IP3SET = 3 .2V

95

IP3SET = OPEN

90 85 80 75 70 65 60 55 50 45 40 35 30 25 20

DISTRIBUT ION PERCENTAGE (%)

15 10

5 0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

VPTAT (V)

+25°C –40°C +85°C

8817-109

Figure 37. VPTAT MUXOUT Voltage

ANALOG DEVICES ADRF6655 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESPCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

DOWNCONVERSION

UPCONVERSION

PLL CHARACTERISTIC

COMPLIMENTARY CUMULATIVE DISTRIBUTION FUNCTION (CCDF): DOWNCONVERSION, LO = 1100 MHz, RF = 900 MHz