ANALOG DEVICES AD9994 Service Manual

12-Bit CCD Signal Processor with

FEATURES

10-phase or 12-phase vertical transfer clocking Supports 4-field and 5-field CCD readouts Correlated double sampler (CDS) 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) 12-bit, 36 MHz analog-to-digital converter (ADC) Black-level clamp with variable level control Complete on-chip timing generator Precision Timing core with <600 ps resolution On-chip 3 V horizontal and RG drivers 2-phase and 4-phase H-clock modes Electronic and mechanical shutter support On-chip driver for external crystal On-chip sync generator with external sync input 64-lead LFCSP package (9 mm × 9 mm, 0.5 mm pitch)

APPLICATION

Digital still cameras

Precision TimingTM Generator

AD9994

GENERAL DESCRIPTION

The AD9994 is a highly integrated CCD signal processor for digital still camera applications. It includes a complete analog front end with analog-to-digital conversion, combined with a fully programmable timing generator. The timing generator is capable of up to 12-phase vertical clocking to support advanced CCDs with 4-field and 5-field readouts. A Precision Timing core allows adjustment of high speed clocks with approximately 600 ps resolution at 36 MHz operation.

The AD9994 is specified at pixel rates of up to 36 MHz. The analog front end includes black-level clamping, CDS, VGA, and a 12-bit ADC. The timing generator provides the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface.

Packaged in a 64-lead LFCSP, the AD9994 is specified over an operating temperature range of –25°C to +85°C.

CCDIN

H1 TO H4

V1 TO V10

(V1 TO V12)

VSG1 TO VSG8

(VSG1 TO VSG6)

CDS VGA

–3dB, 0dB, +3dB, +6dB

10 OR 12

8 OR 6

For more information about the AD9994, email

FUNCTIONAL BLOCK DIAGRAM

REFT REFB

6dB TO 42dB

HORIZONTAL

DRIVERS

VERTICAL

TIMING

CONTROL

afe.ccd@analog.com.

VREF

CLAMP

INTERNAL CLOCKS

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

HD VD SYNC

Figure 1.

12-BIT

ADC

CLI

CLOVSUB VSUB

AD9994

INTERNAL

REGISTERS

SL SCK DATA

DOUT

DCLK

MSHUT STROBE

04972-0-001

Rev. SpA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9994

NOTES

Rev. SpA | Page 2 of 2