Analog Devices AD9959 prd Datasheet

4 Channel 500MSPS DDS with 10-bit DACs

Preliminary Technical Data

FEATURES

Four synchronized DDS channels @500 MSPS Independent Frequency/Phase/Amplitude control between channels Matched latencies for Frequency/Phase/Amplitude changes Excellent channel to channel isolation (>60dB) Linear Frequency/Phase/Amplitude sweeping capability Up to 16 levels of Frequency/Phase/Amplitude modulation (pin

selectable P0-P3) Individually programmable DAC full scale currents Four integrated 10-bit D/A converters (DACs) 32-bit Frequency tuning resolution 14-bit Phase Offset resolution 10-bit Output Amplitude Scaling resolution Serial I/O Port (SPI) with enhanced data throughput

FUNCTIONAL BLOCK DIAGRAM

Σ

32 32

Σ

32 32

Σ

32

Σ

32

TIMING & CONTROL LOGIC

SYSTEM

CLK

Figure 1 AD9959 Block Diagram

SYNC_IN

SYNC_OUT

I/O_UPDATE

SYNC_CLK

REF_CLK

FTW

BUFFER / XTAL

OSCILLATOR

CLK_MODE_SEL

32

÷4

REF CLOCK MULTIPLIER

FTW

4x to 20x

Σ

M U X

Software/Hardware controlled power-down Dual supply operation (1.8 V DDS core / 3.3 V serial I/O) Built-in synchronization for multiple devices Selectable REF_CLK multipier (PLL) 4x to 20x (bypassable) Selectable REF_CLK crystal operation 56 pin LFCSP package

APPLICATIONS

Agile L.O. frequency synthesis Phased array radar / sonar Instrumentation Synchronized clocking RF source for AOTF

DDS CORE

COS(X)

15

DDS CORE

COS(X)

15

DDS CORE

COS(X)

15

DDS CORE

COS(X)

15

14

1.8V 1.8V 3.3V

AVDD DVDD

10

AMP /

AMP

×

10

×

10

×

10

×

10

CONTROL

REGISTERS

CHANNEL

REGISTERS

PROFILE

REGISTERS

P

S

2

1

0

PHASE /

PHASE

Σ

P S 3

DAC

SCALABLE

DAC REF

CURRENT

DVDD_I/O

I/O

Port

Buffer

AD9959

IOUT

IOUT IOUT

DAC_RSET

PWR_DWN_CTL

MASTER_RESET

SCLK

CS

SDIO_0 SDIO_1 SDIO_2 SDIO_3

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Preliminary Technical Data AD9959

TABLE OF CONTENTS

Features……………………………………………….1

Functional Block Diagram…………….……………...1

Specifications…………………………….……...……3

Absolute Maximum Ratings………….……….......….6

Equivalent Circuits……………………………………6

Product Overview…………………………………….7

Pin Configuration………………………………….....8

Pin Function Description……………….…………….9

Typical Performance Characteristics……………...…10

Application Circuits………………………………….13

Theory of Operation.....................................................14

Modes of Operation.....................................................16

Single Tone………...............................................16

Matched Pipe Line Delay……………………….16

REF CLK ………………………….. ………16

Serial Port Operation……………….…………………28

Overview………………………………………..28

General Serial Port Operation…………………..28

Serial I/O Port Pin Description…………………29

Serial I/O Port Function Description…………...29

MSB / LSB Transfer description……...….…….29

Serial I/O Modes of Operation…………………30

Serial I/O Timing……………………………….31

Control Register Map…………………………...……33

Channel Register Map……………..…………………34

Channel Register Map……………..…………………35

Register Map Bit Description……………………...…36

Package Outline…….……………..…………………40

Scalable DAC reference…………….…………..17

Power Down Functions………………………….17

Direct Modulation……….………………………18

Linear Sweep……………………………………21

Output Ramp…………………………………….24

Synchronizing multiple AD9959 devices..….…..26

REVISION HISTORY

PrA- Intial Release

PrB- Pin Out change

PrC-Internal edit update

Rev. PrD | Page 2 of 41

Preliminary Technical Data AD9959

AD9959—SPECIFICATIONS

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R Frequency = 500 MSPS (REF_CLK multiplier bypassed)

Parameter

REF CLOCK INPUT CHARACTERISTICS

Frequency Range REF_CLK Multiplier bypassed 0 500 MHz REF_CLK Multiplier enabled at 4x(min) 25 125 MHz REF_CLK Multiplier enabled at 20x(max) 5 25 MHz Internal VCO range w/ REF_CLK multiplier enabled 100 500 MHz Crystal REF_CLK source mode 20 30 MHz Input Power Sensitivity -5 3 dBm External 50 ohm termination Input voltage level 400 mV Input Capacitance 3 pF Input Impedance 1500 ohms

Duty Cycle w/ REF_CLK Multiplier bypassed 50 %

Duty Cycle w/ REF_CLK Multiplier enabled 35 65 % CLK Mode Select logic 1 Voltage 1.25 V Not a 3.3V digital input CLK Mode Select logic 0 Voltage 0.6 V Not a 3.3V digital input

DAC OUTPUT CHARACTERISTICS

Resolution 10 Bits Full Scale Ouput Current 10 mA Gain Error -10 10 %FS Output Offset 0.6 uA Differential Nonlinearity -0.5 0.5 LSB Integral Nonlinearity -1 1 LSB Output Capactiance

Voltage Compliance Range

Channel to Channel Isolation 60 dB Channel to Channel Output Amplitude Matching Error 2 %

WIDEBAND SFDR

1-20 MHz Analog Out -65 dBc

20-60 MHz Analog Out -62 dBc

60-100 MHz Analog Out -59 dBc 100-150 MHz Analog Out -56 dBc 150-200 MHz Analog Out -54 dBc

NARROWBAND SFDR

1.1 MHz Analog Out (+/- 10kHz) -90 dBc

1.1 MHz Analog Out (+/- 50kHz) -88 dBc

1.1 MHz Analog Out (+/- 250kHz) -86 dBc

1.1 MHz Analog Out (+/- 1MHz) -85 dBc

15.1 MHz Analog Out (+/- 10kHz)

15.1 MHz Analog Out (+/- 50kHz) -87 dBc

15.1 MHz Analog Out (+/- 250kHz) -85 dBc

15.1 MHz Analog Out (+/- 1MHz) -83 dBc

40.1 MHz Analog Out (+/- 10kHz)

40.1 MHz Analog Out (+/- 50kHz) -87 dBc

40.1 MHz Analog Out (+/- 250kHz) -84 dBc

40.1 MHz Analog Out (+/- 1MHz) -82 dBc

Min Typ

5

AVDD–

0.50

-90

Max Units

pF

AVDD

+ 0.50

= 1.96 kΩ, External Reference Clock

SET

Test Conditions/Comments

REF_CLK inputs must be AC

coupled due to internal biasing

Must be referenced to AVDD

V

Wideband SFDR defined as DC to

dBc

Nyquist

Rev. PrD | Page 3 of 41

Preliminary Technical Data AD9959

Parameter

75.1 MHz Analog Out (+/- 10kHz) -87 dBc

75.1 MHz Analog Out (+/- 50kHz) -85 dBc

75.1 MHz Analog Out (+/- 250kHz) -83 dBc

75.1 MHz Analog Out (+/- 1MHz) -82 dBc

100.3 MHz Analog Out (+/- 10kHz) -87 dBc

100.3 MHz Analog Out (+/- 50kHz) -85 dBc

100.3 MHz Analog Out (+/- 250kHz) -83 dBc

100.3 MHz Analog Out (+/- 1MHz) -81

200.3 MHz Analog Out (+/- 10kHz) -87 dBc

200.3 MHz Analog Out (+/- 50kHz) -85 dBc

200.3 MHz Analog Out (+/- 250kHz) -83 dBc

200.3 MHz Analog Out (+/- 1MHz) -81

PHASE NOISE CHARACTERISTICS

Residual Phase Noise @15.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz @10kHz offset TBD dBc/ Hz @100kHz offset TBD dBc/ Hz @1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 75.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz @10kHz offset TBD dBc/ Hz @100kHz offset TBD dBc/ Hz @1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 200.1 MHz(Aout)

@1kHz offset TBD dBc/ Hz @10kHz offset TBD dBc/ Hz @100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz Residual Phase Noise @ 15.1 MHz(Aout) w/ REF CLK multiplier enabled 4x

@1kHz offset TBD dBc/ Hz

@10kHz offset TBD dBc/ Hz

@100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz

Residual Phase Noise @ 75.1 MHz(Aout) w/ REF CLK multiplier enabled 4x

@1kHz offset TBD dBc/ Hz

@10kHz offset TBD dBc/ Hz

@100kHz offset TBD dBc/ Hz

@1MHz offset TBD dBc/ Hz Residual Phase Noise @ 200.1 MHz(Aout) w/ REF CLK multiplier enabled 4x

@1kHz offset

@10kHz offset

@100kHz offset

@1MHz offset

SERIAL PORT TIMING CHARACTERISTICS

Maximum Frequency

Minimum Clock Pulsewidth Low (t

Minimum Clock Pulsewidth High (t

) TBD

PWL

) TBD

PWH

Min Typ

TBD

Max Units Test Conditions/Comments

dBc

dBc/ Hz

200 MHz

ns

Rev. PrD | Page 4 of 41

Preliminary Technical Data AD9959

Maximum Clock Rise/Fall Time

Minimum Data Setup Time (tDS) TBD

Minimum Data Hold Time TBD

MISC TIMING CHARACTERISTICS

Master_Reset minimum Pulsewidth TBD

I/O_Update minimum Pulsewidth 1

Minimum setup time (IO_Update to Sync_CLK) TBD

Minimum hold time (IO_Update to Sync_CLK) 0 Minimum setup time (Profile inputs to Sync_CLK) TBD Minimum hold time (Profile inputs to Sync_CLK) 0

DATA LATENCY (PIPE LINE DELAY)

Freq, Phase, Amplitude words to DAC output w/ matched latency enabled

Frequency word to DAC output w/ matched latency disabled TBD TBD

Phase Offset word to DAC output w/ matched latency disabled TBD TBD

Amplitude word to DAC output w/ matched latency disabled TBD TBD

CMOS LOGIC INPUTS

VIH 2.2

VIL

Logic 1 Current 3

Logic 0 Current -12

Input Capacitance 2

CMOS LOGIC OUTPUTS (1 mA Load)

VOH 2.8

VOL

POWER SUPPLY

Total Power Dissipation- all channels ON, single-tone mode TBD

Maximum Power Dissipation- all channels, freq accumulator output multiplier ON Iavdd – All Channels ON, Single tone mode TBD

Iavdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD

Idvdd – All Ch(s) ON, Single tone mode TBD

Idvdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD

Idvdd_I/O TBD

Power down Mode TBD

TBD TBD

TBD

TBD ns

ns

Sync CLK

ns Rising edge to rising edge

ns

Sys Clks

V

0.6 V

12 uA

uA

pF

V

0.4 V

mW

mA

Rev. PrD | Page 5 of 41

Preliminary Technical Data AD9959

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C DVDD_I/O (Pin 49) 4 V AVDD, DVDD 2 V Digital Input Voltage (DVDD_I/O = 3.3 V) –0.7 V to +4V Digital Output Current 5 mA Storage Temperature –65°C to +150°C Operating Temperature –40°C to +105°C Lead Temperature (10 sec Soldering) 300°C

θJA 21°C/W

θJC 2°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

CMOS

DIGITAL

INPUTS

DVDD_I/O= 3.3V

INPUT

AVOID OVERDRIVING

DIGITAL INPUTS.

FORWARD BIASING

DIODES MAY COUPLE

DIGITAL NOISE ON

POWER PINS.

OUTPUT

DAC OUPUTS

Iout

TERMINATE OUTPUTS

INTO AVDD. DO NO T

EXCEED OUTPUT

VOLTAGE COMPLIANCE.

Iout

REF_CLK

AVDD AVDD

OSC OSC

OSC / REF_CLK

1.5 k

INPUTS

AVDD

zz

AMP

1.5 k REF_CLK

Figure 1 Equivalent input and output circuits

Rev. PrD | Page 6 of 41

REF_CLK INPUTS ARE

INTERNALLY BIASED AND

NEED TO BE AC-COUPLED.

OSC INPUTS ARE DC

COUPLED

Friday, Feb 4, 2005 4:06 PM /

Preliminary Technical Data

PRODUCT OVERVIEW

The AD9959 consists of four DDS cores that provide independent frequency, phase, and amplitude control between channels. This flexibility can be used to correct imbalances between signals due to analog processing such as filtering, amplification, or PCB layout related mismatches. Since all channels share a common system clock, they are inherently synchronized. If additional channels are required, synchronizing multiple AD9959s is a simple task.

The AD9959 can perform 2/4/8 or 16 level modulation of frequency, phase or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers a SPI compatible mode of operation which is virtually identical to the SPI operation found in earlier ADI DDS products. The flexibility is provided by four data (SDIO_0:3) pins that allow four programmable modes of serial I/O operation.

The AD9959 uses advanced DDS technology which provides low power dissipation with high performance. The device incorporates four integrated high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each channel has a 32-bit frequency tuning word, 14-bits of phase offset, and a 10-

AD9959

bit output scale multiplier.

The DDS acts as a high resolution frequency divider with the REF_ CLK as the input and the DAC providing the output. The REF_CLK input source is common to all DDS channels, and can be driven directly, or used in combination with an integrated REF_CLK multiplier (using a PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input also features an oscillator circuit to support an external crystal as the REF_CLK source. The crystal must be between 20MHz and 30MHz. The crystal can be used in combination with or without the REF_CLK multiplier.

The DAC outputs are supply referenced and must be terminated into AVDD by a resistor, or an AVDD center-tapped transformer. Each DAC has its own programmable reference to enable a different full scale current for each channel.

The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) must be powered by a

1.8V supply. The digital I/O interface (SPI) operates at 3.3V and requires that the pin labeled “DVDD_I/O” (pin 49) be connected to 3.3V.

The AD9959 operates over the industrial temperature range of 40C to +85C.

Preliminary Technical Data AD9959

PIN CONFIGURATION

I/O_UPDATE

DGND

55

56

SDIO_3

DVDD

SYNC_CLK 54

53

52

51

SCLK

49

48

50

47

CS

DVDD_ I/O

SDIO_0

SDIO_1

SDIO_2

DVDD

DGND

P3

46

45

44

43

SYNC_IN

SYNC_OUT

MASTER_RESET

PWR_DWN_CTL

AVDD

AGND

AVDD

CH2_IOUT

CH2 _IOUT

AGND

AVDD

AGND

CH3_IOUT CH3_IOUT

1

2 3 4 5 6 7 8

9 10 11 12 13 14

16

15

AVDD

AGND

AD9959

56-LD LFCSP

TOP VIEW

(Not to Scale)

17

18

19

20

AVDD

AGND

DAC_RSET

22

23

24

21

AVDD

REF_CLK

25

AGND

REF_CLK

CLK_MODE_SEL

Notes :

1) The exposed EPAD on bottom side of package is an electrical connection and must be soldered to ground.

2) Pin 49 is DVDD_IO and is tied to 3.3V.

42

P2

41

P1 P0

40 39

AVDD

38

AGND

37

AVDD

36

CH1_IOUT

35

CH1_IOUT

34

AGND

33

AVDD

32

AGND

31

AVDD

30

CH0_IOUT

29

CH0_IOUT

26

27

28

AVDD

AGND

LOOP _FILTER

Rev. PrD | Page 8 of 41

Preliminary Technical Data AD9959

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 SYNC_IN I Used to synchronize multiple AD9959s. Connect to the SYNC_OUT pin of the master AD9959. 2 SYNC_OUT O Used to synchronize multiple AD9959s. Connect to the SYNC_IN pin of the slave AD9959. 3 MASTER_RESET I Active high reset pin. Asserting the RESET pin forces the AD9959’s internal registers to their default state, as

4 PWR_DWN_CTL I External Power-Down Control. 5,7,11,15,19,21, 26,31,33,37,39 6,10,12,16,18,20, 25,28,32,34,38 45, 55 DVDD I Digital Power Supply Pins (1.8 V). 44, 56 DGND I Digital Power Ground Pins. 8 CH2_IOUT O True DAC Output. Terminate into AVDD.

9

13 CH3_IOUT O True DAC Output. Terminate into AVDD.

14

17 DAC_RSET I Establishes the reference current for all DACs. A 1.91 kΩ resistor (nominal) is connected from pin 17 to AGND. 22

23 REF_CLK I Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. See

24 CLK_MODE_SEL I CAUTION: Do not drive this pin beyond 1.8V. Control Pin for the Oscillator Section. When high (1.8V), the

27 LOOP_FILTER I Connect to the external zero compensation network of the PLL loop filter for the REFCLK multiplier. For a 20x

AVDD I Analog Power Supply Pins (1.8V).

AGND I Analog Ground Pins.

_________ CH2_IOUT

_________ CH3_IOUT

REF_CLK

described in the serial I/O port register map section in this document.

O Complementary DAC Output. Terminate into AVDD.

I Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this

pin should be decoupled to AVDD or AGND with a 0.1 µF capacitor.

Mode of Opertion section for Reference Clock configuration schematic.

oscillator section is enabled to accept a crystal as the REFCLK source. When low, the oscillator section is bypassed.

multiplier value the network should be a 1.2kΩ resistor in series with a 1.2 nF capacitor tied to AVDD.

29

30 CH0_IOUT O True DAC Output. Terminate into AVDD.

35

36 CH1_IOUT O True DAC Output. Terminate into AVDD. 40, 41, 42, 43

46 I/O_UPDATE I A rising edge detected on this pin transfers data from serial port buffer to active registers. 47 CS

48 SCLK I Serial data clock for I/O operations. Data bits are written on rising edge of SCLK and read on the falling edge of

49 DVDD_I/O I 3.3 V Digital Power Supply for SPI port and digital I/O. 50, 51 52, 53 54 SYNC_CLK O I/O_UPDATE and Profile signals must meet the set-up and hold requirements with respect to this signal in

_________ CH0_IOUT

_________ CH1_IOUT

PS0, PS1, PS2, PS3

SDIO_0, SDIO_1 SDIO_2, SDIO_3

O Complementary DAC Output. Terminate into AVDD.

I These pins are ata pins when modulating. They are synchronous to the SYNC_CLK (pin 54). Any change in

Profile inputs transfers the contents of the internal buffer memory to the I/O active registers (same as an external I/O _UPDATE).

I Active low chip select allowing multiple devices to share a common I/O bus (SPI).

SCLK.

I/O Data pin SDIO_0 is dedicated to the serial port I/O only. Data pins SDIO_1:3 can be used for the serial port I/O

or used as data pins for ramp up/down (RU/RD) of the DAC output amplitude.

order to guarantee a fixed pipeline delay of data to DAC outputs.

Rev. PrD | Page 9 of 41

TYPICAL PERFORMANCE CHARACTERISTICS

Figure x. F

= 1.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

= 40.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 15.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 75.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 100.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Figure x. F

= 200.1 MHz FCLK = 500 MSPS, Wide band SFDR

OUT

Preliminary Technical Data AD9959

Figure x. F

= 1.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

= 40.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Figure x. F

= 15.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Figure x. F

= 75.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Figure x. F

= 100.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Rev. PrD | Page 11 of 41

Figure x. F

= 200.1 MHz, FCLK = 500 MSPS, NBSFDR, ±1 MHz

OUT

Preliminary Technical Data AD9959

Figure x. Residual Phase Noise with F

100.1 MHz 200.1 MHz

F

= 500 MHz with REF_CLK Multiplier bypassed

CLK

= 15.1 MHz, 40.1 MHz,75.1 MHz

OUT

Figure x. Residual Phase Noise with F

100.1 MHz 200.1 MHz

F

= 500 MHz with REF_CLK Multiplier = 4x

CLK

Figure x. Residual Phase Noise with F

100.1 MHw00.1 MHz

F

= 500 MHz with REF_CLK Multiplier = 20x

CLK

= 15.1 MHz, 40.1 MHz,75.1 MHz

OUT

= 15.1 MHz, 40.1 MHz,75.1 MHz

OUT

Rev. PrD | Page 12 of 41

Preliminary Technical Data AD9959

APPLICATION CIRCUITS

REF CLK

AD9959

RF / IF Input Modulated / Demodulated

LPF

signal

Figure x. L.O. for Up/Down conversion

FILTER

AD9959

LOOP

VCO

REF CLK

PHASE

COMPARATOR

LPF

Figure x. Digitally Programmable Divide-by-N Function in PLL

I Baseband

LPF

I

CH 0

AD9959

REF CLK

CH 1

Q

LPF

Q Baseband

Figure x. Quadrature Up Conversion

Rev. PrD | Page 13 of 41