Analog Devices AD9954 Datasheet

400 MSPS 14-Bit, 1.8 V CMOS

FEATURES

400 MSPS internal clock speed Integrated 14-bit DAC Programmable phase/amplitude dithering 32-bit tuning word Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output) Excellent dynamic performance

>80 dB SFDR @ 160 MHz (±100 kHz offset) A Serial I/O control Ultrahigh speed analog comparator Automatic linear and nonlinear frequency sweeping

capability 4 frequency/phase offset profiles

1.8 V power supply Software and hardware controlled power-down 48-lead TQFP/EP package Integrated 1024 word × 32-bit RAM

OUT

FUNCTIONAL BLOCK DIAGRAM

Direct Digital Synthesizer

AD9954

Support for 5 V input levels on most digital inputs PLL REFCLK multiplier (4× to 20×) Internal oscillator, can be driven by a single crystal Phase modulation capability Multichip synchronization

APPLICATIONS

Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Automotive radar Test and measurement equipment Acousto-optic device drivers

I/O UPDATE

SYNC_CLK

REFCLK REFCLK

FREQUENCY

ACCUMULATOR

RAM DATA

DELTA FREQUENCY TUNING WORD

DELTA FREQUENCY RAMP RATE

32

M U X

OSCILLATOR/BUFFER

ENABLE

CRYSTAL OUT I/O PORTPS<1:0>

STATIC RAM

1024 × 32

S S E R

D D A

M A

RAM CONTROL

R

3

10

0

32

RAM

DATA 32

DDS CLOCK

32

SYNC

4×–20×

CLOCK

MULTIPLIER

M U X

FREQUENCY

TUNING WORD

DDS

CLOCK

PHASE

ACCUMULATOR

TIMING AND CONTROL LOGIC

÷ 4

M

SYSTEM

U

CLOCK

X

DDS CORE

PHASE

–1

Z

PHASE

ACUMULATOR

OFFSET

3232

14

Z

RESET

MUX

RAM DATA

<31:18>

CONTROL REGISTERS

19 14

COS(X)

–1

14

θ

RESET

AD9954

14

COMPARATOR

DAC

SYSTEM

CLOCK

DAC_R

SET

IOUT IOUT

SYNC_IN

OSK PWRDWNCTL

COMP_IN COMP_IN

COMP_OUT

03374-0-001

Figure 1. 48-LeadTQFP/EP

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD9954

GENERAL DESCRIPTION

The AD9954 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9954 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9954 is designed to provide fast frequency hopping and fine tuning resolution (32-bit frequency tuning word). The frequency tuning and control words are loaded into

the AD9954 via a serial I/O port. The AD9954 includes an integrated 1024 × 32 static RAM to support flexible frequency sweep capability in several modes. The AD9954 also supports a user defined linear sweep mode of operation. The device includes an on-chip high speed comparator for applications requiring a square wave output.

The AD9954 is specified to operate over the extended industrial temperature range of –40°C to +105°C.

Rev. 0 | Page 3 of 36

AD9954

AD9954—ELECTRICAL SPECIFICATIONS

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.

Parameter

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled FULL VI 1 400 MHz REFCLK Multiplier Enabled at 4× FULL VI 20 100 MHz

REFCLK Multiplier Enabled at 20× FULL VI 4 20 MHz Input Capacitance 25°C V 3 pF Input Impedance 25°C V 1.5 kΩ Duty Cycle 25°C V 50 % Duty Cycle with REFCLK Multiplier Enabled 25°C V 35 65 % REFCLK Input Power

DAC OUTPUT CHARACTERISTICS

Resolution 14 Bits Full Scale Output Current 25°C 5 10 15 mA Gain Error 25°C I –10 +10 %FS Output Offset 25°C I 0.6 µA Differential Nonlinearity 25°C V 1 LSB Integral Nonlinearity 25°C V 2 LSB Output Capacitance 25°C V 5 pF Residual Phase Noise @ 1 kHz Offset, 40 MHz A

REFCLK Multiplier Enabled @ 20× 25°C V –105 dBc/Hz

REFCLK Multiplier Enabled @ 4× 25°C V –115 dBc/Hz

REFCLK Multiplier Disabled 25°C V –132 dBc/Hz Voltage Compliance Range 25°C I AVDD – 0.5 AVDD + 0.5 V Wideband SFDR

1 MHz to 10 MHz Analog Out 25°C V 73 dBc

10 MHz to 40 MHz Analog Out 25°C V 67 dBc

40 MHz to 80 MHz Analog Out 25°C V 62 dBc

80 MHz to 120 MHz Analog Out 25°C V 58 dBc

120 MHz to 160 MHz Analog Out 25°C V 52 dBc Narrow Band SFDR

40 MHz Analog Out (±1 MHz) 25°C V 87 dBc

40 MHz Analog Out (±250 kHz) 25°C V 89 dBc

40 MHz Analog Out (±50 kHz) 25°C V 91 dBc

40 MHz Analog Out (±10 kHz) 25°C V 93 dBc

80 MHz Analog Out (±1 MHz) 25°C V 85 dBc

80 MHz Analog Out (±250 kHz) 25°C V 87 dBc

80 MHz Analog Out (±50 kHz) 25°C V 89 dBc

80 MHz Analog Out (±10 kHz) 25°C V 91 dBc

120 MHz Analog Out (±1 MHz) 25°C V 83 dBc

120 MHz Analog Out (±250 kHz) 25°C V 85 dBc

120 MHz Analog Out (±50 kHz) 25°C V 87 dBc

120 MHz Analog Out (±10 kHz) 25°C V 89 dBc

160 MHz Analog Out (±1 MHz) 25°C V 81 dBc

160 MHz Analog Out (±250 kHz) 25°C V 83 dBc

160 MHz Analog Out (±50 kHz) 25°C V 85 dBc

160 MHz Analog Out (±10 kHz) 25°C V 87 dBc

1

OUT

Temp

FULL IV –15 0 +3 dBm

Test Level Min

= 3.92 kΩ, External Reference Clock

SET

Typ Max

Unit

Rev. 0 | Page 4 of 36

AD9954

Parameter

COMPARATOR INPUT CHARACTERISTICS

Input Capacitance 25°C V 3 pF Input Resistance 25°C IV 500 kΩ Input Current 25°C I ±12 µA Hysteresis 25°C IV 30 45 mV

COMPARATOR OUTPUT CHARACTERISTICS

Logic 1 Voltage, High Z Load FULL VI 1.6 V Logic 0 Voltage, High Z Load FULL VI 0.4 V Propagation Delay 25°C IV 3 ns Output Duty Cycle Error 25°C IV ±5 % Rise/Fall Time, 5 pF Load 25°C IV 1 ns Toggle Rate, High Z Load 25°C IV 200 MHz Output Jitter

2

COMPARATOR NARROWBAND SFDR dBc

10 MHz (1 MHz) 25°C V 80 dBc 10 MHz (250 kHz) 25°C V 85 dBc 10 MHz (50 kHz) 25°C V 90 dBc 10 MHz (10 kHz) 25°C V 95 dBc 70 MHz (1 MHz) 25°C V 80 dBc 70 MHz (250 kHz) 25°C V 85 dBc 70 MHz (50 kHz) 25°C V 90 dBc 70 MHz (10 kHz) 25°C V 95 dBc 110 MHz (1 MHz) 25°C V 80 dBc 110 MHz (250 kHz) 25°C V 85 dBc 110 MHz (50 kHz) 25°C V 90 dBc 110 MHz (10 kHz) 25°C V 95 dBc 140 MHz (1 MHz) 25°C V 80 dBc 140 MHz (250 kHz) 25°C V 85 dBc 140 MHz (50 kHz) 25°C V 90 dBc 140 MHz (10 kHz) 25°C V 95 dBc 160 MHz (1 MHz) 25°C V 80 dBc 160 MHz (250 kHz) 25°C V 85 dBc 160 MHz (50 kHz) 25°C V 90 dBc 160 MHz (10 kHz) 25°C V 95 dBc

CLOCK GENERATOR OUTPUT JITTER

5 MHz A 10 MHz A 40 MHz A 80 MHz A 120 MHz A 140 MHz A 160 MHz A

25°C V 100 ps RMS

OUT

3

TIMING CHARACTERISTICS

Serial Control Bus FULL IV

Maximum Frequency FULL IV 25 Mbps Minimum Clock Pulse Width Low FULL IV 7 ns Minimum Clock Pulse Width High FULL IV 7 ns Maximum Clock Rise/Fall Time FULL IV 2 ns Minimum Data Setup Time DVDD_I/O = 3.3 V FULL IV 3 ns Minimum Data Setup Time DVDD_I/O = 1.8 V FULL IV 5 ns Minimum Data Hold Time FULL IV 0 ns

Temp

Test Level Min

Typ Max

Unit

25°C IV 1 ps RMS

25°C V 60 ps RMS 25°C V 50 ps RMS 25°C V 50 ps RMS 25°C V 50 ps RMS 25°C V 50 ps RMS 25°C V 50 ps RMS

Rev. 0 | Page 5 of 36

AD9954

Parameter

Maximum Data Valid Time FULL IV 25 ns

Wake-Up Time

4

Minimum Reset Pulse Width High FULL IV 5 SYSCLK Cycles

I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V FULL I 4 ns

I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V FULL I 6 ns

I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time FULL I 0 ns Latency

I/O UPDATE to Frequency Change Prop Delay 25°C IV 24 SYSCLK Cycles

I/O UPDATE to Phase Offset Change Prop Delay 25°C IV 24 SYSCLK Cycles

I/O UPDATE to Amplitude Change Prop Delay 25°C IV 16 SYSCLK Cycles

PS0, PS1 to RAM Driven Frequency Change Prop Delay 25°C IV 28 SYSCLK Cycles

PS0, PS1 to RAM Driven Phase Change Prop Delay 25°C IV 28 SYSCLK Cycles

PS0 to Linear Frequency Sweep Prop Delay 25°C IV 28 SYSCLK Cycles

CMOS LOGIC INPUTS

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C I 1.25 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C I 0.6 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C I 2.2 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C I 0.8 V Logic 1 Current 25°C V 3 12 µA Logic 0 Current 25°C 12 µA Input Capacitance 25°C 2 pF

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V

Logic 1 Voltage 25°C I 1.35 V Logic 0 Voltage 25°C I 0.4 V

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V

Logic 1 Voltage 25°C I 2.8 V Logic 0 Voltage 25°C I 0.4 V

POWER CONSUMPTION (AVDD = DVDD = 1.8 V)

Single Tone Mode (Comparator Off) 25°C I 162 171 mW With RAM or Linear Sweep Enabled 25°C I 175 190 mW With Comparator Enabled 25°C I 180 190 mW With RAM and Comparator Enabled 25°C I 198 220 mW Rapid Power-Down Mode 25°C I 150 160 mW Full-Sleep Mode 25°C I 20 27 mW

SYNCHRONIZATION FUNCTION

6

Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V) 25°C VI 62.5 MHz Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V) 25°C VI 100 MHz SYNC_CLK Alignment Resolution

7

1

To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-

formance of the device.

2

Represents the cycle-to-cycle residual jitter from the comparator alone.

3

Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.

4

Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The longest time required is for the reference

clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.

5

SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK frequency is the same as the external reference clock frequency.

6

SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.

7

This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock

edges are aligned, the synchronization function should not increase the skew between the two edges.

Temp

Test Level Min

Typ Max

Unit

FULL IV 1 ms

5

25°C V ±1 SYSCLK Cycles

Rev. 0 | Page 6 of 36

AD9954

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C

DVDD_I/O (Pin 43) 4 V

AVDD, DVDD 2 V

Digital Input Voltage (DVDD_I/O = 3.3 V) –0.7 V to +5.25 V

Digital Input Voltage (DVDD_I/O = 1.8 V) –0.7 V to +2.2 V

Digital Output Current 5 mA

Storage Temperature –65°C to +150°C

Operating Temperature –40°C to +105°C

Lead Temperature (10 sec Soldering) 300°C

θ

JA

θ

JC

38°C/W 15°C/W

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at these or any

other conditions above those indicated in the operational sec-

tion of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 3. Explanation of Test Levels

I 100% Production Tested. II

100% Production Tested at 25°C and sample Tested at

Specified Temperatures. III Sample Tested Only. IV

Parameter is guaranteed by design and characterization

testing. V Parameter is a typical value only. VI

Devices are 100% production tested at 25°C and

guaranteed by design and characterization testing for

industrial operating temperature range.

DIGITAL INPUTS

INPUT

AVOID OVERDRIVING

DIGITAL INPUTS.

FORWARD BIASING

ESD DIODES MAY

COUPLE DIGITAL NOISE

ONTOPOWERPINS.

DVDD_I/O

COMP IN

COMPARATOR

INPUTS

AVDD

DAC OUTPUTS

IOUT

OUTP UTS TO AVDD FOR

COMPLIANCE RATING.

IOUT

MUST TERMINATE

CURRENT FLOW. DO

NOT EXCEED THE

OUTPUT VOLTAGE

Figure 2. Equivalent Input and Output Circuits

COMP IN

COMPARATOR

OUTPUT

AVDD

03374-0-032

Rev. 0 | Page 7 of 36

AD9954

PIN CONFIGURATIONS

PS1

PS0

OSK

SYNC_CLK

SYNC_IN

DVDD_I/O

434241

DGND

SCLK

SDIO

40 39 38 3748 47 46 45 44

SDOCSIOSYNC

I/O UPDATE

DVDD DGND AVDD AGND AVDD

AGND OSC/REFCLK OSC/REFCLK

CRYSTAL OUT

CLKMOD ESELECT

LOOP_FILTER

1

2

3

4

5

6

7

8

9

10

11

12

13 15 16 17 18 19 20 21 22 23 24

14

AVDD

AGND

AD9954

TOP V IEW

(Not to Scale)

AVDD

AGND

AVDD

IOUT

AGND

DACBP

36

35 34

33 32

31

30

29

28

27 26

25

SET

DAC_R

RESET PWRDWN CTL DVDD DGND AGND COMP_IN COMP_IN AVDD COMP_OUT AVDD AGND AVDD

03374-0-002

Figure 3. 48-Lead EP_TQFP

Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V. The DVDD pins (Pin 2 and Pin 34) can only be powered to 1.8 V.

Rev. 0 | Page 8 of 36

AD9954

PIN FUNCTION DESCRIPTIONS

Table 4. Pin Function Descriptions—48-Lead TQFP/EP

Pin No. Mnemonic I/O Description

1 I/O UPDATE I

2, 34 DVDD I Digital Power Supply Pins (1.8 V). 3, 33, 42 DGND I Digital Power Ground Pins. 4, 6, 13, 16,

18, 19, 25, 27, 29

5, 7, 14, 15, 17, 22, 26, 32

8

9 OSC/REFCLK I

10 CRYSTAL OUT O Output of the Oscillator Section. 11 CLKMODESELECT I

12 LOOP_FILTER I

20 21 IOUT O DAC Output. Should be biased through a resistor to AVDD, not AGND.

23 DACBP I DAC Biasline Decoupling Pin. 24 DAC_R

28 COMP_OUT O Comparator Output. 30 COMP_IN I Comparator Input. 31 35 PWRDWNCTL I Input Pin Used as an External Power-Down Control (see Table 13 for details). 36 RESET I

37 IOSYNC I

38 SDO O

39 40 SCLK I This pin functions as the serial data clock for I/O operations. 41 SDIO I/O

43 DVDD_I/O I Digital Power Supply (for I/O Cells Only, 3.3 V). 44 SYNC_IN I

45 SYNC_CLK O Clock Output Pin that Serves as a Synchronizer for External Hardware. 46 OSK I

47, 48 PS0, PS1 I

<49> AGND I

AVDD I Analog Power Supply Pins (1.8 V).

AGND I Analog Power Ground Pins.

OSC/REFCLK

IOUT

SET

COMP_IN

CS

The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin must be set up and held around the SYNC_CLK output signal.

I

Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in singleended mode, REFCLKB should be decoupled to AVDD with a 0.1 µF capacitor.

Reference Clock/Oscillator Input. See Clock Input section for details on the OSCILLATOR/REFCLK operation.

Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the oscillator section is bypassed.

This pin provides the connection for the external zero compensation network of the REFCLK multiplier’s PLL loop filter. The network consists of a 1 kΩ resistor in series with a 0.1 µF capacitor tied to AVDD.

O Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.

I

A resistor (3.92 kΩ nominal) connected from AGND to DAC_R for the DAC.

I Comparator Complementary Input.

Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9954 to the initial state, as described in the I/O port register map.

Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is returned low. If unused, ground this pin; do not allow this pin to float.

When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When operated as a 2-wire serial port, this pin is unused and can be left unconnected.

I This pin functions as an active low chip select that allows multiple devices to share the I/O bus.

When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input, only. When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.

Input signal used to synchronize multiple AD9954s. This input is connected to the SYNC_CLK output of a master AD9954.

Input pin used to control the direction of the shaped on-off keying function when programmed for operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin should be tied to DGND.

Input pin used to select one of the four internal profiles. Profile <1:0> are synchronous to the SYNC_CLK pin. Any change in these inputs transfers the contents of the internal buffer memory to the I/O registers (sends an internal I/O UPDATE).

The exposed paddle on the bottom of the package is a ground connection for the DAC and must be attached to AGND in any board layout.

establishes the reference current

SET

Rev. 0 | Page 9 of 36

AD9954

K

TYPICAL PERFORMANCE CHARACTERISTICS

MKR1 98.0MHz

–70.68dB

SWEEP 55.56 s (401 PTS)

SPAN 200MHz

MKR1 80.0MHz

–69.12dB

SPAN 200MHz

MKR1 0Hz

–68.44dB

SPAN 200MHz

03374-0-016

03374-0-017

03374-0-018

PEA

LOG

10dB/

W1 S2

S3 FC

AA

PEA

LOG

10dB/

W1 S2

S3 FC

AA

PEA

LOG

10dB/

W1 S2

S3 FC

AA

REF 0dBm

0

1R

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 100MHz #RES BW 3kHz

Figure 4. F

REF 0dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 100MHz #RES BW 3kHz

Figure 5. F

REF 0dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 100MHz #RES BW 3kHz

Figure 6. F

ATTEN 10dB

MARKER

100.000000MHz –70.68dB

1

VBW 3kHz

= 1 MHz FCLK = 400 MSPS, WBSFDR

OUT

ATTEN 10dB

1R

MARKER

80.000000MHz –69.12dB

1

VBW 3kHz

= 10 MHz, FCLK = 400 MSPS, WBSFDR

OUT

ATTEN 10dB

1R

MARKER

40.000000MHz –68.44dB

1

VBW 3kHz

= 40 MHz, FCLK = 400 MSPS, WBSFDR

OUT

PEA

LOG

10dB/

W1 S2

S3 FC

AA

PEA

LOG

10dB/

W1 S2

S3 FC

AA

PEA

LOG

10dB/

W1 S2

S3 FC

AA

REF 0dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 100MHz #RES BW 3kHz

Figure 7. F

REF 0dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 100MHz #RES BW 3kHz

Figure 8 F

REF 0dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 100MHz #RES BW 3kHz

Figure 9. F

ATTEN 10dB

1R

MARKER

80.000000MHz –61.55dB

VBW 3kHz

= 80 MHz FCLK = 400 MSPS, WBSFDR

OUT

ATTEN 10dB

MARKER

40.000000MHz –56.2dB

VBW 3kHz

= 120 MHz, FCLK = 400 MSPS, WBSFDR

OUT

ATTEN 10dB

MARKER

80.000000MHz –53.17dB

= 160 MHz, FCLK = 400 MSPS, WBSFDR

OUT

1

VBW 3kHz

MKR1 80.0MHz

–61.55dB

1

1R

SPAN 200MHz

MKR1 40.0MHz

–56.2dB

1

SPAN 200MHz

MKR1 0Hz

–53.17dB

1R

SPAN 200MHz

SWEEP 55.56 s (401 PTS)

03374-0-019

03374-0-020

03374-0-021

Rev. 0 | Page 10 of 36

AD9954

K

PEA

LOG

10dB/

W1 S2

S3 FC

PEA

LOG

10dB/

W1 S2

S3 FC

PEA

LOG

10dB/

W1 S2

S3 FC

AA

ST

AA

REF –4dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 1.105MHz #RES BW 30Hz

Figure 10. F

REF 0dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 10MHz #RES BW 30Hz

Figure 11. F

REF 0dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 39.9MHz #RES BW 30Hz

Figure 12. F

ATTEN 10dB

MARKER

1.105000MHz –5.679dBm

= 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz

OUT

ATTEN 10dB

MARKER

40.000000MHz –56.2dB

= 10 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz

OUT

ATTEN 10dB

MARKER

39.905000MHz –5.347dBm

= 39.9 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz

OUT

1

VBW 30Hz

1R

1

VBW 30Hz

1

VBW 30Hz

MKR1 1.105MHz

SWEEP 199.2 s (401 PTS)

MKR1 85kHz

SWEEP 199.2 s (401 PTS)

MKR1 39.905MHz

SWEEP 199.2 s (401 PTS)

–5.679dBm

SPAN 2MHz

–93.01dB

SPAN 2MHz

–5.347dBm

SPAN 2MHz

03374-0-022

03374-0-023

03374-0-024

PEA

LOG

10dB/

W1 S2

S3 FC

AA

ST

Figure 13. F

PEA

LOG

10dB/

W1 S2

S3 FC

AA

ST

Figure 14. F

PEA

LOG

10dB/

W1 S2

S3 FC

AA

ST

REF –4dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 80.25MHz #RES BW 30Hz

REF –4dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 120.2MHz #RES BW 30Hz

REF –4dBm

0

–10

–20 –30

–40

–50

–60

–70

–80 –90

–100

CENTER 160.5MHz #RES BW 30Hz

Figure 15. F

ATTEN 10dB

MARKER

80.301000MHz –6.318dBm

= 80.3 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz

OUT

ATTEN 10dB

MARKER

120.205000MHz –6.825dBm

= 120.2 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz

OUT

ATTEN 10dB

CENTER

160.5000000MHz

= 160 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz

OUT

1

VBW 30Hz

1

VBW 30Hz

1

VBW 30Hz

MKR1 80.301MHz

–6.318dBm

SWEEP 199.2 s (401 PTS)

SPAN 2MHz

MKR1 120.205MHz

–6.825dBm

SPAN 2MHz

MKR1 600kHz

–0.911dB

SPAN 2MHz

03374-0-025

03374-0-026

03374-0-027

Rev. 0 | Page 11 of 36

Analog Devices AD9954 Datasheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

GENERAL DESCRIPTION

AD9954—ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS

PIN FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS