Analog Devices AD9952 Datasheet

400 MSPS 14-Bit, 1.8 V CMOS

FEATURES

400 MSPS internal clock speed Integrated 14-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/Hz @ 1 kHz offset (DAC output) Excellent dynamic performance

>80 dB SFDR @ 160 MHz (±100 kHz offset) A

Serial I/O control

1.8 V power supply Software and hardware controlled power-down 48-lead TQFP/EP package Support for 5 V input levels on most digital inputs

OUT

FUNCTIONAL BLOCK DIAGRAM

PHASE

ACCUMULATOR

–1

Z

Direct Digital Synthesizer

PLL REFCLK multiplier (4× to 20×) Internal oscillator, can be driven by a single crystal Phase modulation capability Multichip synchronization High speed comparator (200 MHz toggle rate)

APPLICATIONS

Agile LO frequency synthesis Programmable clock generators Test and measurement equipment Acousto-optic device drivers

DDS CORE

PHASE

OFFSET

32

19 14

COS(X)

AD9952

DAC

DAC_R IOUT

IOUT

AD9952

SET

SCALE FACTOR

COMPARATOR

SYSTEM

CLOCK

SYNC_IN

OSK PWRDWNCTL

COMP_IN COMP_IN

COMP_OUT

03358-0-001

I/O UPDATE

SYNC_CLK

REFCLK REFCLK

–1

FREQUENCY

TUNING WORD

32

DDS CLOCK

CLEAR PHASE

ACCUMULATOR

TIMING AND CONTROL LOGIC

0 M U X

OSCILLATOR/BUFFER

ENABLE

CRYSTAL OUT I/O PORT

SYNC

4×–20×

CLOCK

MULTIPLIER

÷ 4

M U X

SYSTEM

CLOCK

CONTROL REGISTERS

Z

14

AMPLITUDE

RESET

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9952

GENERAL DESCRIPTION

The AD9952 is a direct digital synthesizer (DDS) featuring a 14-bit DAC operating up to 400 MSPS. The AD9952 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 200 MHz. The AD9952 is designed to provide fast frequency

hopping and fine tuning resolution (32-bit frequency tuning word). The frequency tuning and control words are loaded into the AD9952 via a serial I/O port.

The AD9952 is specified to operate over the extended industrial temperature range of –40°C to +105°C.

Rev. 0 | Page 3 of 28

AD9952

ELECTRICAL SPECIFICATIONS

Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, R Frequency = 20 MHz with REFCLK Multiplier Enabled at 20×. DAC Output Must Be Referenced to AVDD, Not AGND.

Parameter Temp Min Typ Max Unit

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled FULL 1 400 MHz REFCLK Multiplier Enabled at 4× FULL 20 100 MHz

REFCLK Multiplier Enabled at 20× FULL 4 20 MHz Input Capacitance 25°C 3 pF Input Impedance 25°C 1.5 kΩ Duty Cycle 25°C 50 % Duty Cycle with REFCLK Multiplier Enabled 25°C 35 65 % REFCLK Input Power1 FULL –15 0 +3 dBm

DAC OUTPUT CHARACTERISTICS

Resolution 14 Bits Full-Scale Output Current 25°C 5 10 15 mA Gain Error 25°C –10 +10 %FS Output Offset 25°C 0.6 µA Differential Nonlinearity 25°C 1 LSB Integral Nonlinearity 25°C 2 LSB Output Capacitance 25°C 5 pF Residual Phase Noise @ 1 kHz Offset, 40 MHz A

REFCLK Multiplier Enabled @ 20× 25°C –105 dBc/Hz

REFCLK Multiplier Enabled @ 4× 25°C –115 dBc/Hz

REFCLK Multiplier Disabled 25°C –132 dBc/Hz Voltage Compliance Range 25°C AVDD – 0.5 AVDD + 0.5 V Wideband SFDR

1 MHz to 10 MHz Analog Out 25°C 73 dBc

10 MHz to 40 MHz Analog Out 25°C 67 dBc

40 MHz to 80 MHz Analog Out 25°C 62 dBc

80 MHz to 120 MHz Analog Out 25°C 58 dBc

120 MHz to 160 MHz Analog Out 25°C 52 dBc Narrow-Band SFDR

40 MHz Analog Out (±1 MHz) 25°C 87 dBc

40 MHz Analog Out (±250 kHz) 25°C 89 dBc

40 MHz Analog Out (±50 kHz) 25°C 91 dBc

40 MHz Analog Out (±10 kHz) 25°C 93 dBc

80 MHz Analog Out (±1 MHz) 25°C 85 dBc

80 MHz Analog Out (±250 kHz) 25°C 87 dBc

80 MHz Analog Out (±50 kHz) 25°C 89 dBc

80 MHz Analog Out (±10 kHz) 25°C 91 dBc

120 MHz Analog Out (±1 MHz) 25°C 83 dBc

120 MHz Analog Out (±250 kHz) 25°C 85 dBc

120 MHz Analog Out (±50 kHz) 25°C 87 dBc

120 MHz Analog Out (±10 kHz) 25°C 89 dBc

160 MHz Analog Out (±1 MHz) 25°C 81 dBc

160 MHz Analog Out (±250 kHz) 25°C 83 dBc

160 MHz Analog Out (±50 kHz) 25°C 85 dBc

160 MHz Analog Out (±10 kHz) 25°C 87 dBc

OUT

= 3.92 kΩ, External Reference Clock

SET

Rev. 0 | Page 4 of 28

AD9952

Parameter Temp Min Typ Max Unit

COMPARATOR INPUT CHARACTERISTICS

Input Capacitance 25°C 3 pF Input Resistance 25°C 500 kΩ Input Current 25°C ±12 µA Hysteresis 25°C 30 45 mA

COMPARATOR OUTPUT CHARACTERISTICS

Logic 1 Voltage, High Z Load FULL 1.6 V Logic 0 Voltage, High Z Load FULL 0.4 V Propagation Delay 25°C 3 ns Output Duty Cycle Error 25°C ±5 % Rise/Fall Time, 5 pF Load 25°C 1 ns Toggle Rate, High Z Load 25°C 200 MHz Output Jitter2 25°C 1 ps rms

COMPARATOR NARROW-BAND SFDR

10 MHz (1 MHz) 25°C 80 dBc 10 MHz (250 kHz) 25°C 85 dBc 10 MHz (50 kHz) 25°C 90 dBc 10 MHz (10 kHz) 25°C 95 dBc 70 MHz (1 MHz) 25°C 80 dBc 70 MHz (250 kHz) 25°C 85 dBc 70 MHz (50 kHz) 25°C 90 dBc 70 MHz (10 kHz) 25°C 95 dBc 110 MHz (1 MHz) 25°C 80 dBc 110 MHz (250 kHz) 25°C 85 dBc 110 MHz (50 kHz) 25°C 90 dBc 110 MHz (10 kHz) 25°C 95 dBc 140 MHz (1 MHz) 25°C 80 dBc 140 MHz (250 kHz) 25°C 85 dBc 140 MHz (50 kHz) 25°C 90 dBc 140 MHz (10 kHz) 25°C 95 dBc 160 MHz (1 MHz) 25°C 80 dBc 160 MHz (250 kHz) 25°C 85 dBc 160 MHz (50 kHz) 25°C 90 dBc 160 MHz (10 kHz) 25°C 95 dBc

CLOCK GENERATOR OUTPUT JITTER3

5 MHz A 10 MHz A 40 MHz A 80 MHz A 120 MHz A 140 MHz A 160 MHz A

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency FULL 25 Mbps Minimum Clock Pulse Width Low FULL 7 ns Minimum Clock Pulse Width High FULL 7 ns Maximum Clock Rise/Fall Time FULL 2 ns Minimum Data Setup Time DVDD_I/O = 3.3 V FULL 3 ns Minimum Data Setup Time DVDD_I/O = 1.8 V FULL 5 ns Minimum Data Hold Time FULL 0 ns Maximum Data Valid Time FULL 25 ns

25°C 100 ps rms

OUT

25°C 60 ps rms

OUT

25°C 50 ps rms

OUT

25°C 50 ps rms

OUT

25°C 50 ps rms

OUT

25°C 50 ps rms

OUT

25°C 50 ps rms

OUT

Rev. 0 | Page 5 of 28

AD9952

Parameter Temp Min Typ Max Unit

Wake-Up Time4 FULL 1 ms

Minimum Reset Pulse Width High FULL 5 SYSCLK Cycles5

I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 4 ns

I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V FULL 6 ns

I/O UPDATE, SYNC_CLK Hold Time FULL 0 ns Latency

I/O UPDATE to Frequency Change Prop Delay 25°C 24 SYSCLK Cycles

I/O UPDATE to Phase Offset Change Prop Delay 25°C 24 SYSCLK Cycles

I/O UPDATE to Amplitude Change Prop Delay 25°C 16 SYSCLK Cycles

CMOS LOGIC INPUTS

Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 1.25 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V 25°C 0.6 V Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 2.2 V Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V 25°C 0.8 V Logic 1 Current 25°C 3 12 µA Logic 0 Current 25°C 12 µA Input Capacitance 25°C 2 pF

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V

Logic 1 Voltage 25°C 1.35 V Logic 0 Voltage 25°C 0.4 V

CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V

Logic 1 Voltage 25°C 2.8 V Logic 0 Voltage 25°C 0.4 V

POWER CONSUMPTION (AVDD = DVDD = 1.8 V)

Single-Tone Mode 25°C 162 171 mW Rapid Power-Down Mode 25°C 150 160 mW Full-Sleep Mode 25°C 20 27 mW

SYNCHRONIZATION FUNCTION6

Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V) 25°C 62.5 MHz Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V) 25°C 100 MHz SYNC_CLK Alignment Resolution7 25°C ±1 SYSCLK Cycles

1

To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise

performance of the device.

2

Represents the cycle-to-cycle residual jitter from the comparator alone.

3

Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.

4

Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions of the AD9952 section). The longest time required is for the

reference clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used.

5

SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK frequency is the same as the external reference clock frequency.

6

SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.

7

This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock

edges are aligned, the synchronization function should not increase the skew between the two edges.

Rev. 0 | Page 6 of 28

AD9952

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C

DVDD_I/O (Pin 43) 4 V

AVDD, DVDD 2 V

Digital Input Voltage (DVDD_I/O = 3.3 V) –0.7 V to +5.25 V

Digital Input Voltage (DVDD_I/O = 1.8 V) –0.7 V to +2.2 V

Digital Output Current 5 mA

Storage Temperature –65°C to +150°C

Operating Temperature –40°C to +105°C

Lead Temperature (10 sec Soldering) 300°C

θJA 38°C/W

θJC 15°C/W

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

DIGITAL INPUTS

DVDD_I/O

INPUT

AVOID OVERDRIVING

DIGITAL INPUTS.

FORWARD BIASING

ESD DIODES MAY

COUPLE DIGITALNOISE

ONTOPOWERPINS.

COMP IN

COMPARATOR

INPUTS

AVDD

DAC OUTPUTS

IOUT

OUTP UTS TO AV DD FOR

COMPLIANCE RATING.

IOUT

MUST TERMINATE

CURRENT FLOW. DO

NOT EXCEED THE

OUTPUT VOLTAGE

Figure 2. Equivalent Input and Output Circuits

COMP IN

COMPARATOR

OUTPUT

AVDD

03374-0-032

Rev. 0 | Page 7 of 28

AD9952

K

PIN CONFIGURATION

DVDD

OSK

SYNC_CL

SYNC_IN

DVDD_I/O

424140 39 38 3748 47 46 45 44

43

DGND

SCLK

SDIO

SDOCSIOSYNC

I/O UPDATE

DVDD DGND AVDD AGND AVDD

AGND OSC/REFCLK OSC/REFCLK

CRYSTAL OUT

CLKMODESELECT

LOOP_FILTER

1

2

3

4

5

6

7

8

9

10

11

12

14

13 15 16 17 18 19 20 21 22 23 24

AVDD

AGND

AD9952

TOP VIEW

(Not to Scale)

AVDD

AGND

AVDD

IOUT

AGND

DACBP

SET

DAC_R

RESET

36

PWRDWNCTL

35

DVDD

34

DGND

33

AGND

32

COMP_IN

31

COMP_IN

30

AVDD

29

COMP_OUT

28

AVDD

27

AGND

26

AVDD

25

03358-0-002

Figure 3. 48-Lead TQFP/EP

Note that the exposed paddle on the bottom of the package forms an electrical connection for the DAC and must be attached to analog ground. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only be powered to 1.8 V.

Rev. 0 | Page 8 of 28

AD9952

PIN FUNCTION DESCRIPTIONS

Table 3. 48-Lead TQFP/EP

Pin No. Mnemonic I/O Description

1 I/O UPDATE I

2, 34 DVDD I Digital Power Supply Pins (1.8 V). 3, 33, 42,

47, 48 4, 6, 13,

16, 18, 19, 25, 27, 29

5, 7, 14, 15, 17, 22, 26, 32

8

9 OSC/REFCLK I

10 CRYSTAL OUT O Output of the Oscillator Section. 11 CLKMODESELECT I

12 LOOP_FILTER I

20 21 IOUT O DAC Output. Should be biased through a resistor to AVDD, not AGND. 23 DACBP I DAC Biasline Decoupling Pin. 24 DAC_R

28 COMP_OUT O Comparator Output. 30 COMP_IN I Compator Input. 31

35 PWRDWNCTL I Input Pin Used as an External Power-Down Control (see Table 8 for details). 36 RESET I

37 IOSYNC I

38 SDO O

39 40 SCLK I This pin functions as the serial data clock for I/O operations.

41 SDIO I/O

43 DVDD_I/O I Digital Power Supply (for I/O Cells Only, 3.3 V). 44 SYNC_IN I

45 SYNC_CLK O Clock Output Pin that Serves as a Synchronizer for External Hardware. 46 OSK I

<49> AGND I

DGND I Digital Power Ground Pins.

AVDD I Analog Power Supply Pins (1.8 V).

AGND I Analog Power Ground Pins.

/REFCLK

OSC

IOUT

I

SET

COMP_IN

CS

The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin must be set up and held around the SYNC_CLK output signal.

I

Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in singleended mode, REFCLK

Reference Clock/Oscillator Input. See Clock Input section for details on the OSCILLATOR/REFCLK operation.

Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the oscillator section is bypassed.

This pin provides the connection for the external zero compensation network of the REFCLK multiplier’s PLL loop filter. The network consists of a 1 kΩ resistor in series with a 0.1 µF capacitor tied to AVDD.

O Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.

A resistor (3.92 kΩ nominal) connected from AGND to DAC_R for the DAC.

I Compartor Complementary Input

Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9952 to the initial state, as described in the I/O port register map.

Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is returned low. If unused, ground this pin; do not allow this pin to float.

When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When operated as a 2-wire serial port, this pin is unused and can be left unconnected.

I This pin functions as an active low chip select that allows multiple devices to share the I/O bus.

When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only. When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.

Input Signal Used to Synchronize Multiple AD9952s. This input is connected to the SYNC_CLK output of a master AD9952.

Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when Programmed for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin should be tied to DGND.

The exposed paddle on the bottom of the package is a ground connection for the DAC and must be attached to AGND in any board layout.

should be decoupled to AVDD with a 0.1 µF capacitor.

establishes the reference current

SET

Rev. 0 | Page 9 of 28

Analog Devices AD9952 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

GENERAL DESCRIPTION

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS