Analog Devices AD9887KS-140, AD9887KS-100, AD9887-PCB Datasheet

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

AD9887

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

Dual Interface for

Flat Panel Displays

FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth

0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS

3.3 V Power Supply
Full Sync Processing
Midscale Clamp
4:2:2 Output Format Mode

Digital (DVI 1.0 Compatible) Interface
112 MHz Operation (1 Pixel/Clock Mode)
High Skew Tolerance of One Full Input Clock
Sync Detect for “Hot Plugging”

APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Micro Displays
Digital TV

GENERAL DESCRIPTION

The AD9887 offers designers the flexibility of a dual analog and
digital interface for flat panel displays (FPDs) on a single chip.
Both interfaces are optimized for excellent image quality supporting
display resolutions up to SXGA (1280 × 1024 at 75 Hz). Either the
analog or the digital interface can be selected by the user.

Analog Interface

For ease of design and to minimize cost, the AD9887 is a fully
integrated interface solution for FPDs. The AD9887 includes an
analog interface with a 140 MHz triple ADC with internal 1.25 V
reference, PLL to generate a pixel clock from HSYNC, program­mable gain, offset, and clamp control. The user provides only a

3.3 V power supply, analog input, and HSYNC. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.

The AD9887’s on-chip PLL generates a pixel clock from HSYNC.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is 500 ps p-p typical at 140 MSPS. When a
COAST signal is presented, the PLL maintains its output fre­quency in the absence of HSYNC. A sampling phase adjustment is
provided. Data, HSYNC and Clock output phase relationships are
maintained. The PLL can be disabled and an external clock input
provided as the pixel clock. The AD9887 also offers full sync pro­cessing for composite sync and sync-on-green applications.

A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. The analog interface
is fully programmable via a 2-wire serial interface.

FUNCTIONAL BLOCK DIAGRAM

SERIAL REGISTER

AND

POWER MANAGEMENT

SCL

SDA

A

1

A

0

2

DATAC K

HSOUT

VSOUT

SOGOUT

Rx0+

Rx0–

Rx1+

Rx1–

Rx2+

Rx2–

RxC+

RxC–

R

TERM

DVI

RECEIVER

8

8

8

R

OUTA

R

OUTB

8

8

8

G

OUTA

G

OUTB

8

8

8

B

OUTA

B

OUTB

2

DATAC K

DE

HSYNC

VSYNC

AD9887

DIGITAL

INTERFACE

R

OUTA

R

OUTB

G

OUTA

G

OUTB

B

OUTA

B

OUTB

HSOUT

VSOUT

SOGOUT

DE

DATAC K

8

8

8

8

8

8

2

SYNC

PROCESSING

AND CLOCK

GENERATION

HSYNC

COAST

CLAMP

CKINV

CKEXT

FILT

CLAMP

R

AIN

CLAMP

G

AIN

CLAMP

B

AIN

A/D

8

8

8

R

OUTA

R

OUTB

A/D

8

8

8

G

OUTA

G

OUTB

A/D

8

8

8

B

OUTA

B

OUTB

ANALOG

INTERFACE

M
U
X
E
S

VSYNC

S

CDT

REFIN

REF

REFOUT

Digital Interface

The AD9887 contains a Digital Video Interface (DVI 1.0) compat­ible receiver. This receiver supports displays ranging from VGA
to SXGA (25 MHz to 112 MHz). The receiver operates with
true color (24-bit) panels in 1 or 2 pixel(s)/clock mode, and also
features an intrapair skew tolerance up to one full clock cycle.

Fabricated in an advanced CMOS process, the AD9887 is pro­vided in a 160-lead MQFP surface mount plastic package and is
specified over the 0°C to 70°C temperature range.

REV. 0

–2–

AD9887–SPECIFICATIONS

ANALOG INTERFACE

Test AD9887KS-100 AD9887KS-140

Parameter Temp Level Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bits

DC ACCURACY

Differential Nonlinearity 25°CI ± 0.5 +1.15/–1.0 ±0.5 +1.25/–1.0 LSB

Full VI +1.15/–1.0 +1.25/–1.0 LSB

Integral Nonlinearity 25°CI ± 0.5 ± 1.40 ± 0.5 ± 1.4 LSB

Full VI ± 1.75 ± 2.5 LSB

No Missing Codes Full VI Guaranteed Guaranteed

ANALOG INPUT

Input Voltage Range

Minimum Full VI 0.5 0.5 V p-p

Maximum Full VI 1.0 1.0 V p-p
Gain Tempco 25°C V 135 150 ppm/°C
Input Bias Current 25°CIV 1 1 µA

Full IV 1 1 µA
Input Offset Voltage Full VI 7 50 7 50 mV
Input Full-Scale Matching Full VI 8.0 8.0 % FS
Offset Adjustment Range Full VI 44 50 56 44 50 56 % FS

REFERENCE OUTPUT

Output Voltage Full VI 1.20 1.25 1.30 1.20 1.25 1.30 V

Temperature Coefficient Full V ±50 ± 50 ppm/°C

SWITCHING PERFORMANCE

1

Maximum Conversion Rate Full VI 100 140 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Clock to Data Skew, t

SKEW

Full IV –0.5 +2.0 –0.5 +2.0 ns
t

BUFF

Full VI 4.7 4.7 µs
t

STAH

Full VI 4.0 4.0 µs
t

DHO

Full VI 0 0 µs
t

DAL

Full VI 4.7 4.7 µs
t

DAH

Full VI 4.0 4.0 µs
t

DSU

Full VI 250 250 ns
t

STASU

Full VI 4.7 4.7 µs
t

STOSU

Full VI 4.0 4.0 µs
HSYNC Input Frequency Full IV 15 110 15 110 kHz
Maximum PLL Clock Rate Full VI 100 140 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
PLL Jitter 25°C IV 400 700

2

400 700

3

ps p-p

Full IV 1000

2

1000

3

ps p-p

Sampling Phase Tempco Full IV

15 15 ps/°C

DIGITAL INPUTS

Input Voltage, High (V

IH

) Full VI 2.6 2.6 V

Input Voltage, Low (V

IL

) Full VI 0.8 0.8 V

Input Current, High (V

IH

) Full IV –1.0 –1.0 µA

Input Current, Low (V

IL

) Full IV 1.0 1.0 µA

Input Capacitance 25°CV 3 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI 2.4 2.4 V
Output Voltage, Low (V

OL

) Full VI 0.4 0.4 V

Duty Cycle

DATACK, DATACK Full IV 45 50 55 45 50 55 %

Output Coding Binary Binary

(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)

REV. 0

–3–

AD9887

Test AD9887KS-100 AD9887KS-140

Parameter Temp Level Min Typ Max Min Typ Max Unit

POWER SUPPLY

VD Supply Voltage Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V
V

DD

Supply Voltage Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V

P

VD

Supply Voltage Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V

I

D

Supply Current (VD)25°C V 140 155 mA

I

DD

Supply Current (VDD)

4

25°C V 34 48 mA

IP

VD

Supply Current (PVD)25°C V 15 16 mA

Total Supply Current

4

Full VI 170 258 215 258 mA

Power-Down Supply Current Full VI 18 25 18 25 mA

DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power 25°C V 330 330 MHz
Transient Response 25°CV 2 2 ns
Overvoltage Recovery Time 25° C V 1.5 1.5 ns
Signal-to-Noise Ratio (SNR)

5

25°C V 46 46 dB
(Without Harmonics) Full V 45 45 dB
fIN = 40.7 MHz

Crosstalk Full V 60 60 dBc

THERMAL CHARACTERISTICS

θJA Junction-to-Ambient

6

V30 30 °C/W

Thermal Resistance

NOTES

1

Drive Strength = 11.

2

VCO Range = 01, Charge Pump Current = 001, PLL Divider = 1693.

3

VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1600.

4

DEMUX = 1, DATACK and DATACK Load = 10 pF, Data Load = 5 pF.

5

Using external pixel clock.

6

Simulated typical performance with package mounted to a 4-layer board.

Specifications subject to change without notice.

REV. 0

–4–

AD9887–SPECIFICATIONS

DIGITAL INTERFACE

Test AD9887KS

Parameter Conditions Level Min Typ Max Unit

RESOLUTION 8 Bits

DC DIGITAL I/O SPECIFICATIONS

High-Level Input Voltage, (V

IH

) VI 2.6 V

Low-Level Input Voltage, (V

IL

) VI 0.8 V

High-Level Output Voltage, (V

OH

) VI 2.4 V

Low-Level Output Voltage, (V

OL

) VI 0.4 V

Input Clamp Voltage, (V

CINL

)(I

CL

= –18 mA) IV GND – 0.8 V

Input Clamp Voltage, (V

CIPL

)(I

CL

= +18 mA) IV VDD + 0.8 V

Output Clamp Voltage, (V

CONL

)(I

CL

= –18 mA) IV GND – 0.8 V

Output Clamp Voltage, (V

COPL

)(I

CL

= +18 mA) IV VDD + 0.8 V

Output Leakage Current, (IOL) (High Impedance) IV –10 +10 µA

DC SPECIFICATIONS

Output High Drive Output Drive = High IV 13 mA

(I

OHD

) (V

OUT

= VOH) Output Drive = Med IV 8 mA

Output Drive = Low IV 5 mA
Output Drive = High IV –9 mA

(I

OLD

) (V

OUT

= VOL) Output Drive = Med IV –7 mA

Output Drive = Low IV –5 mA
Output Drive = High IV 25 mA

(V

OHC

) (V

OUT

= VOH) Output Drive = Med IV 12 mA

Output Drive = Low IV 8 mA

DATACK Low Drive Output Drive = High IV –25 mA

(V

OLC

) (V

OUT

= VOL) Output Drive = Med IV –19 mA

Output Drive = Low IV –8 mA

Differential Input Voltage Single-Ended Amplitude IV 75 800 mV

POWER SUPPLY

V

D

Supply Voltage IV 3.0 3.3 3.6 V

V

DD

Supply Voltage Minimum Value for 2 Pixels per

Clock Mode IV 2.2 3.3 3.6 V

P

VD

Supply Voltage IV 3.0 3.3 3.6 V

V

D

Supply Current (Typical Pattern)

1

V 274 mA

VDD Supply Current (Typical Pattern)

1, 4

V38 mA

P

VD

Supply Current (Typical Pattern)

1

V21 mA

Total Supply Current (Typical Pattern)

1, 4

VI 362 mA

V

D

Supply Current (Worst-Case Pattern)

2

V 280 mA

V

DD

Supply Current (Worst-Case Pattern)

2, 4

V75 mA

P

VD

Supply Current (Worst-Case Pattern)

2

V21 mA

Total Supply Current (Worst-Case Pattern)

2, 4

VI 400 mA

Power-Down Supply Current (IPD)VI1325mA

AC SPECIFICATIONS

Intrapair (+ to –) Differential Input Skew (T

DPS

) IV 360 ps

Channel-to-Channel Differential Input Skew (T

CCS

) IV 1.0 Clock

Period

Low-to-High Transition Time for Data and Output Drive = High; CL = 10 pF IV 2.0 ns

Controls (D

LHT

) Output Drive = Med; CL = 7 pF IV 3.0 ns

Output Drive = Low; C

L

= 5 pF IV 3.4 ns

Low-to-High Transition Time for DATACK (D

LHT

) Output Drive = High; CL = 10 pF IV 1.3 ns

Output Drive = Med; C

L

= 7 pF IV 1.9 ns

Output Drive = Low; C

L

= 5 pF IV 2.5 ns

High-to-Low Transition Time for Data and Output Drive = High; C

L

= 10 pF IV 2.7 ns

Controls (D

HLT

) Output Drive = Med; CL = 7 pF IV 3.0 ns

Output Drive = Low; CL = 5 pF IV 3.3 ns

(VD = 3.3 V, VDD = 3 V, Clock = Maximum)

REV. 0

–5–

AD9887

Test AD9887KS

Parameter Conditions Level Min Typ Max Unit

AC SPECIFICATIONS (continued)

High-to-Low Transition Time for DATACK (D

HLT

) Output Drive = High; CL =10 pF IV 1.4 ns

Output Drive = Med; C

L

= 7 pF IV 1.7 ns

Output Drive = Low; C

L

= 5 pF IV 2.1 ns

Clock to Data Skew, t

SKEW

IV –0.5 +2.0 ns

Duty Cycle, t

DCYCLE

IV 45 55 % of

Period
High

DATACK Frequency (F

CIP

) (1 Pixel/Clock) VI 20 112 MHz

DATACK Frequency (F

CIP

) (2 Pixels/Clock) IV 10 56 MHz

NOTES

1

The typical pattern contains a gray scale area, Output Drive = High.

2

The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High.

3

The setup and hold times with respect to the DATACK rising edge are the same as the falling edge.

4

1 Pixel/clock mode, DATACK and DATACK Load = 10 pF, Data Load = 5 pF.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9887 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

*

VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V

V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V

D

to 0.0 V

VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

D

to 0.0 V

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Test Level Explanation

I 100% production tested.
II 100% production tested at 25°C and sample

tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and charac-

terization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed

by design and characterization testing.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9887KS-140 0°C to 70°C Plastic Quad Flatpack S-160
AD9887KS-100 0°C to 70°C Plastic Quad Flatpack S-160
AD9887/PCB 25°C Evaluation Board

REV. 0

–6–

AD9887

PIN CONFIGURATION

RED B<0>

RED B<1>

RED B<2>

RED B<3>

RED B<4>

RED B<5>

RED B<6>

RED B<7>

GND

VDDRED A<0>

RED A<1>

RED A<2>

RED A<3>

RED A<4>

RED A<5>

RED A<6>

RED A<7>

GND

VDDSOGOUT

HSOUT

VSOUTDES

CDT

DATACK

DATACK

GND

VDDGND

GND

SCANINGND

VDREF

OUT

REFINVDVDGND

GND

160

159

158

157

156

155

154

153

152

151

150

149

147

146

145

144

143

142

141

140

139

138

148

137

136

135

133

132

131

130

129

128

134

127

126

125

123

122

121

124

GND

GND

V

DD

GND

SCAN

OUT

CTL0

CTL1

CTL2

CTL3

SCAN

CLK

V

D

GND

R

TERM

VDV

D

Rx2+

Rx2–

GND

Rx1+

Rx1–

GND

Rx0+

Rx0–

GND

RxC+

RxC–

V

DVD

GND

V

D

NCNCNC

GND

PV

D

GND

PV

D

FILT

PV

D

GND

535455565758596061

62

4142434445464748495051

52

6364656668697071726773747576787980

77

5

4

3

2

7

6

9

8

1

14

13

12

11

16

15

17

10

19

18

23

22

21

20

25

24

27

26

29

28

32

31

30

34

33

36

35

40

39

38

37

V

DD

GND
GREEN A<7>
GREEN A<6>
GREEN A<5>
GREEN A<4>
GREEN A<3>
GREEN A<2>
GREEN A<1>
GREEN A<0>

V

DD

GND
GREEN B<7>
GREEN B<6>
GREEN B<5>
GREEN B<4>
GREEN B<3>
GREEN B<2>
GREEN B<1>
GREEN B<0>

V

DD

GND

BLUE A<7>
BLUE A<6>
BLUE A<5>
BLUE A<4>
BLUE A<3>
BLUE A<2>
BLUE A<1>
BLUE A<0>

V

DD

GND

BLUE B<7>
BLUE B<6>
BLUE B<5>
BLUE B<4>
BLUE B<3>
BLUE B<2>
BLUE B<1>
BLUE B<0>

R

MIDSC

V

R

AIN

R

CLAMP

V

V

D

GND
V

D

V

D

GND
GND
G

MIDSC

V

G

AIN

G

CLAMP

V
SOGIN
V

D

GND
V

D

V

D

GND
GND
B

MIDSC

V

B

AIN

B

CLAMP

V
V

D

GND
V

D

GND
CKINV
CLAMP
SDA
SCL
A0
A1
PV

D

PV

D

GND
GND
COAST
CKEXT
HSYNC
VSYNC

104

119

120

114

115

116

117

112

113

111

118

109

110

105

106

107

108

102

103

100

101

98

99

95

96

97

93

94

91

92

90

87

88

89

86

84

85

82

83

81

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AD9887

NC = NO CONNECT

REV. 0

AD9887

–7–

Table I. Complete Pinout List

P

in Pin Pin

Type Name Function Value Number Interface

Analog Video R

AIN

Analog Input for Converter R 0.0 V to 1.0 V 119 Analog

Inputs G

AIN

Analog Input for Converter G 0.0 V to 1.0 V 110 Analog

B

AIN

Analog Input for Converter B 0.0 V to 1.0 V 100 Analog

External HSYNC Horizontal SYNC Input 3.3 V CMOS 82 Analog
Sync/Clock VSYNC Vertical SYNC Input 3.3 V CMOS 81 Analog
Inputs SOGIN Input for Sync-on-Green 0.0 V to 1.0 V 108 Analog

CLAMP Clamp Input (External CLAMP Signal) 3.3 V CMOS 93 Analog
COAST PLL COAST Signal Input 3.3 V CMOS 84 Analog
CKEXT External Pixel Clock Input (to Bypass the PLL) to V

DD

or Ground 3.3 V CMOS 83 Analog

CKINV ADC Sampling Clock Invert 3.3 V CMOS 94 Analog

Sync Outputs HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) 3.3 V CMOS 139 Both

VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) 3.3 V CMOS 138 Both
SOGOUT Sync on Green Slicer Output 3.3 V CMOS 140 Analog

Voltage REFOUT Internal Reference Output (Bypass with 0.1 µF to Ground) 1.25 V 126 Analog
Reference REFIN Reference Input (1.25 V ± 10%) 1.25 V ± 10% 125 Analog

Clamp Voltages R

MIDSC

V Red Channel Midscale Clamp Voltage Output 120 Analog

R

CLAMP

V Red Channel Midscale Clamp Voltage Input 0.0 V to 0.75 V 118 Analog

G

MIDSC

V Green Channel Midscale Clamp Voltage Output 111 Analog

G

CLAMP

V Green Channel Midscale Clamp Voltage Input 0.0 V to 0.75 V 109 Analog

B

MIDSC

V Blue Channel Midscale Clamp Voltage Output 101 Analog

B

CLAMP

V Blue Channel Midscale Clamp Voltage Input 0.0 V to 0.75 V 99 Analog

PLL Filter FILT Connection for External Filter Components for Internal PLL 78 Analog

Power Supply V

D

Analog Power Supply 3.3 V ± 10% Both

V

DD

Output Power Supply 3.3 V ± 10% Both

PV

D

PLL Power Supply 3.3 V ± 10% Both

GND Ground 0 V Both

Serial Port SDA Serial Port Data I/O 3.3 V CMOS 92 Both
(2-Wire SCL Serial Port Data Clock (100 kHz Max) 3.3 V CMOS 91 Both
Serial Interface) A0 Serial Port Address Input 1 3.3 V CMOS 90 Both

A1 Serial Port Address Input 2 3.3 V CMOS 89 Both

Data Outputs Red B[7:0] Port B/Odd Outputs of Converter “Red,” Bit 7 Is the MSB 3.3 V CMOS 153–160 Both

Green B[7:0] Port B/Odd Outputs of Converter “Green,” Bit 7 Is the MSB 3.3 V CMOS 13–20 Both
Blue B[7:0] Port B/Odd Outputs of Converter “Blue,” Bit 7 Is the MSB 3.3 V CMOS 33–40 Both
Red A[7:0] Port A/Even Outputs of Converter “Red,” Bit 7 Is the MSB 3.3 V CMOS 143–150 Both
Green A[7:0] Port A/Even Outputs of Converter “Green,” Bit 7 Is the MSB 3.3 V CMOS 3–10 Both
Blue A[7:0] Port A/Even Outputs of Converter “Blue,” Bit 7 Is the MSB 3.3 V CMOS 23–30 Both

Data Clock DATACK Data Output Clock for the Analog and Digital Interface 3.3 V CMOS 134 Both
Outputs DATACK Data Output Clock Complement for the Analog Interface Only 3.3 V CMOS 135 Both

Sync Detect S

CDT

Sync Detect Output 3.3 V CMOS 136 Both

Scan Function SCAN

IN

Input for SCAN Function 3.3 V CMOS 129 Both

SCAN

OUT

Output for SCAN Function 3.3 V CMOS 45 Both

SCAN

CLK

Clock for SCAN Function 3.3 V CMOS 50 Both

No Connect NC These Pins Should be Left Unconnected 71–73 Both

Digital Video R

x0

+ Digital Input Channel 0 True 62 Digital

Data Inputs R

x0

– Digital Input Channel 0 Complement 63 Digital

R

x1

+ Digital Input Channel 1 True 59 Digital

R

x1

– Digital Input Channel 1 Complement 60 Digital

R

x2

+ Digital Input Channel 2 True 56 Digital

Rx2– Digital Input Channel 2 Complement 57 Digital

Digital Video R

xc

+ Digital Data Clock True 65 Digital

Clock Inputs Rxc– Digital Data Clock Complement 66 Digital

Data Enable DE Data Enable 3.3 V CMOS 137 Digital

Control Bits CTL[0:3] Decoded Control Bits 3.3 V CMOS 46–49 Digital

R

TERM

R

TERM

Sets Internal Termination Resistance 53 Digital

REV. 0

–8–

AD9887

DESCRIPTIONS OF PINS SHARED BETWEEN ANALOG
AND DIGITAL INTERFACES

HSOUT Horizontal Sync Output

A reconstructed and phase-aligned version of
the video HSYNC. The polarity of this output
can be controlled via a serial bus bit. In analog
interface mode the placement and duration
are variable. In digital interface mode the
placement and duration are set by the graphics
transmitter.

VSOUT Vertical Sync Output

The separated VSYNC from a composite
signal or a direct pass through of the VSYNC
input. The polarity of this output can be con­trolled via a serial bus bit. The placement and
duration in all modes is set by the graphics
transmitter.

Serial Port (2-Wire)

SDA Serial Port Data I/O
SCL Serial Port Data Clock
A0 Serial Port Address Input 1
A1 Serial Port Address Input 2

For a full description of the 2-wire serial regis­ter and how it works, refer to the Control
Register section.

Data Outputs

RED A Data Output, Red Channel, Port A/Even
RED B Data Output, Red Channel, Port B/Odd
GREEN A Data Output, Green Channel, Port A/Even
GREEN B Data Output, Green Channel, Port B/Odd
BLUE A Data Output, Blue Channel, Port A/Even
BLUE B Data Output, Blue Channel, Port B/Odd

The main data outputs. Bit 7 is the MSB.
These outputs are shared between the two
interfaces and behave according to which
interface is active. Refer to the sections on the
two interfaces for more information on how
these outputs behave.

Data Clock Outputs

DATACK Data Output Clock
DATACK Data Output Clock Complement

Just like the data outputs, the data clock out­puts are shared between the two interfaces.
They also behave differently depending on
which interface is active. Refer to the sections
on the two interfaces to determine how these
pins behave.

Various

S

CDT

Chip Active/Inactive Detect Output

The logic for the S

CDT

pin is [analog interface
HSYNC detection] OR [digital interface DE
detection]. So, the S

CDT

pin will switch to
logic LOW under two conditions, when nei­ther interface is active or when the chip is in
full chip power-down mode. The data outputs
are automatically three-stated when S

CDT

is
LOW. This pin can be read by a controller in
order to determine periods of inactivity.

SCAN Function

SCAN

IN

Data Input for SCAN Function

Data can be loaded serially into the 48-bit
SCAN register through this pin, clocking it in
with the SCAN

CLK

pin. It then comes out of
the 48 data outputs in parallel. This function
is useful for loading known data into a graph­ics controller chip for testing purposes.

SCAN

OUT

Data Output for SCAN Function

The data in the 48-bit SCAN register can be
read through this pin. Data is read on a FIFO
basis and is clocked via the SCAN

CLK

pin.

SCAN

CLK

Data Clock for SCAN Function

This pin clocks the data through the SCAN
register. It controls both data input and data
output.

REV. 0

AD9887

–9–

Table II. Analog Interface Pin List

Pin Type Pin Name Function Value Pin No.

Analog Video Inputs R

AIN

Analog Input for Converter R 0.0 V to 1.0 V 119

G

AIN

Analog Input for Converter G 0.0 V to 1.0 V 110

B

AIN

Analog Input for Converter B 0.0 V to 1.0 V 100

External HSYNC Horizontal SYNC Input 3.3 V CMOS 82

VSYNC Vertical SYNC Input 3.3 V CMOS 81
Sync/Clock SOGIN Sync-on-Green Input 0.0 V to 1.0 V 108
Inputs CLAMP Clamp Input (External CLAMP Signal) 3.3 V CMOS 93

COAST PLL COAST Signal Input 3.3 V CMOS 84

CKEXT External Pixel Clock Input (to Bypass Internal PLL) 3.3 V CMOS 83

or 10 kΩ to V

DD

CKINV ADC Sampling Clock Invert 3.3 V CMOS 94
Sync Outputs HSOUT HSYNC Output (Phase-Aligned with DATACK and DATACK) 3.3 V CMOS 139

VSOUT VSYNC Output (Asynchronous) 3.3 V CMOS 138

SOGOUT Sync-on-Green Slicer Output or Raw HSYNC Output 3.3 V CMOS 140
Voltage Reference REFOUT Internal Reference Output (bypass with 0.1 µF to ground) 1.25 V 126

REFIN Reference Input (1.25 V ± 10%) 1.25 V ± 10% 125
Clamp Voltages R

MIDSC

V Voltage output equal to the RED converter midscale voltage. 0.5 V ± 50% 120

R

CLAMP

V During midscale clamping, the RED Input is clamped to this pin. 0.0 V to 0.75 V 118

G

MIDSC

V Voltage output equal to the GREEN converter midscale voltage. 0.5 V ± 50% 111

G

CLAMP

V During midscale clamping, the GREEN Input is clamped to this pin. 0.0 V to 0.75 V 109

B

MIDSC

V Voltage output equal to the BLUE converter midscale voltage. 0.5 V ± 50% 101

B

CLAMP

V During midscale clamping, the BLUE Input is clamped to this pin. 0.0 V to 0.75 V 99
PLL Filter FILT Connection for External Filter Components for Internal PLL 78
Power Supply V

D

Main Power Supply 3.3 V ± 5%

PV

D

PLL Power Supply (Nominally 3.3 V) 3.3 V ± 5%

V

DD

Output Power Supply 3.3 V or 2.5 V ± 5%

GND Ground 0 V

PIN FUNCTION DETAILS (ANALOG INTERFACE)
Inputs

R

AIN

Analog Input for RED Channel

G

AIN

Analog Input for GREEN Channel

B

AIN

Analog Input for BLUE Channel

High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. For RGB, the three channels

are
identical and can be used for any colors, but
colors are assigned for convenient reference.
For proper 4:2:2 formatting in a YUV

appli-

cation, the Y channel must be connected

to

the G

AIN

input, U must be connected to the

B

AIN

input, and V must be connected to the

R

AIN

input.

They accommodate input signals ranging
from 0.5 V to 1.0 V full scale. Signals should
be ac-coupled to these pins to support clamp
operation.

HSYNC Horizontal Sync Input

This input receives a logic signal that estab­lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.

The logic sense of this pin is controlled by
serial register 0Fh Bit 7 (HSYNC Polarity).
Only the leading edge of HSYNC is active,
the trailing edge is ignored. When HSYNC

Polarity = 0, the falling edge of HSYNC is
used. When HSYNC Polarity = 1, the rising
edge is active.

The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.

Electrostatic Discharge (ESD) protection
diodes will conduct heavily if this pin is driven
more than 0.5 V above the maximum toler­ance voltage (3.3 V), or more than 0.5 V
below ground.

VSYNC Vertical Sync Input

This is the input for vertical sync.

SOGIN Sync-on-Green Input

This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally
generated threshold, which is set to 0.15 V
above the negative peak of the input signal.

When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.

When not used, this input should be left
unconnected. For more details on this func­tion and how it should be configured, refer to
the Sync-on-Green section.

REV. 0

–10–

AD9887

CLAMP External Clamp Input (Optional)

This logic input may be used to define the
time during which the input signal is clamped
to the reference dc level, (ground for RGB or
midscale for YUV). It should be exercised
when the reference dc level is known to be
present on the analog input channels, typically
during the back porch of the graphics signal.
The CLAMP pin is enabled by setting control
bit EXTCLMP to 1, (the default power-up is 0).
When disabled, this pin is ignored and the
clamp timing is determined internally by
counting a delay and duration from the trailing
edge of the HSYNC input. The logic sense of
this pin is controlled by CLAMPOL. When
not used, this pin must be grounded and
EXTCLMP programmed to 0.

COAST Clock Generator Coast Input (Optional)

This input may be used to cause the pixel clock
generator to stop synchronizing with HSYNC
and continue producing a clock at its current
frequency and phase. This is useful when
processing signals from sources that fail to
produce horizontal sync pulses when in the
vertical interval. The COAST signal is generally
not required for PC-generated signals. Appli­cations requiring COAST can do so through
the internal COAST found in the SYNC
processing engine.

The logic sense of this pin is controlled by
COAST Polarity.

When not used, this pin may be grounded and
COAST Polarity programmed to 1, or tied
HIGH and COAST Polarity programmed to 0.
COAST Polarity defaults to 1 at power-up.

CKEXT External Clock Input (Optional)

This pin may be used to provide an external
clock to the AD9887, in place of the clock
internally generated from HSYNC.

It is enabled by programming EXTCLK to 1.
When an external clock is used, all other internal
functions operate normally. When unused, this
pin should be tied to V

DD

or to GROUND, and

EXTCLK programmed to 0. The clock

phase

adjustment still operates when an external

clock

source is used.

CKINV Sampling Clock Inversion (Optional)

This pin may be used to invert the pixel
sampling clock, which has the effect of
shifting the sampling phase 180°. This is in
support of Alternate Pixel Sampling mode,
wherein higher-frequency input signals (up
to 280 Mpps) may be captured by first sam­pling the odd pixels, then capturing the even
pixels on the subsequent frame.

This pin should be exercised only during blanking
intervals (typically vertical blanking) as it may
produce several samples of corrupted data during
the phase shift.

CKINV should be grounded when not used.

Outputs

DRA

7-0

Data Output, Red Channel, Port A

D

RB7-0

Data Output, Red Channel, Port B

D

GA7-0

Data Output, Green Channel, Port A

D

GB7-0

Data Output, Green Channel, Port B

D

BA7-0

Data Output, Blue Channel, Port A

D

BB7-0

Data Output, Blue Channel, Port B

These are the main data outputs. Bit 7 is the MSB.

Each channel has two ports. When the part is
operated in single-channel mode (DEMUX = 0),
all data are presented to Port A, and Port B is
placed in a high-impedance state.

Programming DEMUX to 1 established dual­channel mode, wherein alternate pixels are
presented to Port A and Port B of each chan­nel. These will appear simultaneously, two
pixels presented at the time of every second
input pixel, when PAR is set to 1 (parallel
mode). When PAR = 0, pixel data appear
alternately on the two ports, one new sample
with each incoming pixel (interleaved mode).

In dual channel mode, the first pixel after
HSYNC is routed to Port A. The second pixel
goes to Port B, the third to A, etc.

The delay from pixel sampling time to output is
fixed. When the sampling time is changed by
adjusting the PHASE register, the output timing is
shifted as well. The DATACK, DATACK, and
HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.

DATACK Data Output Clock
DATACK Data Output Clock Complement

Differential data clock output signals to be
used to strobe the output data and HSOUT
into external logic.

They are produced by the internal clock gen­erator and are synchronous with the internal
pixel sampling clock.

When the AD9887 is operated in single-chan­nel mode, the output frequency is equal to the
pixel sampling frequency. When operating in
dual channel mode, the clock frequency is one­half the pixel frequency.

When the sampling time is changed by adjusting
the PHASE register, the output timing is

shifted

as well. The Data, DATACK,

DATACK, and

HSOUT outputs are all moved, so the timing
relationship among the signals is maintained.

REV. 0

AD9887

–11–

Either or both signals may be used, depend­ing on the timing mode and interface design
employed.

HSOUT Horizontal Sync Output

A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and dura­tion of this output can be programmed via
serial bus registers.

By maintaining alignment with DATACK,
DATACK, and Data, data timing with
respect to horizontal sync can always be
determined.

SOGOUT Sync-On-Green Slicer Output

This pin can be programmed to output
either the output from the Sync-On-Green
slicer comparator or an unprocessed but
delayed version of the HSYNC input. See
the Sync Block Diagram to view how this
pin is connected.

(Note: The output from this pin is the sliced
SOG, without additional processing from the
AD9887.)

Analog Interface

REFOUT Internal Reference Output

Output from the internal 1.25 V bandgap refer­ence. This output is intended to drive relatively
light loads. It can drive the AD9887 Reference
Input directly, but should be externally buff­ered if it is used to drive other loads as well.

The absolute accuracy of this output is ±4%,
and the temperature coefficient is ±50 ppm,
which is adequate for most AD9887 appli­cations. If higher accuracy is required, an
external reference may be employed instead.

If an external reference is used, connect this
pin to ground through a 0.1 µF capacitor.

REFIN Reference Input

The reference input accepts the master refer­ence voltage for all AD9887 internal circuitry
(1.25 V ± 10%). It may be driven directly by
the REFOUT pin. Its high impedance pre­sents a very light load to the reference source.

This pin should always be bypassed to Ground
with a 0.1 µF capacitor.

FILT External Filter Connection

For proper operation, the pixel clock genera­tor PLL requires an external filter. Connect
the filter shown Figure 7 to this pin. For
optimal performance, minimize noise and
parasitics on this node.

Power Supply

V

D

Main Power Supply

These pins supply power to the main elements
of the circuit. It should be filtered

to be

as

quiet

as possible.

V

DD

Digital Output Power Supply

These supply pins are identified separately
from the V

D

pins so special care can be taken
to minimize output noise transferred into the
sensitive analog circuitry.

If the AD9887 is interfacing with lower­voltage logic, V

DD

may be connected to a
lower supply voltage (as low as 2.2 V) for
compatibility.

PV

D

Clock Generator Power Supply

The most sensitive portion of the AD9887 is
the clock generation circuitry. These pins
provide power to the clock PLL and help the
user design for optimal performance. The
designer should provide noise-free power to
these pins.

GND Ground

The ground return for all circuitry on chip.
It is recommended that the application circuit
board have a single, solid ground plane.

THEORY OF OPERATION (INTERFACE DETECTION)
Active Interface Detection and Selection

The AD9887 includes circuitry to detect whether or not an
interface is active.

For detecting the analog interface, the circuitry monitors the
presence of HSYNC, VSYNC, and Sync-on-Green. The result of
the detection circuitry can be read from the 2-wire serial inter­face bus at address 11H Bits 7, 6, and 5 respectively. If one of
these sync signals disappears, the maximum time it takes for the
circuitry to detect it is 100 ms.

There are two stages for detecting the digital interface. The first
stage searches for the presence of the digital interface clock.
The circuitry for detecting the digital interface clock is active
even when the digital interface is powered down. The result of
this detection stage can be read from the 2-wire serial interface
bus at address 11H Bit 4. If the clock disappears, the maximum
time it takes for the circuitry to detect it is 100 ms. The second
stage attempts to detect DE on the digital interface. Detection is
accomplished when 32 DEs have been counted. DE can only be
detected when the digital interface is powered up, so it is not
always active. The DE detection circuitry is one of the logic
inputs used to set the SyncDT output pin (Pin 136). The logic
for the SyncDT pin is [DE detect] OR [HSYNC detect].

There is an override for the automatic interface selection. It is
the AIO bit (Active Interface Override). When the AIO bit is set
to Logic 0, the automatic circuitry will be used. When the AIO
bit is set to Logic 1, the AIS bit will be used to determine the
active interface rather than the automatic circuitry.

REV. 0

–12–

AD9887

Table III. Interface Selection Controls

Analog Digital Active

AIO Interface Detect Interface Detect AIS Interface Description

1 X X 0 Analog Force the analog interface active.

1 Digital Force the digital interface active.

0 0 0 X None Neither interface was detected. Both interfaces are

powered down and the SyncDT pin gets set to Logic 0.

0 1 X Digital The digital interface was detected. Power down the

analog interface.

1 0 X Analog The analog interface was detected. Power down the

digital interface.

1 0 X Analog Both interfaces were detected. The analog interface has

priority.

1 Digital Both interfaces were detected. The digital interface has

priority.

Table IV. Power-Down Mode Descriptions

Inputs

Analog Digital Active Active

Power- Interface Interface Interface Interface

Mode Down1Detect2Detect3Override Select Powered On or Comments

Soft Power-Down (Seek Mode) 1 0 0 0 X Serial Bus, Digital Interface Clock Detect,

Analog Interface Activity Detect, SOG,
Bandgap Reference

Digital Interface On 1 0 1 0 X Serial Bus, Digital Interface, Analog Interface

Activity Detect, SOG, Outputs, Bandgap
Reference

Analog Interface On 1 1 0 0 X Serial Bus, Analog Interface, Digital Interface

Clock Detect, SOG, Outputs, Bandgap

Reference
Serial Bus Arbitrated Interface 1 1 1 0 0 Same as Analog Interface On Mode
Serial Bus Arbitrated Interface 1 1 1 0 1 Same as Digital Interface On Mode
Override to Analog Interface 1 X X 1 0 Same as Analog Interface On Mode
Override to Digital Interface 1 X X 1 1 Same as Digital Interface On Mode
Absolute Power-Down 0 X X X X Serial Bus

NOTES

1

Power-down is controlled via bit 0 in serial bus Register 12h.

2

Analog Interface Detect is determined by OR-ing Bits 7, 6, and 5 in serial bus Register 11h.

3

Digital Interface Detect is determined by Bit 4 in serial bus Register 11h.

Power Management

The AD9887 is a dual interface device with shared outputs.
Only one interface can be used at a time. For this reason, the
chip automatically powers down the unused interface. When
the analog interface is being used, most of the digital interface
circuitry is powered down and vice-versa. This helps to minimize
the AD9887 total power dissipation. In addition, if neither inter­face has activity on it, the chip powers down both interfaces.

The AD9887 uses the activity detect circuits, the active inter­face bits in the serial registers, the active interface override bits,

and the power-down bit to determine the correct power state.
In a given power mode not all circuitry in the inactive interface
is powered down completely. When the digital interface is
active, the bandgap reference and HSYNC detect circuitry is not
powered down. When the analog interface is active, the digital
interface clock detect circuit is not powered down. Table IV
summarizes how the AD9887 determines which power mode to
be in and what circuitry is powered on/off in each of these
modes. The power-down command has priority, followed by the
active interface override, and then the automatic circuitry.