ANALOG DEVICES AD 9835 BRU Datasheet

50 MHz CMOS

a

FEATURES
5 V Power Supply
50 MHz Speed
On-Chip COS Look-Up Table
On-Chip 10-Bit DAC
Serial Loading
Power-Down Option
200 mW Power Consumption
16-Lead TSSOP

APPLICATIONS
DDS Tuning
Digital Demodulation

MCLK

FSELECT

FSELECT

BIT

GENERAL DESCRIPTION

The AD9835 is a numerically controlled oscillator employing
a phase accumulator, a COS Look-Up Table and a 10-bit
D/A converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.

Clock rates up to 50 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is ef­fected by loading registers through the serial interface. A
power-down bit allows the user to power down the AD9835 when
it is not in use, the power consumption being reduced to 1.75 mW.
The part is available in a 16-lead TSSOP package.

FUNCTIONAL BLOCK DIAGRAM

DVDD

SELSRC

SYNC

AVDDDGND

AGND

REFERENCE

REFOUT

ON-BOARD

REFINFS ADJUST

FULL-SCALE

CONTROL

Complete DDS

AD9835

COMP

FREQ0 REG

MUX

FREQ1 REG

SYNC

16-BIT DATA REGISTER

8 LSBs8 MSBs

DECODE LOGIC

SERIAL REGISTER

FSYNC SCLK SDATA

PHASE

ACCUMULATOR

(32 BIT)

PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG

DEFER REGISTER

CONTROL REGISTER

FSELECT/PSEL REGISTER

MUX

12

Σ

COS
ROM

SELSRC

AD9835

SYNC

SYNC

PSEL0

BIT

PSEL0

10-BIT

DAC

PSEL1

PSEL1

BIT

IOUT

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD9835–SPECIFICATIONS

(VDD = +5 V ⴞ 5%; AGND = DGND = 0 V; TA = T

1

R

= 3.9 k⍀; R

SET

= 300 ⍀ for IOUT, unless otherwise noted)

LOAD

MIN

to T

; REFIN = REFOUT;

MAX

Parameter AD9835B Units Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution 10 Bits
Update Rate (f
IOUT Full Scale 4 mA

) 50 MSPS nom

MAX

nom

4.75 mA max
Output Compliance 1.35 V max
DC Accuracy

Integral Nonlinearity ±1 LSB typ
Differential Nonlinearity ±0.5 LSB typ

DDS SPECIFICATIONS

2

Dynamic Specifications

Signal-to-Noise Ratio 50 dB min f
Total Harmonic Distortion –52 dBc max f
Spurious Free Dynamic Range (SFDR)

3

= 50 MHz, f

MCLK

= 50 MHz, f

MCLK

f

= 6.25 MHz, f

MCLK

= 1 MHz

OUT

= 1 MHz

OUT

= 2.11 MHz

OUT

Narrow Band (±50 kHz) –72 dBc min
Wide Band (±2 MHz) –50 dBc min

Clock Feedthrough –60 dBc typ
Wake-Up Time 1 ms typ
Power-Down Option Yes

VOLTAGE REFERENCE

Internal Reference @ +25°C 1.21 V typ

T

MIN

to T

MAX

1.21 ± 7% V min/max
REFIN Input Impedance 10 MΩ typ
Reference TC 100 ppm/°C typ
REFOUT Output Impedance 300 Ω typ

LOGIC INPUTS

V

, Input High Voltage DVDD – 0.9 V min

INH

, Input Low Voltage 0.9 V max

V

INL

, Input Current 10 µA

I

INH

max

CIN, Input Capacitance 10 pF max

POWER SUPPLIES f

AVDD 4.75/5.25 V
DVDD 4.75/5.25 V
I

AA

I

DD

I

AA

+ I

DD

4

5mA

2.5 + 0.33/MHz mA typ

40 mA max

min/V max
min/V max

max

= 50 MHz

MCLK

Low Power Sleep Mode 0.35 mA max

NOTES

1

Operating temperature range is as follows: B Version: –40 °C to +85°C.

2

100% production tested.

3

f

= 6.25 MHz, Frequency Word = 5671C71C HEX, f

MCLK

4

Measured with the digital inputs static and equal to 0 V or DVDD. The AD9835 is tested with a capacitive load of 50 pF. The part can be operated with higher
capacitive loads, but the magnitude of the analog output will be attenuated. See Figure 5.

Specifications subject to change without notice.

= 2.11 MHz.

OUT

R

SET

10-BIT

DAC

3.9kV

FS
ADJUST

COMP

AD9835

AVDD

10nF

IOUT

300V 50pF

10nF

REFOUT

ON-BOARD

REFERENCE

12

COS
ROM

REFIN

FULL-SCALE

CONTROL

Figure 1. Test Circuit with Which Specifications Are Tested

–2– REV. 0

AD9835

t

11A

t

11

VALID DATA VALID DATA VALID DATA

MCLK

FSELECT

PSEL0, PSEL1

TIMING CHARACTERISTICS

(VDD = +5 V ⴞ 5%; AGND = DGND = 0 V, unless otherwise noted)

Limit at

to T

T

MIN

MAX

Parameter (B Version) Units Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

20 ns min MCLK Period
8 ns min MCLK High Duration
8 ns min MCLK Low Duration
50 ns min SCLK Period
20 ns min SCLK High Duration
20 ns min SCLK Low Duration
15 ns min FSYNC to SCLK Falling Edge Setup Time
20 ns min FSYNC to SCLK Hold Time
SCLK – 5 ns max

t

9

t

10

t

11

1

t

11A

NOTES

1

See Pin Description section.

Guaranteed by design but not production tested.

15 ns min Data Setup Time
5 ns min Data Hold Time
8 ns min FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
8 ns min FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

t

1

MCLK

t

2

t

3

Figure 2. Master Clock

SCLK

FSYNC

SDATA

t

t

5

4

t

7

D15 D14 D2 D1 D0 D15 D14

t

6

t

10

t

9

t

8

Figure 3. Serial Timing

Figure 4. Control Timing

–3–REV. 0

AD9835

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND. . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C

TSSOP θ

Thermal Impedance . . . . . . . . . . . . . . . 158°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9835BRU –40°C to +85°C 16-Lead TSSOP RU-16

*RU = Thin Shrink Small Outline Package (TSSOP).

PIN CONFIGURATION

REFIN

DVDD

DGND

MCLK
SCLK

SDATA

1
2

3

AD9835

4

TOP VIEW

5

(Not to Scale)

6
7

8

16
15

14
13
12
11

10

9

COMP
AVDD
IOUT
AGND
PSEL0
PSEL1

FSELECT
FSYNC

FS ADJUST

REFOUT

TERMINOLOGY
Integral Nonlinearity

This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end­points of the transfer function are zero scale, a point 0.5 LSB
below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.

Differential Nonlinearity

This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.

Signal to (Noise + Distortion)

Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (f

/2) but exclud-

MCLK

ing the dc component. Signal to (Noise + Distortion) is depen­dent on the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise.
The theoretical Signal to (Noise + Distortion) ratio for a sine
wave input is given by

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

where N is the number of bits. Thus, for an ideal 10-bit con­verter, Signal to (Noise + Distortion) = 61.96 dB.

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9835, THD is defined as

2

2

2

2

2

+V

)

5

6

THD = 20 log

(V

+V

+V

2

3

+V

4

V

1

where V1 is the rms amplitude of the fundamental and V2, V3,

, V5 and V6 are the rms amplitudes of the second through the

V

4

sixth harmonic.

Output Compliance

The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifica­tions. When voltages greater than that specified for the output
compliance are generated, the AD9835 may not meet the speci­fications listed in the data sheet.

Spurious Free Dynamic Range

Along with the frequency of interest, harmonics of the funda­mental frequency and images of the MCLK frequency are
present at the output of a DDS device. The spurious free dy­namic range (SFDR) refers to the largest spur or harmonic
present in the band of interest. The wideband SFDR gives the
magnitude of the largest harmonic or spur relative to the magni-

tude of the fundamental frequency in the bandwidth ±2 MHz

about the fundamental frequency. The narrow band SFDR gives
the attenuation of the largest spur or harmonic in a bandwidth of

±50 kHz about the fundamental frequency.

Clock Feedthrough

There will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9835’s output spectrum.

–4– REV. 0

AD9835

PIN FUNCTION DESCRIPTIONS

Pin # Mnemonic Function

ANALOG SIGNAL AND REFERENCE

1 FS ADJUST Full-Scale Adjust Control. A resistor (R

the magnitude of the full-scale DAC current. The relationship between R
as follows:

IOUT

V

REFIN

2 REFIN Voltage Reference Input. The AD9835 can be used with either the onboard reference, which is available

from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin.
The AD9835 accepts a reference of 1.21 V nominal.

3 REFOUT Voltage Reference Output. The AD9835 has an onboard reference of value 1.21 V nominal. The refer-

ence is made available on the REFOUT pin. This reference is used as the reference to the DAC by con­necting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.

14 IOUT Current Output. This is a high impedance current source. A load resistor should be connected between

IOUT and AGND.

16 COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling

ceramic capacitor should be connected between COMP and AVDD.

POWER SUPPLY

4 DVDD Positive Power Supply for the Digital Section. A 0.1 µF decoupling capacitor should be connected be-

tween DVDD and DGND. DVDD can have a value of +5 V ± 5%.

5 DGND Digital Ground.
13 AGND Analog Ground.

15 AVDD Positive Power Supply for the Analog Section. A 0.1 µF decoupling capacitor should be connected be-

tween AVDD and AGND. AVDD can have a value of +5 V ± 5%.

) is connected between this pin and AGND. This determines

SET

FULL-SCALE

= 12.5 × V

= 1.21 V nominal, R

REFIN/RSET

= 3.9 kΩ typical

SET

and the full-scale current is

SET

DIGITAL INTERFACE AND CONTROL

6 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.

The output frequency accuracy and phase noise are determined by this clock.

7 SCLK Serial Clock, Logic Input. Data is clocked into the AD9835 on each falling SCLK edge.
8 SDATA Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
9 FSYNC Data Synchronization Signal, Logic Input. When this input is taken low, the internal logic is informed

that a new word is being loaded into the device.

10 FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the

phase accumulator. The frequency register to be used can be selected using the pin FSELECT or the bit
FSELECT. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state
when an MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an
uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid
any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. When the bit is
being used to select the frequency register, the pin FSELECT should be tied to DGND.

11, 12 PSEL0, PSEL1 Phase Select Input. The AD9835 has four phase registers. These registers can be used to alter the value

being input to the COS ROM. The contents of the phase register are added to the phase accumula­tor output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the
phase register to be used can be selected using bits PSEL0 and PSEL1. Like the FSELECT input,
PSEL0 and PSEL1 are sampled on the rising MCLK edge. Therefore, these inputs need to be in
steady state when an MCLK rising edge occurs or there is an uncertainty of one MCLK cycle as to
when control is transferred to the selected phase register. When the phase registers are being con­trolled by the bits PSEL0 and PSEL1, the pins should be tied to DGND.

–5–REV. 0

AD9835

Table I. Control Registers

Register Size Description

FREQ0 REG 32 Bits Frequency Register 0. This de-

fines the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.

FREQ1 REG 32 Bits Frequency Register 1. This de-

fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.

PHASE0 REG 12 Bits Phase Offset Register 0. When

PSEL0 = PSEL1 = 0, the contents
of this register are added to the
output of the phase accumulator.

PHASE1 REG 12 Bits Phase Offset Register 1. When

PSEL0 = 1 and PSEL1 = 0, the con­tents of this register are added to the
output of the phase accumulator.

PHASE2 REG 12 Bits Phase Offset Register 2. When

PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added to
the output of the phase accumulator.

PHASE3 REG 12 Bits Phase Offset Register 3. When

PSEL0 = PSEL1 = 1, the contents
of this register are added to the
output of the phase accumulator.

Table II. Addressing the Registers

A3 A2 A1 A0 Destination Register

0 0 0 0 FREG0 REG 8 L LSBs
0 0 0 1 FREG0 REG 8 H LSBs
0 0 1 0 FREG0 REG 8 L MSBs
0 0 1 1 FREG0 REG 8 H MSBs
0 1 0 0 FREG1 REG 8 L LSBs
0 1 0 1 FREG1 REG 8 H LSBs
0 1 1 0 FREG1 REG 8 L MSBs
0 1 1 1 FREG1 REG 8 H MSBs
1 0 0 0 PHASE0 REG 8 LSBs
1 0 0 1 PHASE0 REG 8 MSBs
1 0 1 0 PHASE1 REG 8 LSBs
1 0 1 1 PHASE1 REG 8 MSBs
1 1 0 0 PHASE2 REG 8 LSBs
1 1 0 1 PHASE2 REG 8 MSBs
1 1 1 0 PHASE3 REG 8 LSBs
1 1 1 1 PHASE3 REG 8 MSBs

Table III. 32-Bit Frequency Word

sBSM61sBSL61

sBSMH8sBSML8sBSLH8sBSLL8

Table IV. 12-Bit Frequency Word

ehtfosBSM4ehT(sBSM4

)0=dedaoLdroWtiB-8

sBSL8

Table V. Commands

C3 C2 C1 C0 Command

0 0 0 0 Write 16 Phase bits (Present 8 Bits + 8 Bits

in Defer Register) to Selected PHASE

REG.
0 0 0 1 Write 8 Phase bits to Defer Register.
0 0 1 0 Write 16 Frequency bits (Present 8 Bits

+ 8 Bits in Defer Register) to Selected

FREQ REG.
0 0 1 1 Write 8 Frequency bits to Defer Register.
0 1 0 0 Bits D9 (PSEL0) and D10 (PSEL1) are

used to Select the PHASE REG when

SELSRC = 1. When SELSRC = 0, the

PHASE REG is selected using the pins

PSEL0 and PSEL1 Respectively.
0 1 0 1 Bit D11 is used to select the FREQ REG

when SELSRC = 1. When SELSRC = 0,

the FREQ REG is selected using the pin

FSELECT.
0 1 1 0 This command is used to control the

PSEL0, PSEL1 and FSELECT bits

using only one write. Bits D9 and D10

are used to select the PHASE REG and

Bit 11 is used to select the FREQ REG

when SELSRC = 1. When SELSRC = 0,

the PHASE REG is selected using the

pins PSEL0 and PSEL1 and the FREQ

REG is selected using the pin FSELECT.
0 1 1 1 Reserved. Configures the AD9835 for

Test Purposes.

Table VI. Controlling the AD9835

D15 D14 Command

1 0 Selects source of Control for the PHASE and

FREQ Registers and Enables Synchronization. Bit
D13 is the SYNC Bit. When this bit is High, read­ing of the FSELECT, PSEL0 and PSEL1 bits/pins
and the loading of the Destination Register with
data is synchronized with the rising edge of MCLK.
The latency is increased by 2 MCLK cycles when
SYNC = 1. When SYNC = 0, the loading of the
data and the sampling of FSELECT/PSEL0/PSEL1
occurs asynchronously. Bit D12 is the Select
Source Bit (SELSRC). When this bit Equals 1, the
PHASE/FREQ REG is Selected using the bits
FSELECT, PSEL0 and PSEL1. When SELSRC =
0, the PHASE/FREQ REG is Selected using the
pins FSELECT, PSEL0 and PSEL1.

1 1 Sleep, Reset and Clear. D13 is the SLEEP bit. When

this bit equals 1, the AD9835 is powered down, inter­nal clocks are disabled and the DAC's current sources
and REFOUT are turned off. When SLEEP = 0, the
AD9835 is powered up. When RESET (D12) = 1,
the phase accumulator is set to zero phase which
corresponds to an analog output of full scale. When
CLR (D11) = 1, SYNC and SELSRC are set to
zero. CLR automatically resets to zero.

–6– REV. 0

AD9835

MCLK FREQUENCY – MHz

–64

–66

–68

–70

–72

–76

–74

10 5020

SFDR (650kHz) – dB

30 40

f

OUT/fMCLK

= 1/3

AVDD = DVDD = +5V

MCLK FREQUENCY – MHz

0

–10

–20

–30

–40

–60

–50

10 5020

SFDR (62MHz) – dB

30 40

f

OUT/fMCLK

= 1/3

AVDD = DVDD = +5V

Table VII. Writing to the AD9835 Data Registers

51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0D

3C2C1C0C3A2A1A0ABSMBSL

Table VIII. Setting SYNC and SELSRC

51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0D

10 CNYSCRSLES XXXXXXXXXXXX

Table IX. Power-Down, Resetting and Clearing the AD9835

51D41D31D21D11D01D9D8D7D6D5D4D3D2D1D0D

11 PEELSTESERRLC XXXXXXXXXXX

Typical Performance Characteristics

0

AVDD = DVDD = +5V

–2

–4

–6

–8

SIGNAL ATTENUATION – dB

–10

–12

0162

468101214

OUTPUT FREQUENCY – MHz

CL = 82pF

CL = 150pF

CL = 100pF

Figure 5. Signal Attenuation vs. Output Frequency for
Various Capacitive Load (R

30

TA = +258C

25

AVDD = DVDD = +5V

20

15

10

TOTAL CURRENT – mA

5

= 300 Ω)

L

Figure 7. Narrow Band SFDR vs. MCLK Frequency

0

10 5020

MCLK FREQUENCY – MHz

30 40

Fi gure 6. Typical Current Consumption vs. MCLK Frequency

Figure 8. Wide Band SFDR vs. MCLK Frequency

–7–REV. 0

AD9835

RBW 1kHz VBW 3kHz ST 50 SEC

10dB/DIV

0Hz

START

25MHz

STOP

RBW 1kHz VBW 3kHz ST 50 SEC

10dB/DIV

0Hz

START

25MHz

STOP

–20

–30

–40

AVDD = DVDD = +5V

–50

–60

SFDR (62MHz) – dB

–70

–80

0.044 0.3640.124

0.084 0.164

50MHz

30MHz

10MHz

0.204 0.284

f

OUT/fMCLK

Figure 9. Wide Band SFDR vs. f
Frequencies

56

55

54

53

SNR – dB

52

51

0.244 0.324

OUT/fMCLK

for Various MCLK

f

OUT/fMCLK

AVDD = DVDD = +5V

= 1/3

10dB/DIV

0Hz

START

RBW 1kHz VBW 3kHz ST 50 SEC

Figure 12. f

= 50 MHz, f

MCLK

= 2.1 MHz. Frequency

OUT

Word = ACO8312

25MHz

STOP

50

10 5020

MCLK FREQUENCY – MHz

30 40

Figure 10. SNR vs. MCLK Frequency

70

60

50

40

SNR – dB

30

20

AVDD = DVDD = +5V

10

0.044 0.3640.124

0.084 0.164

Figure 11. SNR vs. f

0.204 0.284

f

OUT/fMCLK

OUT/fMCLK

for Various MCLK

Frequencies

10MHz

30MHz

50MHz

0.244 0.324

Figure 13. f

= 50 MHz, f

MCLK

Word = FDF3B64

Figure 14. f

= 50 MHz, f

MCLK

Word = 245AICAC

= 3.1 MHz. Frequency

OUT

= 7.1 MHz. Frequency

OUT

–8– REV. 0

10dB/DIV

RBW 1kHz VBW 3kHz ST 50 SEC

10dB/DIV

0Hz

START

25MHz

STOP

RBW 1kHz VBW 3kHz ST 50 SEC

10dB/DIV

0Hz

START

25MHz

STOP

AD9835

0Hz

START

RBW 1kHz VBW 3kHz ST 50 SEC

Figure 15. f

= 50 MHz, f

MCLK

= 9.1 MHz. Frequency

OUT

Word = 2E978D50

10dB/DIV

0Hz

START

RBW 1kHz VBW 3kHz ST 50 SEC

Figure 16. f

= 50 MHz, f

MCLK

= 11.1 MHz. Frequency

OUT

Word = 38D4FDF4

25MHz

STOP

25MHz

STOP

Figure 17. f

= 50 MHz, f

MCLK

Word = 43126E98

Figure 18. f

= 50 MHz, f

MCLK

Word = 547AE148

= 13.1 MHz. Frequency

OUT

= 16.5 MHz. Frequency

OUT

–9–REV. 0

AD9835

CIRCUIT DESCRIPTION

The AD9835 provides an exciting new level of integration for
the RF/Communications system designer. The AD9835 com­bines the Numerical Controlled Oscillator (NCO), COS Look-Up
Table, Frequency and Phase Modulators, and a Digital-to­Analog Converter on a single integrated circuit.

The internal circuitry of the AD9835 consists of three main
sections. These are:

Numerical Controlled Oscillator (NCO) + Phase Modulator
COS Look-Up Table
Digital-to-Analog Converter

The AD9835 is a fully integrated Direct Digital Synthesis (DDS)
chip. The chip requires one reference clock, one low precision
resistor and eight decoupling capacitors to provide digitally
created sine waves up to 25 MHz. In addition to the generation
of this RF signal, the chip is fully capable of a broad range of
simple and complex modulation schemes. These modulation
schemes are fully implemented in the digital domain allowing
accurate and simple realization of complex modulation algo­rithms using DSP techniques.

THEORY OF OPERATION

Cos waves are typically thought of in terms of their magnitude

form a(t) = cos (ωt). However, these are nonlinear and not easy

to generate except through piece-wise construction. On the
other hand, the angular information is linear in nature. That is,
the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal

by the traditional rate of ω = 2 πf.

+1

0

–1

2π

0

MAGNITUDE

PHASE

Figure 19. Cos Wave

Knowing that the phase of a cos wave is linear and given a refer­ence interval (clock period), the phase rotation for that period
can be determined.

∆Phase = ωδt

Solving for ω

ω = ∆Phase/δt = 2 πf

Solving for f and substituting the reference clock frequency for
the reference period (1/f

f = ∆Phase × f

MCLK

= δt)

MCLK

/2 π

The AD9835 builds the output based on this simple equation.
A simple DDS chip can implement this equation with three
major subcircuits.

Numerical Controlled Oscillator and Phase Modulator

This consists of two frequency select registers, a phase accumu­lator and four phase offset registers. The main component of the
NCO is a 32-bit phase accumulator which assembles the phase

–10– REV. 0

component of the output signal. Continuous time signals have a

phase range of 0 π to 2 π. Outside this range of numbers, the

sinusoid functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator simply
scales the range of phase numbers into a multibit digital word.
The phase accumulator in the AD9835 is implemented with

32 bits. Therefore, in the AD9835, 2 π = 2
∆Phase term is scaled into this range of numbers 0 < ∆Phase

32

– 1. Making these substitutions into the equation above

< 2

where 0 < ∆Phase < 2

f = ∆Phase × f

32

MCLK

32

. Likewise, the

32

/2

The input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register
and this is controlled by the FSELECT pin or the FSELECT
bit. NCOs inherently generate continuous phase signals, thus
avoiding any output discontinuity when switching between
frequencies.

Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Registers. The con­tents of this register are added to the most significant bits of the
NCO. The AD9835 has four PHASE registers, the resolution

of these registers being 2 π/4096.

COS Look-Up Table (LUT)

To make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase informa­tion maps directly into amplitude, a ROM LUT converts the
phase information into amplitude. To do this, the digital phase
information is used to address a COS ROM LUT. Although
the NCO contains a 32-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 2

32

entries.

It is necessary only to have sufficient phase resolution in the
LUTs such that the dc error of the output waveform is domi­nated by the quantization error in the DAC. This requires the
look-up table to have two more bits of phase resolution than the
10-bit DAC.

Digital-to-Analog Converter

The AD9835 includes a high impedance current source 10-bit
DAC, capable of driving a wide range of loads at different
speeds. Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of a
single external resistor (R

SET

).

The DAC is configured for single-ended operation. The load
resistor can be any value required, as long as the full-scale volt­age developed across it does not exceed the voltage compliance
range. Since full-scale current is controlled by R
ments to R

can balance changes made to the load resistor.

SET

, adjust-

SET

However, if the DAC full-scale output current is significantly
less than 4 mA, the DAC’s linearity may degrade.

DSP and MPU Interfacing

The AD9835 has a serial interface, with 16 bits being loaded
during each write cycle. SCLK, SDATA and FSYNC are used
to load the word into the AD9835. When FSYNC is taken low,
the AD9835 is informed that a word is being written to the
device. The first bit is read into the device on the next SCLK
falling edge with the remaining bits being read into the device
on the subsequent SCLK falling edges. FSYNC frames the
16 bits; therefore, when 16 SCLK falling edges have occurred,

AD9835

FSYNC should be taken high again. The SCLK can be con­tinuous or, alternatively, the SCLK can idle high or low be­tween write operations.

When writing to a frequency/phase register, the first four bits
identify whether a frequency or phase register is being written
to, the next four bits contain the address of the destination
register while the 8 LSBs contain the data. Table II lists the
addresses for the phase/frequency registers while Table III lists
the commands.

Within the AD9835, 16-bit transfers are used when loading the
destination frequency/phase register. There are two modes for
loading a register—direct data transfer and a deferred data
transfer. With a deferred data transfer, the 8-bit word is loaded
into the defer register (8 LSBs or 8 MSBs). However, this data
is not loaded into the 16-bit data register so the destination
register is not updated. With a direct data transfer, the 8-bit
word is loaded into the appropriate defer register (8 LSBs or
8 MSBs). Immediately following the loading of the defer regis­ter, the contents of the complete defer register are loaded into
the 16-bit data register and the destination register is loaded on
the next MCLK rising edge. When a destination register is
addressed, a deferred transfer is needed first, followed by a
direct transfer. When all 16 bits of the defer register contain
relevant data, the destination register can then be updated using
8-bit loading rather than 16-bit loading, i.e., direct data trans­fers can be used. For example, after a new 16-bit word has
been loaded to a destination register, the defer register will also
contain this word. If the next write instruction is to the same
destination register, the user can use direct data transfers
immediately.

When writing to a phase register, the 4 MSBs of the 16-bit word
loaded into the data register should be zero (the phase registers
are 12 bits wide).

To alter the entire contents of a frequency register, four write
operations are needed. However, the 16 MSBs of a frequency
word are contained in a separate register to the 16 LSBs. There­fore, the 16 MSBs of the frequency word can be altered inde­pendent of the 16 LSBs.

The phase and frequency registers to be used are selected using
the pins FSELECT, PSEL0 and PSEL1 or the corresponding
bits can be used. Bit SELSRC determines whether the bits or
the pins are used. When SELSRC = 0, the pins are used while
the bits are used when SELSRC = 1. When CLR is taken high,
SELSRC is set to 0 so that the pins are the default source.

Data transfers from the serial (defer) register to the 16-bit data
register, and the FSELECT and PSEL registers, occur following
the 16th falling SCLK edge. Transfer of the data from the 16-bit
data register to the destination register or from the FSELECT/
PSEL register to the respective multiplexer occurs on the next
MCLK rising edge. Since the SCLK and the MCLK are asyn­chronous, an MCLK rising edge may occur while the data bits
are in transitional state, which will cause a brief spurious DAC
output if the register being written to is generating the DAC
output. To avoid such spurious outputs, the AD9835 contains
synchronizing circuitry. When the SYNC bit is set to 1, the
synchronizer is enabled and data transfers from the serial

register (defer register) to the 16-bit data register and the
FSELECT/PSEL registers occur following a two-stage pipeline
delay which is triggered on the MCLK falling edge. The pipe­line delay ensures that the data is valid when the transfer occurs.
Similarly, selection of the frequency/phase registers using the
FSELECT/PSEL pins is synchronized with the MCLK rising
edge when SYNC = 1. When SYNC = 0, the synchronizer is
bypassed.

Selecting the frequency/phase registers using the pins is
synchronized with MCLK internally also when SYNC = 1 to
ensure that these inputs are valid at the MCLK rising edge. If
times t
the MCLK rising edge. However, if times t

and t

11

are met, the inputs will be at steady state at

11A

and t

11

11A

are
violated, the internal synchronizing circuitry will delay the
instant at which the pins are sampled, ensuring that the inputs
are valid at the sampling instant.

A latency is associated with each operation. When inputs
FSELECT/PSEL change value, there will be a pipeline delay
before control is transferred to the selected register—there will
be a pipeline delay before the analog output is controlled by
the selected register. When times t

and t

11

are met, PSEL0,

11A

PSEL1 and FSELECT have latencies of six MCLK cycles when
SYNC = 0. When SYNC = 1, the latency is increased to
8 MCLK cycles. When times t

and t

11

are not met, the

11A

latency can increase by one MCLK cycle. Similarly, there is a
latency associated with each write operation. If a selected
frequency/phase register is loaded with a new word, there is a
delay of 6 to 7 MCLK cycles before the analog output will
change (there is an uncertainty of one MCLK cycle regarding
the MCLK rising edge at which the data is loaded into the
destination register). When SYNC = 1, the latency will be 8 or
9 MCLK cycles.

The flowchart in Figure 20 shows the operating routine for the
AD9835. When the AD9835 is powered up, the part should be
reset. This will reset the phase accumulator to zero so that the
analog output is at full scale. To avoid spurious DAC outputs
while the AD9835 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
Taking CLR high will set SYNC and SELSRC to 0 so that the
FSELECT/PSEL pins are used to select the frequency/phase
registers and the synchronization circuitry is bypassed. A write
operation is needed to the SYNC/SELSRC register to enable
the synchronization circuitry or to change control to the
FSELECT/PSEL bits. RESET does not reset the phase and
frequency registers. These registers will contain invalid data
and should therefore be set to a known value by the user. The
RESET bit is then set to 0 to begin generating an output. A
signal will appear at the DAC output 6 MCLK cycles after
RESET is set to 0.

32

/2

The analog output is f

MCLK

× FREG where FREG is the

value loaded into the selected frequency register. This signal
will be phase shifted by the amount specified in the selected

phase register (2 π/4096

× PHASEREG where PHASEREG is

the value contained in the selected phase register).

Control of the frequency/phase registers can be interchanged
from the pins to the bits.

–11–REV. 0

AD9835

DATA WRITE**

DEFERRED TRANSFER WRITE

WRITE 8 BITS TO DEFER REGISTER

DIRECT TRANSFER WRITE
WRITE PRESENT 8 BITS AND 8 BITS IN
DEFER REGISTER TO DATA REGISTER

WRITE ANOTHER WORD TO THIS

REGISTER?

WRITE A WORD TO ANOTHER REGISTER

CHANGE 8 BITS ONLY

YES

CHANGE 16 BITS

NOYES

NO

SELECT DATA SOURCES***

FSELECT/PSEL PINS BEING USED?

YES
SELSRC = 0

SET PINS

SET FSELECT

SET PSEL0
SET PSEL1

FREQUENCY/PHASE REGISTER WRITE

SET FSELECT

SET PSEL0
SET PSEL1

SELSRC = 1

NO

DATA WRITE**

FREG<0> = f
FREG<1> = f

PHASEREG <3:0> = DELTA PHASE<0, 1, 2, 3>

SELECT DATA SOURCES***

WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = 1)

= V

REFIN

*6.25*R

OUT/RSET

NO

NO

V

OUT

CHANGE FSELECT CHANGE PHASEREG?

OUT0/fMCLK
OUT1/fMCLK

SET FSELECT

SET PSEL0, PSEL1

DAC OUTPUT

*(1 + COS(2p (FREG*f

CHANGE PHASE?

CHANGE f

CHANGE FREG?

NO

OUT

YES

YES

32

*2

32

*2

*t/232 + PHASEREG/212)))

MCLK

YES

?

INITIALIZATION*

YES

Figure 20. Flowchart for AD9835 Initialization and Operation

NO

CHANGE PSEL0, PSEL1

INITIALIZATION*

CONTROL REGISTER WRITE

SET SYNC AND/OR SELSRC TO 1

PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>

SET PINS OR FREQUENCY/PHASE REGISTER WRITE

SET FSELECT, PSEL0 AND PSEL1

CONTROL REGISTER WRITE

Figure 21. Initialization

SET SLEEP

RESET = 1

CLR = 1

NO

WRITE INITIAL DATA

FREG<0> = f
FREG<1> = f

OUT0/fMCLK
OUT1/fMCLK

SLEEP = 0
RESET = 0

CLR = 0

YES

CONTROL REGISTER WRITE

SYNC = 1

AND/OR

SELSRC = 1

32

*2

32

*2

Figure 22. Data Writes

Figure 23. Selecting Data Sources

–12– REV. 0

AD9835

APPLICATIONS

The AD9835 contains functions that make it suitable for
modulation applications. The part can be used to perform
simple modulation such as FSK. More complex modulation
schemes such as GMSK and QPSK can also be implemented
using the AD9835. In an FSK application, the two frequency
registers of the AD9835 are loaded with different values; one
frequency will represent the space frequency while the other will
represent the mark frequency. The digital data stream is fed to
the FSELECT pin, which will cause the AD9835 to modulate
the carrier frequency between the two values.

The AD9835 has four phase registers; this enables the part to
perform PSK. With phase shift keying, the carrier frequency is
phase shifted, the phase being altered by an amount that is
related to the bit stream being input to the modulator. The
presence of four shift registers eases the interaction needed
between the DSP and the AD9835.

The AD9835 is also suitable for signal generator applications.
With its low current consumption, the part is suitable for
applications in which it can be used as a local oscillator.

Grounding and Layout

The printed circuit board that houses the AD9835 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes which can be separated easily. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should only be
joined in one place. If the AD9835 is the only device requiring
an AGND to DGND connection, then the ground planes
should be connected at the AGND and DGND pins of the
AD9835. If the AD9835 is in a system where multiple devices
require AGND to DGND connections, the connection should
be made at one point only, a star ground point that should be
established as close as possible to the AD9835.

Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD9835 to avoid noise coupling. The power
supply lines to the AD9835 should use as large a track as is
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals
such as clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This will reduce
the effects of feedthrough through the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.

Good decoupling is important. The analog and digital supplies
to the AD9835 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to

AGND and DGND respectively with 0.1 µF ceramic capacitors
in parallel with 10 µF tantalum capacitors. To achieve the best

from the decoupling capacitors, they should be placed as close

as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the
AVDD and DVDD of the AD9835, it is recommended that the
system’s AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD9835 and AGND and the recommended digital
supply decoupling capacitors between the DVDD pins and
DGND.

Interfacing the AD9835 to Microprocessors

The AD9835 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control informa­tion into the device. The serial clock can have a frequency of
20 MHz maximum. The serial clock can be continuous or it
can idle high or low between write operations. When data/
control information is being written to the AD9835, FSYNC
is taken low and held low while the 16 bits of data are being
written into the AD9835. The FSYNC signal frames the 16 bits
of information being loaded into the AD9835.

AD9835-to-ADSP-21xx Interface

Figure 24 shows the serial interface between the AD9835 and
the ADSP-21xx. The ADSP-21xx should be set up to operate
in the SPORT Transmit Alternate Framing Mode (TFSW = 1).
The ADSP-21xx is programmed through the SPORT control
register and should be configured as follows: Internal clock
operation (ISCLK = 1), Active low framing (INVTFS = 1),
16-bit word length (SLEN = 15), Internal frame sync signal
(ITFS = 1), Generate a frame sync for each write operation
(TFSR = 1). Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled. The data is
clocked out on each rising edge of the serial clock and clocked
into the AD9835 on the SCLK falling edge.

ADSP-2101/

ADSP-2103

TFS

DT

SCLK

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 24. ADSP-2101/ADSP-2103-to-AD9835 Interface

AD9835-to-68HC11/68L11 Interface

AD9835

FSYNC
SDATA

SCLK

Figure 25 shows the serial interface between the AD9835 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting bit MSTR in the SPCR to 1
and, this provides a serial clock on SCK while the MOSI output
drives the serial data line SDATA. Since the microcontroller
does not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The setup conditions for cor­rect operation of the interface are as follows: the SCK idles high
between write operations (CPOL = 0), data is valid on the SCK
falling edge (CPHA = 1). When data is being transmitted to the
AD9835, the FSYNC line is taken low (PC7). Serial data from
the 68HC11/68L11 is transmitted in 8-bit bytes with only eight

–13–REV. 0

AD9835

AD9835.EXE

IBM-COMPATIBLE PC

PARALLEL PORT

CENTRONICS

PRINTER CABLE

AD9835 EVALUATION

BOARD

falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data into the AD9835,
PC7 is held low after the first eight bits are transferred and a
second serial write operation is performed to the AD9835. Only
after the second eight bits have been transferred should FSYNC
be taken high again.

68HC11/68L11

PC7

MOSI

SCK

ADDITIONAL PINS OMITTED FOR CLARITY

AD9835

FSYNC
SDATA

SCLK

Figure 25. 68HC11/68L11-to-AD9835 Interface

AD9835-to-80C51/80L51 Interface

Figure 26 shows the serial interface between the AD9835 and
the 80C51/80L51 microcontroller. The microcontroller is oper­ated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK
of the AD9835 while RXD drives the serial data line SDATA.
The FSYNC signal is again derived from a bit programmable
pin on the port (P3.3 being used in the diagram). When data is
to be transmitted to the AD9835, P3.3 is taken low. The
80C51/80L51 transmits data in 8-bit bytes thus, only eight
falling SCLK edges occur in each cycle. To load the remaining
eight bits to the AD9835, P3.3 is held low after the first eight
bits have been transmitted and a second write operation is initi­ated to transmit the second byte of data. P3.3 is taken high
following the completion of the second write operation. SCLK
should idle high between the two write operations. The 80C51/
80L51 outputs the serial data in a format which has the LSB
first. The AD9835 accepts the MSB first (the 4 MSBs being the
control information, the next 4 bits being the address while the
8 LSBs contain the data when writing to a destination register).
Therefore, the transmit routine of the 80C51/80L51 must take
this into account and rearrange the bits so that the MSB is out­put first.

80C51/80L51

P3.3
RXD

TXD

ADDITIONAL PINS OMITTED FOR CLARITY

AD9835

FSYNC
SDATA

SCLK

Figure 26. 80C51/80L51 to AD9835 Interface

AD9835-to-DSP56002 Interface

Figure 27 shows the interface between the AD9835 and the
DSP56002. The DSP56002 is configured for normal mode
asynchronous operation with a Gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated inter­nally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0
= 0) and the frame sync signal will frame the 16 bits (FSL = 0).

Windows is a registered trademark of Microsoft Corporation.

The frame sync signal is available on pin SC2 but, it needs to be
inverted before being applied to the AD9835. The interface to
the DSP56000/DSP56001 is similar to that of the DSP56002.

DSP56002

SC2

STD

SCK

ADDITIONAL PINS OMITTED FOR CLARITY

AD9835

FSYNC

SDATA

SCLK

Figure 27. AD9835-to-DSP56002 Interface

AD9835 Evaluation Board

The AD9835 Evaluation Board allows designers to evaluate the
high performance AD9835 DDS Modulator with a minimum of
effort.

To prove that this device will meet the user’s waveform synthe­sis requirements, the user only requires a 5 V power supply, an
IBM-compatible PC and a spectrum analyzer along with the
evaluation board. The evaluation setup is shown below.

The DDS Evaluation kit includes a populated, tested AD9835
printed circuit board along with the software that controls the
AD9835 in a Windows

®

environment.

Figure 28. AD9835 Evaluation Board Setup

Using the AD9835 Evaluation Board

The AD9835 Evaluation kit is a test system designed to simplify
the evaluation of the AD9835. Provisions to control the AD9835
from the printer port of an IBM-compatible PC are included
along with the necessary software. An application note is also
available with the evaluation board which gives information on
operating the evaluation board.

Prototyping Area

An area is available on the evaluation board where the user can
add additional circuits to the evaluation test set. Users may
want to build custom analog filters for the output or add buffers
and operational amplifiers to be used in the final application.

XO vs. External Clock

The AD9835 can operate with master clocks up to 50 MHz. A
50 MHz oscillator is included on the evaluation board. How­ever, this oscillator can be removed and an external CMOS
clock connected to the part, if required.

Power Supply

Power to the AD9835 Evaluation Board must be provided ex­ternally through the pin connections. The power leads should be
twisted to reduce ground loops.

–14– REV. 0

AD9835

1
2

SCLK

3

SDATA

4

FSYNC

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

PSEL1

PSEL0

SW

MCLK

R2
10kV

FSELECT

R4
50V

DVDD

0.1mF

J1

SCLK
SDATA
FSYNC

R1
10kV

C5

R3
10kV

DVDD

LK3

DVDD

U3

DGND

DVDD

0.1mF

OUT

C6

4
6

11

LK2

XTAL1

20

110 19

U2

LK1

DVDD AVDD

C1

0.1mF
415

DVDD AVDD

7

16

SCLK

8

14

SDATA

9

9

FSYNC

11

PSEL1

12

PSEL0

10

FSELECT

6

MCLK

DGND AGND

513

U1

AD9835

C2

0.1mF

COMP
REFIN

REFOUT

FSADJUST

IOUT

AVDD

C3

C4
10nF

R5

3.9kV

10nF

REFIN

10mF

C8

R6

300V

DVDD

C7

0.1mF

IOUT

J2 J3

0.1mF

AVDD
C9

C10
10mF

16
2

LK4

3

1

14

Figure 29. Evaluation Board Layout

Integrated Circuits

XTAL1 OSC XTAL 50 MHz
U1 AD9835 (16-Lead TSSOP)
U2 74HCT244 Buffer

Capacitors

C1, C2 0.1 µF Ceramic Chip Capacitor

C3, C4 10 nF Ceramic Capacitor

C5, C6, C7, C9 0.1 µF Ceramic Capacitor
C8, C10 10 µF Tantalum Capacitor

Resistors

R1–R3 10 kΩ Resistor
R4 50 Ω Resistor
R5 3.9 kΩ Resistor
R6 300 Ω Resistor

Links

LK1–LK3 Three Pin Link
LK4 Two Pin Link

Switch

SW End Stackable Switch (SDC Double

Throw)

Sockets

MCLK, PSEL0, Subminiature BNC Connector
PSEL1, FSELECT,
IOUT, REFIN

Connectors

J1 36-Pin Edge Connector
J2, J3 PCB Mounting Terminal Block

–15–REV. 0

AD9835

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-16)

0.201 (5.10)

0.193 (4.90)

16 9

0.177 (4.50)

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

0.169 (4.30)

1

PIN 1

0.0256
(0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

8

0.256 (6.50)

0.246 (6.25)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

8°
0°

0.028 (0.70)

0.020 (0.50)

C3309–8–7/98

–16–

PRINTED IN U.S.A.

REV. 0