Analog Devices AD9241EB, AD9241AS Datasheet

Complete 14-Bit, 1.25 MSPS

a

FEATURES
Monolithic 14-Bit, 1.25 MSPS A/D Converter
Low Power Dissipation: 60 mW
Single +5 V Supply
Integral Nonlinearity Error: 2.5 LSB
Differential Nonlinearity Error: 0.6 LSB
Input Referred Noise: 0.36 LSB
Complete: On-Chip Sample-and-Hold Amplifier and

Voltage Reference
Signal-to-Noise and Distortion Ratio: 78.0 dB
Spurious-Free Dynamic Range: 88.0 dB
Out-of-Range Indicator
Straight Binary Output Data
44-Pin MQFP

PRODUCT DESCRIPTION

The AD9241 is a 1.25 MSPS, single supply, 14-bit analog-to­digital converter (ADC). It combines a low cost, high speed
CMOS process and a novel architecture to achieve the resolution
and speed of existing hybrid implementations at a fraction of the
power consumption and cost. It is a complete, monolithic ADC
with an on-chip, high performance, low noise sample-and-hold
amplifier and programmable voltage reference. An external refer­ence can also be chosen to suit the dc accuracy and temperature
drift requirements of the application. The device uses a multistage
differential pipelined architecture with digital output error correc­tion logic to guarantee no missing codes over the full operating
temperature range.

The input of the AD9241 is highly flexible, allowing for easy
interfacing to imaging, communications, medical, and data­acquisition systems. A truly differential input structure allows
for both single-ended and differential input interfaces of varying
input spans. The sample-and-hold amplifier (SHA) is equally
suited for both multiplexed systems that switch full-scale voltage
levels in successive channels as well as sampling single-channel
inputs at frequencies up to and beyond the Nyquist rate. Also,
the AD9241 performs well in communication systems employ­ing Direct-IF Down Conversion since the SHA in the differen­tial input mode can achieve excellent dynamic performance well
beyond its specified Nyquist frequency of 0.625 MHz.

A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range (OTR) signal indicates an over­flow condition which can be used with the most significant bit
to determine low or high overflow.

Monolithic A/D Converter

AD9241

FUNCTIONAL BLOCK DIAGRAM

CLK

SHA

VINA
VINB

CML
CAPT
CAPB

VREF

SENSE

MODE

SELECT

MDAC1

GAIN = 16

5

5

REFCOM

MDAC2

GAIN = 8

4

A/DA/D

4

DIGITAL CORRECTION LOGIC

OUTPUT BUFFERS

1V

AD9241

AVSS

PRODUCT HIGHLIGHTS

The AD9241 offers a complete single-chip sampling 14-bit,
analog-to-digital conversion function in a 44-pin Metric Quad
Flatpack.

Low Power and Single Supply

The AD9241 consumes only 60 mW on a single +5 V power
supply.

Excellent DC Performance Over Temperature

The AD9241 provides no missing codes, and excellent tempera­ture drift performance over the full operating temperature range.

Excellent AC Performance and Low Noise

The AD9241 provides nearly 13 ENOB performance and has an
input referred noise of 0.36 LSB rms.

Flexible Analog Input Range

The versatile onboard sample-and-hold (SHA) can be configured
for either single-ended or differential inputs of varying input spans.

Flexible Digital Outputs

The digital outputs can be configured to interface with +3 V and
+5 V CMOS logic families.

DVDDAVDD

DRVDD

MDAC3

GAIN = 8

4

A/D

4

14

DVSS

DRVSS

A/D

4

OTR
BIT 1

(MSB)

BIT 14
(LSB)

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

AD9241–SPECIFICATIONS

(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f

DC SPECIFICATIONS

T

to T

MIN

unless otherwise noted)

MAX

Parameter AD9241 Units

RESOLUTION 14 Bits min

MAX CONVERSION RATE 1.25 MHz min

INPUT REFERRED NOISE

VREF = 1 V 0.9 LSB rms typ
VREF = 2.5 V 0.36 LSB rms typ

ACCURACY

Integral Nonlinearity (INL) ±2.5 LSB typ
Differential Nonlinearity (DNL) ±0.6 LSB typ

±1.0 LSB max
±2.5 LSB typ
±0.7 LSB typ

INL
DNL

1

1

No Missing Codes 14 Bits Guaranteed
Zero Error (@ +25°C) 0.3 % FSR max
Gain Error (@ +25°C)
Gain Error (@ +25°C)

2
3

1.5 % FSR max

0.75 % FSR max

TEMPERATURE DRIFT

Zero Error 3.0 ppm/°C typ
Gain Error
Gain Error

2
3

20.0 ppm/°C typ

5.0 ppm/°C typ

= 1.25 MSPS, VREF = 2.5 V, VINB = 2.5 V,

SAMPLE

POWER SUPPLY REJECTION 0.1 % FSR max

ANALOG INPUT

Input Span (with VREF = 1.0 V) 2 V p-p min

Input Span (with VREF = 2.5 V) 5 V p-p max

Input (VINA or VINB) Range 0 V min

AVDD V max

Input Capacitance 16 pF typ

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode) 1 Volts typ
Output Voltage Tolerance (1 V Mode) ±14 mV max
Output Voltage (2.5 V Mode) 2.5 Volts typ
Output Voltage Tolerance (2.5 V Mode) ±35 mV max
Load Regulation

4

5.0 mV max

REFERENCE INPUT RESISTANCE 5 kΩ typ

POWER SUPPLIES

Supply Voltages

AVDD +5 V (±5% AVDD
DVDD +5 V (±5% DVDD
DRVDD +5 V (± 5% DRVDD

Supply Current

IAVDD 13.0 mA max (10 mA typ )
IDRVDD 1.0 mA max (1 mA typ )
IDVDD 3.0 mA max (2 mA typ )

POWER CONSUMPTION 65 mW typ

85 mW max

NOTES

1

VREF =1 V.

2

Including internal reference.

3

Excluding internal reference.

4

Load regulation with 1 mA load current (in addition to that required by the AD9241).

Specification subject to change without notice.

Operating)

Operating)

Operating)

–2–

REV. 0

AD9241

AC SPECIFICATIONS

(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
Differential Input, T

MIN

to T

unless otherwise noted)

MAX

= 1.25 MSPS, VREF = 2.5 V, AIN = –0.5 dBFS, AC Coupled/

SAMPLE

Parameter AD9241 Units

SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D)

= 100 kHz 78.0 dB typ

f

INPUT

= 500 kHz 74.5 dB min

f

INPUT

77.0 dB typ

EFFECTIVE NUMBER OF BITS (ENOB)

f

= 100 kHz 12.7 Bits typ

INPUT

= 500 kHz 12.1 Bits min

f

INPUT

12.5 Bits typ

SIGNAL-TO-NOISE RATIO (SNR)

f

= 100 kHz 79.0 dB typ

INPUT

= 500 kHz 75.5 dB min

f

INPUT

79.0 dB typ

TOTAL HARMONIC DISTORTION (THD)

f

= 100 kHz –88.0 dB typ

INPUT

= 500 kHz –77.5 dB max

f

INPUT

–88.0 dB typ

SPURIOUS FREE DYNAMIC RANGE

f

= 100 kHz 88.0 dB typ

INPUT

f

= 500 kHz 86.0 dB typ

INPUT

DYNAMIC PERFORMANCE

Full Power Bandwidth 25 MHz typ
Small Signal Bandwidth 25 MHz typ
Aperture Delay 1 ns typ
Aperture Jitter 4 ps rms typ
Acquisition to Full-Scale Step (0.0025%) 240 ns typ
Overvoltage Recovery Time 167 ns typ

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

(AVDD = +5 V, DVDD = +5 V, T

MIN

to T

unless otherwise noted)

MAX

Parameters Symbol AD9241 Units

LOGIC INPUTS

High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current (V
Low Level Input Current (V

= DVDD) I

IN

= 0 V) I

IN

Input Capacitance C

IH

IL
IH
IL

IN

+3.5 V min
+1.0 V max

±10 µA max
±10 µA max

5 pF typ

LOGIC OUTPUTS (with DRVDD = 5 V)

High Level Output Voltage (I
High Level Output Voltage (I
Low Level Output Voltage (I
Low Level Output Voltage (I
Output Capacitance C

= 50 µA) V

OH

= 0.5 mA) V

OH

= 1.6 mA) V

OL

= 50 µA) V

OL

OH

OH

OL

OL

OUT

+4.5 V min
+2.4 V min
+0.4 V max
+0.1 V max
5 pF typ

LOGIC OUTPUTS (with DRVDD = 3 V)

High Level Output Voltage (I
Low Level Output Voltage (I

Specifications subject to change without notice.

= 50 µA) V

OH

= 50 µA) V

OL

OH

OL

+2.4 V min
+0.7 V max

REV. 0

–3–

AD9241

(T

to T

SWITCHING SPECIFICATIONS

MIN

Parameters Symbol AD9241 Units

Clock Period
CLOCK Pulse Width High t
CLOCK Pulse Width Low t
Output Delay t

1

t

C
CH
CL
OD

Pipeline Delay (Latency) 3 Clock Cycles

NOTES

1

The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C.

Specifications subject to change without notice.

ANALOG

INPUT

INPUT

CLOCK

DATA

OUTPUT

S1

t

CH

S2

t

C

t

CL

S3

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Parameter to Min Max Units

AVDD AVSS –0.3 +6.5 V
DVDD DVSS –0.3 +6.5 V
AVSS DVSS –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
DRVDD DRVSS –0.3 +6.5 V
DRVSS AVSS –0.3 +0.3 V
REFCOM AVSS –0.3 +0.3 V
CLK DVSS –0.3 DVDD
Digital Outputs DRVSS –0.3 DRVDD
VINA, VINB AVSS –0.3 AVDD
VREF AVSS –0.3 AVDD
SENSE AVSS –0.3 AVDD
CAPB, CAPT AVSS –0.3 AVDD
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9241 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

with AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, CL = 20 pF)

MAX

800 ns min
360 ns min
360 ns min
8 ns min
13 ns typ
19 ns max

THERMAL CHARACTERISTICS

S4

t

OD

DATA 1

Thermal Resistance
44-Pin MQFP

θ

= 53.2°C/W

JA

θ

= 19°C/W

JC

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9241AS –40

o

C to +85oC 44-Pin MQFP S-44

AD9241EB Evaluation Board

*S = Metric Quad Flatpack.

PIN CONNECTION

NC

NC

VINB

1

+ 0.3 V

+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V

DVSS
AVSS
DVDD
AVDD

DRVSS

DRVDD

CLK

NC
NC
NC

(LSB) BIT 14

NC = NO CONNECT

PIN 1
IDENTIFIER

2
3
4
5
6
7
8
9

10
11

121314 15 16 17 18 192021 22

BIT 13

(Not to Scale)

BIT 11

BIT 12

NC

VINA

CML

40 39 3841424344 36 35 3437

AD9241

TOP VIEW

BIT 8

BIT 9

BIT 10

WARNING!

NC

BIT 7

CAPT

NC

CAPB

NC

BIT 4

BIT 5

BIT 6

BIT 3

ESD SENSITIVE DEVICE

33

REFCOM

32

VREF

31

SENSE

30

NC

29

AVSS

28

AVDD

27

NC
NC

26

OTR

25

BIT 1 (MSB)

24

BIT 2

23

–4–

REV. 0

AD9241

PIN FUNCTION DESCRIPTIONS

Pin
Number Name Description

1 DVSS Digital Ground
2, 29 AVSS Analog Ground
3 DVDD +5 V Digital Supply
4, 28 AVDD +5 V Analog Supply
5 DRVSS Digital Output Driver Ground
6 DRVDD Digital Output Driver Supply
7 CLK Clock Input Pin
8–10 NC No Connect
11 BIT 14 Least Significant Data Bit (LSB)
12–23 BIT 13–BIT 2 Data Output Bits
24 BIT 1 Most Significant Data Bit (MSB)
25 OTR Out of Range
26, 27, 30 NC No Connect
31 SENSE Reference Select
32 VREF Reference I/O
33 REFCOM Reference Common
34, 35, 38 NC No Connect
40, 43, 44
36 CAPB Noise Reduction Pin
37 CAPT Noise Reduction Pin
39 CML Common-Mode Level (Midsupply)
41 VINA Analog Input Pin (+)
42 VINB Analog Input Pin (–)

DEFINITIONS OF SPECIFICATION

INTEGRAL NONLINEARITY (INL)

INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.

ZERO ERROR

The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.

GAIN ERROR

The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full
scale. Gain error is the deviation of the actual difference
between first and last code transitions, and the ideal differ­ence between first and last code transitions.

OVERVOLTAGE RECOVERY TIME

Overvoltage recovery time is defined as that amount of time
required for the ADC to achieve a specified accuracy after an

overvoltage (50% greater than full-scale range), measured from
the time the overvoltage signal reenters the converter’s range.

TEMPERATURE DRIFT

The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
T

or T

MIN

POWER SUPPLY REJECTION

MAX

.

The specification shows the maximum change in full scale,
from the value with the supply at the minimum limit to the
value with the supply at its maximum limit.

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.

APERTURE DELAY

Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO

S/N+D is the ratio of the rms value of the measured input sig­nal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the num­ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N,
the effective number of bits.

Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal; this
is expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.

TWO-TONE SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).

REV. 0

–5–

AD9241

Typical Differential AC Characterization Curves/Plots

80

75

70

65

60

55

SINAD – dB

50

45

40

0.01

–0.5dBFS

–6.0dBFS

–20dBFS

0.1

INPUT FREQUENCY – MHz

1.0

10.0

Figure 2. SINAD vs. Input Frequency
(Input Span = 5 V, V

80

75

70

65

60

55

SINAD – dB

50

45

40

0.01 0.1 10.01.0
INPUT FREQUENCY – MHz

CM

–0.5dBFS

–6.0dBFS

–20.0dBFS

= 2.5 V)

–40

–50

–60

–70

THD – dB

–80

–90

–100

0.01 0.1

–20.0dBFS

–6.0dBFS

–0.5dBFS

INPUT FREQUENCY – MHz

1.0

Figure 3. THD vs. Input Frequency
(Input Span = 5 V, V

–40

–50

–60

–70

THD – dB

–80

–90

–100

0.01 0.1 10.01.0

–6.0dBFS

INPUT FREQUENCY – MHz

CM

–20.0dBFS

–0.5dBFS

= 2.5 V)

(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f

1.25 MSPS, TA = +258C, Differential Input)

10.0

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100
–110

AMPLITUDE – dB

–120
–130
–140
–150
–160
–170

0

3

5

8

100 200 300 400 500 600

FREQUENCY – kHz

Figure 4. Typical FFT, fIN > 500 kHz
(Input Span = 5 V, V

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100

5

–110

AMPLITUDE – dB

–120
–130
–140
–150
–160
–170

0

100 200 300 400 500 600

FREQUENCY – kHz

8

2

3

2

CM

7

FUND

6

7

= 2.5 V)

FUND

=

SAMPLE

4

9

4

9

6

Figure 5. SINAD vs. Input Frequency
(Input Span = 2 V, V

–40

–50

–60

–70

THD – dB

–80

–90

–100

0.1 1.0 10.0
SAMPLE RATE – MSPS

5V SPAN

= 2.5 V)

CM

2V SPAN

Figure 8. THD vs. Sample Rate

= 0.3 MHz, AIN = –0.5 dBFS,

(f

IN

= 2.5 V)

V

CM

Figure 6. THD vs. Input Frequency

dBFS - 5V

dBc - 2V

AIN – dBFS

= 2.5 V)

CM

–9 –3

(Input Span = 2 V, V

110

100

90

dBc - 5V

80

70

dBFS - 5V

60

SFDR – dBc AND dBFS

50

40

–39 –33 –27 –21 –15

–45

Figure 9. Single Tone SFDR

= 0.6 MHz, VCM = 2.5 V)

(f

IN

–6–

Figure 7. Typical FFT, fIN > 500 kHz
(Input Span = 2 V, V

110
105
100

WORST CASE SPURIOUS – dBc AND dBFS

0

5V SPAN - dBFS

95
90
85
80

5V SPAN - dBc

75
70
65
60

–40 –35 0

INPUT POWER LEVEL (f1 = f2) – dBFS

CM

2V SPAN - dBFS

2V SPAN - dBc

–30 –25 –20 –15 –10 –5

Figure 10. Dual Tone SFDR
(f

= 0.5 MHz, f2 = 0.6 MHz,

1

= 2.5 V)

V

CM

= 2.5 V)

REV. 0

AD9241

TEMPERATURE – 8C

V

REF

ERROR – V

0.01

–0.004

–0.01

–60 –40 140

–20 0 20 40 60 80 100 120

0.008

–0.002

–0.006
–0.008

0.002
0

0.006

0.004

Other Characterization Curves/Plots

3.0

2.5

2.0

1.5

1.0

0.5

0.0

–0.5

INL – LSB

–1.0
–1.5

–2.0
–2.5
–3.0

0

CODE

Figure 11. Typical INL
(Input Span = 5 V)

90

85

80

75

–0.5dBFS
–6.0dBFS

70

SINAD – dB

65

–20.0dBFS

60

55

50

0.01 0.1 10.0
INPUT FREQUENCY – MHz

1.0

16383

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

DNL – LSB

–0.4
–0.6
–0.8
–1.0

0

Figure 12. Typical DNL
(Input Span = 5 V)

–40

–50

–60

–20dBFS

–70

THD – dB

–6dBFS

–80

–0.5dBFS

–90

–100

0.01 0.1 10.0

(AVDD = +5 V, DVDD = +5 V, DRVDD = +5 V, f
Single-Ended Input)

100%

HITS

CODE

INPUT FREQUENCY – MHz

1.0

16383

Figure 13. “Grounded-Input”
Histogram (Input Span = 5 V)

40

50

60

70

CMR – dB

80

90

0.01 0.1 10.0

= 1.25 MSPS, TA = +258C,

SAMPLE

12,901,627

1,137,700

N–1

N N+1

CODE

1.0

FREQUENCY – MHz

1,146,291

100

Figure 14. SINAD vs. Input Frequency
(Input Span = 2 V, V

90
85

80
75
70
65
60

SINAD – dB

55
50
45
40

0.01 0.1 10.0
INPUT FREQUENCY – MHz

Figure 17. SINAD vs. Input Frequency
(Input Span = 5 V, V

REV. 0

CM

–0.5dBFS

–6dBFS

–20dBFS

CM

= 2.5 V)

1.0

= 2.5 V)

Figure 15. THD vs. Input Frequency
(Input Span = 2 V, V

–40

–50

–60

–70

–20dBFS

THD – dB

–6dBFS

–80

–0.5dBFS

–90

–100

0.01 0.1 1.0
INPUT FREQUENCY – MHz

= 2.5 V)

CM

10.0

Figure 18. THD vs. Input Frequency
(Input Span = 5 V, V

= 2.5 V)

CM

–7–

Figure 16. CMR vs. Input Frequency
(Input Span = 2 V, V

= 2.5 V)

CM

Figure 19. Typical Voltage Reference
Error vs. Temperature

AD9241

INTRODUCTION

The AD9241 uses a four-stage pipeline architecture with a
wideband input sample-and-hold amplifier (SHA) implemented
on a cost-effective CMOS process. Each stage of the pipeline,
excluding the last, consists of a low resolution flash A/D con­nected to a switched capacitor DAC and interstage residue
amplifier (MDAC). The residue amplifier amplifies the differ­ence between the reconstructed DAC output and the flash input
for the next stage in the pipeline. One bit of redundancy is used
in each of the stages to facilitate digital correction of flash er­rors. The last stage simply consists of a flash A/D.

The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. This means that while the
converter is capable of capturing a new input sample every clock
cycle, it actually takes three clock cycles for the conversion to be
fully processed and appear at the output. This latency is not a
concern in most applications. The digital output, together with
the out-of-range indicator (OTR), is latched into an output
buffer to drive the output pins. The output drivers can be con­figured to interface with +5 V or +3.3 V logic families.

The AD9241 uses both edges of the clock in its internal timing
circuitry (see Figure 1 and specification page for exact timing
requirements). The A/D samples the analog input on the rising
edge of the clock input. During the clock low time (between the
falling edge and rising edge of the clock), the input SHA is in
the sample mode; during the clock high time it is in the hold
mode. System disturbances just prior to the rising edge of the
clock and/or excessive clock jitter may cause the input SHA to
acquire the wrong value and should be minimized.

ANALOG INPUT AND REFERENCE OVERVIEW

Figure 20, a simplified model of the AD9241, highlights the rela­tionship between the analog inputs, VINA, VINB, and the
reference voltage, VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF defines
the maximum input voltage to the A/D core. The minimum input
voltage to the A/D core is automatically defined to be –VREF.

VINA

VINB

AD9241

V

CORE

+VREF

A/D

CORE

–VREF

14

Figure 20. Equivalent Functional Input Circuit

The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config­ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the

converter. Specifically, the input to the A/D core is the difference
of the voltages applied at the VINA and VINB input pins.
Therefore, the equation,

V

= VINA – VINB (1)

CORE

defines the output of the differential input stage and provides the
input to the A/D core.

The voltage, V

, must satisfy the condition,

CORE

≤

V

–VREF

≤ VREF (2)

CORE

where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist

to satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9241. The power
supplies bound the valid operating range for VINA and VINB.
The condition,

AVSS – 0.3 V < VINA < AVDD + 0.3 V (3)

AVSS – 0.3 V < VINB < AVDD + 0.3 V

where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both Equa­tions 2 and 3.

For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9241, see
Table IV.

Refer to Table I and Table II for a summary of the various
analog input and reference configurations.

ANALOG INPUT OPERATION

Figure 21 shows the equivalent analog input of the AD9241,
which consists of a differential sample-and-hold amplifier
(SHA). The differential input structure of the SHA is highly
flexible, allowing the devices to be easily configured for either a
differential or single-ended input. The dc offset, or common­mode voltage, of the input(s) can be set to accommodate either
single-supply or dual supply systems. Also, note that the analog
inputs, VINA and VINB, are interchangeable, with the exception
that reversing the inputs to the VINA and VINB pins results in a
polarity inversion.

C

H

Q

S2

Q

S2

C

H

VINA

VINB

+

C

PIN

Q

C

S1

PAR

Q

S1

–

C

PIN

C

PAR

C

S

Q

C

H1

S

Figure 21. Simplified Input Circuit

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